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[bsp][renesas]add ra8d1-vision-board support

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This commit is contained in:
Rbb666
2024-03-05 13:51:03 +08:00
committed by Rbb666
parent 859781232c
commit e1b80650d9
162 changed files with 125967 additions and 4 deletions
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1
.github/workflows/bsp_buildings.yml vendored
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@@ -218,6 +218,7 @@ jobs:
- "renesas/ra2l1-cpk"
- "renesas/ra8m1-ek"
- "renesas/ra8d1-ek"
- "renesas/ra8d1-vision-board"
- RTT_BSP: "gd32_n32_apm32"
RTT_TOOL_CHAIN: "sourcery-arm"
SUB_RTT_BSP:

26
bsp/renesas/libraries/HAL_Drivers/drv_sci.c
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@@ -22,6 +22,15 @@
#endif /* DRV_DEBUG */
#include <rtdbg.h>
#ifdef R_SCI_B_SPI_H
#define R_SCI_SPI_Write R_SCI_B_SPI_Write
#define R_SCI_SPI_Read R_SCI_B_SPI_Read
#define R_SCI_SPI_WriteRead R_SCI_B_SPI_WriteRead
#define R_SCI_SPI_Open R_SCI_B_SPI_Open
#define R_SCI_SPI_Close R_SCI_B_SPI_Close
#define R_SCI_SPI_CallbackSet R_SCI_B_SPI_CallbackSet
#endif
enum
{
#ifdef BSP_USING_SCI0
@@ -108,7 +117,7 @@ struct ra_sci_object
#endif
#ifndef BITS
#define BITS(b,e) ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e))))
#define BITS(b,e) ((((uint32_t)-1)<<(b))&(((uint32_t)-1)>>(31-(e))))
#endif
#define _TO_STR(_a) #_a
@@ -225,7 +234,7 @@ const static struct ra_sci_param sci_param[] =
#endif
};
static struct ra_sci_object sci_obj[RA_SCI_INDEX_MAX] = {0};
static struct ra_sci_object sci_obj[RA_SCI_INDEX_MAX];
rt_used static rt_err_t ra_wait_complete(struct ra_sci_object *obj)
{
rt_uint32_t event = 0;
@@ -625,6 +634,7 @@ static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_sp
LOG_E("%s write and read failed. %d", param->bus_name, err);
return -RT_ERROR;
}
/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
ra_wait_complete(obj);
return message->length;
@@ -648,13 +658,21 @@ static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
configuration->data_width = configuration->data_width / 8;
obj->spi_cfg = configuration;
sci_spi_extended_cfg_t *cfg_ext = (sci_spi_extended_cfg_t *)cfg->p_extend;
#ifdef R_SCI_B_SPI_H
sci_b_spi_extended_cfg_t spi_cfg = *(sci_b_spi_extended_cfg_t *)cfg->p_extend;
#else
sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)cfg->p_extend;
#endif
/**< Configure Select Line */
rt_pin_write(device->cs_pin, PIN_HIGH);
/**< config bitrate */
#ifdef R_SCI_B_SPI_H
R_SCI_B_SPI_CalculateBitrate(obj->spi_cfg->max_hz, SCI_B_SPI_SOURCE_CLOCK_PCLK, &spi_cfg.clk_div);
#else
R_SCI_SPI_CalculateBitrate(obj->spi_cfg->max_hz, &cfg_ext->clk_div, false);
#endif
/**< init */
err = R_SCI_SPI_Open((spi_ctrl_t *)param->sci_ctrl, cfg);
@@ -863,7 +881,7 @@ rt_weak int rt_hw_usart_init(void)
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
#ifdef BSP_USING_SCIn_SPI
rt_err_t drv_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
rt_err_t rt_hw_sci_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);

2
bsp/renesas/ra8d1-vision-board/.api_xml Normal file
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@@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<ddscApi/>

1083
bsp/renesas/ra8d1-vision-board/.config Normal file
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File diff suppressed because it is too large Load Diff

222
bsp/renesas/ra8d1-vision-board/.cproject Normal file
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File diff suppressed because one or more lines are too long

5
bsp/renesas/ra8d1-vision-board/.gitignore vendored Normal file
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@@ -0,0 +1,5 @@
/RTE
/Listings
/Objects
ra_cfg.txt

9
bsp/renesas/ra8d1-vision-board/.ignore_format.yml Normal file
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@@ -0,0 +1,9 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- ra
- ra_gen
- ra_cfg
- RTE

28
bsp/renesas/ra8d1-vision-board/.project Normal file
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@@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ra6m3-temp</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.rt-thread.studio.rttnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources />
</projectDescription>

151
bsp/renesas/ra8d1-vision-board/.secure_azone Normal file
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@@ -0,0 +1,151 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<azone>
<rzone name="R7FA8D1BHECBD.rzone"/>
<partition>
<peripheral name="PORT0" group="PORT">
<slot name="P002" secure="true"/>
<slot name="P003" secure="true"/>
<slot name="P004" secure="true"/>
<slot name="P005" secure="true"/>
<slot name="P007" secure="true"/>
<slot name="P008" secure="true"/>
<slot name="P009" secure="true"/>
<slot name="P011" secure="true"/>
<slot name="P014" secure="true"/>
<slot name="P015" secure="true"/>
</peripheral>
<peripheral name="PORT1" group="PORT">
<slot name="P100" secure="true"/>
<slot name="P101" secure="true"/>
<slot name="P103" secure="true"/>
<slot name="P107" secure="true"/>
<slot name="P112" secure="true"/>
<slot name="P113" secure="true"/>
<slot name="P114" secure="true"/>
<slot name="P115" secure="true"/>
</peripheral>
<peripheral name="PORT2" group="PORT">
<slot name="P206" secure="true"/>
<slot name="P207" secure="true"/>
<slot name="P208" secure="true"/>
<slot name="P209" secure="true"/>
<slot name="P210" secure="true"/>
<slot name="P211" secure="true"/>
</peripheral>
<peripheral name="PORT3" group="PORT">
<slot name="P300" secure="true"/>
<slot name="P301" secure="true"/>
<slot name="P302" secure="true"/>
<slot name="P303" secure="true"/>
<slot name="P304" secure="true"/>
<slot name="P305" secure="true"/>
<slot name="P306" secure="true"/>
<slot name="P307" secure="true"/>
<slot name="P308" secure="true"/>
<slot name="P309" secure="true"/>
<slot name="P310" secure="true"/>
<slot name="P311" secure="true"/>
<slot name="P312" secure="true"/>
</peripheral>
<peripheral name="PORT4" group="PORT">
<slot name="P400" secure="true"/>
<slot name="P401" secure="true"/>
<slot name="P405" secure="true"/>
<slot name="P406" secure="true"/>
<slot name="P407" secure="true"/>
<slot name="P408" secure="true"/>
<slot name="P409" secure="true"/>
</peripheral>
<peripheral name="PORT5" group="PORT">
<slot name="P500" secure="true"/>
<slot name="P501" secure="true"/>
<slot name="P502" secure="true"/>
<slot name="P503" secure="true"/>
<slot name="P504" secure="true"/>
<slot name="P505" secure="true"/>
<slot name="P506" secure="true"/>
<slot name="P515" secure="true"/>
</peripheral>
<peripheral name="PORT6" group="PORT">
<slot name="P600" secure="true"/>
<slot name="P601" secure="true"/>
<slot name="P602" secure="true"/>
<slot name="P603" secure="true"/>
<slot name="P604" secure="true"/>
<slot name="P605" secure="true"/>
<slot name="P606" secure="true"/>
<slot name="P607" secure="true"/>
<slot name="P609" secure="true"/>
<slot name="P610" secure="true"/>
<slot name="P611" secure="true"/>
<slot name="P612" secure="true"/>
<slot name="P613" secure="true"/>
<slot name="P614" secure="true"/>
<slot name="P615" secure="true"/>
</peripheral>
<peripheral name="PORT7" group="PORT">
<slot name="P700" secure="true"/>
<slot name="P701" secure="true"/>
<slot name="P702" secure="true"/>
<slot name="P703" secure="true"/>
<slot name="P708" secure="true"/>
<slot name="P709" secure="true"/>
<slot name="P710" secure="true"/>
<slot name="P711" secure="true"/>
<slot name="P712" secure="true"/>
<slot name="P713" secure="true"/>
<slot name="P714" secure="true"/>
<slot name="P715" secure="true"/>
</peripheral>
<peripheral name="PORT8" group="PORT">
<slot name="P803" secure="true"/>
<slot name="P805" secure="true"/>
<slot name="P806" secure="true"/>
<slot name="P807" secure="true"/>
<slot name="P808" secure="true"/>
<slot name="P809" secure="true"/>
<slot name="P810" secure="true"/>
<slot name="P811" secure="true"/>
<slot name="P812" secure="true"/>
<slot name="P814" secure="true"/>
<slot name="P815" secure="true"/>
</peripheral>
<peripheral name="PORT9" group="PORT">
<slot name="P902" secure="true"/>
<slot name="P903" secure="true"/>
<slot name="P904" secure="true"/>
<slot name="P905" secure="true"/>
<slot name="P906" secure="true"/>
<slot name="P908" secure="true"/>
<slot name="P909" secure="true"/>
<slot name="P910" secure="true"/>
<slot name="P911" secure="true"/>
<slot name="P912" secure="true"/>
<slot name="P913" secure="true"/>
<slot name="P914" secure="true"/>
<slot name="P915" secure="true"/>
</peripheral>
<peripheral name="PORTA" group="PORT">
<slot name="PA00" secure="true"/>
<slot name="PA02" secure="true"/>
<slot name="PA03" secure="true"/>
<slot name="PA08" secure="true"/>
<slot name="PA09" secure="true"/>
<slot name="PA10" secure="true"/>
<slot name="PA11" secure="true"/>
<slot name="PA13" secure="true"/>
</peripheral>
<peripheral name="PORTB" group="PORT">
<slot name="PB01" secure="true"/>
<slot name="PB05" secure="true"/>
<slot name="PB06" secure="true"/>
<slot name="PB07" secure="true"/>
</peripheral>
<peripheral name="ICU">
<slot name="IRQ0" secure="true"/>
<slot name="IRQ1" secure="true"/>
<slot name="IRQ2" secure="true"/>
<slot name="IRQ3" secure="true"/>
</peripheral>
</partition>
</azone>

213
bsp/renesas/ra8d1-vision-board/.secure_xml Normal file
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@@ -0,0 +1,213 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="8">
<generalSettings>
<option key="#Board#" value="board.ra8d1ek"/>
<option key="CPU" value="RA8D1"/>
<option key="Core" value="CM85"/>
<option key="#TargetName#" value="R7FA8D1BHECBD"/>
<option key="#TargetARCHITECTURE#" value="cortex-m85"/>
<option key="#DeviceCommand#" value="R7FA8D1BH"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA8M1AHECBD.pincfg"/>
<option key="#FSPVersion#" value="5.1.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra8m1_ek##|Renesas##BSP##Board##ra8d1_ek##"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raBspConfiguration/>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.1"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.48_00"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll1p.div" option="board.clock.pll1p.div.2"/>
<node id="board.clock.pll1p.display" option="board.clock.pll1p.display.value"/>
<node id="board.clock.pll1q.div" option="board.clock.pll1q.div.4"/>
<node id="board.clock.pll1q.display" option="board.clock.pll1q.display.value"/>
<node id="board.clock.pll1r.div" option="board.clock.pll1r.div.2"/>
<node id="board.clock.pll1r.display" option="board.clock.pll1r.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.1"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.48_00"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.pll2p.div" option="board.clock.pll2p.div.2"/>
<node id="board.clock.pll2p.display" option="board.clock.pll2p.display.value"/>
<node id="board.clock.pll2q.div" option="board.clock.pll2q.div.2"/>
<node id="board.clock.pll2q.display" option="board.clock.pll2q.display.value"/>
<node id="board.clock.pll2r.div" option="board.clock.pll2r.div.2"/>
<node id="board.clock.pll2r.display" option="board.clock.pll2r.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll1p"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.sciclk.source" option="board.clock.sciclk.source.pll1p"/>
<node id="board.clock.spiclk.source" option="board.clock.spiclk.source.disabled"/>
<node id="board.clock.canfdclk.source" option="board.clock.canfdclk.source.disabled"/>
<node id="board.clock.lcdclk.source" option="board.clock.lcdclk.source.pll1p"/>
<node id="board.clock.i3cclk.source" option="board.clock.i3cclk.source.disabled"/>
<node id="board.clock.uck.source" option="board.clock.uck.source.pll1q"/>
<node id="board.clock.u60ck.source" option="board.clock.u60ck.source.disabled"/>
<node id="board.clock.octaspiclk.source" option="board.clock.octaspiclk.source.disabled"/>
<node id="board.clock.cpuclk.div" option="board.clock.cpuclk.div.1"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.4"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.8"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.8"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.4"/>
<node id="board.clock.pclke.div" option="board.clock.pclke.div.2"/>
<node id="board.clock.sdclkout.enable" option="board.clock.sdclkout.enable.enabled"/>
<node id="board.clock.bclk.div" option="board.clock.bclk.div.4"/>
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.8"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.sciclk.div" option="board.clock.sciclk.div.4"/>
<node id="board.clock.spiclk.div" option="board.clock.spiclk.div.4"/>
<node id="board.clock.canfdclk.div" option="board.clock.canfdclk.div.8"/>
<node id="board.clock.lcdclk.div" option="board.clock.lcdclk.div.2"/>
<node id="board.clock.i3cclk.div" option="board.clock.i3cclk.div.3"/>
<node id="board.clock.uck.div" option="board.clock.uck.div.5"/>
<node id="board.clock.u60ck.div" option="board.clock.u60ck.div.5"/>
<node id="board.clock.octaspiclk.div" option="board.clock.octaspiclk.div.4"/>
<node id="board.clock.cpuclk.display" option="board.clock.cpuclk.display.value"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.pclke.display" option="board.clock.pclke.display.value"/>
<node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.sciclk.display" option="board.clock.sciclk.display.value"/>
<node id="board.clock.spiclk.display" option="board.clock.spiclk.display.value"/>
<node id="board.clock.canfdclk.display" option="board.clock.canfdclk.display.value"/>
<node id="board.clock.lcdclk.display" option="board.clock.lcdclk.display.value"/>
<node id="board.clock.i3cclk.display" option="board.clock.i3cclk.display.value"/>
<node id="board.clock.uck.display" option="board.clock.uck.display.value"/>
<node id="board.clock.u60ck.display" option="board.clock.u60ck.display.value"/>
<node id="board.clock.octaspiclk.display" option="board.clock.octaspiclk.display.value"/>
</raClockConfiguration>
<raPinConfiguration>
<pincfg active="true" name="" symbol="">
<configSetting altId="adc0.an000.p004" configurationId="adc0.an000"/>
<configSetting altId="adc0.an001.p005" configurationId="adc0.an001"/>
<configSetting altId="adc0.an004.p007" configurationId="adc0.an004"/>
<configSetting altId="adc0.an007.p014" configurationId="adc0.an007"/>
<configSetting altId="adc1.an102.p002" configurationId="adc1.an102"/>
<configSetting altId="adc1.an104.p003" configurationId="adc1.an104"/>
<configSetting altId="adc1.an105.p015" configurationId="adc1.an105"/>
<configSetting altId="adc1.an106.p011" configurationId="adc1.an106"/>
<configSetting altId="ceu.vio_clk.p708" configurationId="ceu.vio_clk"/>
<configSetting altId="ceu.vio_d0.p400" configurationId="ceu.vio_d0"/>
<configSetting altId="ceu.vio_d1.p401" configurationId="ceu.vio_d1"/>
<configSetting altId="ceu.vio_d2.p405" configurationId="ceu.vio_d2"/>
<configSetting altId="ceu.vio_d3.p406" configurationId="ceu.vio_d3"/>
<configSetting altId="ceu.vio_d4.p700" configurationId="ceu.vio_d4"/>
<configSetting altId="ceu.vio_d5.p701" configurationId="ceu.vio_d5"/>
<configSetting altId="ceu.vio_d6.p702" configurationId="ceu.vio_d6"/>
<configSetting altId="ceu.vio_d7.p703" configurationId="ceu.vio_d7"/>
<configSetting altId="ceu.vio_hd.p709" configurationId="ceu.vio_hd"/>
<configSetting altId="ceu.vio_vd.p710" configurationId="ceu.vio_vd"/>
<configSetting altId="glcd.lcd_clk.p806" configurationId="glcd.lcd_clk"/>
<configSetting altId="glcd.lcd_data0.p914" configurationId="glcd.lcd_data0"/>
<configSetting altId="glcd.lcd_data1.p915" configurationId="glcd.lcd_data1"/>
<configSetting altId="glcd.lcd_data10.p711" configurationId="glcd.lcd_data10"/>
<configSetting altId="glcd.lcd_data11.p712" configurationId="glcd.lcd_data11"/>
<configSetting altId="glcd.lcd_data12.p713" configurationId="glcd.lcd_data12"/>
<configSetting altId="glcd.lcd_data13.p714" configurationId="glcd.lcd_data13"/>
<configSetting altId="glcd.lcd_data14.p715" configurationId="glcd.lcd_data14"/>
<configSetting altId="glcd.lcd_data15.pb07" configurationId="glcd.lcd_data15"/>
<configSetting altId="glcd.lcd_data16.pb06" configurationId="glcd.lcd_data16"/>
<configSetting altId="glcd.lcd_data17.pb05" configurationId="glcd.lcd_data17"/>
<configSetting altId="glcd.lcd_data2.p910" configurationId="glcd.lcd_data2"/>
<configSetting altId="glcd.lcd_data3.p911" configurationId="glcd.lcd_data3"/>
<configSetting altId="glcd.lcd_data4.p912" configurationId="glcd.lcd_data4"/>
<configSetting altId="glcd.lcd_data5.p913" configurationId="glcd.lcd_data5"/>
<configSetting altId="glcd.lcd_data6.p904" configurationId="glcd.lcd_data6"/>
<configSetting altId="glcd.lcd_data7.p903" configurationId="glcd.lcd_data7"/>
<configSetting altId="glcd.lcd_data8.p902" configurationId="glcd.lcd_data8"/>
<configSetting altId="glcd.lcd_data9.p207" configurationId="glcd.lcd_data9"/>
<configSetting altId="glcd.lcd_tcon0.p805" configurationId="glcd.lcd_tcon0"/>
<configSetting altId="glcd.lcd_tcon1.p807" configurationId="glcd.lcd_tcon1"/>
<configSetting altId="glcd.lcd_tcon3.p515" configurationId="glcd.lcd_tcon3"/>
<configSetting altId="gpt6.gtioc6a.pa11" configurationId="gpt6.gtioc6a"/>
<configSetting altId="irq12.irq12_dash_ds.p008" configurationId="irq12.irq12_dash_ds"/>
<configSetting altId="irq13.irq13_dash_ds.p009" configurationId="irq13.irq13_dash_ds"/>
<configSetting altId="jtag_fslash_swd.swclk.p211" configurationId="jtag_fslash_swd.swclk"/>
<configSetting altId="jtag_fslash_swd.swdio.p210" configurationId="jtag_fslash_swd.swdio"/>
<configSetting altId="mipi.dsi_te.p206" configurationId="mipi.dsi_te"/>
<configSetting altId="ospi.om_cs0.p107" configurationId="ospi.om_cs0"/>
<configSetting altId="ospi.om_sclk.p808" configurationId="ospi.om_sclk"/>
<configSetting altId="ospi.om_sio0.p100" configurationId="ospi.om_sio0"/>
<configSetting altId="ospi.om_sio1.p803" configurationId="ospi.om_sio1"/>
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<configSetting altId="p504.input" configurationId="p504"/>
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<configSetting altId="p506.input" configurationId="p506"/>
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<configSetting altId="sdram.cke.p113" configurationId="sdram.cke"/>
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<configSetting altId="sdram.dq1.p602" configurationId="sdram.dq1"/>
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<configSetting altId="sdram.sdcs.p115" configurationId="sdram.sdcs"/>
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<configSetting altId="usbfs.usb_dm.p815" configurationId="usbfs.usb_dm"/>
<configSetting altId="usbfs.usb_dp.p814" configurationId="usbfs.usb_dp"/>
<configSetting altId="usbfs.usb_vbus.p407" configurationId="usbfs.usb_vbus"/>
<configSetting altId="usbhs.usbhs_vbus.pb01" configurationId="usbhs.usbhs_vbus"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

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bsp/renesas/ra8d1-vision-board/.settings/.rtmenus Normal file
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2
bsp/renesas/ra8d1-vision-board/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs Normal file
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eclipse.preferences.version=1
toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin

14
bsp/renesas/ra8d1-vision-board/.settings/language.settings.xml Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
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2
bsp/renesas/ra8d1-vision-board/.settings/local_temp_storage.prefs Normal file
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eclipse.preferences.version=1
temp.toolchain.exec.path=D\:\\software\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\10.2.1/bin

3
bsp/renesas/ra8d1-vision-board/.settings/org.eclipse.core.runtime.prefs Normal file
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content-types/enabled=true
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
eclipse.preferences.version=1

20
bsp/renesas/ra8d1-vision-board/.settings/projcfg.ini Normal file
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@@ -0,0 +1,20 @@
#RT-Thread Studio Project Configuration
#Wed Feb 07 13:55:22 CST 2024
project_type=rt-thread
chip_name=R7FA8D1BH
project_base_rtt_bsp=true
os_branch=full
example_name=
os_version=5.1.0
selected_rtt_version=5.1.0
cfg_version=v3.0
board_base_nano_proj=false
is_use_scons_build=true
output_project_path=C\:\\Users\\rb\\Desktop\\sdk-bsp-ra8d1-vision-board-studio\\projects
hardware_adapter=DAP-LINK
project_name=ra8d1-vision-board
is_base_example_project=false
board_name=Vision-board
device_vendor=Renesas
bsp_path=
bsp_version=

64
bsp/renesas/ra8d1-vision-board/.settings/ra8d1-vision-board.DAPLink.Debug.rttlaunch Normal file
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21
bsp/renesas/ra8d1-vision-board/.settings/standalone.prefs Normal file
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@@ -0,0 +1,21 @@
#Fri Dec 29 16:24:19 CST 2023
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra8d1_ek\#\#\#\#5.1.0/all=3509892698,ra/board/ra8d1_ek/board_leds.h|3819758545,ra/board/ra8d1_ek/board_sdram.c|2603656871,ra/board/ra8d1_ek/board_leds.c|3640013112,ra/board/ra8d1_ek/board_sdram.h|105041966,ra/board/ra8d1_ek/board_init.h|95488157,ra/board/ra8d1_ek/board.h|1628416776,ra/board/ra8d1_ek/board_ethernet_phy.h|777474786,ra/board/ra8d1_ek/board_init.c
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.1.0/all=3058606325,ra/fsp/inc/instances/r_ioport.h|1896254027,ra/fsp/inc/api/r_ioport_api.h|3002446768,ra/fsp/src/r_ioport/r_ioport.c
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#R7FA8D1BHECBD\#\#5.1.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=DeviceAndToolSelection
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#\#\#5.1.0/all=3387474234,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#fsp\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_b_uart\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#fsp\#\#\#\#5.1.0/all=4143092756,script/fsp.scat|346195372,script/ac6/fsp_keep.via|934437302,ra/fsp/inc/fsp_features.h|3058606325,ra/fsp/inc/instances/r_ioport.h|543620856,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1171232788,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|296810838,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1632728582,ra/fsp/src/bsp/mcu/all/bsp_common.h|2702335218,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3171976222,ra/fsp/src/bsp/mcu/all/bsp_security.c|429234293,ra/fsp/src/bsp/mcu/all/bsp_common.c|2365965045,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1835725510,ra/fsp/src/bsp/mcu/all/bsp_io.c|271204625,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3610800851,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3569788004,ra/fsp/src/bsp/mcu/all/bsp_io.h|3085135894,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|1246740431,ra/fsp/src/bsp/mcu/all/bsp_delay.h|248082807,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|1884526901,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2942105346,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1331691689,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|4116718951,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1668386995,ra/fsp/src/bsp/mcu/all/bsp_security.h|2551036977,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3324174567,ra/fsp/src/bsp/mcu/all/bsp_exceptions.h|3881030941,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1437525339,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|4092753007,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2550773705,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|690210506,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2190391198,ra/fsp/src/bsp/mcu/ra8d1/bsp_mcu_info.h|944400528,ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h|3051997639,ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h|4150320773,ra/fsp/src/bsp/mcu/ra8d1/bsp_override.h
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.5.1.0/all=1441545198,ra/arm/CMSIS_5/LICENSE.txt|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_b_uart\#\#\#\#5.1.0/all=419014891,ra/fsp/inc/instances/r_sci_b_uart.h|3115705082,ra/fsp/inc/api/r_transfer_api.h|1476071459,ra/fsp/inc/api/r_uart_api.h|3063216256,ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra8d1\#\#device\#\#R7FA8D1BHECBD\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#5.1.0/all=3217525171,ra/fsp/inc/fsp_version.h|1896254027,ra/fsp/inc/api/r_ioport_api.h|2560512765,ra/fsp/inc/api/bsp_api.h|1037141086,ra/fsp/inc/api/fsp_common_api.h|4290340792,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3088407548,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra8d1_ek\#\#\#\#5.1.0/libraries=
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_b_uart.1514241209=false
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.5.1.0/libraries=

29
bsp/renesas/ra8d1-vision-board/Kconfig Normal file
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@@ -0,0 +1,29 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "$BSP_DIR/board/Kconfig"

185
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# Vision Board 开发板 BSP 说明
## 简介
Vision-Board 开发板是 RT-Thread 推出基于瑞萨 Cortex-M85 架构 RA8D1 芯片，为工程师们提供了一个灵活、全面的开发平台，助力开发者在机器视觉领域获得更深层次的体验。
![](docs/picture/logo.png)
## 开发板介绍
该开发板常用 **板载资源** 如下：
![](docs/picture/hw.png)
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------: | :----------: | :-----------------------: |
| UART | 支持 | UART9 为默认日志输出端口 |
| GPIO | 支持 | |
| USB | 支持 | TinyUSB |
| Camera | 支持 | ov2640、ov7725、ov7670... |
| SDHC | 支持 | 1bit、4bit |
| ADC | 支持 | |
| DAC | 支持 | |
| SPI | 支持 | |
| PWM | 支持 | |
| RTC | 支持 | |
| FLASH | 支持 | |
| WDT | 支持 | |
| IIC | 支持 | |
| Wi-Fi | 支持 | RW007 |
* 注意：仓库刚拉下来是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
## 模板工程说明
![](docs/picture/1.png)
![](docs/picture/2.png)
如上图所示，RGB-LED 属于共阳 LED， **阴极** 分别与单片机的引脚相连，其中蓝色 LED 对应 P102 引脚。单片机引脚输出低电平即可点亮 LED，输出高电平则会熄灭 LED。
## 软件说明
闪灯的源代码位于 `ra8d1-vision-board/src/hal_entry.c` 中。首先定义了一个宏 `LED_PIN` ，代表闪灯的 LED 引脚编号，然后与 `BSP_IO_PORT_01_PIN_02`（**P102 **）对应：
```
#define LED_PIN BSP_IO_PORT_01_PIN_02 /* Onboard LED pins */
```
在 main 函数中，将该引脚配置为输出模式，并在下面的 while 循环中，周期性（500毫秒）开关 LED。
```
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 支持的编译平台
* armclang（AC6 V6.19）
* LLVM（V16/17）[ARM-software/LLVM-embedded-toolchain-for-Arm (github.com)](https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/tag/release-17.0.1)
## FSP版本说明
本BSP使用的是FSP5.1.0版本，进行外设相关开发需要下载并安装。
* 下载链接：[rasc-5.1.0](https://github.com/renesas/fsp/releases/download/v5.1.0/setup_fsp_v5_1_0_rasc_v2023-10.exe)
* 注意：BSP默认是最小系统，若需添加/使能其他外设需参考：[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
### 快速上手
#### 1、使用 MDK 编译：
本 BSP 目前提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**编译下载**
- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
- 下载：点击 MDK 的 Debug 按钮进行下载调试
#### 2、使用 LLVM 编译
使用 env 工具打开当前 bsp，设定要使用的工具链和对应的路径。
```shell
set RTT_CC=llvm-arm
set RTT_EXEC_PATH=D:\Progrem\LLVMEmbeddedToolchainForArm-17.0.1-Windows-x86_64\bin
```
然后运行 scons 命令，执行编译
```shell
scons
```
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
[D/main] sdram init success, mapped at 0x68000000, size is 33554432 bytes, data width is 16
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Mar 5 2024 13:57:23
2006 - 2024 Copyright by RT-Thread team
Hello RT-Thread!
msh >
msh >
```
### 进阶使用
**资料及文档**
- [开发板官网主页](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8d1-evaluation-kit-ra8d1-mcu-group#overview)
- [开发板用户手册](https://www.renesas.cn/cn/zh/document/mat/ek-ra8d1-v1-users-manual?r=25452351)
- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
**ENV 配置**
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
此 BSP 默认只开启了 UART9 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
**FSP配置**
* 如何使用 FSP：[RA系列使用 FSP 配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)
目前仓库 bsp 默认使能最小体量配置，用户可通过如下步骤使能 env 外设配置：
1. 在 bsp 目录下打开 env 工具，使用 `scons --target=mdk5`命令生成 MDK 工程。
2. 打开 bsp 目录下的`project.uvprojx`文件，选择上方导航栏的 `Software Components`配置，打开后找到`Flex Software`下的`RA Configuration`旁的配置按钮，该操作会自动查找当前电脑环境下安装的 fsp 版本，选择指定版本后进入 fsp。
![](../docs/figures/mdk_rasc.png)
3. 在进入 fsp 后我们可以发现，已经存在了一些已经配置完成的外设，此时我们点击`Generate Project Content`按钮即可生成所需驱动文件。
![](../docs/figures/fsp_configure.png)
4. 接下来回到 env，使能所需的外设配置后保存退出即可。
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## SDK 仓库
这是 Vision Board 的 SDK 仓库地址：[sdk-bsp-ra8d1-vision-board](https://github.com/RT-Thread-Studio/sdk-bsp-ra8d1-vision-board)，该仓库包括了外设驱动以及丰富的示例工程，如果像体验官网/社区提供的开源示例请转移到该仓库进行开发。RT-Thread 主仓库只维护最新的驱动相关代码。
## 贡献代码
如果您对 Vision Board 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

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bsp/renesas/ra8d1-vision-board/SConscript Normal file
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# for module compiling
import os
Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
CPPPATH = []
list = os.listdir(cwd)
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
CPPPATH = [cwd]
src = Glob('./src/*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
Return('group')

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bsp/renesas/ra8d1-vision-board/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
rtconfig.BSP_LIBRARY_TYPE = None
def startup_check():
import subprocess
startup_check_path = os.getcwd() + "/../tools/startup_check.py"
if os.path.exists(startup_check_path):
try:
subprocess.call(["python", startup_check_path])
except:
subprocess.call(["python3", startup_check_path])
RegisterPreBuildingAction(startup_check)
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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bsp/renesas/ra8d1-vision-board/board/Kconfig Normal file
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bsp/renesas/ra8d1-vision-board/board/SConscript Normal file
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import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
CPPPATH = [cwd]
src = Glob('*.c')
if GetDepend(['BSP_USING_FS']):
src += Glob('ports/mnt.c')
CPPDEFINES = ['BSP_CFG_RTOS = 2']
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

38
bsp/renesas/ra8d1-vision-board/board/board.h Normal file
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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-10 Sherman first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RA_SRAM_SIZE 896 /* The SRAM size of the chip needs to be modified */
#define RA_SRAM_END (0x22000000 + RA_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __RAM_segment_used_end__;
#define HEAP_BEGIN (&__RAM_segment_used_end__)
#endif
#define HEAP_END RA_SRAM_END
#ifdef __cplusplus
}
#endif
#endif

16
bsp/renesas/ra8d1-vision-board/board/ports/SConscript Normal file
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@@ -0,0 +1,16 @@
import os
from building import *
objs = []
src = Glob('*.c')
cwd = GetCurrentDir()
CPPPATH = [cwd]
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

262
bsp/renesas/ra8d1-vision-board/board/ports/drv_sdram.c Normal file
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/***********************************************************************************************************************
* Copyright [2020-2023] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "r_ioport.h"
#include "bsp_cfg.h"
#include "bsp_pin_cfg.h"
#include <rtthread.h>
#define DRV_DEBUG
#define LOG_TAG "drv_sdram"
#include <drv_log.h>
/*
* Set ACTIVE-to-PRECHARGE command (tRAS) timing
* e.g. tRAS = 42ns -> 6cycles are needed at SDCLK 120MHz
* tRAS = 37ns -> 5cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRAS (6U)
/*
* Set ACTIVE-to-READ or WRITE delay tRCD (tRCD) timing
* e.g. tRCD = 18ns -> 3cycles are needed at SDCLK 120MHz
* tRCD = 15ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRCD (3U)
/*
* Set PRECHARGE command period (tRP) timing
* e.g. tRP = 18ns -> 3cycles are needed at SDCLK 120MHz
* tRP = 15ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRP (3U)
/*
* Set WRITE recovery time (tWR) timing
* e.g. tWR = 1CLK + 6ns -> 2cycles are needed at SDCLK 120MHz
* tWR = 1CLK + 7ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TWR (2U)
/*
* Set CAS (READ) latency (CL) timing
* e.g. CL = 18ns -> 3cycles are needed at SDCLK 120MHz
* e.g. CL = 15ns -> 2cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_CL (3U)
/*
* Set AUTO REFRESH period (tRFC) timing
* e.g. tRFC = 60nS -> 8cycles are needed at SDCLK 120MHz
* tRFC = 66nS -> 8cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_TRFC (8U)
/*
* Set Average Refresh period
* e.g. tREF = 64ms/8192rows -> 7.8125us/each row. 937cycles are needed at SDCLK 120MHz
*/
#define BSP_PRV_SDRAM_REF_CMD_INTERVAL (937U)
/*
* Set Auto-Refresh issue times in initialization sequence needed for SDRAM device
* Typical SDR SDRAM device needs twice of Auto-Refresh command issue
*/
#define BSP_PRV_SDRAM_SDIR_REF_TIMES (2U)
/*
* Set RAW address offset
* Available settings are
* 8 : 8-bit
* 9 : 9-bit
* 10 : 10-bit
* 11 : 11-bit
*/
#define BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET (9U)
/*
* Select endian mode for SDRAM address space
* 0 : Endian of SDRAM address space is the same as the endian of operating mode
* 1 : Endian of SDRAM address space is not the endian of operating mode
*/
#define BSP_PRV_SDRAM_ENDIAN_MODE (0U)
/*
* Select access mode
* Typically Continuous access should be enabled to get better SDRAM bandwidth
* 0: Continuous access is disabled
* 1: Continuous access is enabled
*/
#define BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE (1U)
/*
* Select bus width
* 0: 16-bit
* 1: 32-bit
* 2: 8-bit
*/
#define BSP_PRV_SDRAM_BUS_WIDTH (0U)
#if ((BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 8U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 9U) \
&& (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET != 10U) && (BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET > 11U))
#error "BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET must be either of 8,9,10 or 11"
#endif
#if ((BSP_PRV_SDRAM_BUS_WIDTH != 0) && (BSP_PRV_SDRAM_BUS_WIDTH != 1U) && (BSP_PRV_SDRAM_BUS_WIDTH != 2U))
#error "BSP_PRV_SDRAM_BUS_WIDTH must be either of 0(16-bit) or 1(32-bit) or 2(8-bit)"
#endif
#if ((BSP_PRV_SDRAM_ENDIAN_MODE != 0) && (BSP_PRV_SDRAM_ENDIAN_MODE != 1))
#error \
"BSP_PRV_SDRAM_ENDIAN_MODE must be either of 0(same endian as operating mode) or 2(another endian against operating mode)"
#endif
#if ((BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 0) && (BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE != 1))
#error \
"BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE must be either of 0(continuous access is disabled) or 1(continuous access is enabled)"
#endif
#define BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC (1U) /* MR.M9 : Single Location Access */
#define BSP_PRV_SDRAM_MR_OP_MODE (0U) /* MR.M8:M7 : Standard Operation */
#define BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL (0U) /* MR.M3 Burst Type : Sequential */
#define BSP_PRV_SDRAM_MR_BURST_LENGTH (0U) /* MR.M2:M0 Burst Length: 0(1 burst) */
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
void drv_sdram_init(void)
{
/** Setting for SDRAM initialization sequence */
#if (BSP_PRV_SDRAM_TRP < 3)
R_BUS->SDRAM.SDIR_b.PRC = 3U;
#else
R_BUS->SDRAM.SDIR_b.PRC = BSP_PRV_SDRAM_TRP - 3U;
#endif
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
}
R_BUS->SDRAM.SDIR_b.ARFC = BSP_PRV_SDRAM_SDIR_REF_TIMES;
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDIR modification. */
}
#if (BSP_PRV_SDRAM_TRFC < 3)
R_BUS->SDRAM.SDIR_b.ARFI = 0U;
#else
R_BUS->SDRAM.SDIR_b.ARFI = BSP_PRV_SDRAM_TRFC - 3U;
#endif
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDICR modification. */
}
/** Start SDRAM initialization sequence.
* Following operation is automatically done when set SDICR.INIRQ bit.
* Perform a PRECHARGE ALL command and wait at least tRP time.
* Issue an AUTO REFRESH command and wait at least tRFC time.
* Issue an AUTO REFRESH command and wait at least tRFC time.
*/
R_BUS->SDRAM.SDICR_b.INIRQ = 1U;
while (R_BUS->SDRAM.SDSR_b.INIST)
{
/* Wait the end of initialization sequence. */
}
/** Setting for SDRAM controller */
R_BUS->SDRAM.SDCCR_b.BSIZE = BSP_PRV_SDRAM_BUS_WIDTH; /* set SDRAM bus width */
R_BUS->SDRAM.SDAMOD_b.BE = BSP_PRV_SDRAM_CONTINUOUS_ACCESSMODE; /* enable continuous access */
R_BUS->SDRAM.SDCMOD_b.EMODE = BSP_PRV_SDRAM_ENDIAN_MODE; /* set endian mode for SDRAM address space */
while (R_BUS->SDRAM.SDSR)
{
/* According to h/w maual, need to confirm that all the status bits in SDSR are 0 before SDMOD modification. */
}
/** Using LMR command, program the mode register */
R_BUS->SDRAM.SDMOD = ((((uint16_t)(BSP_PRV_SDRAM_MR_WB_SINGLE_LOC_ACC << 9) |
(uint16_t)(BSP_PRV_SDRAM_MR_OP_MODE << 7)) |
(uint16_t)(BSP_PRV_SDRAM_CL << 4)) |
(uint16_t)(BSP_PRV_SDRAM_MR_BT_SEQUENCTIAL << 3)) |
(uint16_t)(BSP_PRV_SDRAM_MR_BURST_LENGTH << 0);
/** wait at least tMRD time */
while (R_BUS->SDRAM.SDSR_b.MRSST)
{
/* Wait until Mode Register setting done. */
}
/** Set timing parameters for SDRAM */
R_BUS->SDRAM.SDTR_b.RAS = BSP_PRV_SDRAM_TRAS - 1U; /* set ACTIVE-to-PRECHARGE command cycles*/
R_BUS->SDRAM.SDTR_b.RCD = BSP_PRV_SDRAM_TRCD - 1U; /* set ACTIVE to READ/WRITE delay cycles */
R_BUS->SDRAM.SDTR_b.RP = BSP_PRV_SDRAM_TRP - 1U; /* set PRECHARGE command period cycles */
R_BUS->SDRAM.SDTR_b.WR = BSP_PRV_SDRAM_TWR - 1U; /* set write recovery cycles */
R_BUS->SDRAM.SDTR_b.CL = BSP_PRV_SDRAM_CL; /* set SDRAM column latency cycles */
/** Set row address offset for target SDRAM */
R_BUS->SDRAM.SDADR_b.MXC = BSP_PRV_SDRAM_SDADR_ROW_ADDR_OFFSET - 8U;
R_BUS->SDRAM.SDRFCR_b.REFW = (uint16_t)(BSP_PRV_SDRAM_TRFC - 1U); /* set Auto-Refresh issuing cycle */
R_BUS->SDRAM.SDRFCR_b.RFC = BSP_PRV_SDRAM_REF_CMD_INTERVAL - 1U; /* set Auto-Refresh period */
/** Start Auto-refresh */
R_BUS->SDRAM.SDRFEN_b.RFEN = 1U;
/** Enable SDRAM access */
R_BUS->SDRAM.SDCCR_b.EXENB = 1U;
}
#ifdef BSP_USING_SDRAM
#ifdef RT_USING_MEMHEAP_AS_HEAP
struct rt_memheap system_heap;
#endif
static int SDRAM_Init(void)
{
drv_sdram_init();
LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", 0x68000000, BSP_USING_SDRAM_SIZE, 16);
#ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
rt_memheap_init(&system_heap, "sdram", (void *)0x68000000, BSP_USING_SDRAM_SIZE);
#endif
return RT_EOK;
}
INIT_BOARD_EXPORT(SDRAM_Init);
#endif

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bsp/renesas/ra8d1-vision-board/board/ports/fal_cfg.h Normal file
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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-07-20 Sherman the first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include "hal_data.h"
extern const struct fal_flash_dev _onchip_flash_hp0;
extern const struct fal_flash_dev _onchip_flash_hp1;
extern const struct fal_flash_dev _onchip_flash_hp3;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&_onchip_flash_hp0, \
&_onchip_flash_hp1, \
&_onchip_flash_hp3, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/** partition table, The chip flash partition is defined in "\ra\fsp\src\bsp\mcu\ra6m4\bsp_feature.h".
* More details can be found in the RA6M4 Group User Manual: Hardware section 47 Flash memory.*/
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "boot", "onchip_flash_hp0", 0, BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE, 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_hp1", 0, (BSP_ROM_SIZE_BYTES - BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE), 0}, \
{FAL_PART_MAGIC_WROD, "disk", "onchip_flash_hp3", 0, (BSP_DATA_FLASH_SIZE_BYTES), 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */

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bsp/renesas/ra8d1-vision-board/board/ports/gpio_cfg.h Normal file
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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-01-19 Sherman first version
*/
/* Number of IRQ channels on the device */
#define RA_IRQ_MAX 16
/* PIN to IRQx table */
#define PIN2IRQX_TABLE(pin) \
{ \
switch (pin) \
{ \
case BSP_IO_PORT_04_PIN_00: \
case BSP_IO_PORT_02_PIN_06: \
case BSP_IO_PORT_01_PIN_05: \
return 0; \
case BSP_IO_PORT_02_PIN_05: \
case BSP_IO_PORT_01_PIN_01: \
case BSP_IO_PORT_01_PIN_04: \
return 1; \
case BSP_IO_PORT_02_PIN_03: \
case BSP_IO_PORT_01_PIN_00: \
case BSP_IO_PORT_02_PIN_13: \
return 2; \
case BSP_IO_PORT_02_PIN_02: \
case BSP_IO_PORT_01_PIN_10: \
case BSP_IO_PORT_02_PIN_12: \
return 3; \
case BSP_IO_PORT_04_PIN_02: \
case BSP_IO_PORT_01_PIN_11: \
case BSP_IO_PORT_04_PIN_11: \
return 4; \
case BSP_IO_PORT_04_PIN_01: \
case BSP_IO_PORT_03_PIN_02: \
case BSP_IO_PORT_04_PIN_10: \
return 5; \
case BSP_IO_PORT_03_PIN_01: \
case BSP_IO_PORT_00_PIN_00: \
case BSP_IO_PORT_04_PIN_09: \
return 6; \
case BSP_IO_PORT_00_PIN_01: \
case BSP_IO_PORT_04_PIN_08: \
return 7; \
case BSP_IO_PORT_00_PIN_02: \
case BSP_IO_PORT_03_PIN_05: \
case BSP_IO_PORT_04_PIN_15: \
return 8; \
case BSP_IO_PORT_00_PIN_04: \
case BSP_IO_PORT_03_PIN_04: \
case BSP_IO_PORT_04_PIN_14: \
return 9; \
case BSP_IO_PORT_00_PIN_05: \
case BSP_IO_PORT_07_PIN_09: \
return 10; \
case BSP_IO_PORT_05_PIN_01: \
case BSP_IO_PORT_00_PIN_06: \
case BSP_IO_PORT_07_PIN_08: \
return 11; \
case BSP_IO_PORT_05_PIN_02: \
case BSP_IO_PORT_00_PIN_08: \
return 12; \
case BSP_IO_PORT_00_PIN_15: \
case BSP_IO_PORT_00_PIN_09: \
return 13; \
case BSP_IO_PORT_04_PIN_03: \
case BSP_IO_PORT_05_PIN_12: \
case BSP_IO_PORT_05_PIN_05: \
return 14; \
case BSP_IO_PORT_04_PIN_04: \
case BSP_IO_PORT_05_PIN_11: \
case BSP_IO_PORT_05_PIN_06: \
return 15; \
default : \
return -1; \
} \
}

36
bsp/renesas/ra8d1-vision-board/board/ports/lcd_port.h Normal file
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/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-07-28 liu2guang the first version for STM32F469NI-Discovery.
*/
#ifndef __DRV_LCD_H_
#define __DRV_LCD_H_
#include <rtthread.h>
#include <rtdevice.h>
typedef enum
{
ROTATION_ZERO = 0,
ROTATION_090 = 90,
ROTATION_180 = 180,
ROTATION_270 = 270,
} bsp_rotation;
#define LCD_WIDTH DISPLAY_HSIZE_INPUT0
#define LCD_HEIGHT DISPLAY_VSIZE_INPUT0
#define LCD_BITS_PER_PIXEL DISPLAY_BITS_PER_PIXEL_INPUT1
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
#define LCD_XSTRIDE_PHYS (((DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0 * LCD_BITS_PER_PIXEL + 0x1FF) & 0xFFFFFE00) / LCD_BITS_PER_PIXEL)
#define LCD_NUM_FRAMEBUFFERS (2)
#define LCD_BL_PIN BSP_IO_PORT_04_PIN_04
#endif

13
bsp/renesas/ra8d1-vision-board/board/ports/mipi_lcd/SConscript Normal file
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import os
from building import *
src = []
objs = []
cwd = GetCurrentDir()
CPPPATH = [cwd]
src = Glob('*.c')
objs = DefineGroup('Drivers', src, depend = ['BSP_USING_MIPI_LCD'], CPPPATH = CPPPATH)
Return('objs')

154
bsp/renesas/ra8d1-vision-board/board/ports/mipi_lcd/mipi_config.c Normal file
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#include <rtthread.h>
#if (defined(BSP_USING_LCD)) || (defined(SOC_SERIES_R7FA8M85))
#include <lcd_port.h>
#include "hal_data.h"
#define DRV_DEBUG
#define LOG_TAG "mipi_cfg"
#include <drv_log.h>
#define MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG ((mipi_dsi_cmd_id_t) 0xFE)
#define MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE ((mipi_dsi_cmd_id_t) 0xFD)
typedef struct
{
unsigned char size;
unsigned char buffer[20];
mipi_dsi_cmd_id_t cmd_id;
mipi_dsi_cmd_flag_t flags;
} lcd_table_setting_t;
volatile static bool g_message_sent = false;
volatile static mipi_dsi_phy_status_t g_phy_status;
const lcd_table_setting_t g_lcd_init_focuslcd[] =
{
{6, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x13}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xEF, 0x08}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{6, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x10}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{3, {0xC0, 0x2C, 0x00}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER}, // SCNL = (0x2c + 1) * 8 = 360
// Porch Control
{3, {0xC1, 0x0D, 0x02}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER}, // VFB=0x08 VBF=0x02
// Inversion selection & Frame Rate Control
{3, {0xC2, 0x31, 0x05}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER}, // PCLK= 512 + (0x05 * 16) = 592
{2, {0xCC, 0x10}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER}, // Positive Voltage Gamma Control
{17, {0xB0, 0x0A, 0x14, 0x1B, 0x0D, 0x10, 0x05, 0x07, 0x08, 0x06, 0x22, 0x03, 0x11, 0x10, 0xAD, 0x31, 0x1B}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER}, // Negative Voltage Gamma Control
{17, {0xB1, 0x0A, 0x14, 0x1B, 0x0D, 0x10, 0x05, 0x07, 0x08, 0x06, 0x22, 0x03, 0x11, 0x10, 0xAD, 0x31, 0x1B}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{6, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x11}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xB0, 0x50}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xB1, 0x5E}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xB2, 0x87}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xB3, 0x80}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xB5, 0x47}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xB7, 0x85}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xB8, 0x21}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xC1, 0x78}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xC2, 0x78}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xD0, 0x88}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0xE0, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x1B, 0x02}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{12, {0xE1, 0x08, 0xA0, 0x00, 0x00, 0x07, 0xA0, 0x00, 0x00, 0x00, 0x44, 0x44}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{13, {0xE2, 0x11, 0x11, 0x44, 0x44, 0x75, 0xA0, 0x00, 0x00, 0x74, 0xA0, 0x00, 0x00}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{5, {0xE3, 0x00, 0x00, 0x11, 0x11}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{3, {0xE4, 0x44, 0x44}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{17, {0xE5, 0x0A, 0x71, 0xD8, 0xA0, 0x0C, 0x73, 0xD8, 0xA0, 0x0E, 0x75, 0xD8, 0xA0, 0x10, 0x77, 0xD8, 0xA0}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{5, {0xE6, 0x00, 0x00, 0x11, 0x11}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{3, {0xE7, 0x44, 0x44}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{17, {0xE8, 0x09, 0x70, 0xD8, 0xA0, 0x0B, 0x72, 0xD8, 0xA0, 0x0D, 0x74, 0xD8, 0xA0, 0x0F, 0x76, 0xD8, 0xA0}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{8, {0xEB, 0x02, 0x00, 0xE4, 0xE4, 0x88, 0x00, 0x40}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{3, {0xEC, 0x3C, 0x00}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{17, {0xED, 0xAB, 0x89, 0x76, 0x54, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x20, 0x45, 0x67, 0x98, 0xBA}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{7, {0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{6, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x13}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{3, {0xE8, 0x00, 0x0E}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{3, {0xE8, 0x00, 0x0C}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{3, {0xE8, 0x00, 0x00}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{6, {0xFF, 0x77, 0x01, 0x00, 0x00, 0x00}, MIPI_DSI_CMD_ID_DCS_LONG_WRITE, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x3A, 0x55}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x36, 0x48}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x11, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{120, {0}, MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG, (mipi_dsi_cmd_flag_t)0},
{5, {0}, MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG, (mipi_dsi_cmd_flag_t)0},
{2, {0x29, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{2, {0x21, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER}, //invt on
{2, {0x35, 0x00}, MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM, MIPI_DSI_CMD_FLAG_LOW_POWER},
{0x00, {0}, MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE, (mipi_dsi_cmd_flag_t)0},
};
void mipi_dsi0_callback(mipi_dsi_callback_args_t *p_args)
{
switch (p_args->event)
{
case MIPI_DSI_EVENT_SEQUENCE_0:
{
if (MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED == p_args->tx_status)
{
g_message_sent = true;
}
break;
}
case MIPI_DSI_EVENT_PHY:
{
g_phy_status |= p_args->phy_status;
break;
}
default:
{
break;
}
}
}
static void mipi_dsi_push_table(const lcd_table_setting_t *table)
{
fsp_err_t err = FSP_SUCCESS;
const lcd_table_setting_t *p_entry = table;
while (MIPI_DSI_DISPLAY_CONFIG_DATA_END_OF_TABLE != p_entry->cmd_id)
{
mipi_dsi_cmd_t msg =
{
.channel = 0,
.cmd_id = p_entry->cmd_id,
.flags = p_entry->flags,
.tx_len = p_entry->size,
.p_tx_buffer = p_entry->buffer,
};
if (MIPI_DSI_DISPLAY_CONFIG_DATA_DELAY_FLAG == msg.cmd_id)
{
R_BSP_SoftwareDelay(table->size, BSP_DELAY_UNITS_MILLISECONDS);
}
else
{
g_message_sent = false;
/* Send a command to the peripheral device */
err = R_MIPI_DSI_Command(&g_mipi_dsi0_ctrl, &msg);
if (err != FSP_SUCCESS)
{
LOG_E("R_MIPI_DSI_Command error\n");
}
/* Wait */
while (!g_message_sent);
}
p_entry++;
}
}
void ra8_mipi_lcd_init(void)
{
mipi_dsi_push_table(g_lcd_init_focuslcd);
}
#endif

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#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_FS
#include <dfs_fs.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#ifdef BSP_USING_ONCHIP_FS
#include "fal.h"
#define FS_PARTITION_NAME "disk"
static void sd_mount(void)
{
struct rt_device *flash_dev = fal_blk_device_create(FS_PARTITION_NAME);
if (flash_dev == NULL)
{
rt_kprintf("Can't create a block device on '%s' partition.\n", FS_PARTITION_NAME);
}
else
{
rt_kprintf("Create a block device on the %s partition of flash successful.\n", FS_PARTITION_NAME);
}
if(rt_device_find(FS_PARTITION_NAME) != RT_NULL)
{
dfs_mkfs("elm", FS_PARTITION_NAME);
if (dfs_mount(FS_PARTITION_NAME, "/", "elm", 0, 0) == RT_EOK)
{
rt_kprintf("onchip elm filesystem mount to '/'\n");
}
else
{
rt_kprintf("onchip elm filesystem mount to '/' failed!\n");
}
}
else
{
rt_kprintf("find filesystem portion failed\r\n");
}
}
#elif defined(BSP_USING_SDCARD_FS)
#include <drv_sdhi.h>
/* SD Card hot plug detection pin */
#define SD_CHECK_PIN "p405"
static rt_base_t sd_check_pin = 0;
static void _sdcard_mount(void)
{
rt_device_t device;
device = rt_device_find("sd");
rt_kprintf("rt_device_find %x \r\n", device);
if (device == NULL)
{
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
device = rt_device_find("sd");
}
if (device != RT_NULL)
{
if (dfs_mount("sd", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
static void _sdcard_unmount(void)
{
rt_thread_mdelay(200);
dfs_unmount("/sdcard");
LOG_I("Unmount \"/sdcard\"");
mmcsd_wait_cd_changed(0);
sdcard_change();
mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
}
static void sd_auto_mount(void *parameter)
{
rt_uint8_t re_sd_check_pin = 1;
rt_thread_mdelay(20);
if (!rt_pin_read(sd_check_pin))
{
_sdcard_mount();
}
while (1)
{
rt_thread_mdelay(200);
if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) == 0)
{
_sdcard_mount();
}
if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(sd_check_pin)) != 0)
{
_sdcard_unmount();
}
}
}
static void sd_mount(void)
{
rt_thread_t tid;
sd_check_pin = rt_pin_get(SD_CHECK_PIN);
rt_pin_mode(sd_check_pin, PIN_MODE_INPUT_PULLUP);
tid = rt_thread_create("sd_mount", sd_auto_mount, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
return;
}
}
#else
#include <spi_msd.h>
#include "drv_sci_spi.h"
int sd_mount(void)
{
uint32_t cs_pin = BSP_IO_PORT_10_PIN_05;
rt_hw_sci_spi_device_attach("scpi2", "scpi20", cs_pin);
msd_init("sd0", "scpi20");
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
LOG_I("Mount \"/dev/sd0\" on \"/\"\n");
}
else
{
LOG_W("sd card mount to '/' failed!");
}
return 0;
}
#endif /* BSP_USING_SDCARD_FS */
int mount_init(void)
{
sd_mount();
return RT_EOK;
}
// INIT_ENV_EXPORT(mount_init);
#endif

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#include <rtthread.h>
#include "hal_data.h"
#ifdef BSP_USING_SCI_SPI
rt_weak void sci_spi3_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi4_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi6_callback(spi_callback_args_t *p_args)
{
}
rt_weak void sci_spi7_callback(spi_callback_args_t *p_args)
{
}
#endif

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<vendor>Renesas</vendor>
<name>Project Content</name>
<description>Project content managed by the Renesas Smart Configurator</description>
<url/>
<releases>
<release version="1.0.0"/>
</releases>
<generators>
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="source" name="src/hal_entry.c"/>
</project_files>
</generator>
</generators>
<components generator="Renesas RA Smart Configurator">
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
<files>
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
<file category="include" name="ra/fsp/inc/"/>
<file category="include" name="ra/fsp/inc/api/"/>
<file category="include" name="ra/fsp/inc/instances/"/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
<file category="header" name="ra/board/ra8d1_ek/board.h" path=""/>
<file category="header" name="ra/board/ra8d1_ek/board_ethernet_phy.h" path=""/>
<file category="source" name="ra/board/ra8d1_ek/board_init.c"/>
<file category="header" name="ra/board/ra8d1_ek/board_init.h" path=""/>
<file category="source" name="ra/board/ra8d1_ek/board_leds.c"/>
<file category="header" name="ra/board/ra8d1_ek/board_leds.h" path=""/>
<file category="source" name="ra/board/ra8d1_ek/board_sdram.c"/>
<file category="header" name="ra/board/ra8d1_ek/board_sdram.h" path=""/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_b_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA8D1BH.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_exceptions.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_mcu_info.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra8d1/bsp_override.h" path=""/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
<file category="source" name="ra/fsp/src/r_sci_b_uart/r_sci_b_uart.c"/>
<file category="other" name="ra/fsp/src/r_sci_b_uart/r_sci_b_uart.o"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Build Configuration">
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_b_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Generated Data">
<files>
<file category="include" name="ra_gen/"/>
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
<file category="source" name="ra_gen/common_data.c"/>
<file category="header" name="ra_gen/common_data.h" path=""/>
<file category="source" name="ra_gen/hal_data.c"/>
<file category="header" name="ra_gen/hal_data.h" path=""/>
<file category="source" name="ra_gen/main.c"/>
<file category="source" name="ra_gen/pin_data.c"/>
<file category="other" name="ra_gen/SConscript"/>
<file category="source" name="ra_gen/vector_data.c"/>
<file category="header" name="ra_gen/vector_data.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Linker Script">
<files>
<file category="linkerScript" name="script/fsp.scat"/>
<file category="other" name="script/ac6/fsp_keep.via"/>
</files>
</component>
</components>
</package>

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/* generated memory regions file - do not edit */
#define RAM_START 0x22000000
#define RAM_LENGTH 0xE0000
#define FLASH_START 0x02000000
#define FLASH_LENGTH 0x1F8000
#define DATA_FLASH_START 0x27000000
#define DATA_FLASH_LENGTH 0x3000
#define OPTION_SETTING_START 0x0300A100
#define OPTION_SETTING_LENGTH 0x100
#define OPTION_SETTING_S_START 0x0300A200
#define OPTION_SETTING_S_LENGTH 0x100
#define OPTION_SETTING_DATA_FLASH_S_START 0x27030080
#define OPTION_SETTING_DATA_FLASH_S_LENGTH 0x800
#define ID_CODE_START 0x00000000
#define ID_CODE_LENGTH 0x0
#define SDRAM_START 0x68000000
#define SDRAM_LENGTH 0x8000000
#define QSPI_FLASH_START 0x60000000
#define QSPI_FLASH_LENGTH 0x0
#define OSPI_DEVICE_0_START 0x80000000
#define OSPI_DEVICE_0_LENGTH 0x10000000
#define OSPI_DEVICE_1_START 0x90000000
#define OSPI_DEVICE_1_LENGTH 0x10000000
#define ITCM_START 0x00000000
#define ITCM_LENGTH 0x10000
#define DTCM_START 0x20000000
#define DTCM_LENGTH 0x10000
#define NS_OFFSET_START 0x10000000
#define NS_OFFSET_LENGTH 0x0

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bsp/renesas/ra8d1-vision-board/project.uvprojx Normal file
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26
bsp/renesas/ra8d1-vision-board/ra/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
src += Glob(cwd + '/fsp/src/r_*/*.c')
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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