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bsp/stm32:Separate STM32U5 HAL drivers (#10167)
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@@ -73,6 +73,7 @@ config SOC_SERIES_STM32U5
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bool
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select ARCH_ARM_CORTEX_M33
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select SOC_FAMILY_STM32
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select PKG_USING_STM32U5_HAL_DRIVER
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config SOC_SERIES_STM32H5
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bool
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@@ -1,69 +0,0 @@
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/**
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******************************************************************************
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* @file partition_stm32u5xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32U5xx Device Header File for Initial Setup for
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* Secure / Non-Secure Zones based on CMSIS CORE V5.4.0
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*
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* The file is included in system_stm32u5xx_s.c in secure application.
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* It includes the configuration section that allows to select the
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* STM32U5xx device partitioning file for system core secure attributes
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* and interrupt secure and non-secure assignment.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32u5xx
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* @{
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*/
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#ifndef PARTITION_STM32U5XX_H
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#define PARTITION_STM32U5XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Secure_configuration_section
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* @{
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*/
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#if defined(STM32U575xx)
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#include "partition_stm32u575xx.h"
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#elif defined(STM32U585xx)
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#include "partition_stm32u585xx.h"
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#else
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#error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
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#endif
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* PARTITION_STM32U5XX_H */
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/**
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* @}
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*/
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/**
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* @}
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*/
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@@ -1,233 +0,0 @@
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/**
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******************************************************************************
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* @file stm32u5xx.h
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* @author MCD Application Team
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* @brief CMSIS STM32U5xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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* is using in the C source code, usually in main.c. This file contains:
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* - Configuration section that allows to select:
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* - The STM32U5xx device used in the target application
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* - To use or not the peripheral’s drivers in application code(i.e.
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* code will be based on direct access to peripheral’s registers
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* rather than drivers API), this option is controlled by
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* "#define USE_HAL_DRIVER"
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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||||
*
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* This software is licensed under terms that can be found in the LICENSE file
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||||
* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32u5xx
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* @{
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*/
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#ifndef STM32U5xx_H
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#define STM32U5xx_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/** @addtogroup Library_configuration_section
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* @{
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*/
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/**
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* @brief STM32 Family
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*/
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#if !defined (STM32U5)
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#define STM32U5
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#endif /* STM32U5 */
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/* Uncomment the line below according to the target STM32U5 device used in your
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application
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*/
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#if !defined (STM32U575xx) && !defined (STM32U585xx)
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/* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */
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/* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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In this case, these drivers will not be included and the application code will
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be based on direct access to peripherals registers
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*/
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/*#define USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number 1.0.0
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*/
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#define __STM32U5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32U5_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __STM32U5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32U5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\
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|(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\
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|(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\
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|(__STM32U5_CMSIS_VERSION_RC))
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/**
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* @}
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*/
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/** @addtogroup Device_Included
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* @{
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*/
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#if defined(STM32U575xx)
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#include "stm32u575xx.h"
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#elif defined(STM32U585xx)
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#include "stm32u585xx.h"
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#else
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#error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
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#endif
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/**
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* @}
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*/
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/** @addtogroup Exported_types
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* @{
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*/
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typedef enum
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{
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RESET = 0,
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SET = !RESET
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} FlagStatus, ITStatus;
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typedef enum
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{
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DISABLE = 0,
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ENABLE = !DISABLE
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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{
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SUCCESS = 0,
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ERROR = !SUCCESS
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} ErrorStatus;
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/**
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* @}
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*/
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/** @addtogroup Exported_macros
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* @{
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*/
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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/* Use of CMSIS compiler intrinsics for register exclusive access */
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/* Atomic 32-bit register access macro to set one or several bits */
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#define ATOMIC_SET_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEAR_BIT(REG, BIT) \
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do { \
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uint32_t val; \
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do { \
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val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 32-bit register access macro to clear and set one or several bits */
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#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint32_t val; \
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do { \
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val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
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} while(0)
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/* Atomic 16-bit register access macro to set one or several bits */
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#define ATOMIC_SETH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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} while(0)
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|
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/* Atomic 16-bit register access macro to clear one or several bits */
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#define ATOMIC_CLEARH_BIT(REG, BIT) \
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do { \
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uint16_t val; \
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do { \
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val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
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||||
} while(0)
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|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
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||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
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do { \
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uint16_t val; \
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do { \
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val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
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} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
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||||
#include "stm32u5xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* STM32U5xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -1,109 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32u5xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device System Source File for STM32U5xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32u5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_STM32U5XX_H
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||||
#define SYSTEM_STM32U5XX_H
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||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||
extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable.
|
||||
*
|
||||
* Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable from secure application and return its value
|
||||
* when security is implemented in the system (Non-secure callable function).
|
||||
*
|
||||
* Returns the SystemCoreClock value with current core Clock retrieved from cpu registers.
|
||||
*/
|
||||
extern uint32_t SECURE_SystemCoreClockUpdate(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_STM32U5XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -1,201 +0,0 @@
|
||||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by
|
||||
the copyright owner that is granting the License.
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||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all
|
||||
other entities that control, are controlled by, or are under common
|
||||
control with that entity. For the purposes of this definition,
|
||||
"control" means (i) the power, direct or indirect, to cause the
|
||||
direction or management of such entity, whether by contract or
|
||||
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||
outstanding shares, or (iii) beneficial ownership of such entity.
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||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity
|
||||
exercising permissions granted by this License.
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||||
|
||||
"Source" form shall mean the preferred form for making modifications,
|
||||
including but not limited to software source code, documentation
|
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source, and configuration files.
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||||
"Object" form shall mean any form resulting from mechanical
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transformation or translation of a Source form, including but
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not limited to compiled object code, generated documentation,
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and conversions to other media types.
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"Work" shall mean the work of authorship, whether in Source or
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Object form, made available under the License, as indicated by a
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copyright notice that is included in or attached to the work
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"Derivative Works" shall mean any work, whether in Source or Object
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editorial revisions, annotations, elaborations, or other modifications
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represent, as a whole, an original work of authorship. For the purposes
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of this License, Derivative Works shall not include works that remain
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separable from, or merely link (or bind by name) to the interfaces of,
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the Work and Derivative Works thereof.
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"Contribution" shall mean any work of authorship, including
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the original version of the Work and any modifications or additions
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|
||||
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||||
|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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||||
You may add Your own copyright statement to Your modifications and
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||||
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||||
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|
||||
5. Submission of Contributions. Unless You explicitly state otherwise,
|
||||
any Contribution intentionally submitted for inclusion in the Work
|
||||
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|
||||
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||||
Notwithstanding the above, nothing herein shall supersede or modify
|
||||
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||||
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||||
|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
whether in tort (including negligence), contract, or otherwise,
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||||
unless required by applicable law (such as deliberate and grossly
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||||
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||||
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||||
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|
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||||
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||||
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||||
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9. Accepting Warranty or Additional Liability. While redistributing
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|
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||||
of your accepting any such warranty or additional liability.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
APPENDIX: How to apply the Apache License to your work.
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||||
|
||||
To apply the Apache License to your work, attach the following
|
||||
boilerplate notice, with the fields enclosed by brackets "[]"
|
||||
replaced with your own identifying information. (Don't include
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||||
the brackets!) The text should be enclosed in the appropriate
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comment syntax for the file format. We also recommend that a
|
||||
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|
||||
same "printed page" as the copyright notice for easier
|
||||
identification within third-party archives.
|
||||
|
||||
Copyright [2021] [name of copyright owner]
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
@@ -1,6 +0,0 @@
|
||||
This software component is provided to you as part of a software package and
|
||||
applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the Apache-2.0 license shall apply.
|
||||
You may obtain a copy of the Apache-2.0 at:
|
||||
https://opensource.org/licenses/Apache-2.0
|
||||
@@ -1,42 +0,0 @@
|
||||
# STM32CubeU5 CMSIS Device MCU Component
|
||||
|
||||
|
||||
|
||||
## Overview
|
||||
|
||||
**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
|
||||
|
||||
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
|
||||
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
|
||||
* The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
|
||||
* The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
|
||||
* A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
|
||||
* A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
|
||||
|
||||
Two models of publication are proposed for the STM32Cube embedded software:
|
||||
* The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
|
||||
* The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
|
||||
|
||||
## Description
|
||||
|
||||
This **cmsis_device_u5** MCU component repo is one element of the STM32CubeU5 MCU embedded software package, providing the **cmsis device** part.
|
||||
|
||||
## Release note
|
||||
|
||||
Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_u5/blob/main/Release_Notes.html).
|
||||
|
||||
## Compatibility information
|
||||
|
||||
In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package:
|
||||
|
||||
CMSIS Device U5 | CMSIS Core | Was delivered in the full MCU package
|
||||
--------------- | --------------- | -------------------------------------
|
||||
Tag v1.0.0 | Tag v5.6.0_cm33 | Tag v1.0.0 (and following, if any, till next CMSIS tag)
|
||||
Tag v1.0.1 | Tag v5.6.0_cm33 | Tag v1.0.1 (and following, if any, till next CMSIS tag)
|
||||
|
||||
|
||||
The full **STM32CubeU5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeU5).
|
||||
|
||||
## Troubleshooting
|
||||
|
||||
Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
|
||||
@@ -1,59 +0,0 @@
|
||||
<!DOCTYPE html>
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
||||
<head>
|
||||
<meta charset="utf-8" />
|
||||
<meta name="generator" content="pandoc" />
|
||||
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
||||
<title>Release Notes for STM32U5xx CMSIS</title>
|
||||
<style type="text/css">
|
||||
code{white-space: pre-wrap;}
|
||||
span.smallcaps{font-variant: small-caps;}
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
||||
</style>
|
||||
<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
|
||||
<!--[if lt IE 9]>
|
||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
|
||||
</head>
|
||||
<body>
|
||||
<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
|
||||
<center>
|
||||
<h1 id="release-notes-for-stm32u5xx-cmsis">Release Notes for <mark> STM32U5xx CMSIS </mark></h1>
|
||||
<p>Copyright © 2021 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history"><strong>Update History</strong></h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.0.1 / 01-October-2021</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define</li>
|
||||
<li>Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define</li>
|
||||
<li>Add LSI_STARTUP_TIME define</li>
|
||||
<li>Fix wrong IRQn name in partition_stm32u5xx.h</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 28-June-2021</strong></label>
|
||||
<div>
|
||||
<h2 id="main-changes-1">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,184 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U575xx Device from STM32U5 series
|
||||
** 2048Kbytes ROM
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 768K
|
||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "ROM" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "ROM" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "ROM" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,184 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U575xx Device from STM32U5 series
|
||||
** 2048Kbytes ROM
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20040000, LENGTH = 512K /* Memory is divided. Actual start is 0x20000000 and actual length is 768K */
|
||||
ROM (rx) : ORIGIN = 0x08100000, LENGTH = 1024K /* Memory is divided. Actual start is 0x08000000 and actual length is 2048K */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "ROM" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "ROM" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "ROM" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,192 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U575xx Device from STM32U5 series
|
||||
** 2048Kbytes ROM
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 256K /* Memory is divided. Actual start is 0x30000000 and actual length is 768K */
|
||||
ROM (rx) : ORIGIN = 0x0C000000, LENGTH = 1016K /* Memory is divided. Actual start is 0x0C000000 and actual length is 2048K */
|
||||
ROM_NSC (rx) : ORIGIN = 0x0C0FE000, LENGTH = 8K /* Non-Secure Call-able region */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "ROM" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "ROM" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "ROM" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway stubs */
|
||||
. = ALIGN(8);
|
||||
} >ROM_NSC
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,182 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U575xx Device from STM32U5 series
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 768K
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >RAM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,182 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U575xx Device from STM32U5 series
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20040000, LENGTH = 512K /* Memory is divided. Actual start is 0x20000000 and actual length is 768K */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >RAM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,190 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U575xx Device from STM32U5 series
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 256K - 512 /* Memory is divided. Actual start is 0x30000000 and actual length is 768K */
|
||||
RAM_NSC (xrw) : ORIGIN = 0x3003FE00, LENGTH = 512 /* Non-Secure Call-able region */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >RAM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway stubs */
|
||||
. = ALIGN(8);
|
||||
} >RAM_NSC
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,184 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U585xx Device from STM32U5 series
|
||||
** 2048Kbytes ROM
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 768K
|
||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "ROM" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "ROM" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "ROM" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,184 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U585xx Device from STM32U5 series
|
||||
** 2048Kbytes ROM
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20040000, LENGTH = 512K /* Memory is divided. Actual start is 0x20000000 and actual length is 768K */
|
||||
ROM (rx) : ORIGIN = 0x08100000, LENGTH = 1024K /* Memory is divided. Actual start is 0x08000000 and actual length is 2048K */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "ROM" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "ROM" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "ROM" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,192 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U585xx Device from STM32U5 series
|
||||
** 2048Kbytes ROM
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 256K /* Memory is divided. Actual start is 0x30000000 and actual length is 768K */
|
||||
ROM (rx) : ORIGIN = 0x0C000000, LENGTH = 1016K /* Memory is divided. Actual start is 0x0C000000 and actual length is 2048K */
|
||||
ROM_NSC (rx) : ORIGIN = 0x0C0FE000, LENGTH = 8K /* Non-Secure Call-able region */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "ROM" Rom type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "ROM" Rom type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "ROM" Rom type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway stubs */
|
||||
. = ALIGN(8);
|
||||
} >ROM_NSC
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,182 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U585xx Device from STM32U5 series
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 768K
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >RAM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,182 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U585xx Device from STM32U5 series
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20040000, LENGTH = 512K /* Memory is divided. Actual start is 0x20000000 and actual length is 768K */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >RAM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -1,190 +0,0 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** File : LinkerScript.ld (debug in RAM dedicated)
|
||||
**
|
||||
** Author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** Abstract : Linker script for STM32U585xx Device from STM32U5 series
|
||||
** 768Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
*****************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 256K - 512 /* Memory is divided. Actual start is 0x30000000 and actual length is 768K */
|
||||
RAM_NSC (xrw) : ORIGIN = 0x3003FE00, LENGTH = 512 /* Non-Secure Call-able region */
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(8);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >RAM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM.extab : {
|
||||
. = ALIGN(8);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.ARM : {
|
||||
. = ALIGN(8);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway stubs */
|
||||
. = ALIGN(8);
|
||||
} >RAM_NSC
|
||||
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(8);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,33 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20040000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -1,41 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FDFFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x0C0FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3003FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ROM_NS_start__ = 0x08100000;
|
||||
define symbol __region_ROM_NS_end__ = 0x081FFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_ROM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -1,33 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20040000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20040000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20040000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2007FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20080000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
@@ -1,40 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x30000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x3002DFFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x3002E000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x3002FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30030000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3003FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM_NS_start__ = 0x20040000;
|
||||
define symbol __region_RAM_NS_end__ = 0x200BFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_RAM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -1,32 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -1,32 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08100000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08100000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20040000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -1,41 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x0C000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FDFFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x0C0FE000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x0C0FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3003FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_ROM_NS_start__ = 0x08100000;
|
||||
define symbol __region_ROM_NS_end__ = 0x081FFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_ROM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -1,33 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20040000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x20040000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x20040000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x2007FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20080000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x200BFFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
||||
@@ -1,40 +0,0 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x30000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x30000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x3002DFFF;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_start__ = 0x3002E000;
|
||||
define symbol __ICFEDIT_region_ROM_NSC_end__ = 0x3002FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x30030000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x3003FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __region_RAM_NS_start__ = 0x20040000;
|
||||
define symbol __region_RAM_NS_end__ = 0x200BFFFF;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_NSC_region = mem:[from __ICFEDIT_region_ROM_NSC_start__ to __ICFEDIT_region_ROM_NSC_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define exported symbol __VTOR_TABLE_start = __ICFEDIT_intvec_start__;
|
||||
define exported symbol __VTOR_TABLE_NS_start = __region_RAM_NS_start__;
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_NSC_region { section Veneer$$CMSE };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,362 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32u5xx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32u5xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | MSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB3 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_M | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_N | 8
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_P | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_SRC | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_M | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_Q | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_SRC | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_M | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32u5xx.h"
|
||||
#include <math.h>
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000U;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
|
||||
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
|
||||
const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
|
||||
1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR = RCC_CR_MSISON;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR1 = 0U;
|
||||
RCC->CFGR2 = 0U;
|
||||
RCC->CFGR3 = 0U;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, PLLxON bits */
|
||||
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLL1CFGR = 0U;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= ~(RCC_CR_HSEBYP);
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0U;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
|
||||
float_t fracn1, pllvco;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
|
||||
{
|
||||
/* MSISRANGE from RCC_CSR applies */
|
||||
msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MSIRANGE from RCC_CR applies */
|
||||
msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
|
||||
}
|
||||
|
||||
/*MSI frequency range in HZ*/
|
||||
msirange = MSIRangeTable[msirange];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR1 & RCC_CFGR1_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
|
||||
pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
|
||||
pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x00: /* No clock sent to PLL*/
|
||||
pllvco = (float_t)0U;
|
||||
break;
|
||||
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = ((float_t)msirange / (float_t)pllm);
|
||||
break;
|
||||
}
|
||||
|
||||
pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
|
||||
pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
|
||||
SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -1,210 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32u5xx_ns.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
|
||||
* to be used in non-secure application when the system implements
|
||||
* the TrustZone-M security.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at non-secure startup before
|
||||
* branch to non-secure main program.
|
||||
* This call is made inside the "startup_stm32u5xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
|
||||
* configure the system clock before to branch to main secure program.
|
||||
* Later, when non-secure SystemInit() function is called, in "startup_stm32u5xx.s"
|
||||
* file, the system clock may have been updated from reset value by the main
|
||||
* secure program.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32u5xx.h"
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000U;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
|
||||
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
|
||||
const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
|
||||
1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Nothing done in non-secure */
|
||||
|
||||
/* Non-secure main application shall call SystemCoreClockUpdate() to update */
|
||||
/* the SystemCoreClock variable to insure non-secure application relies on */
|
||||
/* the initial clock reference set by secure application. */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note From the non-secure application, the SystemCoreClock value is
|
||||
* retrieved from the secure domain via a Non-Secure Callable function
|
||||
* since the RCC peripheral may be protected with security attributes
|
||||
* that prevent to compute the SystemCoreClock variable from the RCC
|
||||
* peripheral registers.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* Get the SystemCoreClock value from the secure domain */
|
||||
SystemCoreClock = SECURE_SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -1,399 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32u5xx_s.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
|
||||
* to be used in secure application when the system implements
|
||||
* the TrustZone-M security.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at secure startup just after reset
|
||||
* and before branch to secure main program.
|
||||
* This call is made inside the "startup_stm32u5xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
|
||||
* the variable SystemCoreClock and return
|
||||
* its value to the non-secure calling
|
||||
* application. It must be called whenever
|
||||
* the core clock is changed during program
|
||||
* execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | MSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB3 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_SRC | No clock
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_M | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_N | 8
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_P | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL1_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_SRC | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_M | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_Q | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL2_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_SRC | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_M | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL3_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32u5xx.h"
|
||||
#include "partition_stm32u5xx.h" /* Trustzone-M core secure attributes */
|
||||
#include <math.h>
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
# define CMSE_NS_ENTRY __cmse_nonsecure_entry
|
||||
#else
|
||||
# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000U;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
|
||||
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
|
||||
const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
|
||||
1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32U5xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
|
||||
TZ_SAU_Setup();
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||||
|
||||
SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR = RCC_CR_MSISON;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR1 = 0U;
|
||||
RCC->CFGR2 = 0U;
|
||||
RCC->CFGR3 = 0U;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, PLLxON bits */
|
||||
RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLL1CFGR = 0U;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= ~(RCC_CR_HSEBYP);
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0U;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Depending on secure or non-secure compilation, the adequate RCC peripheral
|
||||
* memory are is accessed thanks to RCC alias defined in stm32u5xxxx.h device file
|
||||
* so either from RCC_S peripheral register mapped memory in secure or from
|
||||
* RCC_NS peripheral register mapped memory in non-secure.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
|
||||
float_t fracn1, pllvco;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
|
||||
{
|
||||
/* MSISRANGE from RCC_CSR applies */
|
||||
msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MSIRANGE from RCC_CR applies */
|
||||
msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
|
||||
}
|
||||
|
||||
/*MSI frequency range in HZ*/
|
||||
msirange = MSIRangeTable[msirange];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR1 & RCC_CFGR1_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
|
||||
pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
|
||||
pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x00: /* No clock sent to PLL*/
|
||||
pllvco = (float_t)0U;
|
||||
break;
|
||||
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = ((float_t)msirange / (float_t)pllm);
|
||||
break;
|
||||
}
|
||||
|
||||
pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
|
||||
pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
|
||||
SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Secure Non-Secure-Callable function to return the current
|
||||
* SystemCoreClock value after SystemCoreClock update.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
* @retval SystemCoreClock value (HCLK)
|
||||
*/
|
||||
CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
return SystemCoreClock;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -1,2 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
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|
||||
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||||
<?xml version="1.0" encoding="UTF-8"?>
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||||
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|
||||
|
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Reference in New Issue
Block a user