mirror of
https://github.com/RT-Thread/rt-thread.git
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[bsp][hpmicro] add HPM5300EVK,HPM5301EVKLITE and HPM6800EVK support & update hpm_sdk
- added new boards: hpm5300evk, hpm5301evklite and hpm6800evk - upgaded hpm_sdk - driver updates and bugfixes - add hpmicro BSPs to CI Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
This commit is contained in:
Fan YANG
Rbb666
@@ -326,6 +326,17 @@ jobs:
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- "bluetrum/ab32vg1-ab-prougen"
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- "bouffalo_lab/bl60x"
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- "bouffalo_lab/bl70x"
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- RTT_BSP: "hpmicro"
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RTT_TOOL_CHAIN: "RISC-V-GCC-RV32"
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SUB_RTT_BSP:
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- "hpmicro/hpm6750evkmini"
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- "hpmicro/hpm6750evk"
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- "hpmicro/hpm6750evk2"
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- "hpmicro/hpm6300evk"
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- "hpmicro/hpm6200evk"
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- "hpmicro/hpm5300evk"
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- "hpmicro/hpm5301evklite"
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- "hpmicro/hpm6800evk"
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- RTT_BSP: "llvm-arm"
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RTT_TOOL_CHAIN: "llvm-arm"
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SUB_RTT_BSP:
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@@ -406,6 +417,14 @@ jobs:
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/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version
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echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV
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- name: Install riscv32-unknown-elf Toolchains
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if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'RISC-V-GCC-RV32' && success() }}
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run: |
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wget -q https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz
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sudo tar zxf riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz -C /opt
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/opt/riscv32-unknown-elf-newlib-multilib/bin/riscv32-unknown-elf-gcc --version
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echo "RTT_EXEC_PATH=/opt/riscv32-unknown-elf-newlib-multilib/bin/" >> $GITHUB_ENV
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- name: Install Riscv-none-embed ToolChains
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if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv-none-embed' && success() }}
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run: |
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@@ -8,4 +8,7 @@ dir_path:
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- hpm6750evk/startup
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- hpm6750evk2/startup
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- hpm6750evkmini/startup
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- hpm5300evk/startup
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- hpm5301evklite/startup
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- hpm6800evk/startup
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- libraries/hpm_sdk
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,21 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "../libraries/Kconfig"
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source "board/Kconfig"
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@@ -0,0 +1,113 @@
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# HPMicro HPM5300EVK BSP(Board Support Package) Introduction
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[中文页](README_zh.md) |
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## Introduction
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This document provides brief introduction of the BSP (board support package) for the HPM5300EVK development board.
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The document consists of the following parts:
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- HPM5300EVK Board Resources Introduction
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- Quickly Getting Started
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- Refreences
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By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
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## Board Resources Introduction
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HPM5300EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc.
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## Peripheral Condition
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Each peripheral supporting condition for this BSP is as follows:
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| **On-board Peripherals** | **Support** | **Note** |
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| ------------------------ | ----------- | ------------------------------------- |
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| USB | √ | |
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| QSPI Flash | √ | |
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| GPIO | √ | |
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| SPI | √ | |
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| I2C | √ | |
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| CAN | √ | |
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| On-Board Debugger | √ | ft2232 |
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## Execution Instruction
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### Quickly Getting Started
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The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
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#### Parpare Environment
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- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
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- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
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- Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
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- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
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- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
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- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
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- Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
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- Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
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- For example: `C:\DevTools\openocd-hpmicro\bin`
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#### Configure and Build project
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Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
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- Configure the project via `menuconfig` in `RT-Thread ENV`
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- Build the project using `scons -jN`, `N` equals to the number of CPU cores
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- Clean the project using `scons -c`
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#### Hardware Connection
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- Switch BOOT pin to 2'b00
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- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
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#### Dowload / Debug
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- Users can download the project via the below command:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
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```
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- Users can debug the project via the below command:
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- Connect debugger via `OpenOCD`:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg
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```
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- Start Debugger via `GDB`:
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```console
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%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
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```
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- In the `gdb shell`, type the following commands:
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```console
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load
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c
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```
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### **Running Results**
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Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
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Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 5.1.0 build Aug 16 2023 18:18:18
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2006 - 2024 Copyright by RT-Thread team
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```
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## **References**
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- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
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- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
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- [HPM5300EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5300evk)
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@@ -0,0 +1,112 @@
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# 先楫 HPM5300EVK BSP(板级支持包)说明
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[English](README.md) |
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## 简介
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本文档为 HPM5300EVK 的 BSP (板级支持包) 说明。
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本文包含如下部分:
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- HPM5300EVK 板级资源介绍
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- 快速上手指南
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- 参考链接
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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## 板级资源介绍
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HPM5300EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。
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开发板外观如下图所示：
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## 板载外设
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本 BSP 目前对外设的支持情况如下:
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| **板载外设** | **支持情况** | **备注** |
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| ------------------------ | ----------- | ------------------------------------- |
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| USB | √ | |
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| QSPI Flash | √ | |
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| GPIO | √ | |
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| SPI | √ | |
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| I2C | √ | |
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| CAN | √ | |
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| 板载调试器 | √ | ft2232 |
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## 使用说明
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### 快速开始
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本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
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#### 准备环境
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- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
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- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
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- 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
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- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
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- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
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- 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
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- 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
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#### 配置和构建工程
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通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
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- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
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- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
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- 通过 `scons -c` 命令清除构建
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#### 硬件连接
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- 将BOOT 引脚拨到2'b00
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- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
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#### 下载 和 调试
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- 通过如下命令完成下载:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
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```
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|
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- 通过如下命令实现调试:
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|
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- 通过 `OpenOCD` 来连接开发板:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg
|
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```
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- 通过 `GDB` 实现调试:
|
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```console
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%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
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```
|
||||
|
||||
- 在`GDB Shell`中使用如下命令来加载和运行:
|
||||
|
||||
```console
|
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load
|
||||
c
|
||||
```
|
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|
||||
### **运行结果**
|
||||
|
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一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
|
||||
|
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配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.1.0 build Aug 16 2023 18:18:18
|
||||
2006 - 2023 Copyright by RT-Thread team
|
||||
```
|
||||
|
||||
## **参考链接**
|
||||
|
||||
- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
|
||||
- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
|
||||
- [HPM5300EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5300evk)
|
||||
@@ -0,0 +1,17 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
ASFLAGS = ' -I' + cwd
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,75 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
AddOption('--run',
|
||||
dest = 'run',
|
||||
type='string',
|
||||
nargs=1,
|
||||
action = 'store',
|
||||
default = "",
|
||||
help = 'Upload or debug application using openocd')
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
env['ASCOM'] = env['ASPPCOM']
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
|
||||
libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
|
||||
else:
|
||||
libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
|
||||
GDB = rtconfig.GDB
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
hpm_library = 'hpm_sdk'
|
||||
rtconfig.BSP_LIBRARY_TYPE = hpm_library
|
||||
|
||||
# include soc
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
|
||||
|
||||
# include components
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
|
||||
|
||||
|
||||
# includes rtt drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,14 @@
|
||||
import rtconfig
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Glob('*.c')
|
||||
|
||||
CPPDEFINES=[]
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2021 hpmicro
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-13 Fan YANG first version
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "rtt_board.h"
|
||||
#include <drv_gpio.h>
|
||||
|
||||
void thread_entry(void *arg);
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
static uint32_t led_thread_arg = 0;
|
||||
rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
|
||||
rt_thread_startup(led_thread);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void thread_entry(void *arg)
|
||||
{
|
||||
rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT);
|
||||
|
||||
while(1){
|
||||
rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,18 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers
|
||||
src = Split("""
|
||||
board.c
|
||||
rtt_board.c
|
||||
pinmux.c
|
||||
fal_flash_port.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D25', 'HPM5361']
|
||||
|
||||
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,79 @@
|
||||
# Copyright (c) 2023 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit 6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3000000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000
|
||||
|
||||
proc init_clock {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x1
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x2
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000800
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000810
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000820
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000830
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event gdb-attach {
|
||||
reset halt
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 8000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/cmsis-dap.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0208 0x020b
|
||||
ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6014
|
||||
|
||||
ftdi_layout_init 0x0018 0x001b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
@@ -0,0 +1,11 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/jlink.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
reset_config srst_only
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0008 0x010b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
set _CHIP hpm5301
|
||||
set _CPUTAPID 0x1000563D
|
||||
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGET0 $_CHIP.cpu0
|
||||
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
|
||||
|
||||
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
targets $_TARGET0
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2022 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef RT_USING_FAL
|
||||
#define NOR_FLASH_DEV_NAME "norflash0"
|
||||
#define NOR_FLASH_MEM_BASE 0x80000000UL
|
||||
#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL
|
||||
|
||||
/* ===================== Flash device Configuration ========================= */
|
||||
extern const struct fal_flash_dev stm32f2_onchip_flash;
|
||||
extern struct fal_flash_dev nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&nor_flash0, \
|
||||
}
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
#endif /* RT_USING_FAL */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2022 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HPM_PINMUX_H
|
||||
#define HPM_PINMUX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void init_xtal_pins(void);
|
||||
void init_py_pins_as_pgpio(void);
|
||||
void init_uart_pins(UART_Type *ptr);
|
||||
void init_uart_pin_as_gpio(UART_Type *ptr);
|
||||
void init_i2c_pins(I2C_Type *ptr);
|
||||
void init_gpio_pins(void);
|
||||
void init_spi_pins(SPI_Type *ptr);
|
||||
void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
|
||||
void init_gptmr_pins(GPTMR_Type *ptr);
|
||||
void init_hall_trgm_pins(void);
|
||||
void init_qei_trgm_pins(void);
|
||||
void init_butn_pins(void);
|
||||
void init_acmp_pins(void);
|
||||
void init_pwm_pins(PWM_Type *ptr);
|
||||
void init_adc_pins(void);
|
||||
void init_adc_bldc_pins(void);
|
||||
void init_adc_qeiv2_pins(void);
|
||||
void init_usb_pins(void);
|
||||
void init_can_pins(MCAN_Type *ptr);
|
||||
void init_dac_pins(DAC_Type *ptr);
|
||||
void init_led_pins_as_gpio(void);
|
||||
void init_led_pins_as_pwm(void);
|
||||
void init_plb_pins(void);
|
||||
void init_qeo_pins(QEO_Type *ptr);
|
||||
void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
|
||||
void init_rdc_pin(void);
|
||||
void init_qeiv2_uvw_pins(QEIV2_Type *ptr);
|
||||
void init_qeiv2_ab_pins(QEIV2_Type *ptr);
|
||||
void init_qeiv2_abz_pins(QEIV2_Type *ptr);
|
||||
void init_opamp_pins(void);
|
||||
void init_lin_transceiver_ctrl_pin(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPM_PINMUX_H */
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Copyright (c) 2023-2024 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "rtt_board.h"
|
||||
#include "hpm_uart_drv.h"
|
||||
#include "hpm_gpio_drv.h"
|
||||
#include "hpm_pmp_drv.h"
|
||||
#include "assert.h"
|
||||
#include "hpm_clock_drv.h"
|
||||
#include "hpm_sysctl_drv.h"
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "hpm_dma_mgr.h"
|
||||
#include "hpm_mchtmr_drv.h"
|
||||
|
||||
extern int rt_hw_uart_init(void);
|
||||
void os_tick_config(void);
|
||||
void rtt_board_init(void);
|
||||
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
rtt_board_init();
|
||||
|
||||
/* Call the RT-Thread Component Board Initialization */
|
||||
rt_components_board_init();
|
||||
}
|
||||
|
||||
void os_tick_config(void)
|
||||
{
|
||||
sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
|
||||
sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
|
||||
mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
|
||||
enable_mchtmr_irq();
|
||||
}
|
||||
|
||||
void rtt_board_init(void)
|
||||
{
|
||||
board_init_clock();
|
||||
board_init_console();
|
||||
board_init_pmp();
|
||||
|
||||
dma_mgr_init();
|
||||
|
||||
/* initialize memory system */
|
||||
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
|
||||
/* Configure the OS Tick */
|
||||
os_tick_config();
|
||||
|
||||
/* Configure the USB pins*/
|
||||
board_init_usb_pins();
|
||||
|
||||
/* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
|
||||
rt_hw_uart_init();
|
||||
|
||||
/* Set console device */
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
}
|
||||
|
||||
void app_init_led_pins(void)
|
||||
{
|
||||
gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
|
||||
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
|
||||
}
|
||||
|
||||
void app_led_write(uint32_t index, bool state)
|
||||
{
|
||||
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
|
||||
}
|
||||
|
||||
void BOARD_LED_write(uint32_t index, bool state)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case 0:
|
||||
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
|
||||
break;
|
||||
default:
|
||||
/* Suppress the toolchain warnings */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while (*str != '\0')
|
||||
{
|
||||
uart_send_byte(BOARD_APP_UART_BASE, *str++);
|
||||
}
|
||||
}
|
||||
|
||||
void app_init_usb_pins(void)
|
||||
{
|
||||
board_init_usb_pins();
|
||||
}
|
||||
|
||||
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
|
||||
{
|
||||
HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
|
||||
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
void rt_hw_cpu_reset(void)
|
||||
{
|
||||
HPM_PPOR->RESET_ENABLE = (1UL << 31);
|
||||
|
||||
HPM_PPOR->SOFTWARE_RESET = 1000U;
|
||||
while(1) {
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2021 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RTT_BOARD_H
|
||||
#define _RTT_BOARD_H
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
#include <drv_gpio.h>
|
||||
|
||||
/* gpio section */
|
||||
#define APP_LED0_PIN_NUM GET_PIN(A, 23)
|
||||
#define APP_LED_ON (1)
|
||||
#define APP_LED_OFF (0)
|
||||
|
||||
/* mchtimer section */
|
||||
#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
|
||||
|
||||
/* CAN section */
|
||||
#define BOARD_CAN_NAME "can0"
|
||||
#define BOARD_CAN_HWFILTER_INDEX (0U)
|
||||
|
||||
/* UART section */
|
||||
#define BOARD_UART_NAME "uart2"
|
||||
#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE
|
||||
|
||||
/* PWM section */
|
||||
#define BOARD_PWM_NAME "pwm0"
|
||||
#define BOARD_PWM_CHANNEL (6)
|
||||
|
||||
#define IRQn_PendSV IRQn_DEBUG0
|
||||
|
||||
/***************************************************************
|
||||
*
|
||||
* RT-Thread related definitions
|
||||
*
|
||||
**************************************************************/
|
||||
extern unsigned int __heap_start__;
|
||||
extern unsigned int __heap_end__;
|
||||
|
||||
#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
|
||||
#define RT_HW_HEAP_END ((void*)&__heap_end__)
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint16_t vdd;
|
||||
uint8_t bus_width;
|
||||
uint8_t drive_strength;
|
||||
}sdxc_io_cfg_t;
|
||||
|
||||
void app_init_led_pins(void);
|
||||
void app_led_write(uint32_t index, bool state);
|
||||
void app_init_usb_pins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* _RTT_BOARD_H */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 366 KiB |
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,109 @@
|
||||
# Copyright 2021-2023 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='risc-v'
|
||||
CPU='hpmicro'
|
||||
CHIP_NAME='HPM5361'
|
||||
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
# Fallback toolchain info
|
||||
FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
|
||||
FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
|
||||
FALLBACK_TOOLCHAIN_VER='2022-04-12'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
if RTT_EXEC_PATH != None:
|
||||
folders = RTT_EXEC_PATH.split(os.sep)
|
||||
# If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
|
||||
if 'arm_gcc' in folders and 'platform' in folders:
|
||||
RTT_EXEC_PATH = ''
|
||||
for path in folders:
|
||||
if path != 'platform':
|
||||
RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
|
||||
else:
|
||||
break
|
||||
RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
|
||||
# Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
|
||||
if 'platform' in folders:
|
||||
os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_RISCV_TOOLCHAIN'):
|
||||
EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
|
||||
else:
|
||||
EXEC_PATH = r'/opt/riscv-gnu-gcc/bin'
|
||||
else:
|
||||
print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
|
||||
|
||||
BUILD = 'flash_debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'riscv32-unknown-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
GDB = PREFIX + 'gdb'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
ARCH_ABI = ' -mcmodel=medlow '
|
||||
DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = CFLAGS
|
||||
LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'ram_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'ram_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'flash_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
elif BUILD == 'flash_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
LFLAGS += ' -T ' + LINKER_FILE
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
CFLAGS = CFLAGS + ' -std=gnu11'
|
||||
@@ -0,0 +1,19 @@
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the startup files
|
||||
|
||||
src = Glob('*.c')
|
||||
|
||||
if rtconfig.PLATFORM == 'gcc':
|
||||
src += [os.path.join('toolchains', 'gcc', 'start.S')]
|
||||
src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D25', rtconfig.CHIP_NAME]
|
||||
|
||||
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
#include "hpm_l1c_drv.h"
|
||||
#include <rtthread.h>
|
||||
|
||||
void system_init(void);
|
||||
|
||||
extern int entry(void);
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern void __libc_fini_array(void);
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
disable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
disable_irq_from_intc();
|
||||
enable_irq_from_intc();
|
||||
enable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
#ifndef CONFIG_NOT_ENABLE_ICACHE
|
||||
l1c_ic_enable();
|
||||
#endif
|
||||
#ifndef CONFIG_NOT_ENABLE_DCACHE
|
||||
l1c_dc_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak)) void c_startup(void)
|
||||
{
|
||||
uint32_t i, size;
|
||||
#ifdef FLASH_XIP
|
||||
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
|
||||
size = __vector_ram_end__ - __vector_ram_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern uint8_t __etext[];
|
||||
extern uint8_t __bss_start__[], __bss_end__[];
|
||||
extern uint8_t __tbss_start__[], __tbss_end__[];
|
||||
extern uint8_t __tdata_start__[], __tdata_end__[];
|
||||
extern uint8_t __data_start__[], __data_end__[];
|
||||
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
|
||||
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
|
||||
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
|
||||
|
||||
/* tbss section */
|
||||
size = __tbss_end__ - __tbss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tbss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* bss section */
|
||||
size = __bss_end__ - __bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* noncacheable bss section */
|
||||
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* tdata section LMA: etext */
|
||||
size = __tdata_end__ - __tdata_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tdata_start__ + i) = *(__etext + i);
|
||||
}
|
||||
|
||||
/* data section LMA: etext */
|
||||
size = __data_end__ - __data_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* ramfunc section LMA: etext + data length */
|
||||
size = __ramfunc_end__ - __ramfunc_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* noncacheable init section LMA: etext + data length + ramfunc length */
|
||||
size = __noncacheable_init_end__ - __noncacheable_init_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((weak)) int main(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
void reset_handler(void)
|
||||
{
|
||||
/**
|
||||
* Disable preemptive interrupt
|
||||
*/
|
||||
HPM_PLIC->FEATURE = 0;
|
||||
/*
|
||||
* Initialize LMA/VMA sections.
|
||||
* Relocation for any sections that need to be copied from LMA to VMA.
|
||||
*/
|
||||
c_startup();
|
||||
|
||||
/* Call platform specific hardware initialization */
|
||||
system_init();
|
||||
|
||||
/* Do global constructors */
|
||||
__libc_init_array();
|
||||
|
||||
|
||||
|
||||
/* Entry function */
|
||||
entry();
|
||||
}
|
||||
|
||||
|
||||
__attribute__((weak)) void _init()
|
||||
{
|
||||
}
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include "cpuport.h"
|
||||
|
||||
.globl rt_hw_do_after_save_above
|
||||
.type rt_hw_do_after_save_above,@function
|
||||
rt_hw_do_after_save_above:
|
||||
addi sp, sp, -4
|
||||
STORE ra, 0 * REGBYTES(sp)
|
||||
|
||||
csrr t1, mcause
|
||||
andi t1, t1, 0x3FF
|
||||
/* get ISR */
|
||||
la t2, trap_entry
|
||||
jalr t2
|
||||
|
||||
LOAD ra, 0 * REGBYTES(sp)
|
||||
addi sp, sp, 4
|
||||
ret
|
||||
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include <rtconfig.h>
|
||||
#include "hpm_csr_regs.h"
|
||||
.section .start, "ax"
|
||||
|
||||
.global _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
/* Initialize global pointer */
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
la tp, __thread_pointer
|
||||
.option pop
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
/* Initialize stack pointer */
|
||||
la t0, _stack
|
||||
mv sp, t0
|
||||
|
||||
#ifdef __nds_execit
|
||||
/* Initialize EXEC.IT table */
|
||||
la t0, _ITB_BASE_
|
||||
csrw uitb, t0
|
||||
#endif
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
/* Disable Vector mode */
|
||||
csrci CSR_MMISC_CTL, 2
|
||||
/* Initialize trap_entry base */
|
||||
la t0, SW_handler
|
||||
csrw mtvec, t0
|
||||
|
||||
|
||||
/* System reset handler */
|
||||
call reset_handler
|
||||
|
||||
/* Infinite loop, if returned accidently */
|
||||
1: j 1b
|
||||
|
||||
.weak nmi_handler
|
||||
nmi_handler:
|
||||
1: j 1b
|
||||
|
||||
.global default_irq_handler
|
||||
.weak default_irq_handler
|
||||
.align 2
|
||||
default_irq_handler:
|
||||
1: j 1b
|
||||
|
||||
.macro IRQ_HANDLER irq
|
||||
.weak default_isr_\irq
|
||||
.set default_isr_\irq, default_irq_handler
|
||||
.long default_isr_\irq
|
||||
.endm
|
||||
|
||||
#include "vectors.S"
|
||||
@@ -0,0 +1,109 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
.section .vector_table, "a"
|
||||
.global __vector_table
|
||||
.align 9
|
||||
|
||||
__vector_table:
|
||||
.weak default_isr_trap
|
||||
.set default_isr_trap, SW_handler
|
||||
.long default_isr_trap
|
||||
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
|
||||
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
|
||||
IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
|
||||
IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
|
||||
IRQ_HANDLER 5 /* GPIO0_X IRQ handler */
|
||||
IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */
|
||||
IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */
|
||||
IRQ_HANDLER 8 /* GPIO1_A IRQ handler */
|
||||
IRQ_HANDLER 9 /* GPIO1_B IRQ handler */
|
||||
IRQ_HANDLER 10 /* GPIO1_C IRQ handler */
|
||||
IRQ_HANDLER 11 /* GPIO1_D IRQ handler */
|
||||
IRQ_HANDLER 12 /* GPIO1_X IRQ handler */
|
||||
IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */
|
||||
IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */
|
||||
IRQ_HANDLER 15 /* ADC0 IRQ handler */
|
||||
IRQ_HANDLER 16 /* ADC1 IRQ handler */
|
||||
IRQ_HANDLER 17 /* ADC2 IRQ handler */
|
||||
IRQ_HANDLER 18 /* SDFM IRQ handler */
|
||||
IRQ_HANDLER 19 /* DAC0 IRQ handler */
|
||||
IRQ_HANDLER 20 /* DAC1 IRQ handler */
|
||||
IRQ_HANDLER 21 /* ACMP[0] IRQ handler */
|
||||
IRQ_HANDLER 22 /* ACMP[1] IRQ handler */
|
||||
IRQ_HANDLER 23 /* ACMP[2] IRQ handler */
|
||||
IRQ_HANDLER 24 /* ACMP[3] IRQ handler */
|
||||
IRQ_HANDLER 25 /* SPI0 IRQ handler */
|
||||
IRQ_HANDLER 26 /* SPI1 IRQ handler */
|
||||
IRQ_HANDLER 27 /* SPI2 IRQ handler */
|
||||
IRQ_HANDLER 28 /* SPI3 IRQ handler */
|
||||
IRQ_HANDLER 29 /* UART0 IRQ handler */
|
||||
IRQ_HANDLER 30 /* UART1 IRQ handler */
|
||||
IRQ_HANDLER 31 /* UART2 IRQ handler */
|
||||
IRQ_HANDLER 32 /* UART3 IRQ handler */
|
||||
IRQ_HANDLER 33 /* UART4 IRQ handler */
|
||||
IRQ_HANDLER 34 /* UART5 IRQ handler */
|
||||
IRQ_HANDLER 35 /* UART6 IRQ handler */
|
||||
IRQ_HANDLER 36 /* UART7 IRQ handler */
|
||||
IRQ_HANDLER 37 /* CAN0 IRQ handler */
|
||||
IRQ_HANDLER 38 /* CAN1 IRQ handler */
|
||||
IRQ_HANDLER 39 /* CAN2 IRQ handler */
|
||||
IRQ_HANDLER 40 /* CAN3 IRQ handler */
|
||||
IRQ_HANDLER 41 /* PTPC IRQ handler */
|
||||
IRQ_HANDLER 42 /* WDG0 IRQ handler */
|
||||
IRQ_HANDLER 43 /* WDG1 IRQ handler */
|
||||
IRQ_HANDLER 44 /* TSNS IRQ handler */
|
||||
IRQ_HANDLER 45 /* MBX0A IRQ handler */
|
||||
IRQ_HANDLER 46 /* MBX0B IRQ handler */
|
||||
IRQ_HANDLER 47 /* MBX1A IRQ handler */
|
||||
IRQ_HANDLER 48 /* MBX1B IRQ handler */
|
||||
IRQ_HANDLER 49 /* GPTMR0 IRQ handler */
|
||||
IRQ_HANDLER 50 /* GPTMR1 IRQ handler */
|
||||
IRQ_HANDLER 51 /* GPTMR2 IRQ handler */
|
||||
IRQ_HANDLER 52 /* GPTMR3 IRQ handler */
|
||||
IRQ_HANDLER 53 /* I2C0 IRQ handler */
|
||||
IRQ_HANDLER 54 /* I2C1 IRQ handler */
|
||||
IRQ_HANDLER 55 /* I2C2 IRQ handler */
|
||||
IRQ_HANDLER 56 /* I2C3 IRQ handler */
|
||||
IRQ_HANDLER 57 /* PWM0 IRQ handler */
|
||||
IRQ_HANDLER 58 /* HALL0 IRQ handler */
|
||||
IRQ_HANDLER 59 /* QEI0 IRQ handler */
|
||||
IRQ_HANDLER 60 /* PWM1 IRQ handler */
|
||||
IRQ_HANDLER 61 /* HALL1 IRQ handler */
|
||||
IRQ_HANDLER 62 /* QEI1 IRQ handler */
|
||||
IRQ_HANDLER 63 /* PWM2 IRQ handler */
|
||||
IRQ_HANDLER 64 /* HALL2 IRQ handler */
|
||||
IRQ_HANDLER 65 /* QEI2 IRQ handler */
|
||||
IRQ_HANDLER 66 /* PWM3 IRQ handler */
|
||||
IRQ_HANDLER 67 /* HALL3 IRQ handler */
|
||||
IRQ_HANDLER 68 /* QEI3 IRQ handler */
|
||||
IRQ_HANDLER 69 /* SDP IRQ handler */
|
||||
IRQ_HANDLER 70 /* XPI0 IRQ handler */
|
||||
IRQ_HANDLER 71 /* XDMA IRQ handler */
|
||||
IRQ_HANDLER 72 /* HDMA IRQ handler */
|
||||
IRQ_HANDLER 73 /* RNG IRQ handler */
|
||||
IRQ_HANDLER 74 /* USB0 IRQ handler */
|
||||
IRQ_HANDLER 75 /* PSEC IRQ handler */
|
||||
IRQ_HANDLER 76 /* PGPIO IRQ handler */
|
||||
IRQ_HANDLER 77 /* PWDG IRQ handler */
|
||||
IRQ_HANDLER 78 /* PTMR IRQ handler */
|
||||
IRQ_HANDLER 79 /* PUART IRQ handler */
|
||||
IRQ_HANDLER 80 /* FUSE IRQ handler */
|
||||
IRQ_HANDLER 81 /* SECMON IRQ handler */
|
||||
IRQ_HANDLER 82 /* RTC IRQ handler */
|
||||
IRQ_HANDLER 83 /* BUTN IRQ handler */
|
||||
IRQ_HANDLER 84 /* BGPIO IRQ handler */
|
||||
IRQ_HANDLER 85 /* BVIO IRQ handler */
|
||||
IRQ_HANDLER 86 /* BROWNOUT IRQ handler */
|
||||
IRQ_HANDLER 87 /* SYSCTL IRQ handler */
|
||||
IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */
|
||||
IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */
|
||||
IRQ_HANDLER 90 /* LIN0 IRQ handler */
|
||||
IRQ_HANDLER 91 /* LIN1 IRQ handler */
|
||||
IRQ_HANDLER 92 /* LIN2 IRQ handler */
|
||||
IRQ_HANDLER 93 /* LIN3 IRQ handler */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('rtconfig')
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
|
||||
objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
|
||||
ASFLAGS = ' -I' + cwd
|
||||
|
||||
Return('objs')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,21 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "../libraries/Kconfig"
|
||||
source "board/Kconfig"
|
||||
@@ -0,0 +1,112 @@
|
||||
# HPMicro HPM5301EVKLITE BSP(Board Support Package) Introduction
|
||||
|
||||
[中文页](README_zh.md) |
|
||||
|
||||
## Introduction
|
||||
|
||||
This document provides brief introduction of the BSP (board support package) for the HPM5301EVKLITE development board.
|
||||
|
||||
The document consists of the following parts:
|
||||
|
||||
- HPM5301EVKLITE Board Resources Introduction
|
||||
- Quickly Getting Started
|
||||
- Refreences
|
||||
|
||||
By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
|
||||
|
||||
## Board Resources Introduction
|
||||
|
||||
HPM5301EVKLITE is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc.
|
||||
|
||||
|
||||
|
||||
## Peripheral Condition
|
||||
|
||||
Each peripheral supporting condition for this BSP is as follows:
|
||||
|
||||
|
||||
| **On-board Peripherals** | **Support** | **Note** |
|
||||
| ------------------------ | ----------- | ------------------------------------- |
|
||||
| USB | √ | |
|
||||
| QSPI Flash | √ | |
|
||||
| GPIO | √ | |
|
||||
| SPI | √ | |
|
||||
| I2C | √ | |
|
||||
| On-Board Debugger | x | 20-PIN Standard JTAG Port |
|
||||
|
||||
|
||||
## Execution Instruction
|
||||
|
||||
### Quickly Getting Started
|
||||
|
||||
The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
|
||||
|
||||
#### Parpare Environment
|
||||
- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
|
||||
- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
|
||||
- Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
|
||||
- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
|
||||
- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
|
||||
- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
|
||||
- Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
|
||||
- Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
|
||||
- For example: `C:\DevTools\openocd-hpmicro\bin`
|
||||
|
||||
#### Configure and Build project
|
||||
|
||||
Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
|
||||
|
||||
- Configure the project via `menuconfig` in `RT-Thread ENV`
|
||||
- Build the project using `scons -jN`, `N` equals to the number of CPU cores
|
||||
- Clean the project using `scons -c`
|
||||
|
||||
#### Hardware Connection
|
||||
|
||||
- Switch BOOT pin to 2'b00
|
||||
- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
|
||||
|
||||
|
||||
#### Dowload / Debug
|
||||
|
||||
- Users can download the project via the below command:
|
||||
```console
|
||||
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
|
||||
```
|
||||
|
||||
- Users can debug the project via the below command:
|
||||
|
||||
- Connect debugger via `OpenOCD`:
|
||||
|
||||
```console
|
||||
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg
|
||||
```
|
||||
- Start Debugger via `GDB`:
|
||||
|
||||
```console
|
||||
%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
|
||||
```
|
||||
- In the `gdb shell`, type the following commands:
|
||||
|
||||
```console
|
||||
load
|
||||
c
|
||||
```
|
||||
|
||||
### **Running Results**
|
||||
|
||||
Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
|
||||
|
||||
Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.1.0 build Aug 16 2023 18:18:18
|
||||
2006 - 2024 Copyright by RT-Thread team
|
||||
```
|
||||
|
||||
## **References**
|
||||
|
||||
- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
|
||||
- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
|
||||
- [HPM5301EVKLITE RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5301evklite)
|
||||
@@ -0,0 +1,111 @@
|
||||
# 先楫 HPM5301EVKLITE BSP(板级支持包)说明
|
||||
|
||||
[English](README.md) |
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为 HPM5301EVKLITE 的 BSP (板级支持包) 说明。
|
||||
|
||||
本文包含如下部分:
|
||||
|
||||
- HPM5301EVKLITE 板级资源介绍
|
||||
- 快速上手指南
|
||||
- 参考链接
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
||||
|
||||
## 板级资源介绍
|
||||
|
||||
HPM5301EVKLITE 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。
|
||||
|
||||
开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
|
||||
## 板载外设
|
||||
|
||||
本 BSP 目前对外设的支持情况如下:
|
||||
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| ------------------------ | ----------- | ------------------------------------- |
|
||||
| USB | √ | |
|
||||
| QSPI Flash | √ | |
|
||||
| GPIO | √ | |
|
||||
| SPI | √ | |
|
||||
| I2C | √ | |
|
||||
| 板载调试器 | x | 20-PIN标准JTAG调试接口 |
|
||||
|
||||
|
||||
## 使用说明
|
||||
|
||||
### 快速开始
|
||||
|
||||
本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
|
||||
|
||||
#### 准备环境
|
||||
- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
|
||||
- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
|
||||
- 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
|
||||
- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
|
||||
- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
|
||||
- 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
|
||||
- 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
|
||||
|
||||
#### 配置和构建工程
|
||||
|
||||
通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
|
||||
|
||||
- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
|
||||
- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
|
||||
- 通过 `scons -c` 命令清除构建
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
- 将BOOT 引脚拨到2'b00
|
||||
- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
|
||||
|
||||
#### 下载 和 调试
|
||||
|
||||
- 通过如下命令完成下载:
|
||||
```console
|
||||
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
|
||||
```
|
||||
|
||||
- 通过如下命令实现调试:
|
||||
|
||||
- 通过 `OpenOCD` 来连接开发板:
|
||||
```console
|
||||
%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5301evklite.cfg
|
||||
```
|
||||
- 通过 `GDB` 实现调试:
|
||||
```console
|
||||
%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
|
||||
```
|
||||
|
||||
- 在`GDB Shell`中使用如下命令来加载和运行:
|
||||
|
||||
```console
|
||||
load
|
||||
c
|
||||
```
|
||||
|
||||
### **运行结果**
|
||||
|
||||
一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
|
||||
|
||||
配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.1.0 build Aug 16 2023 18:18:18
|
||||
2006 - 2023 Copyright by RT-Thread team
|
||||
```
|
||||
|
||||
## **参考链接**
|
||||
|
||||
- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
|
||||
- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
|
||||
- [HPM5301EVKLITE RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5301evklite)
|
||||
@@ -0,0 +1,17 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
ASFLAGS = ' -I' + cwd
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,75 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
AddOption('--run',
|
||||
dest = 'run',
|
||||
type='string',
|
||||
nargs=1,
|
||||
action = 'store',
|
||||
default = "",
|
||||
help = 'Upload or debug application using openocd')
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
|
||||
CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
|
||||
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
env['ASCOM'] = env['ASPPCOM']
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
|
||||
libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
|
||||
else:
|
||||
libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
|
||||
GDB = rtconfig.GDB
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
hpm_library = 'hpm_sdk'
|
||||
rtconfig.BSP_LIBRARY_TYPE = hpm_library
|
||||
|
||||
# include soc
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
|
||||
|
||||
# include components
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
|
||||
|
||||
|
||||
# includes rtt drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,14 @@
|
||||
import rtconfig
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Glob('*.c')
|
||||
|
||||
CPPDEFINES=[]
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2021 hpmicro
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-13 Fan YANG first version
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "rtt_board.h"
|
||||
#include <drv_gpio.h>
|
||||
|
||||
void thread_entry(void *arg);
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
static uint32_t led_thread_arg = 0;
|
||||
rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
|
||||
rt_thread_startup(led_thread);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void thread_entry(void *arg)
|
||||
{
|
||||
rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT);
|
||||
|
||||
while(1){
|
||||
rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,189 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_HPM5000
|
||||
bool
|
||||
select SOC_SERIES_HPM5300
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN if BSP_USING_GPIO
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
|
||||
if BSP_USING_UART
|
||||
menuconfig BSP_USING_UART0
|
||||
bool "Enable UART0 (Debugger)"
|
||||
default y
|
||||
if BSP_USING_UART0
|
||||
config BSP_UART0_RX_USING_DMA
|
||||
bool "Enable UART0 RX DMA"
|
||||
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART0_TX_USING_DMA
|
||||
bool "Enable UART0 TX DMA"
|
||||
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART0_RX_BUFSIZE
|
||||
int "Set UART0 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 128
|
||||
config BSP_UART0_TX_BUFSIZE
|
||||
int "Set UART0 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
menuconfig BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default y
|
||||
if BSP_USING_UART2
|
||||
config BSP_UART2_RX_USING_DMA
|
||||
bool "Enable UART2 RX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default y
|
||||
config BSP_UART2_TX_USING_DMA
|
||||
bool "Enable UART2 TX DMA"
|
||||
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART2_RX_BUFSIZE
|
||||
int "Set UART2 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 1024
|
||||
config BSP_UART2_TX_BUFSIZE
|
||||
int "Set UART2 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
menuconfig BSP_USING_UART6
|
||||
bool "Enable UART6"
|
||||
default n
|
||||
if BSP_USING_UART6
|
||||
config BSP_UART6_RX_USING_DMA
|
||||
bool "Enable UART6 RX DMA"
|
||||
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART6_TX_USING_DMA
|
||||
bool "Enable UART6 TX DMA"
|
||||
depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
config BSP_UART6_RX_BUFSIZE
|
||||
int "Set UART6 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 1024
|
||||
config BSP_UART6_TX_BUFSIZE
|
||||
int "Set UART6 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SPI
|
||||
bool "Enable SPI"
|
||||
default n
|
||||
select RT_USING_SPI if BSP_USING_SPI
|
||||
if BSP_USING_SPI
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1"
|
||||
default y
|
||||
config BSP_USING_SPI2
|
||||
bool "Enable SPI2"
|
||||
default n
|
||||
config BSP_USING_SPI3
|
||||
bool "Enable SPI3"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_GPTMR
|
||||
bool "Enable GPTMR"
|
||||
default n
|
||||
select RT_USING_HWTIMER if BSP_USING_GPTMR
|
||||
if BSP_USING_GPTMR
|
||||
config BSP_USING_GPTMR1
|
||||
bool "Enable GPTMR1"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_I2C
|
||||
bool "Enable I2C"
|
||||
default n
|
||||
if BSP_USING_I2C
|
||||
config BSP_USING_I2C0
|
||||
bool "Enable I2C0"
|
||||
default y
|
||||
if BSP_USING_I2C0
|
||||
config BSP_I2C0_USING_DMA
|
||||
bool "Enable I2C0 DMA"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_I2C3
|
||||
bool "Enable I2C3"
|
||||
default n
|
||||
if BSP_USING_I2C3
|
||||
config BSP_I2C3_USING_DMA
|
||||
bool "Enable I2C3 DMA"
|
||||
default n
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_XPI_FLASH
|
||||
bool "Enable XPI FLASH"
|
||||
default n
|
||||
select RT_USING_FAL if BSP_USING_XPI_FLASH
|
||||
|
||||
menuconfig BSP_USING_USB
|
||||
bool "Enable USB"
|
||||
default n
|
||||
if BSP_USING_USB
|
||||
config BSP_USING_USB_DEVICE
|
||||
bool "Enable USB Device"
|
||||
default n
|
||||
config BSP_USING_USB_HOST
|
||||
bool "Enable USB HOST"
|
||||
select RT_USING_CACHE
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_EWDG
|
||||
bool "Enable EWDG"
|
||||
default n
|
||||
select RT_USING_WDT if BSP_USING_EWDG
|
||||
if BSP_USING_EWDG
|
||||
config BSP_USING_EWDG0
|
||||
bool "Enable EWDG0"
|
||||
default n
|
||||
config BSP_USING_EWDG1
|
||||
bool "Enable EWDG1"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ADC
|
||||
bool "Enable ADC"
|
||||
default n
|
||||
select RT_USING_ADC if BSP_USING_ADC
|
||||
if BSP_USING_ADC
|
||||
menuconfig BSP_USING_ADC16
|
||||
bool "Enable ADC16"
|
||||
default y
|
||||
if BSP_USING_ADC16
|
||||
config BSP_USING_ADC0
|
||||
bool "Enable ADC0"
|
||||
default y
|
||||
endif
|
||||
endif
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,18 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers
|
||||
src = Split("""
|
||||
board.c
|
||||
rtt_board.c
|
||||
pinmux.c
|
||||
fal_flash_port.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D25', 'HPM5361']
|
||||
|
||||
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,79 @@
|
||||
# Copyright (c) 2023 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit 6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3000000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000
|
||||
|
||||
proc init_clock {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x1
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x2
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000800
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000810
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000820
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000830
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event gdb-attach {
|
||||
reset halt
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 8000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/cmsis-dap.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0208 0x020b
|
||||
ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6014
|
||||
|
||||
ftdi_layout_init 0x0018 0x001b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
@@ -0,0 +1,11 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/jlink.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
reset_config srst_only
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0008 0x010b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (c) 2021 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
set _CHIP hpm5301
|
||||
set _CPUTAPID 0x1000563D
|
||||
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGET0 $_CHIP.cpu0
|
||||
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
|
||||
|
||||
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
targets $_TARGET0
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2022 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef RT_USING_FAL
|
||||
#define NOR_FLASH_DEV_NAME "norflash0"
|
||||
#define NOR_FLASH_MEM_BASE 0x80000000UL
|
||||
#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL
|
||||
|
||||
/* ===================== Flash device Configuration ========================= */
|
||||
extern const struct fal_flash_dev stm32f2_onchip_flash;
|
||||
extern struct fal_flash_dev nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&nor_flash0, \
|
||||
}
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
#endif /* RT_USING_FAL */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,177 @@
|
||||
/*
|
||||
* Copyright (c) 2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note:
|
||||
* PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
|
||||
* besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
|
||||
* expected SoC function can be enabled on these IOs.
|
||||
*
|
||||
*/
|
||||
#include "board.h"
|
||||
#include "pinmux.h"
|
||||
|
||||
void init_xtal_pins(void)
|
||||
{
|
||||
/* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */
|
||||
/*
|
||||
* HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
* HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
*/
|
||||
}
|
||||
|
||||
void init_py_pins_as_pgpio(void)
|
||||
{
|
||||
/* Set PY00-PY05 default function to PGPIO */
|
||||
HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PGPIO_Y_00;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PGPIO_Y_01;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_PGPIO_Y_04;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_PGPIO_Y_05;
|
||||
}
|
||||
|
||||
void init_uart_pins(UART_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_UART0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD;
|
||||
} else if (ptr == HPM_UART2) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE;
|
||||
} else if (ptr == HPM_UART3) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_UART3_TXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_UART3_RXD;
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
/* for uart_lin case, need to configure pin as gpio to sent break signal */
|
||||
void init_uart_pin_as_gpio(UART_Type *ptr)
|
||||
{
|
||||
/* pull-up */
|
||||
uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
if (ptr == HPM_UART3) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB15].PAD_CTL = pad_ctl;
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].PAD_CTL = pad_ctl;
|
||||
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPIO_B_15;
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_GPIO_B_14;
|
||||
}
|
||||
}
|
||||
|
||||
void init_i2c_pins(I2C_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_I2C2) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_I2C2_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
} else {
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
void init_gpio_pins(void)
|
||||
{
|
||||
/* configure pad setting: pull enable and pull down, schmitt trigger enable */
|
||||
/* enable schmitt trigger to eliminate jitter of pin used as button */
|
||||
|
||||
/* Button */
|
||||
uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0) | IOC_PAD_PAD_CTL_HYS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PA03].FUNC_CTL = IOC_PA03_FUNC_CTL_GPIO_A_03;
|
||||
HPM_IOC->PAD[IOC_PAD_PA03].PAD_CTL = pad_ctl;
|
||||
}
|
||||
|
||||
void init_spi_pins(SPI_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_SPI1) {
|
||||
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
|
||||
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
|
||||
}
|
||||
}
|
||||
|
||||
void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_SPI1) {
|
||||
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26;
|
||||
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO;
|
||||
HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void init_gptmr_pins(GPTMR_Type *ptr)
|
||||
{
|
||||
(void) ptr;
|
||||
}
|
||||
|
||||
void init_butn_pins(void)
|
||||
{
|
||||
/* configure pad setting: pull enable and pull up, schmitt trigger enable */
|
||||
/* enable schmitt trigger to eliminate jitter of pin used as button */
|
||||
|
||||
/* Button */
|
||||
uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09;
|
||||
HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl;
|
||||
}
|
||||
|
||||
void init_acmp_pins(void)
|
||||
{
|
||||
/* configure to ACMP_COMP_1(ALT16) function */
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ACMP_COMP_1;
|
||||
/* configure to CMP1_INN4 function */
|
||||
HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_adc_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_A: ADC0.11/ADC1.11 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_B: ADC0.1 /ADC1.1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_C: ADC0.2 /ADC1.2 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_D: ADC0.3 /ADC1.3 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.4 /ADC1.4 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* Board ID: ADC0.7 /ADC1.7 */
|
||||
}
|
||||
|
||||
void init_adc_bldc_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */
|
||||
}
|
||||
|
||||
void init_usb_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
|
||||
/* USB0_ID */
|
||||
HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID;
|
||||
/* USB0_OC */
|
||||
HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC;
|
||||
/* USB0_PWR */
|
||||
HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR;
|
||||
|
||||
/* PY port IO needs to configure PIOC as well */
|
||||
HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02;
|
||||
}
|
||||
|
||||
void init_led_pins_as_gpio(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HPM_PINMUX_H
|
||||
#define HPM_PINMUX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void init_xtal_pins(void);
|
||||
void init_py_pins_as_pgpio(void);
|
||||
void init_uart_pins(UART_Type *ptr);
|
||||
void init_i2c_pins(I2C_Type *ptr);
|
||||
void init_gpio_pins(void);
|
||||
void init_spi_pins(SPI_Type *ptr);
|
||||
void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
|
||||
void init_gptmr_pins(GPTMR_Type *ptr);
|
||||
void init_butn_pins(void);
|
||||
void init_acmp_pins(void);
|
||||
void init_adc_pins(void);
|
||||
void init_adc_bldc_pins(void);
|
||||
void init_usb_pins(void);
|
||||
void init_led_pins_as_gpio(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPM_PINMUX_H */
|
||||
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
* Copyright (c) 2023-2024 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "rtt_board.h"
|
||||
#include "hpm_uart_drv.h"
|
||||
#include "hpm_gpio_drv.h"
|
||||
#include "hpm_pmp_drv.h"
|
||||
#include "assert.h"
|
||||
#include "hpm_clock_drv.h"
|
||||
#include "hpm_sysctl_drv.h"
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "hpm_dma_mgr.h"
|
||||
#include "hpm_mchtmr_drv.h"
|
||||
|
||||
extern int rt_hw_uart_init(void);
|
||||
void os_tick_config(void);
|
||||
void rtt_board_init(void);
|
||||
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
rtt_board_init();
|
||||
|
||||
/* Call the RT-Thread Component Board Initialization */
|
||||
rt_components_board_init();
|
||||
}
|
||||
|
||||
void os_tick_config(void)
|
||||
{
|
||||
sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
|
||||
sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
|
||||
mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
|
||||
enable_mchtmr_irq();
|
||||
}
|
||||
|
||||
void rtt_board_init(void)
|
||||
{
|
||||
board_init_clock();
|
||||
board_init_console();
|
||||
board_init_pmp();
|
||||
|
||||
dma_mgr_init();
|
||||
|
||||
/* initialize memory system */
|
||||
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
|
||||
/* Configure the OS Tick */
|
||||
os_tick_config();
|
||||
|
||||
/* Configure the USB pins*/
|
||||
board_init_usb_pins();
|
||||
|
||||
/* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
|
||||
rt_hw_uart_init();
|
||||
|
||||
/* Set console device */
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
}
|
||||
|
||||
void app_init_led_pins(void)
|
||||
{
|
||||
gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
|
||||
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
|
||||
}
|
||||
|
||||
void app_led_write(uint32_t index, bool state)
|
||||
{
|
||||
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
|
||||
}
|
||||
|
||||
|
||||
void BOARD_LED_write(uint32_t index, bool state)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case 0:
|
||||
gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
|
||||
break;
|
||||
default:
|
||||
/* Suppress the toolchain warnings */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while (*str != '\0')
|
||||
{
|
||||
uart_send_byte(BOARD_APP_UART_BASE, *str++);
|
||||
}
|
||||
}
|
||||
|
||||
void app_init_usb_pins(void)
|
||||
{
|
||||
board_init_usb_pins();
|
||||
}
|
||||
|
||||
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
|
||||
{
|
||||
HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
|
||||
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
void rt_hw_cpu_reset(void)
|
||||
{
|
||||
HPM_PPOR->RESET_ENABLE = (1UL << 31);
|
||||
|
||||
HPM_PPOR->SOFTWARE_RESET = 1000U;
|
||||
while(1) {
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* Copyright (c) 2021 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RTT_BOARD_H
|
||||
#define _RTT_BOARD_H
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
#include <drv_gpio.h>
|
||||
|
||||
/* gpio section */
|
||||
#define APP_LED0_PIN_NUM GET_PIN(A, 10)
|
||||
#define APP_LED_ON (1)
|
||||
#define APP_LED_OFF (0)
|
||||
|
||||
|
||||
|
||||
/* mchtimer section */
|
||||
#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
|
||||
|
||||
/* CAN section */
|
||||
#define BOARD_CAN_NAME "can0"
|
||||
#define BOARD_CAN_HWFILTER_INDEX (0U)
|
||||
|
||||
/* UART section */
|
||||
#define BOARD_UART_NAME "uart2"
|
||||
#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE
|
||||
|
||||
#define IRQn_PendSV IRQn_DEBUG0
|
||||
|
||||
/***************************************************************
|
||||
*
|
||||
* RT-Thread related definitions
|
||||
*
|
||||
**************************************************************/
|
||||
extern unsigned int __heap_start__;
|
||||
extern unsigned int __heap_end__;
|
||||
|
||||
#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
|
||||
#define RT_HW_HEAP_END ((void*)&__heap_end__)
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint16_t vdd;
|
||||
uint8_t bus_width;
|
||||
uint8_t drive_strength;
|
||||
}sdxc_io_cfg_t;
|
||||
|
||||
void app_init_led_pins(void);
|
||||
void app_led_write(uint32_t index, bool state);
|
||||
void app_init_usb_pins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* _RTT_BOARD_H */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 363 KiB |
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,109 @@
|
||||
# Copyright 2021-2023 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='risc-v'
|
||||
CPU='hpmicro'
|
||||
CHIP_NAME='HPM5301'
|
||||
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
# Fallback toolchain info
|
||||
FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
|
||||
FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
|
||||
FALLBACK_TOOLCHAIN_VER='2022-04-12'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
if RTT_EXEC_PATH != None:
|
||||
folders = RTT_EXEC_PATH.split(os.sep)
|
||||
# If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
|
||||
if 'arm_gcc' in folders and 'platform' in folders:
|
||||
RTT_EXEC_PATH = ''
|
||||
for path in folders:
|
||||
if path != 'platform':
|
||||
RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
|
||||
else:
|
||||
break
|
||||
RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
|
||||
# Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
|
||||
if 'platform' in folders:
|
||||
os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_RISCV_TOOLCHAIN'):
|
||||
EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
|
||||
else:
|
||||
EXEC_PATH = r'/opt/riscv-gnu-gcc/bin'
|
||||
else:
|
||||
print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
|
||||
|
||||
BUILD = 'flash_debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'riscv32-unknown-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
GDB = PREFIX + 'gdb'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
ARCH_ABI = ' -mcmodel=medlow '
|
||||
DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = CFLAGS
|
||||
LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'ram_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'ram_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'flash_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
elif BUILD == 'flash_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
LFLAGS += ' -T ' + LINKER_FILE
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
CFLAGS = CFLAGS + ' -std=gnu11'
|
||||
@@ -0,0 +1,22 @@
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the startup files
|
||||
|
||||
src = Split('''
|
||||
startup.c
|
||||
trap.c
|
||||
''')
|
||||
|
||||
if rtconfig.PLATFORM == 'gcc':
|
||||
src += [os.path.join('toolchains', 'gcc', 'start.S')]
|
||||
src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D45', rtconfig.CHIP_NAME]
|
||||
|
||||
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
#include "hpm_l1c_drv.h"
|
||||
#include <rtthread.h>
|
||||
|
||||
void system_init(void);
|
||||
|
||||
extern int entry(void);
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern void __libc_fini_array(void);
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
disable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
disable_irq_from_intc();
|
||||
enable_irq_from_intc();
|
||||
enable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
#ifndef CONFIG_NOT_ENABLE_ICACHE
|
||||
l1c_ic_enable();
|
||||
#endif
|
||||
#ifndef CONFIG_NOT_ENABLE_DCACHE
|
||||
l1c_dc_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak)) void c_startup(void)
|
||||
{
|
||||
uint32_t i, size;
|
||||
#ifdef FLASH_XIP
|
||||
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
|
||||
size = __vector_ram_end__ - __vector_ram_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern uint8_t __etext[];
|
||||
extern uint8_t __bss_start__[], __bss_end__[];
|
||||
extern uint8_t __tbss_start__[], __tbss_end__[];
|
||||
extern uint8_t __tdata_start__[], __tdata_end__[];
|
||||
extern uint8_t __data_start__[], __data_end__[];
|
||||
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
|
||||
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
|
||||
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
|
||||
|
||||
/* tbss section */
|
||||
size = __tbss_end__ - __tbss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tbss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* bss section */
|
||||
size = __bss_end__ - __bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* noncacheable bss section */
|
||||
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* tdata section LMA: etext */
|
||||
size = __tdata_end__ - __tdata_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tdata_start__ + i) = *(__etext + i);
|
||||
}
|
||||
|
||||
/* data section LMA: etext */
|
||||
size = __data_end__ - __data_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* ramfunc section LMA: etext + data length */
|
||||
size = __ramfunc_end__ - __ramfunc_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* noncacheable init section LMA: etext + data length + ramfunc length */
|
||||
size = __noncacheable_init_end__ - __noncacheable_init_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((weak)) int main(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
void reset_handler(void)
|
||||
{
|
||||
/**
|
||||
* Disable preemptive interrupt
|
||||
*/
|
||||
HPM_PLIC->FEATURE = 0;
|
||||
/*
|
||||
* Initialize LMA/VMA sections.
|
||||
* Relocation for any sections that need to be copied from LMA to VMA.
|
||||
*/
|
||||
c_startup();
|
||||
|
||||
/* Call platform specific hardware initialization */
|
||||
system_init();
|
||||
|
||||
/* Do global constructors */
|
||||
__libc_init_array();
|
||||
|
||||
|
||||
|
||||
/* Entry function */
|
||||
entry();
|
||||
}
|
||||
|
||||
|
||||
__attribute__((weak)) void _init()
|
||||
{
|
||||
}
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include "cpuport.h"
|
||||
|
||||
.globl rt_hw_do_after_save_above
|
||||
.type rt_hw_do_after_save_above,@function
|
||||
rt_hw_do_after_save_above:
|
||||
addi sp, sp, -4
|
||||
STORE ra, 0 * REGBYTES(sp)
|
||||
|
||||
csrr t1, mcause
|
||||
andi t1, t1, 0x3FF
|
||||
/* get ISR */
|
||||
la t2, trap_entry
|
||||
jalr t2
|
||||
|
||||
LOAD ra, 0 * REGBYTES(sp)
|
||||
addi sp, sp, 4
|
||||
ret
|
||||
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include <rtconfig.h>
|
||||
#include "hpm_csr_regs.h"
|
||||
.section .start, "ax"
|
||||
|
||||
.global _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
/* Initialize global pointer */
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
la tp, __thread_pointer
|
||||
.option pop
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
/* Initialize stack pointer */
|
||||
la t0, _stack
|
||||
mv sp, t0
|
||||
|
||||
#ifdef __nds_execit
|
||||
/* Initialize EXEC.IT table */
|
||||
la t0, _ITB_BASE_
|
||||
csrw uitb, t0
|
||||
#endif
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
/* Disable Vector mode */
|
||||
csrci CSR_MMISC_CTL, 2
|
||||
/* Initialize trap_entry base */
|
||||
la t0, SW_handler
|
||||
csrw mtvec, t0
|
||||
|
||||
|
||||
/* System reset handler */
|
||||
call reset_handler
|
||||
|
||||
/* Infinite loop, if returned accidently */
|
||||
1: j 1b
|
||||
|
||||
.weak nmi_handler
|
||||
nmi_handler:
|
||||
1: j 1b
|
||||
|
||||
.global default_irq_handler
|
||||
.weak default_irq_handler
|
||||
.align 2
|
||||
default_irq_handler:
|
||||
1: j 1b
|
||||
|
||||
.macro IRQ_HANDLER irq
|
||||
.weak default_isr_\irq
|
||||
.set default_isr_\irq, default_irq_handler
|
||||
.long default_isr_\irq
|
||||
.endm
|
||||
|
||||
#include "vectors.S"
|
||||
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
.section .vector_table, "a"
|
||||
.global __vector_table
|
||||
.align 9
|
||||
|
||||
__vector_table:
|
||||
.weak default_isr_trap
|
||||
.set default_isr_trap, SW_handler
|
||||
.long default_isr_trap
|
||||
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
|
||||
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
|
||||
IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
|
||||
IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
|
||||
IRQ_HANDLER 5 /* GPIO0_X IRQ handler */
|
||||
IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */
|
||||
IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */
|
||||
IRQ_HANDLER 8 /* ADC0 IRQ handler */
|
||||
IRQ_HANDLER 9 /* ADC1 IRQ handler */
|
||||
IRQ_HANDLER 10 /* ADC2 IRQ handler */
|
||||
IRQ_HANDLER 11 /* DAC IRQ handler */
|
||||
IRQ_HANDLER 12 /* ACMP[0] IRQ handler */
|
||||
IRQ_HANDLER 13 /* ACMP[1] IRQ handler */
|
||||
IRQ_HANDLER 14 /* SPI0 IRQ handler */
|
||||
IRQ_HANDLER 15 /* SPI1 IRQ handler */
|
||||
IRQ_HANDLER 16 /* SPI2 IRQ handler */
|
||||
IRQ_HANDLER 17 /* SPI3 IRQ handler */
|
||||
IRQ_HANDLER 18 /* UART0 IRQ handler */
|
||||
IRQ_HANDLER 19 /* UART1 IRQ handler */
|
||||
IRQ_HANDLER 20 /* UART2 IRQ handler */
|
||||
IRQ_HANDLER 21 /* UART3 IRQ handler */
|
||||
IRQ_HANDLER 22 /* UART4 IRQ handler */
|
||||
IRQ_HANDLER 23 /* UART5 IRQ handler */
|
||||
IRQ_HANDLER 24 /* UART6 IRQ handler */
|
||||
IRQ_HANDLER 25 /* UART7 IRQ handler */
|
||||
IRQ_HANDLER 26 /* CAN0 IRQ handler */
|
||||
IRQ_HANDLER 27 /* CAN1 IRQ handler */
|
||||
IRQ_HANDLER 28 /* PTPC IRQ handler */
|
||||
IRQ_HANDLER 29 /* WDG0 IRQ handler */
|
||||
IRQ_HANDLER 30 /* WDG1 IRQ handler */
|
||||
IRQ_HANDLER 31 /* TSNS IRQ handler */
|
||||
IRQ_HANDLER 32 /* MBX0A IRQ handler */
|
||||
IRQ_HANDLER 33 /* MBX0B IRQ handler */
|
||||
IRQ_HANDLER 34 /* GPTMR0 IRQ handler */
|
||||
IRQ_HANDLER 35 /* GPTMR1 IRQ handler */
|
||||
IRQ_HANDLER 36 /* GPTMR2 IRQ handler */
|
||||
IRQ_HANDLER 37 /* GPTMR3 IRQ handler */
|
||||
IRQ_HANDLER 38 /* I2C0 IRQ handler */
|
||||
IRQ_HANDLER 39 /* I2C1 IRQ handler */
|
||||
IRQ_HANDLER 40 /* I2C2 IRQ handler */
|
||||
IRQ_HANDLER 41 /* I2C3 IRQ handler */
|
||||
IRQ_HANDLER 42 /* PWM0 IRQ handler */
|
||||
IRQ_HANDLER 43 /* HALL0 IRQ handler */
|
||||
IRQ_HANDLER 44 /* QEI0 IRQ handler */
|
||||
IRQ_HANDLER 45 /* PWM1 IRQ handler */
|
||||
IRQ_HANDLER 46 /* HALL1 IRQ handler */
|
||||
IRQ_HANDLER 47 /* QEI1 IRQ handler */
|
||||
IRQ_HANDLER 48 /* SDP IRQ handler */
|
||||
IRQ_HANDLER 49 /* XPI0 IRQ handler */
|
||||
IRQ_HANDLER 50 /* XPI1 IRQ handler */
|
||||
IRQ_HANDLER 51 /* XDMA IRQ handler */
|
||||
IRQ_HANDLER 52 /* HDMA IRQ handler */
|
||||
IRQ_HANDLER 53 /* DRAM IRQ handler */
|
||||
IRQ_HANDLER 54 /* RNG IRQ handler */
|
||||
IRQ_HANDLER 55 /* I2S0 IRQ handler */
|
||||
IRQ_HANDLER 56 /* I2S1 IRQ handler */
|
||||
IRQ_HANDLER 57 /* DAO IRQ handler */
|
||||
IRQ_HANDLER 58 /* PDM IRQ handler */
|
||||
IRQ_HANDLER 59 /* FFA IRQ handler */
|
||||
IRQ_HANDLER 60 /* NTMR0 IRQ handler */
|
||||
IRQ_HANDLER 61 /* USB0 IRQ handler */
|
||||
IRQ_HANDLER 62 /* ENET0 IRQ handler */
|
||||
IRQ_HANDLER 63 /* SDXC0 IRQ handler */
|
||||
IRQ_HANDLER 64 /* PSEC IRQ handler */
|
||||
IRQ_HANDLER 65 /* PGPIO IRQ handler */
|
||||
IRQ_HANDLER 66 /* PWDG IRQ handler */
|
||||
IRQ_HANDLER 67 /* PTMR IRQ handler */
|
||||
IRQ_HANDLER 68 /* PUART IRQ handler */
|
||||
IRQ_HANDLER 69 /* FUSE IRQ handler */
|
||||
IRQ_HANDLER 70 /* SECMON IRQ handler */
|
||||
IRQ_HANDLER 71 /* RTC IRQ handler */
|
||||
IRQ_HANDLER 72 /* BUTN IRQ handler */
|
||||
IRQ_HANDLER 73 /* BGPIO IRQ handler */
|
||||
IRQ_HANDLER 74 /* BVIO IRQ handler */
|
||||
IRQ_HANDLER 75 /* BROWNOUT IRQ handler */
|
||||
IRQ_HANDLER 76 /* SYSCTL IRQ handler */
|
||||
IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */
|
||||
IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('rtconfig')
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
|
||||
objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
|
||||
ASFLAGS = ' -I' + cwd
|
||||
|
||||
Return('objs')
|
||||
@@ -49,7 +49,7 @@ The BSP support being build via the 'scons' command, below is the steps of compi
|
||||
- Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
|
||||
- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
|
||||
- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
|
||||
- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
|
||||
- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
|
||||
- Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
|
||||
- Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
|
||||
- For example: `C:\DevTools\openocd-hpmicro\bin`
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
|
||||
- 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
|
||||
- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
|
||||
- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
|
||||
- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
|
||||
- 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
|
||||
- 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -135,6 +135,12 @@ SECTIONS
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
} > XPI0
|
||||
|
||||
.rel : {
|
||||
|
||||
@@ -85,6 +85,12 @@ SECTIONS
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
|
||||
@@ -20,8 +20,8 @@ void init_uart_pins(UART_Type *ptr)
|
||||
HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD;
|
||||
/* PY port IO needs to configure PIOC */
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06;
|
||||
} else if (ptr == HPM_UART1) {
|
||||
HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_UART1_TXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_UART1_RXD;
|
||||
@@ -29,11 +29,22 @@ void init_uart_pins(UART_Type *ptr)
|
||||
HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD;
|
||||
} else if (ptr == HPM_PUART) {
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART_RXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART_TXD;
|
||||
} else if (ptr == HPM_UART6) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_UART6_RXD;
|
||||
HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART6_TXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_UART_RXD;
|
||||
HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_UART_TXD;
|
||||
}
|
||||
}
|
||||
|
||||
/* for uart_lin case, need to configure pin as gpio to sent break signal */
|
||||
void init_uart_pin_as_gpio(UART_Type *ptr)
|
||||
{
|
||||
/* pull-up */
|
||||
uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
|
||||
if (ptr == HPM_UART2) {
|
||||
HPM_IOC->PAD[IOC_PAD_PC26].PAD_CTL = pad_ctl;
|
||||
HPM_IOC->PAD[IOC_PAD_PC27].PAD_CTL = pad_ctl;
|
||||
HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_GPIO_C_26;
|
||||
HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_GPIO_C_27;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -43,6 +54,10 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr)
|
||||
/* I2C0 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_GPIO_B_22;
|
||||
HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_GPIO_B_23;
|
||||
} else if (ptr == HPM_I2C3) {
|
||||
/* I2C3 */
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_GPIO_B_20;
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_GPIO_B_21;
|
||||
} else {
|
||||
while (1) {
|
||||
}
|
||||
@@ -59,12 +74,12 @@ void init_i2c_pins(I2C_Type *ptr)
|
||||
HPM_IOC->PAD[IOC_PAD_PB22].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB23].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
} else if (ptr == HPM_I2C3) {
|
||||
HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_I2C3_SCL
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_I2C3_SCL
|
||||
| IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_I2C3_SDA
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_I2C3_SDA
|
||||
| IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
|
||||
} else {
|
||||
while (1) {
|
||||
}
|
||||
@@ -89,7 +104,7 @@ void init_gpio_pins(void)
|
||||
HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ02].PAD_CTL = pad_ctl;
|
||||
/* PZ port IO needs to configure BIOC as well */
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = BIOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02;
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -125,14 +140,17 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
|
||||
|
||||
void init_pins(void)
|
||||
{
|
||||
init_uart_pins(BOARD_CONSOLE_BASE);
|
||||
#ifdef BOARD_CONSOLE_UART_BASE
|
||||
init_uart_pins(BOARD_CONSOLE_UART_BASE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void init_gptmr_pins(GPTMR_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_GPTMR2) {
|
||||
HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0;
|
||||
if (ptr == HPM_GPTMR1) {
|
||||
HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPTMR1_COMP_0;
|
||||
HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPTMR1_COMP_1;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -185,10 +203,8 @@ void init_hrpwm_pins(PWM_Type *ptr)
|
||||
|
||||
void init_adc_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_BUS:ADC0.INA1 */
|
||||
HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.INA12/ADC1.INA8/ADC2.INA4 */
|
||||
HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.INA13/ADC1.INA9/ADC2.INA5 */
|
||||
HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.INA11/ADC1.INA7.ADC2.INA3 */
|
||||
/* ADC0.INA8 */
|
||||
HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_adc_bldc_pins(void)
|
||||
@@ -207,26 +223,13 @@ void init_usb_pins(void)
|
||||
void init_can_pins(MCAN_Type *ptr)
|
||||
{
|
||||
if (ptr == HPM_MCAN0) {
|
||||
HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_CAN0_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_CAN0_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_CAN0_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_MCAN0_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_MCAN0_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_MCAN0_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = 0x10;
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = 0x810;
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = 0x810;
|
||||
}
|
||||
if (ptr == HPM_MCAN3) {
|
||||
HPM_IOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_CAN3_RXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_CAN3_TXD | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_CAN3_STBY | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
|
||||
HPM_IOC->PAD[IOC_PAD_PZ03].PAD_CTL = 0x10;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ04].PAD_CTL = 0x810;
|
||||
HPM_IOC->PAD[IOC_PAD_PZ05].PAD_CTL = 0x810;
|
||||
/* PZ port IO needs to configure BIOC as well */
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05;
|
||||
HPM_IOC->PAD[IOC_PAD_PB19].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB20].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -262,6 +265,19 @@ void init_pla_pins(void)
|
||||
HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_TRGM0_P_05;
|
||||
}
|
||||
|
||||
void init_pla_tamagawa_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_GPIO_B_30;
|
||||
HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PB31_FUNC_CTL_GPIO_B_31;
|
||||
HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_TRGM0_P_01;
|
||||
HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_TRGM0_P_02;
|
||||
HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_TRGM0_P_03;
|
||||
HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_SPI2_CSN;
|
||||
HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI;
|
||||
HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO;
|
||||
HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK;
|
||||
}
|
||||
|
||||
void init_lin_pins(LIN_Type *ptr)
|
||||
{
|
||||
/** enable open drain and pull up */
|
||||
@@ -282,6 +298,13 @@ void init_lin_pins(LIN_Type *ptr)
|
||||
}
|
||||
}
|
||||
|
||||
void init_motor_over_zero_sensorless_adc_pins(void)
|
||||
{
|
||||
HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK;
|
||||
}
|
||||
|
||||
void init_led_pins_as_pwm(void)
|
||||
{
|
||||
/* Blue */
|
||||
@@ -291,3 +314,13 @@ void init_led_pins_as_pwm(void)
|
||||
/* Red */
|
||||
HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM3_P_07;
|
||||
}
|
||||
|
||||
void init_tamper_pins(void)
|
||||
{
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ04].FUNC_CTL = BIOC_PZ04_FUNC_CTL_BATT_TAMPER_04 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_BATT_TAMPER_05;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_BATT_TAMPER_06;
|
||||
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ04].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK;
|
||||
HPM_BIOC->PAD[IOC_PAD_PZ05].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK;
|
||||
}
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
void init_uart_pins(UART_Type *ptr);
|
||||
void init_uart_pin_as_gpio(UART_Type *ptr);
|
||||
void init_i2c_pins(I2C_Type *ptr);
|
||||
void init_gpio_pins(void);
|
||||
void init_spi_pins(SPI_Type *ptr);
|
||||
@@ -37,6 +38,10 @@ void init_trgmux_pins(uint32_t pin);
|
||||
void init_pla_pins(void);
|
||||
void init_lin_pins(LIN_Type *ptr);
|
||||
void init_sdm_pins(void);
|
||||
void init_pla_tamagawa_pins(void);
|
||||
void init_motor_over_zero_sensorless_adc_pins(void);
|
||||
void init_tamper_pins(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
* Copyright (c) 2021-2024 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
@@ -8,18 +8,34 @@
|
||||
#include "rtt_board.h"
|
||||
#include "hpm_uart_drv.h"
|
||||
#include "hpm_gpio_drv.h"
|
||||
#include "hpm_mchtmr_drv.h"
|
||||
#include "hpm_pmp_drv.h"
|
||||
#include "assert.h"
|
||||
#include "hpm_clock_drv.h"
|
||||
#include "hpm_sysctl_drv.h"
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "hpm_dma_manager.h"
|
||||
|
||||
void os_tick_config(void);
|
||||
#include "hpm_dma_mgr.h"
|
||||
#include "hpm_mchtmr_drv.h"
|
||||
|
||||
extern int rt_hw_uart_init(void);
|
||||
void os_tick_config(void);
|
||||
void rtt_board_init(void);
|
||||
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
rtt_board_init();
|
||||
|
||||
/* Call the RT-Thread Component Board Initialization */
|
||||
rt_components_board_init();
|
||||
}
|
||||
|
||||
void os_tick_config(void)
|
||||
{
|
||||
sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
|
||||
sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
|
||||
mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
|
||||
enable_mchtmr_irq();
|
||||
}
|
||||
|
||||
void rtt_board_init(void)
|
||||
{
|
||||
@@ -27,7 +43,7 @@ void rtt_board_init(void)
|
||||
board_init_console();
|
||||
board_init_pmp();
|
||||
|
||||
dma_manager_init();
|
||||
dma_mgr_init();
|
||||
|
||||
/* initialize memory system */
|
||||
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
@@ -67,24 +83,6 @@ void BOARD_LED_write(uint32_t index, bool state)
|
||||
}
|
||||
}
|
||||
|
||||
void os_tick_config(void)
|
||||
{
|
||||
sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
|
||||
sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
|
||||
|
||||
mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
|
||||
|
||||
enable_mchtmr_irq();
|
||||
}
|
||||
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
rtt_board_init();
|
||||
|
||||
/* Call the RT-Thread Component Board Initialization */
|
||||
rt_components_board_init();
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while (*str != '\0')
|
||||
@@ -93,18 +91,16 @@ void rt_hw_console_output(const char *str)
|
||||
}
|
||||
}
|
||||
|
||||
void app_init_usb_pins(void)
|
||||
{
|
||||
board_init_usb_pins();
|
||||
}
|
||||
|
||||
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
|
||||
{
|
||||
HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
|
||||
|
||||
rt_interrupt_enter();
|
||||
rt_tick_increase();
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void rt_hw_us_delay(rt_uint32_t us)
|
||||
{
|
||||
clock_cpu_delay_us(us);
|
||||
}
|
||||
|
||||
void rt_hw_cpu_reset(void)
|
||||
|
||||
@@ -23,6 +23,17 @@
|
||||
|
||||
/* CAN section */
|
||||
#define BOARD_CAN_NAME "can0"
|
||||
#define BOARD_CAN_HWFILTER_INDEX (0U)
|
||||
|
||||
/* UART section */
|
||||
#define BOARD_UART_NAME "uart2"
|
||||
#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE
|
||||
|
||||
/* PWM section */
|
||||
#define BOARD_PWM_NAME "pwm0"
|
||||
#define BOARD_PWM_CHANNEL (0)
|
||||
|
||||
#define IRQn_PendSV IRQn_DEBUG_0
|
||||
|
||||
/***************************************************************
|
||||
*
|
||||
@@ -44,7 +55,7 @@ typedef struct {
|
||||
|
||||
void app_init_led_pins(void);
|
||||
void app_led_write(uint32_t index, bool state);
|
||||
|
||||
void app_init_usb_pins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
|
||||
@@ -81,8 +81,8 @@ if PLATFORM == 'gcc':
|
||||
LFLAGS += ' -O0'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'ram_release':
|
||||
CFLAGS += ' -O2 -Os'
|
||||
LFLAGS += ' -O2 -Os'
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'flash_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
@@ -92,13 +92,13 @@ if PLATFORM == 'gcc':
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
elif BUILD == 'flash_release':
|
||||
CFLAGS += ' -O2 -Os'
|
||||
LFLAGS += ' -O2 -Os'
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
else:
|
||||
CFLAGS += ' -O2 -Os'
|
||||
LFLAGS += ' -O2 -Os'
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
LFLAGS += ' -T ' + LINKER_FILE
|
||||
|
||||
|
||||
@@ -51,7 +51,7 @@ The BSP support being build via the 'scons' command, below is the steps of compi
|
||||
- Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
|
||||
- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
|
||||
- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
|
||||
- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
|
||||
- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
|
||||
- Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
|
||||
- Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
|
||||
- For example: `C:\DevTools\openocd-hpmicro\bin`
|
||||
|
||||
@@ -53,7 +53,7 @@
|
||||
- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
|
||||
- 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
|
||||
- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
|
||||
- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
|
||||
- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
|
||||
- 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
|
||||
- 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -8,7 +8,6 @@ src = Split("""
|
||||
rtt_board.c
|
||||
pinmux.c
|
||||
fal_flash_port.c
|
||||
eth_phy_port.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd]
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -27,6 +27,13 @@ extern struct fal_flash_dev nor_flash0;
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#ifdef CONFIG_WEBNET_FAL_FS
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \
|
||||
}
|
||||
#else
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \
|
||||
@@ -34,6 +41,7 @@ extern struct fal_flash_dev nor_flash0;
|
||||
{FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
#endif /* RT_USING_FAL */
|
||||
|
||||
|
||||
@@ -141,6 +141,12 @@ SECTIONS
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
} > XPI0
|
||||
|
||||
.rel : {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -141,6 +141,12 @@ SECTIONS
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
} > XPI0
|
||||
|
||||
.rel : {
|
||||
|
||||
@@ -87,6 +87,12 @@ SECTIONS
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
@@ -225,10 +231,6 @@ SECTIONS
|
||||
KEEP(*(.backup_sram))
|
||||
} > APB_SRAM
|
||||
|
||||
.fast_ram (NOLOAD) : {
|
||||
KEEP(*(.fast_ram))
|
||||
} > DLM
|
||||
|
||||
.stack(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__stack_base__ = .;
|
||||
|
||||
@@ -87,6 +87,12 @@ SECTIONS
|
||||
|
||||
/* RT-Thread related sections - end */
|
||||
|
||||
/* section information for usbh class */
|
||||
. = ALIGN(8);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
PROVIDE (__etext = .);
|
||||
PROVIDE (_etext = .);
|
||||
PROVIDE (etext = .);
|
||||
@@ -225,10 +231,6 @@ SECTIONS
|
||||
KEEP(*(.backup_sram))
|
||||
} > APB_SRAM
|
||||
|
||||
.fast_ram (NOLOAD) : {
|
||||
KEEP(*(.fast_ram))
|
||||
} > DLM
|
||||
|
||||
.stack(NOLOAD) : {
|
||||
. = ALIGN(8);
|
||||
__stack_base__ = .;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user