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[errno code][-RT_EINVAL] fix that use RT_EINVAL without -

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This commit is contained in:
Meco Man
2023-03-16 00:44:05 -04:00
committed by Man, Jianting (Meco)
parent e4e88b2f3e
commit dfddd79b24
136 changed files with 316 additions and 324 deletions
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2
bsp/Infineon/libraries/HAL_Drivers/drv_pwm.c
View File

@@ -153,7 +153,7 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
return drv_pwm_get(htim, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

2
bsp/airm2m/air105/libraries/rt_drivers/drv_spi.c
View File

@@ -96,7 +96,7 @@ static rt_err_t spi_configure(struct rt_spi_device *device,
RT_ASSERT(configuration != RT_NULL);
rt_uint32_t spi_id = device->bus->parent.user_data;
rt_uint8_t mode = configuration->mode & (RT_SPI_CPHA | RT_SPI_CPOL);
if (configuration->mode & RT_SPI_SLAVE) return RT_EINVAL;
if (configuration->mode & RT_SPI_SLAVE) return -RT_EINVAL;
switch(spi_id)
{
case 0:

2
bsp/airm2m/air32f103/libraries/rt_drivers/drv_hwtimer.c
View File

@@ -171,7 +171,7 @@ static rt_err_t air32_hwtimer_control(struct rt_hwtimer_device *device, rt_uint3
}
else
{
result = RT_EINVAL;
result = -RT_EINVAL;
}
}
break;

22
bsp/allwinner_tina/drivers/drv_clock.c
View File

@@ -211,7 +211,7 @@ rt_err_t cpu_set_pll_clk(int clk)
int p = 0, k = 1, m = 1, n = 0;
if (clk == 0)
return RT_EINVAL;
return -RT_EINVAL;
if (clk > 1152000000)
{
@@ -244,7 +244,7 @@ rt_err_t audio_set_pll_clk(int clk)
int m_temp = _24MHZ_ * 2;
if ((clk > 200000000) || (clk < 20000000))
return RT_EINVAL;
return -RT_EINVAL;
if (clk == 0)
{
@@ -288,7 +288,7 @@ rt_err_t video_set_pll_clk(int clk)
int m_temp = _24MHZ_;
if ((clk > 600000000) || (clk < 30000000))
return RT_EINVAL;
return -RT_EINVAL;
if (clk == 0)
{
@@ -333,7 +333,7 @@ rt_err_t ve_set_pll_clk(int clk)
int m_temp = _24MHZ_;
if ((clk > 600000000) || (clk < 30000000))
return RT_EINVAL;
return -RT_EINVAL;
if (clk == 0)
{
@@ -377,7 +377,7 @@ rt_err_t periph_set_pll_clk(int clk)
int n = 0, k = 0;
if ((clk > 1800000000) || (clk < 200000000) || (clk == 0) || (clk % _24MHZ_ != 0))
return RT_EINVAL;
return -RT_EINVAL;
n = clk / _24MHZ_;
@@ -413,7 +413,7 @@ rt_err_t periph_set_pll_clk(int clk)
rt_err_t cpu_set_clk(int clk)
{
if (clk < _24MHZ_)
return RT_EINVAL;
return -RT_EINVAL;
if (clk == cpu_get_clk())
return RT_EOK;
@@ -446,7 +446,7 @@ rt_err_t bus_gate_clk_enalbe(enum bus_gate bus)
else if (gate_reg == 0x02)
CCU->bus_clk_gating2 |= (0x1 << offset);
else
return RT_EINVAL;
return -RT_EINVAL;
return RT_EOK;
}
@@ -466,7 +466,7 @@ rt_err_t bus_gate_clk_disalbe(enum bus_gate bus)
else if (gate_reg == 0x02)
CCU->bus_clk_gating2 &= ~(0x1 << offset);
else
return RT_EINVAL;
return -RT_EINVAL;
return RT_EOK;
}
@@ -486,7 +486,7 @@ rt_err_t bus_software_reset_disalbe(enum bus_gate bus)
else if (gate_reg == 0x02)
CCU->bus_soft_rst2 |= (0x1 << offset);
else
return RT_EINVAL;
return -RT_EINVAL;
return RT_EOK;
}
@@ -506,7 +506,7 @@ rt_err_t bus_software_reset_enalbe(enum bus_gate bus)
else if (gate_reg == 0x02)
CCU->bus_soft_rst2 &= ~(0x1 << offset);
else
return RT_EINVAL;
return -RT_EINVAL;
return RT_EOK;
}
@@ -519,7 +519,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
if (hz < 0)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if (hz == 0)

10
bsp/allwinner_tina/drivers/drv_gpio.c
View File

@@ -25,7 +25,7 @@
/*********************************************************
** IO
*********************************************************/
int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func)
rt_err_t gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func)
{
rt_uint32_t addr;
rt_uint32_t offset;
@@ -37,7 +37,7 @@ int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func)
if (func & 0x8)
{
LOG_W("[line]:%d There is a warning with parameter input", __LINE__);
return RT_EINVAL;
return -RT_EINVAL;
}
addr = GPIOn_CFG_ADDR(port) + (pin / 8) * 4;
@@ -64,7 +64,7 @@ int gpio_set_value(enum gpio_port port, enum gpio_pin pin, rt_uint8_t value)
if (value & 0xE)
{
LOG_W("[line]:%d There is a warning with parameter input", __LINE__);
return RT_EINVAL;
return -RT_EINVAL;
}
addr = GPIOn_DATA_ADDR(port);
@@ -109,7 +109,7 @@ int gpio_set_pull_mode(enum gpio_port port, enum gpio_pin pin, enum gpio_pull p
if (pull & 0xC)
{
LOG_W("[line]:%d There is a warning with parameter input", __LINE__);
return RT_EINVAL;
return -RT_EINVAL;
}
addr = GPIOn_PUL_ADDR(port);
@@ -137,7 +137,7 @@ int gpio_set_drive_level(enum gpio_port port, enum gpio_pin pin, enum gpio_drv_l
if (level & 0xC)
{
LOG_W("[line]:%d There is a warning with parameter input", __LINE__);
return RT_EINVAL;
return -RT_EINVAL;
}
addr = GPIOn_DRV_ADDR(port);

2
bsp/allwinner_tina/drivers/drv_gpio.h
View File

@@ -212,7 +212,7 @@ typedef struct tina_gpio *tina_gpio_t;
#define GPIO ((tina_gpio_t)GPIO_BASE_ADDR)
int gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func);
rt_err_t gpio_set_func(enum gpio_port port, enum gpio_pin pin, rt_uint8_t func);
int gpio_set_value(enum gpio_port port, enum gpio_pin pin, rt_uint8_t value);
int gpio_get_value(enum gpio_port port, enum gpio_pin pin);
int gpio_set_pull_mode(enum gpio_port port, enum gpio_pin pin, enum gpio_pull pull);

2
bsp/apm32/libraries/Drivers/drv_pwm.c
View File

@@ -583,7 +583,7 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
case PWM_CMD_GET:
return drv_pwm_get(tmr, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

2
bsp/at32/libraries/rt_drivers/drv_pwm.c
View File

@@ -423,7 +423,7 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
case PWM_CMD_GET:
return drv_pwm_get(tmr_x, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

2
bsp/essemi/es32f0654/drivers/drv_hwtimer.c
View File

@@ -305,7 +305,7 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
break;
default:
ret = RT_EINVAL;
ret = -RT_EINVAL;
break;
}

2
bsp/essemi/es32f0654/drivers/drv_pwm.c
View File

@@ -80,7 +80,7 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *
_ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK;
}
else
return RT_EINVAL;
return -RT_EINVAL;
switch (cmd)
{

2
bsp/essemi/es32f369x/drivers/drv_hwtimer.c
View File

@@ -301,7 +301,7 @@ static rt_err_t es32f3_hwtimer_control(rt_hwtimer_t *timer,
break;
default:
ret = RT_EINVAL;
ret = -RT_EINVAL;
break;
}

2
bsp/essemi/es32f369x/drivers/drv_pwm.c
View File

@@ -81,7 +81,7 @@ static rt_err_t es32f3_pwm_control(struct rt_device_pwm *device, int cmd, void *
_ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK;
}
else
return RT_EINVAL;
return -RT_EINVAL;
switch (cmd)
{

2
bsp/ft2004/drivers/drv_sdctrl.c
View File

@@ -243,7 +243,7 @@ static void rthw_sdctrl_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req
if (pkg.cmd->cmd_code == 5 || pkg.cmd->cmd_code == 1)
{
rt_kprintf("cmd_code is not vaild %x \r\n", pkg.cmd->cmd_code);
pkg.cmd->err = RT_EINVAL;
pkg.cmd->err = -RT_EINVAL;
goto _exit;
}

20
bsp/gd32105c-eval/drivers/drv_gpio.c
View File

@@ -325,12 +325,12 @@ static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -364,12 +364,12 @@ static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -397,20 +397,20 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if (enabled == PIN_IRQ_ENABLE)
{
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[hdr_index].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
irqmap = &pin_irq_map[hdr_index];
@@ -427,7 +427,7 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
break;
default:
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
rcu_periph_clock_enable(RCU_AF);
@@ -449,13 +449,13 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
nvic_irq_disable(irqmap->irqno);
}
else
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

20
bsp/gd32107c-eval/drivers/drv_gpio.c
View File

@@ -325,12 +325,12 @@ static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -364,12 +364,12 @@ static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -397,20 +397,20 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if (enabled == PIN_IRQ_ENABLE)
{
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[hdr_index].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
irqmap = &pin_irq_map[hdr_index];
@@ -427,7 +427,7 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
break;
default:
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
rcu_periph_clock_enable(RCU_AF);
@@ -449,13 +449,13 @@ static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
nvic_irq_disable(irqmap->irqno);
}
else
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

20
bsp/gd32303e-eval/drivers/drv_gpio.c
View File

@@ -350,12 +350,12 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -389,12 +389,12 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -422,20 +422,20 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if (enabled == PIN_IRQ_ENABLE)
{
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[hdr_index].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
irqmap = &pin_irq_map[hdr_index];
@@ -452,7 +452,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
break;
default:
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
rcu_periph_clock_enable(RCU_AF);
@@ -474,13 +474,13 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
nvic_irq_disable(irqmap->irqno);
}
else
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

20
bsp/gd32350r-eval/drivers/drv_gpio.c
View File

@@ -272,13 +272,13 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -313,13 +313,13 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -348,7 +348,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if (enabled == PIN_IRQ_ENABLE)
@@ -356,14 +356,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[hdr_index].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
irqmap = &pin_irq_map[hdr_index];
@@ -381,7 +381,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
break;
default:
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
rcu_periph_clock_enable(RCU_CFGCMP);
@@ -403,13 +403,13 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
nvic_irq_disable(irqmap->irqno);
}
else
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

20
bsp/gd32e230k-start/drivers/drv_gpio.c
View File

@@ -245,12 +245,12 @@ rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -284,12 +284,12 @@ rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
@@ -317,20 +317,20 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if (enabled == PIN_IRQ_ENABLE)
{
hdr_index = bit2bitno(index->pin);
if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map))
{
return RT_EINVAL;
return -RT_EINVAL;
}
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[hdr_index].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
irqmap = &pin_irq_map[hdr_index];
@@ -347,7 +347,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
break;
default:
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
//rcu_periph_clock_enable(RCU_AF);
@@ -369,13 +369,13 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
nvic_irq_disable(irqmap->irqno);
}
else
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

2
bsp/hc32/libraries/hc32_drivers/drv_can.c
View File

@@ -160,7 +160,7 @@ static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg
int32_t ret = CAN_Init(p_can_dev->instance, &p_can_dev->ll_init);
if (ret != LL_OK)
{
rt_ret = RT_EINVAL;
rt_ret = -RT_EINVAL;
}
return rt_ret;

2
bsp/hc32/libraries/hc32_drivers/drv_pwm_tmra.c
View File

@@ -209,7 +209,7 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
case PWM_CMD_GET:
return drv_pwm_get(TMRAx, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

2
bsp/hc32/libraries/hc32_drivers/drv_spi.c
View File

@@ -156,7 +156,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat
/* SI/SO pin shared */
if (cfg->mode & RT_SPI_3WIRE)
{
return RT_EINVAL;
return -RT_EINVAL;
}
else
{

2
bsp/hpmicro/libraries/drivers/drv_gpio.c
View File

@@ -297,7 +297,7 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u
}
else
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

2
bsp/hpmicro/libraries/drivers/drv_rtc.c
View File

@@ -86,7 +86,7 @@ static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args)
hpm_rtc_set_timestamp(*(time_t *)args);
break;
default:
err = RT_EINVAL;
err = -RT_EINVAL;
break;
}

2
bsp/hpmicro/libraries/drivers/drv_spi.c
View File

@@ -73,7 +73,7 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co
if (cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32)
{
return RT_EINVAL;
return -RT_EINVAL;
}
spi_master_get_default_timing_config(&timing_config);

2
bsp/hpmicro/libraries/drivers/drv_usb.c
View File

@@ -93,7 +93,7 @@ rt_err_t hpm_usb_control(rt_device_t dev, int cmd, void *args)
break;
default:
ret = RT_EINVAL;
ret = -RT_EINVAL;
break;
}

2
bsp/hpmicro/libraries/drivers/drv_wdt.c
View File

@@ -207,7 +207,7 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args)
hpm_wdog_close(wdt);
break;
default:
ret = RT_EINVAL;
ret = -RT_EINVAL;
break;
}

2
bsp/imxrt/libraries/drivers/drv_gpio.c
View File

@@ -774,7 +774,7 @@ static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt
}
else
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

4
bsp/imxrt/libraries/drivers/drv_pwm.c
View File

@@ -144,7 +144,7 @@ static rt_err_t imxrt_drv_pwm_control(struct rt_device_pwm *device, int cmd, voi
case PWM_CMD_GET:
return imxrt_drv_pwm_get(device, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}
@@ -422,7 +422,7 @@ static rt_err_t imxrt_drv_qtmr_control(struct rt_device_pwm *device, int cmd, vo
case PWM_CMD_GET:
return imxrt_drv_qtmr_get(device, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

2
bsp/imxrt/libraries/drivers/drv_spi.c
View File

@@ -279,7 +279,7 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config
if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32)
{
return RT_EINVAL;
return -RT_EINVAL;
}
LPSPI_MasterGetDefaultConfig(&masterConfig);

4
bsp/imxrt/libraries/drivers/drv_wdt.c
View File

@@ -139,7 +139,7 @@ static rt_err_t imxrt_hp_wdog3_control(rt_watchdog_t *wdt, int cmd, void *args)
}
break;
default:
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;
@@ -274,7 +274,7 @@ static rt_err_t imxrt_hp_wdog_control(rt_watchdog_t *wdt, int cmd, void *args)
}
break;
default:
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

2
bsp/loongson/ls2kdev/drivers/drv_pwm.c
View File

@@ -107,7 +107,7 @@ static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *
rc = RT_ENOSYS;
break;
default:
rc = RT_EINVAL;
rc = -RT_EINVAL;
break;
}
return rc;

2
bsp/lpc55sxx/Libraries/drivers/drv_pwm.c
View File

@@ -239,7 +239,7 @@ static rt_err_t lpc_drv_pwm_control(struct rt_device_pwm *device, int cmd, void
case PWM_CMD_GET:
return lpc_drv_pwm_get(device, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

2
bsp/lpc55sxx/Libraries/drivers/drv_rtc.c
View File

@@ -116,7 +116,7 @@ static rt_err_t lpc_rtc_control(rt_device_t dev, int cmd, void *args)
break;
default:
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

2
bsp/lpc55sxx/Libraries/drivers/drv_wdt.c
View File

@@ -204,7 +204,7 @@ static rt_err_t lpc_wwdt_control(rt_watchdog_t *wdt, int cmd, void *args)
}
break;
default:
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

4
bsp/n32/libraries/n32_drivers/drv_adc.c
View File

@@ -92,7 +92,7 @@ static rt_err_t n32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
{
if (channel > ADC_CH_18)
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;
}
@@ -104,7 +104,7 @@ static rt_err_t n32_adc_convert(struct rt_adc_device *device, rt_uint32_t channe
if (channel > ADC_CH_18)
{
return RT_EINVAL;
return -RT_EINVAL;
}
config = (struct n32_adc_config *)(device->parent.user_data);

2
bsp/n32/libraries/n32_drivers/drv_wdt.c
View File

@@ -151,7 +151,7 @@ static rt_err_t n32_wdt_control(rt_watchdog_t *wdt, int cmd, void *args)
break;
default:
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

2
bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c
View File

@@ -314,7 +314,7 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
case PWM_CMD_GET:
return drv_pwm_get(pwm_dev, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

6
bsp/nrf5x/libraries/drivers/drv_gpio.c
View File

@@ -356,7 +356,7 @@ const static struct rt_pin_ops _nrf5x_pin_ops =
RT_NULL,
};
int rt_hw_pin_init(void)
rt_err_t rt_hw_pin_init(void)
{
nrfx_err_t err_code;
@@ -366,11 +366,11 @@ int rt_hw_pin_init(void)
switch(err_code)
{
case NRFX_ERROR_INVALID_STATE:
return RT_EINVAL;
return -RT_EINVAL;
case NRFX_SUCCESS:
return RT_EOK;
default:
return RT_ERROR;;
return -RT_ERROR;;
}
}

12
bsp/nrf5x/libraries/drivers/drv_gpio.h
View File

@@ -35,18 +35,10 @@ struct pin_index
{
int index;
NRF_GPIO_Type *gpio;//NRF_P0 or NRF_P1
uint32_t pin;
rt_base_t pin;
};
static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value);
static int nrf5x_pin_read(rt_device_t dev, rt_base_t pin);
static void nrf5x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode);
static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args);
static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin);
static rt_err_t nrf5x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled);
int rt_hw_pin_init(void);
rt_err_t rt_hw_pin_init(void);
#endif /* __DRV_GPIO_H__ */

2
bsp/nrf5x/libraries/drivers/drv_pwm.c
View File

@@ -212,7 +212,7 @@ static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg
case PWM_CMD_GET:
return drv_pwm_get(p_mcu, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

4
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_adc.c
View File

@@ -66,7 +66,7 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
{
if (channel > ADC_CHANNEL_17)
{
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;
}
@@ -78,7 +78,7 @@ static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t chann
if (channel > ADC_CHANNEL_17)
{
return RT_EINVAL;
return -RT_EINVAL;
}
config = (struct gd32_adc_config *)(device->parent.user_data);

4
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c
View File

@@ -379,7 +379,7 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
break;
default:
rt_hw_interrupt_enable(level);
return RT_EINVAL;
return -RT_EINVAL;
}
/* connect EXTI line to GPIO pin */
@@ -404,7 +404,7 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
{

12
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_pwm.c
View File

@@ -71,7 +71,7 @@ static rt_err_t gd32_pwm_enable(struct rt_device_pwm *device, struct rt_pwm_conf
if (configuration->channel > GD32_MAX_PWM_CHANNELS)
{
return RT_EINVAL;
return -RT_EINVAL;
}
if (!enable)
{
@@ -143,12 +143,12 @@ static rt_err_t gd32_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configu
if (configuration->channel > GD32_MAX_PWM_CHANNELS)
{
LOG_I("max channel supported is %d\n", GD32_MAX_PWM_CHANNELS);
return RT_EINVAL;
return -RT_EINVAL;
}
if (configuration->period < configuration->pulse)
{
LOG_I("period should > pulse \n");
return RT_EINVAL;
return -RT_EINVAL;
}
pwmclk = gd32_get_pwm_clk(config->periph);
@@ -157,12 +157,12 @@ static rt_err_t gd32_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configu
period_cmp = (uint64_t)(1000000000 / pwmclk) * 10;
if (configuration->period < period_cmp)
{
return RT_EINVAL;
return -RT_EINVAL;
}
period_cmp = (uint64_t)(1000000000 / (pwmclk / 65536 / 4)) * 65536;
if (configuration->period > period_cmp)
{
return RT_EINVAL;
return -RT_EINVAL;
}
period_cmp = (uint64_t) pwmclk * configuration->period / 1000000000;
@@ -252,7 +252,7 @@ static rt_err_t gd32_pwm_control(struct rt_device_pwm *device, int cmd, void *ar
case PWM_CMD_GET:
return gd32_pwm_get(device, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

2
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_rtc.c
View File

@@ -127,7 +127,7 @@ static rt_err_t gd32_rtc_control(rt_device_t dev, int cmd, void *args)
break;
default:
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

2
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_wdt.c
View File

@@ -124,7 +124,7 @@ static rt_err_t gd32_wdog_control(rt_watchdog_t *wdt, int cmd, void *args)
}
break;
default:
return RT_EINVAL;
return -RT_EINVAL;
}
return RT_EOK;

2
bsp/nuvoton/libraries/m031/rtt_port/drv_bpwm.c
View File

@@ -205,7 +205,7 @@ static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg
case PWM_CMD_GET:
return nu_bpwm_get(device, configuration);
default:
return RT_EINVAL;
return -RT_EINVAL;
}
}

14
bsp/nuvoton/libraries/m031/rtt_port/drv_pdma.c
View File

@@ -284,7 +284,7 @@ exit_pdma_channel_terminate:
static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us)
{
rt_err_t ret = RT_EINVAL;
rt_err_t ret = -RT_EINVAL;
if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
goto exit_nu_pdma_timeout_set;
@@ -355,7 +355,7 @@ exit_nu_pdma_channel_allocate:
rt_err_t nu_pdma_channel_free(int i32ChannID)
{
rt_err_t ret = RT_EINVAL;
rt_err_t ret = -RT_EINVAL;
if (! nu_pdma_inited)
goto exit_nu_pdma_channel_free;
@@ -373,7 +373,7 @@ exit_nu_pdma_channel_free:
rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_cb_handler_t pfnHandler, void *pvUserData, uint32_t u32EventFilter)
{
rt_err_t ret = RT_EINVAL;
rt_err_t ret = -RT_EINVAL;
if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
goto exit_nu_pdma_callback_register;
@@ -461,7 +461,7 @@ exit_nu_pdma_channel_memctrl_get:
rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl)
{
rt_err_t ret = RT_EINVAL;
rt_err_t ret = -RT_EINVAL;
nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos];
@@ -518,7 +518,7 @@ rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u3
uint32_t u32SrcCtl = 0;
uint32_t u32DstCtl = 0;
rt_err_t ret = RT_EINVAL;
rt_err_t ret = -RT_EINVAL;
if (!dma_desc)
goto exit_nu_pdma_desc_setup;
@@ -714,7 +714,7 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, uint32_t u32IdleTimeout_us)
{
rt_err_t ret = RT_EINVAL;
rt_err_t ret = -RT_EINVAL;
nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
@@ -744,7 +744,7 @@ exit_nu_pdma_transfer:
rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
{
rt_err_t ret = RT_EINVAL;
rt_err_t ret = -RT_EINVAL;
nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
if (!head)

2
bsp/nuvoton/libraries/m031/rtt_port/drv_qspi.c
View File

@@ -111,7 +111,7 @@ static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device,
configuration->data_width == 24 ||
configuration->data_width == 32))
{
ret = RT_EINVAL;
ret = -RT_EINVAL;
goto exit_nu_qspi_bus_configure;
}

2
bsp/nuvoton/libraries/m031/rtt_port/drv_spi.c
View File

@@ -130,7 +130,7 @@ static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device,
configuration->data_width == 24 ||
configuration->data_width == 32))
{
ret = RT_EINVAL;
ret = -RT_EINVAL;
goto exit_nu_spi_bus_configure;
}

2
bsp/nuvoton/libraries/m031/rtt_port/drv_timer.c
View File

@@ -191,7 +191,7 @@ static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg
break;
default:
ret = RT_EINVAL;
ret = -RT_EINVAL;
break;
}

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