[BSP][HC32]add lckfb-hc32f4a0-lqfp100 (#9119)

* -以ev_hc32f4a0_lqfp176为模板进行修改 * -修改对应引脚 * -更新readme * -update readme * -添加 lckfb-hc32f4a0-lqfp100
2026-03-28 02:03:20 +08:00 · 2024-06-28 23:41:31 +08:00
parent 099e24951c
commit df715100f2
63 changed files with 22486 additions and 0 deletions
--- a/.github/workflows/bsp_buildings.yml
+++ b/.github/workflows/bsp_buildings.yml
@@ -87,6 +87,7 @@ jobs:
                - "hc32/ev_hc32f448_lqfp80"
                - "hc32/ev_hc32f460_lqfp100_v2"
                - "hc32/ev_hc32f472_lqfp100"
+                - "hc32/lckfb-hc32f4a0-lqfp100"
                - "hc32l196"
                - "mm32/mm32f3270-100ask-pitaya"
                - "mm32f327x"
--- a/bsp/hc32/README.md
+++ b/bsp/hc32/README.md
@@ -11,6 +11,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
 | [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
 | [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 |
 | [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 |
+| [lckfb-hc32f4a0-lqfp100](lckfb-hc32f4a0-lqfp100) | 立创开发板 天空星-HC32F4A0PITB |
 | **M1 系列** |  |
 | **M4 系列** |  |

--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.cproject
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.cproject
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.gitignore
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.gitignore
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.project
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.project
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources>
+    <link>
+      <name>rt-thread</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/components</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/include</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/libcpu</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/src</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32</name>
+      <type>2</type>
+      <locationURI>virtual:/virtual</locationURI>
+    </link>
+    <link>
+      <name>rt-thread/bsp/hc32/libraries</name>
+      <type>2</type>
+      <locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
+    </link>
+  </linkedResources>
+</projectDescription>
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/Kconfig
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/Kconfig
@@ -0,0 +1,12 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+RTT_DIR := ../../..
+
+PKGS_DIR := packages
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+rsource "../libraries/Kconfig"
+rsource "board/Kconfig"
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/README.md
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/README.md
@@ -0,0 +1,97 @@
+# lckfb-hc32f4a0-lqfp100立创天空星开发板BSP说明
+
+## 简介
+
+该开发板是由立创开发板精心打造的一款高性价比的开发工具，**软硬件全开源**。设计上充分考虑了与多种100脚封装的单片机的兼容性。这种设计使得它不仅适用于特定的芯片，还能够适配市场上多种不同厂家生产的100脚微控制器，极大地提高了适用范围和灵活性。该BSP适配立创梁山派·天空星开发板的主控芯片为**HC32F4A0PITB**。
+
+为了最大限度的方便开发者和爱好者，该核心板通过排针将所有可用的IO（输入/输出）引脚都引出，这样大家就可以轻松地连接各种外部模块和设备，无需进行复杂的焊接工作。这一特点特别适合那些需要快速原型制作和迭代的场合，如学生电子竞赛、创客活动以及个人DIY项目。
+
+此外，这款核心板的设计考虑到了大家在电子竞赛中对于稳定性和可靠性的需求，以及在小型项目开发中对低成本的追求。具体请看硬件设计手册。
+
+![[(lckfb.com)](https://lckfb.com/project/detail/lckfb-lspi-skystar-stm32f407vet6-lite?param=baseInfo)](figures/board.png)
+
+## 资料罗列：
+
+* [硬件开源地址](https://oshwhub.com/li-chuang-kai-fa-ban/li-chuang-liang-shan-pai-tian-kong-xing-kai-fa-ban)
+* [硬件文档](https://lceda001.feishu.cn/wiki/D4cqwUkiTi6723knO2cczSThnYb)
+* [入门手册](https://lceda001.feishu.cn/wiki/MqcKwTiJ2isvASk5xQzcdeUJnOb)
+* [模块移植手册](https://lceda001.feishu.cn/wiki/RvtIwNuQ6iVhqvk4cELcr1vPncQ)
+* [购买地址](https://lckfb.com/project/detail/lckfb-lspi-skystar-hc32f4a0pitb-lite?param=baseInfo)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注**                        |
+| :----------- | :----------: | :------------------------------ |
+| GPIO         |     支持     | PA0, PA1... ---> PIN: 0, 1...81 |
+| UART         |     支持     | UART0 - UART6                   |
+| I2C          |     支持     | I2C1                            |
+| SPI          |     支持     | SPI0 -  SPI2                    |
+| ADC          |     支持     | ADC0 - ADC2                     |
+| TF CARD      |     支持     | SDIO1                           |
+| SPI FLASH    |   暂不支持   |                                 |
+| **扩展模块** | **支持情况** | **备注**                        |
+| 暂无         |   暂不支持   | 暂不支持                        |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+  
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+  
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)，上电。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.2.0 build Jun 28 2024 16:55:59
+ 2006 - 2024 Copyright by RT-Thread team
+
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口0的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+- [yuanzihao](https://github.com/zihao-yuan/), 邮箱：[y@yzh.email](mailto:y@yzh.email)
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConscript
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConscript
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/SConstruct
@@ -0,0 +1,62 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hc32_library = 'hc32f4a0_ddl'
+rtconfig.BSP_LIBRARY_TYPE = hc32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
+
+objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/SConscript
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/SConscript
@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/main.c
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/main.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ * 2024-06-28     yuanzihao    adaptation for SkyStar HC32F4A0PITB version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED_GREEN pin: PB2 */
+#define LED_GREEN_PIN GET_PIN(B, 2)
+
+
+int main(void)
+{
+    /* set LED_GREEN_PIN pin mode to output */
+    rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_GREEN_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-10-27     CDT          first version
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+
+#define XTAL32_FCM_THREAD_STACK_SIZE    (1024)
+
+/**
+ * @brief This thread is used to monitor whether XTAL32 is stable.
+ *        This thread only runs once after the system starts.
+ *        When stability is detected or 2s times out, the thread will end.
+ *       (When a timeout occurs it will be prompted via rt_kprintf)
+ */
+void xtal32_fcm_thread_entry(void *parameter)
+{
+    stc_fcm_init_t stcFcmInit;
+    uint32_t u32TimeOut = 0UL;
+    uint32_t u32Time = 200UL; /* 200*10ms = 2s */
+
+    /* FCM config */
+    FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
+    (void)FCM_StructInit(&stcFcmInit);
+    stcFcmInit.u32RefClock       = FCM_REF_CLK_MRC;
+    stcFcmInit.u32RefClockDiv    = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
+    stcFcmInit.u32RefClockEdge   = FCM_REF_CLK_RISING;
+    stcFcmInit.u32TargetClock    = FCM_TARGET_CLK_XTAL32;
+    stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+    stcFcmInit.u16LowerLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
+    stcFcmInit.u16UpperLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
+    (void)FCM_Init(&stcFcmInit);
+    /* Enable FCM, to ensure xtal32 stable */
+    FCM_Cmd(ENABLE);
+
+    while (1)
+    {
+        if (SET == FCM_GetStatus(FCM_FLAG_END))
+        {
+            FCM_ClearStatus(FCM_FLAG_END);
+            if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
+            {
+                FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
+            }
+            else
+            {
+                (void)FCM_DeInit();
+                FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+                /* XTAL32 stabled */
+                break;
+            }
+        }
+        u32TimeOut++;
+        if (u32TimeOut > u32Time)
+        {
+            (void)FCM_DeInit();
+            FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+            rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
+            break;
+        }
+        rt_thread_mdelay(10);
+    }
+}
+
+int xtal32_fcm_thread_create(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
+                           XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        rt_kprintf("create xtal32_fcm thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(xtal32_fcm_thread_create);
+
+#endif
+
+
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/SConscript
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/SConscript
@@ -0,0 +1,38 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+board_config.c
+''')
+
+if GetDepend(['BSP_USING_TCA9539']):
+    src += Glob('ports/tca9539.c')
+
+if GetDepend(['BSP_USING_SPI_FLASH']):
+    src += Glob('ports/drv_spi_flash.c')
+
+path =  [cwd]
+path += [cwd + '/ports']
+path += [cwd + '/config']
+path += [cwd + '/config/usb_config']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s']
+elif rtconfig.PLATFORM in ['iccarm']:
+    src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
+
+CPPDEFINES = ['HC32F4A0', '__DEBUG']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include "board.h"
+#include "board_config.h"
+
+/* unlock/lock peripheral */
+#define EXAMPLE_PERIPH_WE               (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
+                                         LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
+#define EXAMPLE_PERIPH_WP               (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+/**
+ * @brief Switch clock stable time
+ * @note Approx. 30us
+ */
+#define CLK_SYSCLK_SW_STB               (HCLK_VALUE / 50000UL)
+/**
+ * @brief Clk delay function
+ * @param [in] u32Delay         count
+ * @retval when switch clock source, should be delay some time to wait stable.
+ */
+static void CLK_Delay(uint32_t u32Delay)
+{
+    __IO uint32_t u32Timeout = 0UL;
+
+    while (u32Timeout < u32Delay)
+    {
+        u32Timeout++;
+    }
+}
+#endif
+
+/** System Base Configuration
+*/
+void SystemBase_Config(void)
+{
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
+    EFM_ICacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
+    EFM_DCacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
+    EFM_PrefetchCmd(ENABLE);
+#endif
+    /* Reset the VBAT area */
+    PWC_VBAT_Reset();
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+    stc_clock_xtal_init_t stcXtalInit;
+    stc_clock_pll_init_t stcPLLHInit;
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    stc_clock_pllx_init_t stcPLLAInit;
+#endif
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    stc_clock_xtal32_init_t stcXtal32Init;
+#endif
+
+    /* PCLK0, HCLK  Max 240MHz */
+    /* PCLK1, PCLK4 Max 120MHz */
+    /* PCLK2, PCLK3 Max 60MHz  */
+    /* EX BUS Max 120MHz */
+    CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
+                    (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
+                     CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
+                     CLK_HCLK_DIV1));
+
+    GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
+    (void)CLK_XtalStructInit(&stcXtalInit);
+    /* Config Xtal and enable Xtal */
+    stcXtalInit.u8Mode   = CLK_XTAL_MD_OSC;
+    stcXtalInit.u8Drv    = CLK_XTAL_DRV_ULOW;
+    stcXtalInit.u8State  = CLK_XTAL_ON;
+    stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
+    (void)CLK_XtalInit(&stcXtalInit);
+
+    (void)CLK_PLLStructInit(&stcPLLHInit);
+    /* VCO = (8/1)*120 = 960MHz*/
+    stcPLLHInit.u8PLLState = CLK_PLL_ON;
+    stcPLLHInit.PLLCFGR = 0UL;
+    stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
+    (void)CLK_PLLInit(&stcPLLHInit);
+
+    /* Highspeed SRAM set to 0 Read/Write wait cycle */
+    SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
+    /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
+    SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
+    /* 0-wait @ 40MHz */
+    (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
+    /* 4 cycles for 200 ~ 250MHz */
+    GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
+    CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    /* PLLX for USB */
+    (void)CLK_PLLxStructInit(&stcPLLAInit);
+    /* VCO = (8/2)*120 = 480MHz*/
+    stcPLLAInit.u8PLLState = CLK_PLL_ON;
+    stcPLLAInit.PLLCFGR = 0UL;
+    stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    (void)CLK_PLLxInit(&stcPLLAInit);
+#endif
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    /* Xtal32 config */
+    GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
+    (void)CLK_Xtal32StructInit(&stcXtal32Init);
+    stcXtal32Init.u8State  = CLK_XTAL32_ON;
+    stcXtal32Init.u8Drv    = CLK_XTAL32_DRV_HIGH;
+    stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
+    (void)CLK_Xtal32Init(&stcXtal32Init);
+#endif
+}
+
+/** Peripheral Clock Configuration
+*/
+void PeripheralClock_Config(void)
+{
+#if defined(BSP_USING_CAN1)
+    CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+#if defined(BSP_USING_CAN2)
+    CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+
+#if defined(RT_USING_ADC)
+    CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
+#endif
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
+    /* Wait stable here, since the current DDL API does not include this */
+    CLK_Delay(CLK_SYSCLK_SW_STB);
+#endif
+}
+
+/** Peripheral Registers Unlock
+*/
+void PeripheralRegister_Unlock(void)
+{
+    LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
+}
+
+/*@}*/
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "hc32_ll.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_SIZE                 (2 * 1024 * 1024)
+#define HC32_FLASH_START_ADDRESS        (0)
+#define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
+
+#define HC32_SRAM_SIZE                  (512)
+#define HC32_SRAM_END                   (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RW_IRAM2$$ZI$$Limit;
+#define HEAP_BEGIN                      (&Image$$RW_IRAM2$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN                      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN                      (&__bss_end)
+#endif
+
+#define HEAP_END                        HC32_SRAM_END
+
+void PeripheralRegister_Unlock(void);
+void PeripheralClock_Config(void);
+void SystemBase_Config(void);
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_INIT_PARAMS
+#define ADC1_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc1",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC1_INIT_PARAMS */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_INIT_PARAMS
+#define ADC2_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc2",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC2_INIT_PARAMS */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_INIT_PARAMS
+#define ADC3_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc3",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_ADTRG_PIN,               \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_MAX,                          \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC3_INIT_PARAMS */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_CAN1
+#define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN1_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN1_NAME                       ("can1")
+#ifndef CAN1_INIT_PARAMS
+#define CAN1_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN1_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN1_INIT_PARAMS */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+#define CAN2_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN2_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN2_NAME                       ("can2")
+#ifndef CAN2_INIT_PARAMS
+#define CAN2_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN2_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN2_INIT_PARAMS */
+#endif /* BSP_USING_CAN2 */
+
+/* Bit time config
+  Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
+
+  Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
+  TQ = u32Prescaler / CANClock.
+  Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
+
+  The following bit time configures are based on CAN Clock 40M
+*/
+#define CAN_BIT_TIME_CONFIG_1M_BAUD                         \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_800K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 20,                                  \
+        .u32TimeSeg2 = 5,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_500K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 4,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_250K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 8,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_125K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 16,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_100K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 20,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_50K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 40,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_20K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 100,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_10K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 200,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-05-12     CDT          first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_INIT_PARAMS
+#define DAC1_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac1",                                 \
+    }
+#endif /* DAC1_INIT_PARAMS */
+#endif /* BSP_USING_DAC1 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_INIT_PARAMS
+#define DAC2_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac2",                                 \
+    }
+#endif /* DAC2_INIT_PARAMS */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 ch0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_RX_DMA_INSTANCE            CM_DMA1
+#define SPI1_RX_DMA_CHANNEL             DMA_CH0
+#define SPI1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define SPI1_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define SPI1_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define SPI1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE)
+#define SDIO1_RX_DMA_INSTANCE           CM_DMA1
+#define SDIO1_RX_DMA_CHANNEL            DMA_CH0
+#define SDIO1_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO1_RX_DMA_TRIG_SELECT        AOS_DMA1_0
+#define SDIO1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define SDIO1_RX_DMA_IRQn               BSP_DMA1_CH0_IRQ_NUM
+#define SDIO1_RX_DMA_INT_PRIO           BSP_DMA1_CH0_IRQ_PRIO
+#define SDIO1_RX_DMA_INT_SRC            INT_SRC_DMA1_TC0
+#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
+#define I2C1_TX_DMA_INSTANCE            CM_DMA1
+#define I2C1_TX_DMA_CHANNEL             DMA_CH0
+#define I2C1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_TX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define I2C1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C1_TX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define I2C1_TX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define I2C1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#endif
+
+/* DMA1 ch1 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_TX_DMA_INSTANCE            CM_DMA1
+#define SPI1_TX_DMA_CHANNEL             DMA_CH1
+#define SPI1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define SPI1_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define SPI1_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define SPI1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE)
+#define SDIO1_TX_DMA_INSTANCE           CM_DMA1
+#define SDIO1_TX_DMA_CHANNEL            DMA_CH1
+#define SDIO1_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO1_TX_DMA_TRIG_SELECT        AOS_DMA1_1
+#define SDIO1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define SDIO1_TX_DMA_IRQn               BSP_DMA1_CH1_IRQ_NUM
+#define SDIO1_TX_DMA_INT_PRIO           BSP_DMA1_CH1_IRQ_PRIO
+#define SDIO1_TX_DMA_INT_SRC            INT_SRC_DMA1_TC1
+#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
+#define I2C1_RX_DMA_INSTANCE            CM_DMA1
+#define I2C1_RX_DMA_CHANNEL             DMA_CH1
+#define I2C1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_RX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define I2C1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C1_RX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define I2C1_RX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define I2C1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#endif
+
+/* DMA1 ch2 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_RX_DMA_INSTANCE            CM_DMA1
+#define SPI2_RX_DMA_CHANNEL             DMA_CH2
+#define SPI2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_RX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define SPI2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define SPI2_RX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define SPI2_RX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define SPI2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE)
+#define SDIO2_RX_DMA_INSTANCE           CM_DMA1
+#define SDIO2_RX_DMA_CHANNEL            DMA_CH2
+#define SDIO2_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO2_RX_DMA_TRIG_SELECT        AOS_DMA1_2
+#define SDIO2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define SDIO2_RX_DMA_IRQn               BSP_DMA1_CH2_IRQ_NUM
+#define SDIO2_RX_DMA_INT_PRIO           BSP_DMA1_CH2_IRQ_PRIO
+#define SDIO2_RX_DMA_INT_SRC            INT_SRC_DMA1_TC2
+#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
+#define I2C2_TX_DMA_INSTANCE            CM_DMA1
+#define I2C2_TX_DMA_CHANNEL             DMA_CH2
+#define I2C2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_TX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define I2C2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define I2C2_TX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define I2C2_TX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define I2C2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#endif
+
+/* DMA1 ch3 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_TX_DMA_INSTANCE            CM_DMA1
+#define SPI2_TX_DMA_CHANNEL             DMA_CH3
+#define SPI2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_TX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define SPI2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define SPI2_TX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define SPI2_TX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define SPI2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE)
+#define SDIO2_TX_DMA_INSTANCE           CM_DMA1
+#define SDIO2_TX_DMA_CHANNEL            DMA_CH3
+#define SDIO2_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SDIO2_TX_DMA_TRIG_SELECT        AOS_DMA1_3
+#define SDIO2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
+#define SDIO2_TX_DMA_IRQn               BSP_DMA1_CH3_IRQ_NUM
+#define SDIO2_TX_DMA_INT_PRIO           BSP_DMA1_CH3_IRQ_PRIO
+#define SDIO2_TX_DMA_INT_SRC            INT_SRC_DMA1_TC3
+#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_INSTANCE               CM_DMA1
+#define QSPI_DMA_CHANNEL                DMA_CH3
+#define QSPI_DMA_CLOCK                  (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define QSPI_DMA_TRIG_SELECT            AOS_DMA1_3
+#define QSPI_DMA_TRANS_FLAG             DMA_FLAG_TC_CH3
+#define QSPI_DMA_IRQn                   BSP_DMA1_CH3_IRQ_NUM
+#define QSPI_DMA_INT_PRIO               BSP_DMA1_CH3_IRQ_PRIO
+#define QSPI_DMA_INT_SRC                INT_SRC_DMA1_TC3
+#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
+#define I2C2_RX_DMA_INSTANCE            CM_DMA1
+#define I2C2_RX_DMA_CHANNEL             DMA_CH3
+#define I2C2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_RX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define I2C2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define I2C2_RX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define I2C2_RX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define I2C2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+#endif
+
+/* DMA1 ch4 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_RX_DMA_INSTANCE            CM_DMA1
+#define SPI3_RX_DMA_CHANNEL             DMA_CH4
+#define SPI3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_RX_DMA_TRIG_SELECT         AOS_DMA1_4
+#define SPI3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH4
+#define SPI3_RX_DMA_IRQn                BSP_DMA1_CH4_IRQ_NUM
+#define SPI3_RX_DMA_INT_PRIO            BSP_DMA1_CH4_IRQ_PRIO
+#define SPI3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC4
+#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE)
+#define I2C3_TX_DMA_INSTANCE            CM_DMA1
+#define I2C3_TX_DMA_CHANNEL             DMA_CH4
+#define I2C3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C3_TX_DMA_TRIG_SELECT         AOS_DMA1_4
+#define I2C3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH4
+#define I2C3_TX_DMA_IRQn                BSP_DMA1_CH4_IRQ_NUM
+#define I2C3_TX_DMA_INT_PRIO            BSP_DMA1_CH4_IRQ_PRIO
+#define I2C3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC4
+#endif
+
+/* DMA1 ch5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_TX_DMA_INSTANCE            CM_DMA1
+#define SPI3_TX_DMA_CHANNEL             DMA_CH5
+#define SPI3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_TX_DMA_TRIG_SELECT         AOS_DMA1_5
+#define SPI3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH5
+#define SPI3_TX_DMA_IRQn                BSP_DMA1_CH5_IRQ_NUM
+#define SPI3_TX_DMA_INT_PRIO            BSP_DMA1_CH5_IRQ_PRIO
+#define SPI3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC5
+#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE)
+#define I2C3_RX_DMA_INSTANCE            CM_DMA1
+#define I2C3_RX_DMA_CHANNEL             DMA_CH5
+#define I2C3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C3_RX_DMA_TRIG_SELECT         AOS_DMA1_5
+#define I2C3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH5
+#define I2C3_RX_DMA_IRQn                BSP_DMA1_CH5_IRQ_NUM
+#define I2C3_RX_DMA_INT_PRIO            BSP_DMA1_CH5_IRQ_PRIO
+#define I2C3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC5
+#endif
+
+/* DMA1 ch6 */
+#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_RX_DMA_INSTANCE            CM_DMA1
+#define SPI4_RX_DMA_CHANNEL             DMA_CH6
+#define SPI4_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI4_RX_DMA_TRIG_SELECT         AOS_DMA1_6
+#define SPI4_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH6
+#define SPI4_RX_DMA_IRQn                BSP_DMA1_CH6_IRQ_NUM
+#define SPI4_RX_DMA_INT_PRIO            BSP_DMA1_CH6_IRQ_PRIO
+#define SPI4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC6
+#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE)
+#define I2C4_TX_DMA_INSTANCE            CM_DMA1
+#define I2C4_TX_DMA_CHANNEL             DMA_CH6
+#define I2C4_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C4_TX_DMA_TRIG_SELECT         AOS_DMA1_6
+#define I2C4_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH6
+#define I2C4_TX_DMA_IRQn                BSP_DMA1_CH6_IRQ_NUM
+#define I2C4_TX_DMA_INT_PRIO            BSP_DMA1_CH6_IRQ_PRIO
+#define I2C4_TX_DMA_INT_SRC             INT_SRC_DMA1_TC6
+#endif
+
+/* DMA1 ch7 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_TX_DMA_INSTANCE            CM_DMA1
+#define SPI4_TX_DMA_CHANNEL             DMA_CH7
+#define SPI4_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI4_TX_DMA_TRIG_SELECT         AOS_DMA1_7
+#define SPI4_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH7
+#define SPI4_TX_DMA_IRQn                BSP_DMA1_CH7_IRQ_NUM
+#define SPI4_TX_DMA_INT_PRIO            BSP_DMA1_CH7_IRQ_PRIO
+#define SPI4_TX_DMA_INT_SRC             INT_SRC_DMA1_TC7
+#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE)
+#define I2C4_RX_DMA_INSTANCE            CM_DMA1
+#define I2C4_RX_DMA_CHANNEL             DMA_CH7
+#define I2C4_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C4_RX_DMA_TRIG_SELECT         AOS_DMA1_7
+#define I2C4_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH7
+#define I2C4_RX_DMA_IRQn                BSP_DMA1_CH7_IRQ_NUM
+#define I2C4_RX_DMA_INT_PRIO            BSP_DMA1_CH7_IRQ_PRIO
+#define I2C4_RX_DMA_INT_SRC             INT_SRC_DMA1_TC7
+#endif
+
+/* DMA2 ch0 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_RX_DMA_INSTANCE           CM_DMA2
+#define UART1_RX_DMA_CHANNEL            DMA_CH0
+#define UART1_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_RX_DMA_TRIG_SELECT        AOS_DMA2_0
+#define UART1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define UART1_RX_DMA_IRQn               BSP_DMA2_CH0_IRQ_NUM
+#define UART1_RX_DMA_INT_PRIO           BSP_DMA2_CH0_IRQ_PRIO
+#define UART1_RX_DMA_INT_SRC            INT_SRC_DMA2_TC0
+#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE)
+#define I2C5_TX_DMA_INSTANCE            CM_DMA2
+#define I2C5_TX_DMA_CHANNEL             DMA_CH0
+#define I2C5_TX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C5_TX_DMA_TRIG_SELECT         AOS_DMA2_0
+#define I2C5_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C5_TX_DMA_IRQn                BSP_DMA2_CH0_IRQ_NUM
+#define I2C5_TX_DMA_INT_PRIO            BSP_DMA2_CH0_IRQ_PRIO
+#define I2C5_TX_DMA_INT_SRC             INT_SRC_DMA2_TC0
+#endif
+
+/* DMA2 ch1 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_TX_DMA_INSTANCE           CM_DMA2
+#define UART1_TX_DMA_CHANNEL            DMA_CH1
+#define UART1_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_TX_DMA_TRIG_SELECT        AOS_DMA2_1
+#define UART1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define UART1_TX_DMA_IRQn               BSP_DMA2_CH1_IRQ_NUM
+#define UART1_TX_DMA_INT_PRIO           BSP_DMA2_CH1_IRQ_PRIO
+#define UART1_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
+#elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE)
+#define I2C5_RX_DMA_INSTANCE            CM_DMA2
+#define I2C5_RX_DMA_CHANNEL             DMA_CH1
+#define I2C5_RX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C5_RX_DMA_TRIG_SELECT         AOS_DMA2_1
+#define I2C5_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C5_RX_DMA_IRQn                BSP_DMA2_CH1_IRQ_NUM
+#define I2C5_RX_DMA_INT_PRIO            BSP_DMA2_CH1_IRQ_PRIO
+#define I2C5_RX_DMA_INT_SRC             INT_SRC_DMA2_TC1
+#endif
+
+/* DMA2 ch2 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_RX_DMA_INSTANCE           CM_DMA2
+#define UART2_RX_DMA_CHANNEL            DMA_CH2
+#define UART2_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_RX_DMA_TRIG_SELECT        AOS_DMA2_2
+#define UART2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define UART2_RX_DMA_IRQn               BSP_DMA2_CH2_IRQ_NUM
+#define UART2_RX_DMA_INT_PRIO           BSP_DMA2_CH2_IRQ_PRIO
+#define UART2_RX_DMA_INT_SRC            INT_SRC_DMA2_TC2
+#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE)
+#define I2C6_TX_DMA_INSTANCE            CM_DMA2
+#define I2C6_TX_DMA_CHANNEL             DMA_CH2
+#define I2C6_TX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C6_TX_DMA_TRIG_SELECT         AOS_DMA2_2
+#define I2C6_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define I2C6_TX_DMA_IRQn                BSP_DMA2_CH2_IRQ_NUM
+#define I2C6_TX_DMA_INT_PRIO            BSP_DMA2_CH2_IRQ_PRIO
+#define I2C6_TX_DMA_INT_SRC             INT_SRC_DMA2_TC2
+#endif
+
+/* DMA2 ch3 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_TX_DMA_INSTANCE           CM_DMA2
+#define UART2_TX_DMA_CHANNEL            DMA_CH3
+#define UART2_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_TX_DMA_TRIG_SELECT        AOS_DMA2_3
+#define UART2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
+#define UART2_TX_DMA_IRQn               BSP_DMA2_CH3_IRQ_NUM
+#define UART2_TX_DMA_INT_PRIO           BSP_DMA2_CH3_IRQ_PRIO
+#define UART2_TX_DMA_INT_SRC            INT_SRC_DMA2_TC3
+#elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE)
+#define I2C6_RX_DMA_INSTANCE            CM_DMA2
+#define I2C6_RX_DMA_CHANNEL             DMA_CH3
+#define I2C6_RX_DMA_CLOCK               (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define I2C6_RX_DMA_TRIG_SELECT         AOS_DMA2_3
+#define I2C6_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define I2C6_RX_DMA_IRQn                BSP_DMA2_CH3_IRQ_NUM
+#define I2C6_RX_DMA_INT_PRIO            BSP_DMA2_CH3_IRQ_PRIO
+#define I2C6_RX_DMA_INT_SRC             INT_SRC_DMA2_TC3
+#endif
+
+/* DMA2 ch4 */
+#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_RX_DMA_INSTANCE           CM_DMA2
+#define UART6_RX_DMA_CHANNEL            DMA_CH4
+#define UART6_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART6_RX_DMA_TRIG_SELECT        AOS_DMA2_4
+#define UART6_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH4
+#define UART6_RX_DMA_IRQn               BSP_DMA2_CH4_IRQ_NUM
+#define UART6_RX_DMA_INT_PRIO           BSP_DMA2_CH4_IRQ_PRIO
+#define UART6_RX_DMA_INT_SRC            INT_SRC_DMA2_TC4
+#endif
+
+/* DMA2 ch5 */
+#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_TX_DMA_INSTANCE           CM_DMA2
+#define UART6_TX_DMA_CHANNEL            DMA_CH5
+#define UART6_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART6_TX_DMA_TRIG_SELECT        AOS_DMA2_5
+#define UART6_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH5
+#define UART6_TX_DMA_IRQn               BSP_DMA2_CH5_IRQ_NUM
+#define UART6_TX_DMA_INT_PRIO           BSP_DMA2_CH5_IRQ_PRIO
+#define UART6_TX_DMA_INT_SRC            INT_SRC_DMA2_TC5
+#endif
+
+/* DMA2 ch6 */
+#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_RX_DMA_INSTANCE           CM_DMA2
+#define UART7_RX_DMA_CHANNEL            DMA_CH6
+#define UART7_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART7_RX_DMA_TRIG_SELECT        AOS_DMA2_6
+#define UART7_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH6
+#define UART7_RX_DMA_IRQn               BSP_DMA2_CH6_IRQ_NUM
+#define UART7_RX_DMA_INT_PRIO           BSP_DMA2_CH6_IRQ_PRIO
+#define UART7_RX_DMA_INT_SRC            INT_SRC_DMA2_TC6
+#endif
+
+/* DMA2 ch7 */
+#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_TX_DMA_INSTANCE           CM_DMA2
+#define UART7_TX_DMA_CHANNEL            DMA_CH7
+#define UART7_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART7_TX_DMA_TRIG_SELECT        AOS_DMA2_7
+#define UART7_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH7
+#define UART7_TX_DMA_IRQn               BSP_DMA2_CH7_IRQ_NUM
+#define UART7_TX_DMA_INT_PRIO           BSP_DMA2_CH7_IRQ_PRIO
+#define UART7_TX_DMA_INT_SRC            INT_SRC_DMA2_TC7
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __ETH_CONFIG_H__
+#define __ETH_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_ETH)
+
+#ifndef ETH_IRQ_CONFIG
+#define ETH_IRQ_CONFIG                                      \
+    {                                                       \
+        .irq_num    = BSP_ETH_IRQ_NUM,                      \
+        .irq_prio   = BSP_ETH_IRQ_PRIO,                     \
+        .int_src    = INT_SRC_ETH_GLB_INT,                  \
+    }
+#endif /* ETH_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ETH_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __GPIO_CONFIG_H__
+#define __GPIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(RT_USING_PIN)
+
+#ifndef EXTINT0_IRQ_CONFIG
+#define EXTINT0_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT0_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT0_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ0,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT1_IRQ_CONFIG
+#define EXTINT1_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT1_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT1_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ1,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT2_IRQ_CONFIG
+#define EXTINT2_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT2_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT2_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ2,                   \
+    }
+#endif /* EXTINT2_IRQ_CONFIG */
+
+#ifndef EXTINT3_IRQ_CONFIG
+#define EXTINT3_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT3_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT3_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ3,                   \
+    }
+#endif /* EXTINT3_IRQ_CONFIG */
+
+#ifndef EXTINT4_IRQ_CONFIG
+#define EXTINT4_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT4_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT4_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ4,                   \
+    }
+#endif /* EXTINT4_IRQ_CONFIG */
+
+#ifndef EXTINT5_IRQ_CONFIG
+#define EXTINT5_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT5_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT5_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ5,                   \
+    }
+#endif /* EXTINT5_IRQ_CONFIG */
+
+#ifndef EXTINT6_IRQ_CONFIG
+#define EXTINT6_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT6_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT6_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ6,                   \
+    }
+#endif /* EXTINT6_IRQ_CONFIG */
+
+#ifndef EXTINT7_IRQ_CONFIG
+#define EXTINT7_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT7_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT7_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ7,                   \
+    }
+#endif /* EXTINT7_IRQ_CONFIG */
+
+#ifndef EXTINT8_IRQ_CONFIG
+#define EXTINT8_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT8_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT8_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ8,                   \
+    }
+#endif /* EXTINT8_IRQ_CONFIG */
+
+#ifndef EXTINT9_IRQ_CONFIG
+#define EXTINT9_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT9_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT9_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ9,                   \
+    }
+#endif /* EXTINT9_IRQ_CONFIG */
+
+#ifndef EXTINT10_IRQ_CONFIG
+#define EXTINT10_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT10_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT10_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ10,                  \
+    }
+#endif /* EXTINT10_IRQ_CONFIG */
+
+#ifndef EXTINT11_IRQ_CONFIG
+#define EXTINT11_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT11_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT11_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ11,                  \
+    }
+#endif /* EXTINT11_IRQ_CONFIG */
+
+#ifndef EXTINT12_IRQ_CONFIG
+#define EXTINT12_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT12_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT12_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ12,                  \
+    }
+#endif /* EXTINT12_IRQ_CONFIG */
+
+#ifndef EXTINT13_IRQ_CONFIG
+#define EXTINT13_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT13_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT13_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ13,                  \
+    }
+#endif /* EXTINT13_IRQ_CONFIG */
+
+#ifndef EXTINT14_IRQ_CONFIG
+#define EXTINT14_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT14_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT14_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ14,                  \
+    }
+#endif /* EXTINT14_IRQ_CONFIG */
+
+#ifndef EXTINT15_IRQ_CONFIG
+#define EXTINT15_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT15_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT15_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ15,                  \
+    }
+#endif /* EXTINT15_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __I2C_CONFIG_H__
+#define __I2C_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_I2C1)
+#ifndef I2C1_CONFIG
+#define I2C1_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c1",                                     \
+        .Instance = CM_I2C1,                                    \
+        .clock    = FCG1_PERIPH_I2C1,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C1_CONFIG */
+#endif
+
+#if defined(BSP_I2C1_USING_DMA)
+#ifndef I2C1_TX_DMA_CONFIG
+#define I2C1_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_TX_DMA_INSTANCE,                 \
+        .channel        = I2C1_TX_DMA_CHANNEL,                  \
+        .clock          = I2C1_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_TEI,                     \
+        .flag           = I2C1_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_TX_DMA_CONFIG */
+
+#ifndef I2C1_RX_DMA_CONFIG
+#define I2C1_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_RX_DMA_INSTANCE,                 \
+        .channel        = I2C1_RX_DMA_CHANNEL,                  \
+        .clock          = I2C1_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_RXI,                     \
+        .flag           = I2C1_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_RX_DMA_CONFIG */
+#endif /* BSP_I2C1_USING_DMA */
+
+#if defined(BSP_USING_I2C2)
+#ifndef I2C2_CONFIG
+#define I2C2_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c2",                                     \
+        .Instance = CM_I2C2,                                    \
+        .clock    = FCG1_PERIPH_I2C2,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C2_CONFIG */
+
+#if defined(BSP_I2C2_USING_DMA)
+#ifndef I2C2_TX_DMA_CONFIG
+#define I2C2_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_TX_DMA_INSTANCE,                 \
+        .channel        = I2C2_TX_DMA_CHANNEL,                  \
+        .clock          = I2C2_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_TEI,                     \
+        .flag           = I2C2_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_TX_DMA_CONFIG */
+
+#ifndef I2C2_RX_DMA_CONFIG
+#define I2C2_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_RX_DMA_INSTANCE,                 \
+        .channel        = I2C2_RX_DMA_CHANNEL,                  \
+        .clock          = I2C2_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_RXI,                     \
+        .flag           = I2C2_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_RX_DMA_CONFIG */
+#endif /* BSP_I2C2_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C3)
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c3",                                     \
+        .Instance = CM_I2C3,                                    \
+        .clock    = FCG1_PERIPH_I2C3,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C3_CONFIG */
+
+#if defined(BSP_I2C3_USING_DMA)
+#ifndef I2C3_TX_DMA_CONFIG
+#define I2C3_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_TX_DMA_INSTANCE,                 \
+        .channel        = I2C3_TX_DMA_CHANNEL,                  \
+        .clock          = I2C3_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_TEI,                     \
+        .flag           = I2C3_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_TX_DMA_CONFIG */
+
+#ifndef I2C3_RX_DMA_CONFIG
+#define I2C3_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_RX_DMA_INSTANCE,                 \
+        .channel        = I2C3_RX_DMA_CHANNEL,                  \
+        .clock          = I2C3_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_RXI,                     \
+        .flag           = I2C3_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_RX_DMA_CONFIG */
+#endif /* BSP_I2C3_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C4)
+#ifndef I2C4_CONFIG
+#define I2C4_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c4",                                     \
+        .Instance = CM_I2C4,                                    \
+        .clock    = FCG1_PERIPH_I2C4,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C4_CONFIG */
+
+#if defined(BSP_I2C4_USING_DMA)
+#ifndef I2C4_TX_DMA_CONFIG
+#define I2C4_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_TX_DMA_INSTANCE,                 \
+        .channel        = I2C4_TX_DMA_CHANNEL,                  \
+        .clock          = I2C4_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_TEI,                     \
+        .flag           = I2C4_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_TX_DMA_CONFIG */
+
+#ifndef I2C4_RX_DMA_CONFIG
+#define I2C4_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_RX_DMA_INSTANCE,                 \
+        .channel        = I2C4_RX_DMA_CHANNEL,                  \
+        .clock          = I2C4_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_RXI,                     \
+        .flag           = I2C4_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_RX_DMA_CONFIG */
+#endif /* BSP_I2C4_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C5)
+#ifndef I2C5_CONFIG
+#define I2C5_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c5",                                     \
+        .Instance = CM_I2C5,                                    \
+        .clock    = FCG1_PERIPH_I2C5,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C5_CONFIG */
+
+#if defined(BSP_I2C5_USING_DMA)
+#ifndef I2C5_TX_DMA_CONFIG
+#define I2C5_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_TX_DMA_INSTANCE,                 \
+        .channel        = I2C5_TX_DMA_CHANNEL,                  \
+        .clock          = I2C5_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_TEI,                     \
+        .flag           = I2C5_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_TX_DMA_CONFIG */
+
+#ifndef I2C5_RX_DMA_CONFIG
+#define I2C5_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_RX_DMA_INSTANCE,                 \
+        .channel        = I2C5_RX_DMA_CHANNEL,                  \
+        .clock          = I2C5_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_RXI,                     \
+        .flag           = I2C5_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_RX_DMA_CONFIG */
+#endif /* BSP_I2C5_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C6)
+#ifndef I2C6_CONFIG
+#define I2C6_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c6",                                     \
+        .Instance = CM_I2C6,                                    \
+        .clock    = FCG1_PERIPH_I2C6,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C6_CONFIG */
+
+#if defined(BSP_I2C6_USING_DMA)
+#ifndef I2C6_TX_DMA_CONFIG
+#define I2C6_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_TX_DMA_INSTANCE,                 \
+        .channel        = I2C6_TX_DMA_CHANNEL,                  \
+        .clock          = I2C6_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_TEI,                     \
+        .flag           = I2C6_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_TX_DMA_CONFIG */
+
+#ifndef I2C6_RX_DMA_CONFIG
+#define I2C6_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_RX_DMA_INSTANCE,                 \
+        .channel        = I2C6_RX_DMA_CHANNEL,                  \
+        .clock          = I2C6_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_RXI,                     \
+        .flag           = I2C6_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_RX_DMA_CONFIG */
+#endif /* BSP_I2C6_USING_DMA */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h
@@ -0,0 +1,479 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __IRQ_CONFIG_H__
+#define __IRQ_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_EXTINT0_IRQ_NUM             INT022_IRQn
+#define BSP_EXTINT0_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT1_IRQ_NUM             INT023_IRQn
+#define BSP_EXTINT1_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT2_IRQ_NUM             INT024_IRQn
+#define BSP_EXTINT2_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT3_IRQ_NUM             INT025_IRQn
+#define BSP_EXTINT3_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT4_IRQ_NUM             INT026_IRQn
+#define BSP_EXTINT4_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT5_IRQ_NUM             INT027_IRQn
+#define BSP_EXTINT5_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT6_IRQ_NUM             INT028_IRQn
+#define BSP_EXTINT6_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT7_IRQ_NUM             INT029_IRQn
+#define BSP_EXTINT7_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT8_IRQ_NUM             INT030_IRQn
+#define BSP_EXTINT8_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT9_IRQ_NUM             INT031_IRQn
+#define BSP_EXTINT9_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT10_IRQ_NUM            INT032_IRQn
+#define BSP_EXTINT10_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT11_IRQ_NUM            INT033_IRQn
+#define BSP_EXTINT11_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT12_IRQ_NUM            INT034_IRQn
+#define BSP_EXTINT12_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT13_IRQ_NUM            INT035_IRQn
+#define BSP_EXTINT13_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT14_IRQ_NUM            INT036_IRQn
+#define BSP_EXTINT14_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT15_IRQ_NUM            INT037_IRQn
+#define BSP_EXTINT15_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+/* DMA1 ch0 */
+#define BSP_DMA1_CH0_IRQ_NUM            INT038_IRQn
+#define BSP_DMA1_CH0_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch1 */
+#define BSP_DMA1_CH1_IRQ_NUM            INT039_IRQn
+#define BSP_DMA1_CH1_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch2 */
+#define BSP_DMA1_CH2_IRQ_NUM            INT040_IRQn
+#define BSP_DMA1_CH2_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch3 */
+#define BSP_DMA1_CH3_IRQ_NUM            INT041_IRQn
+#define BSP_DMA1_CH3_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch4 */
+#define BSP_DMA1_CH4_IRQ_NUM            INT042_IRQn
+#define BSP_DMA1_CH4_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch5 */
+#define BSP_DMA1_CH5_IRQ_NUM            INT043_IRQn
+#define BSP_DMA1_CH5_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch6 */
+#define BSP_DMA1_CH6_IRQ_NUM            INT018_IRQn
+#define BSP_DMA1_CH6_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch7 */
+#define BSP_DMA1_CH7_IRQ_NUM            INT019_IRQn
+#define BSP_DMA1_CH7_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+/* DMA2 ch0 */
+#define BSP_DMA2_CH0_IRQ_NUM            INT044_IRQn
+#define BSP_DMA2_CH0_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch1 */
+#define BSP_DMA2_CH1_IRQ_NUM            INT045_IRQn
+#define BSP_DMA2_CH1_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch2 */
+#define BSP_DMA2_CH2_IRQ_NUM            INT046_IRQn
+#define BSP_DMA2_CH2_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch3 */
+#define BSP_DMA2_CH3_IRQ_NUM            INT047_IRQn
+#define BSP_DMA2_CH3_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch4 */
+#define BSP_DMA2_CH4_IRQ_NUM            INT048_IRQn
+#define BSP_DMA2_CH4_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch5 */
+#define BSP_DMA2_CH5_IRQ_NUM            INT049_IRQn
+#define BSP_DMA2_CH5_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch6 */
+#define BSP_DMA2_CH6_IRQ_NUM            INT020_IRQn
+#define BSP_DMA2_CH6_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch7 */
+#define BSP_DMA2_CH7_IRQ_NUM            INT021_IRQn
+#define BSP_DMA2_CH7_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_USING_ETH)
+#define BSP_ETH_IRQ_NUM                 INT104_IRQn
+#define BSP_ETH_IRQ_PRIO                DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_UART1)
+#define BSP_UART1_RXERR_IRQ_NUM         INT010_IRQn
+#define BSP_UART1_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART1_RX_IRQ_NUM            INT089_IRQn
+#define BSP_UART1_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART1_TX_IRQ_NUM            INT088_IRQn
+#define BSP_UART1_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#define BSP_UART1_RXTO_IRQ_NUM          INT006_IRQn
+#define BSP_UART1_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
+#define BSP_UART1_TX_CPLT_IRQ_NUM       INT086_IRQn
+#define BSP_UART1_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
+#define BSP_UART1_TX_CPLT_IRQ_NUM       INT086_IRQn
+#define BSP_UART1_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#define BSP_UART2_RXERR_IRQ_NUM         INT011_IRQn
+#define BSP_UART2_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART2_RX_IRQ_NUM            INT091_IRQn
+#define BSP_UART2_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART2_TX_IRQ_NUM            INT090_IRQn
+#define BSP_UART2_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#define BSP_UART2_RXTO_IRQ_NUM          INT007_IRQn
+#define BSP_UART2_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
+#define BSP_UART2_TX_CPLT_IRQ_NUM       INT087_IRQn
+#define BSP_UART2_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
+#define BSP_UART2_TX_CPLT_IRQ_NUM       INT087_IRQn
+#define BSP_UART2_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#define BSP_UART3_RXERR_IRQ_NUM         INT012_IRQn
+#define BSP_UART3_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART3_RX_IRQ_NUM            INT095_IRQn
+#define BSP_UART3_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART3_TX_IRQ_NUM            INT094_IRQn
+#define BSP_UART3_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#define BSP_UART4_RXERR_IRQ_NUM         INT013_IRQn
+#define BSP_UART4_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART4_RX_IRQ_NUM            INT097_IRQn
+#define BSP_UART4_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART4_TX_IRQ_NUM            INT096_IRQn
+#define BSP_UART4_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#define BSP_UART5_RXERR_IRQ_NUM         INT014_IRQn
+#define BSP_UART5_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART5_RX_IRQ_NUM            INT101_IRQn
+#define BSP_UART5_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART5_TX_IRQ_NUM            INT100_IRQn
+#define BSP_UART5_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#define BSP_UART6_RXERR_IRQ_NUM         INT015_IRQn
+#define BSP_UART6_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART6_RX_IRQ_NUM            INT103_IRQn
+#define BSP_UART6_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART6_TX_IRQ_NUM            INT102_IRQn
+#define BSP_UART6_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#define BSP_UART6_RXTO_IRQ_NUM          INT008_IRQn
+#define BSP_UART6_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA)
+#define BSP_UART6_TX_CPLT_IRQ_NUM       INT099_IRQn
+#define BSP_UART6_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
+#define BSP_UART6_TX_CPLT_IRQ_NUM       INT099_IRQn
+#define BSP_UART6_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#define BSP_UART7_RXERR_IRQ_NUM         INT016_IRQn
+#define BSP_UART7_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART7_RX_IRQ_NUM            INT107_IRQn
+#define BSP_UART7_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART7_TX_IRQ_NUM            INT106_IRQn
+#define BSP_UART7_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_UART7_RX_USING_DMA)
+#define BSP_UART7_RXTO_IRQ_NUM          INT009_IRQn
+#define BSP_UART7_RXTO_IRQ_PRIO         DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA)
+#define BSP_UART7_TX_CPLT_IRQ_NUM       INT105_IRQn
+#define BSP_UART7_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#elif defined(RT_USING_SERIAL_V2)
+#define BSP_UART7_TX_CPLT_IRQ_NUM       INT105_IRQn
+#define BSP_UART7_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2)
+#define BSP_SPI1_ERR_IRQ_NUM            INT009_IRQn
+#define BSP_SPI1_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_SPI2_ERR_IRQ_NUM            INT016_IRQn
+#define BSP_SPI2_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART7 */
+
+#if defined(BSP_USING_SPI3)
+#define BSP_SPI3_ERR_IRQ_NUM            INT092_IRQn
+#define BSP_SPI3_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI4)
+#define BSP_SPI4_ERR_IRQ_NUM            INT093_IRQn
+#define BSP_SPI4_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_UART8)
+#define BSP_UART8_RXERR_IRQ_NUM         INT017_IRQn
+#define BSP_UART8_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART8_RX_IRQ_NUM            INT109_IRQn
+#define BSP_UART8_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART8_TX_IRQ_NUM            INT108_IRQn
+#define BSP_UART8_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#if defined(RT_USING_SERIAL_V2)
+#define BSP_UART8_TX_CPLT_IRQ_NUM       INT001_IRQn
+#define BSP_UART8_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART8 */
+
+#if defined(BSP_USING_UART9)
+#define BSP_UART9_RXERR_IRQ_NUM         INT112_IRQn
+#define BSP_UART9_RXERR_IRQ_PRIO        DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART9_RX_IRQ_NUM            INT110_IRQn
+#define BSP_UART9_RX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART9_TX_IRQ_NUM            INT111_IRQn
+#define BSP_UART9_TX_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART9 */
+
+#if defined(BSP_USING_UART10)
+#define BSP_UART10_RXERR_IRQ_NUM        INT115_IRQn
+#define BSP_UART10_RXERR_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART10_RX_IRQ_NUM           INT114_IRQn
+#define BSP_UART10_RX_IRQ_PRIO          DDL_IRQ_PRIO_DEFAULT
+#define BSP_UART10_TX_IRQ_NUM           INT113_IRQn
+#define BSP_UART10_TX_IRQ_PRIO          DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART10 */
+
+#if defined(BSP_USING_CAN1)
+#define BSP_CAN1_IRQ_NUM                INT092_IRQn
+#define BSP_CAN1_IRQ_PRIO               DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_CAN1 */
+
+#if defined(BSP_USING_CAN2)
+#define BSP_CAN2_IRQ_NUM                INT093_IRQn
+#define BSP_CAN2_IRQ_PRIO               DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_CAN2 */
+
+#if defined(BSP_USING_SDIO1)
+#define BSP_SDIO1_IRQ_NUM               INT004_IRQn
+#define BSP_SDIO1_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_SDIO1 */
+
+#if defined(BSP_USING_SDIO2)
+#define BSP_SDIO2_IRQ_NUM               INT005_IRQn
+#define BSP_SDIO2_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_SDIO2 */
+
+#if defined(RT_USING_ALARM)
+#define BSP_RTC_ALARM_IRQ_NUM           INT050_IRQn
+#define BSP_RTC_ALARM_IRQ_PRIO          DDL_IRQ_PRIO_DEFAULT
+#endif/* RT_USING_ALARM */
+
+
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+#define BSP_USB_GLB_IRQ_NUM             INT003_IRQn
+#define BSP_USB_GLB_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_USBD */
+
+#if defined (BSP_USING_QSPI)
+#define BSP_QSPI_ERR_IRQ_NUM            INT002_IRQn
+#define BSP_QSPI_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_QSPI */
+
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM   INT074_IRQn
+#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM   INT075_IRQn
+#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
+#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM   INT076_IRQn
+#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM   INT077_IRQn
+#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
+#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM   INT080_IRQn
+#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM   INT081_IRQn
+#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
+#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM   INT082_IRQn
+#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM   INT083_IRQn
+#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
+#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM   INT092_IRQn
+#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM   INT093_IRQn
+#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_6)
+#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM   INT094_IRQn
+#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM   INT095_IRQn
+#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_7)
+#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM   INT096_IRQn
+#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM   INT097_IRQn
+#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_8)
+#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM   INT096_IRQn
+#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM   INT097_IRQn
+#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_9)
+#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM   INT098_IRQn
+#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM   INT099_IRQn
+#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_10)
+#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM   INT100_IRQn
+#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM   INT101_IRQn
+#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_11)
+#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM   INT102_IRQn
+#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM   INT103_IRQn
+#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_12)
+#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM   INT102_IRQn
+#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM   INT103_IRQn
+#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */
+
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM   INT056_IRQn
+#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM   INT057_IRQn
+#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
+#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM   INT058_IRQn
+#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM   INT059_IRQn
+#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_3)
+#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM   INT062_IRQn
+#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM   INT063_IRQn
+#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_4)
+#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM   INT068_IRQn
+#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM   INT069_IRQn
+#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_5)
+#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM   INT074_IRQn
+#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM   INT075_IRQn
+#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_6)
+#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM   INT076_IRQn
+#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM   INT077_IRQn
+#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_7)
+#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM   INT080_IRQn
+#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM   INT081_IRQn
+#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_8)
+#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM   INT082_IRQn
+#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM   INT083_IRQn
+#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO  DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */
+
+#if defined(BSP_USING_TMRA_1)
+#define BSP_USING_TMRA_1_IRQ_NUM        INT074_IRQn
+#define BSP_USING_TMRA_1_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_1 */
+#if defined(BSP_USING_TMRA_2)
+#define BSP_USING_TMRA_2_IRQ_NUM        INT075_IRQn
+#define BSP_USING_TMRA_2_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_2 */
+#if defined(BSP_USING_TMRA_3)
+#define BSP_USING_TMRA_3_IRQ_NUM        INT080_IRQn
+#define BSP_USING_TMRA_3_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_3 */
+#if defined(BSP_USING_TMRA_4)
+#define BSP_USING_TMRA_4_IRQ_NUM        INT081_IRQn
+#define BSP_USING_TMRA_4_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_4 */
+#if defined(BSP_USING_TMRA_5)
+#define BSP_USING_TMRA_5_IRQ_NUM        INT092_IRQn
+#define BSP_USING_TMRA_5_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_5 */
+#if defined(BSP_USING_TMRA_6)
+#define BSP_USING_TMRA_6_IRQ_NUM        INT093_IRQn
+#define BSP_USING_TMRA_6_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_6 */
+#if defined(BSP_USING_TMRA_7)
+#define BSP_USING_TMRA_7_IRQ_NUM        INT094_IRQn
+#define BSP_USING_TMRA_7_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_7 */
+#if defined(BSP_USING_TMRA_8)
+#define BSP_USING_TMRA_8_IRQ_NUM        INT095_IRQn
+#define BSP_USING_TMRA_8_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_8 */
+#if defined(BSP_USING_TMRA_9)
+#define BSP_USING_TMRA_9_IRQ_NUM        INT098_IRQn
+#define BSP_USING_TMRA_9_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_9 */
+#if defined(BSP_USING_TMRA_10)
+#define BSP_USING_TMRA_10_IRQ_NUM       INT099_IRQn
+#define BSP_USING_TMRA_10_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_10 */
+#if defined(BSP_USING_TMRA_11)
+#define BSP_USING_TMRA_11_IRQ_NUM       INT100_IRQn
+#define BSP_USING_TMRA_11_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_11 */
+#if defined(BSP_USING_TMRA_12)
+#define BSP_USING_TMRA_12_IRQ_NUM       INT101_IRQn
+#define BSP_USING_TMRA_12_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_12 */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-05-12     CDT          first version
+ */
+
+#ifndef __PM_CONFIG_H__
+#define __PM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PM
+extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
+
+#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
+#define PM_TICKLESS_TIMER_ENABLE_MASK                                          \
+(   (1UL << PM_SLEEP_MODE_IDLE)  |                                             \
+    (1UL << PM_SLEEP_MODE_DEEP))
+#endif
+
+/**
+ * @brief  run mode config @ref pm_run_mode_config structure
+ */
+#ifndef PM_RUN_MODE_CFG
+#define PM_RUN_MODE_CFG                                                        \
+    {                                                                          \
+       .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg                                \
+    }
+#endif /* PM_RUN_MODE_CFG */
+
+/**
+ * @brief  sleep idle config @ref pm_sleep_mode_idle_config structure
+ */
+#ifndef PM_SLEEP_IDLE_CFG
+#define PM_SLEEP_IDLE_CFG                                                      \
+{                                                                              \
+    .pwc_sleep_type = PWC_SLEEP_WFE_INT,                                       \
+}
+#endif /*PM_SLEEP_IDLE_CFG*/
+
+/**
+ * @brief  sleep deep config @ref pm_sleep_mode_deep_config structure
+ */
+#ifndef PM_SLEEP_DEEP_CFG
+#define PM_SLEEP_DEEP_CFG                                                      \
+{                                                                              \
+    {                                                                          \
+        .u16Clock = PWC_STOP_CLK_KEEP,                                         \
+        .u8StopDrv = PWC_STOP_DRV_HIGH,                                        \
+        .u16ExBusHold = PWC_STOP_EXBUS_HIZ,                                    \
+        .u16FlashWait = PWC_STOP_FLASH_WAIT_ON,                                \
+    },                                                                         \
+    .pwc_stop_type = PWC_STOP_WFE_INT,                                         \
+}
+#endif /*PM_SLEEP_DEEP_CFG*/
+
+/**
+ * @brief  sleep standby config @ref pm_sleep_mode_standby_config structure
+ */
+#ifndef PM_SLEEP_STANDBY_CFG
+#define PM_SLEEP_STANDBY_CFG                                                   \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD1,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_STANDBY_CFG*/
+
+/**
+ * @brief  sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
+ */
+#ifndef PM_SLEEP_SHUTDOWN_CFG
+#define PM_SLEEP_SHUTDOWN_CFG                                                  \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD3,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_SHUTDOWN_CFG*/
+
+#endif /* BSP_USING_PM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PM_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-06-15     CDT          first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_QSPI,                                \
+        .clock    = FCG1_PERIPH_QSPI,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_QSPI_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_QSPI_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_QSPI_INTR,                \
+        },                                                  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+
+#ifndef QSPI_INIT_PARAMS
+#define QSPI_INIT_PARAMS                                        \
+    {                                                           \
+        .u32PrefetchMode   = QSPI_PREFETCH_MD_INVD,             \
+        .u32SetupTime      = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5,   \
+        .u32ReleaseTime    = QSPI_QSSN_RELEASE_DELAY_QSCK32,    \
+        .u32IntervalTime   = QSPI_QSSN_INTERVAL_QSCK1,          \
+    }
+#endif /* QSPI_INIT_PARAMS */
+
+#define QSPI_WP_PIN_LEVEL               QSPI_WP_PIN_HIGH
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                     \
+    {                                                       \
+        .Instance       = QSPI_DMA_INSTANCE,                \
+        .channel        = QSPI_DMA_CHANNEL,                 \
+        .clock          = QSPI_DMA_CLOCK,                   \
+        .trigger_select = QSPI_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_AOS_STRG,                 \
+        .flag           = QSPI_DMA_TRANS_FLAG,              \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = QSPI_DMA_IRQn,                    \
+            .irq_prio   = QSPI_DMA_INT_PRIO,                \
+            .int_src    = QSPI_DMA_INT_SRC,                 \
+        }                                                   \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__QSPI_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_SDIO1)
+#ifndef SDIO1_BUS_CONFIG
+#define SDIO1_BUS_CONFIG                                        \
+    {                                                           \
+        .name       = "sdio1",                                  \
+        .instance   = CM_SDIOC1,                                \
+        .clock      = FCG1_PERIPH_SDIOC1,                       \
+        .irq_config =                                           \
+        {                                                       \
+            .irq_num  = BSP_SDIO1_IRQ_NUM,                      \
+            .irq_prio = BSP_SDIO1_IRQ_PRIO,                     \
+            .int_src  = INT_SRC_SDIOC1_SD,                      \
+        },                                                      \
+        .dma_rx =                                               \
+        {                                                       \
+            .Instance       = SDIO1_RX_DMA_INSTANCE,            \
+            .channel        = SDIO1_RX_DMA_CHANNEL,             \
+            .clock          = SDIO1_RX_DMA_CLOCK,               \
+            .trigger_select = SDIO1_RX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC1_DMAR,              \
+        },                                                      \
+        .dma_tx =                                               \
+        {                                                       \
+            .Instance       = SDIO1_TX_DMA_INSTANCE,            \
+            .channel        = SDIO1_TX_DMA_CHANNEL,             \
+            .clock          = SDIO1_TX_DMA_CLOCK,               \
+            .trigger_select = SDIO1_TX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC1_DMAW,              \
+        },                                                      \
+    }
+#endif /* SDIO1_BUS_CONFIG */
+#endif /* BSP_USING_SDIO1 */
+
+#if defined(BSP_USING_SDIO2)
+#ifndef SDIO2_BUS_CONFIG
+#define SDIO2_BUS_CONFIG                                        \
+    {                                                           \
+        .name       = "sdio2",                                  \
+        .instance   = CM_SDIOC2,                                \
+        .clock      = FCG1_PERIPH_SDIOC2,                       \
+        .irq_config =                                           \
+        {                                                       \
+            .irq_num  = BSP_SDIO2_IRQ_NUM,                      \
+            .irq_prio = BSP_SDIO2_IRQ_PRIO,                     \
+            .int_src  = INT_SRC_SDIOC2_SD,                      \
+        },                                                      \
+        .dma_rx =                                               \
+        {                                                       \
+            .Instance       = SDIO2_RX_DMA_INSTANCE,            \
+            .channel        = SDIO2_RX_DMA_CHANNEL,             \
+            .clock          = SDIO2_RX_DMA_CLOCK,               \
+            .trigger_select = SDIO2_RX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC2_DMAR,              \
+        },                                                      \
+        .dma_tx =                                               \
+        {                                                       \
+            .Instance       = SDIO2_TX_DMA_INSTANCE,            \
+            .channel        = SDIO2_TX_DMA_CHANNEL,             \
+            .clock          = SDIO2_TX_DMA_CLOCK,               \
+            .trigger_select = SDIO2_TX_DMA_TRIG_SELECT,         \
+            .trigger_event  = EVT_SRC_SDIOC2_DMAW,              \
+        },                                                      \
+    }
+#endif /* SDIO2_BUS_CONFIG */
+#endif /* BSP_USING_SDIO2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h
@@ -0,0 +1,376 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI1,                                \
+        .bus_name = "spi1",                                 \
+        .clock    = FCG1_PERIPH_SPI1,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI1_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI1_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI1_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_TX_DMA_INSTANCE,             \
+        .channel        = SPI1_TX_DMA_CHANNEL,              \
+        .clock          = SPI1_TX_DMA_CLOCK,                \
+        .trigger_select = SPI1_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPTI,                \
+        .flag           = SPI1_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_RX_DMA_INSTANCE,             \
+        .channel        = SPI1_RX_DMA_CHANNEL,              \
+        .clock          = SPI1_RX_DMA_CLOCK,                \
+        .trigger_select = SPI1_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPRI,                \
+        .flag           = SPI1_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI2,                                \
+        .bus_name = "spi2",                                 \
+        .clock    = FCG1_PERIPH_SPI2,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI2_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI2_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI2_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_TX_DMA_INSTANCE,             \
+        .channel        = SPI2_TX_DMA_CHANNEL,              \
+        .clock          = SPI2_TX_DMA_CLOCK,                \
+        .trigger_select = SPI2_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPTI,                \
+        .flag           = SPI2_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_RX_DMA_INSTANCE,             \
+        .channel        = SPI2_RX_DMA_CHANNEL,              \
+        .clock          = SPI2_RX_DMA_CLOCK,                \
+        .trigger_select = SPI2_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPRI,                \
+        .flag           = SPI2_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI3,                                \
+        .bus_name = "spi3",                                 \
+        .clock    = FCG1_PERIPH_SPI3,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI3_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI3_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI3_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_TX_DMA_INSTANCE,             \
+        .channel        = SPI3_TX_DMA_CHANNEL,              \
+        .clock          = SPI3_TX_DMA_CLOCK,                \
+        .trigger_select = SPI3_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPTI,                \
+        .flag           = SPI3_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_RX_DMA_INSTANCE,             \
+        .channel        = SPI3_RX_DMA_CHANNEL,              \
+        .clock          = SPI3_RX_DMA_CLOCK,                \
+        .trigger_select = SPI3_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPRI,                \
+        .flag           = SPI3_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI4,                                \
+        .bus_name = "spi4",                                 \
+        .clock    = FCG1_PERIPH_SPI4,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI4_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI4_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI4_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_TX_DMA_INSTANCE,             \
+        .channel        = SPI4_TX_DMA_CHANNEL,              \
+        .clock          = SPI4_TX_DMA_CLOCK,                \
+        .trigger_select = SPI4_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPTI,                \
+        .flag           = SPI4_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_RX_DMA_INSTANCE,             \
+        .channel        = SPI4_RX_DMA_CHANNEL,              \
+        .clock          = SPI4_RX_DMA_CLOCK,                \
+        .trigger_select = SPI4_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPRI,                \
+        .flag           = SPI4_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI5,                                \
+        .bus_name = "spi5",                                 \
+        .clock    = FCG1_PERIPH_SPI5,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI5_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI5_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI5_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_TX_DMA_INSTANCE,             \
+        .channel        = SPI5_TX_DMA_CHANNEL,              \
+        .clock          = SPI5_TX_DMA_CLOCK,                \
+        .trigger_select = SPI5_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPTI,                \
+        .flag           = SPI5_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_RX_DMA_INSTANCE,             \
+        .channel        = SPI5_RX_DMA_CHANNEL,              \
+        .clock          = SPI5_RX_DMA_CLOCK,                \
+        .trigger_select = SPI5_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPRI,                \
+        .flag           = SPI5_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI6
+#ifndef SPI6_BUS_CONFIG
+#define SPI6_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI6,                                \
+        .bus_name = "spi6",                                 \
+        .clock    = FCG1_PERIPH_SPI6,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI6_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI6_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI6_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI6_BUS_CONFIG */
+#endif /* BSP_USING_SPI6 */
+
+#ifdef BSP_SPI6_TX_USING_DMA
+#ifndef SPI6_TX_DMA_CONFIG
+#define SPI6_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_TX_DMA_INSTANCE,             \
+        .channel        = SPI6_TX_DMA_CHANNEL,              \
+        .clock          = SPI6_TX_DMA_CLOCK,                \
+        .trigger_select = SPI6_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPTI,                \
+        .flag           = SPI6_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_TX_DMA_CONFIG */
+#endif /* BSP_SPI6_TX_USING_DMA */
+
+#ifdef BSP_SPI6_RX_USING_DMA
+#ifndef SPI6_RX_DMA_CONFIG
+#define SPI6_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_RX_DMA_INSTANCE,             \
+        .channel        = SPI6_RX_DMA_CHANNEL,              \
+        .clock          = SPI6_RX_DMA_CLOCK,                \
+        .trigger_select = SPI6_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPRI,                \
+        .flag           = SPI6_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_RX_DMA_CONFIG */
+#endif /* BSP_SPI6_RX_USING_DMA */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2023-06-21     CDT               first version
+ */
+
+#ifndef __TMR_CONFIG_H__
+#define __TMR_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_TMRA_1
+#ifndef TMRA_1_CONFIG
+#define TMRA_1_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_1,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_1,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_1_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_1_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_1"                          \
+    }
+#endif /* TMRA_1_CONFIG */
+#endif /* BSP_USING_TMRA_1 */
+
+#ifdef BSP_USING_TMRA_2
+#ifndef TMRA_2_CONFIG
+#define TMRA_2_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_2,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_2,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_2_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_2_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_2"                          \
+    }
+#endif /* TMRA_2_CONFIG */
+#endif /* BSP_USING_TMRA_2 */
+
+#ifdef BSP_USING_TMRA_3
+#ifndef TMRA_3_CONFIG
+#define TMRA_3_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_3,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_3,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_3_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_3_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_3"                          \
+    }
+#endif /* TMRA_3_CONFIG */
+#endif /* BSP_USING_TMRA_3 */
+
+#ifdef BSP_USING_TMRA_4
+#ifndef TMRA_4_CONFIG
+#define TMRA_4_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_4,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_4,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_4_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_4_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_4"                          \
+    }
+#endif /* TMRA_4_CONFIG */
+#endif /* BSP_USING_TMRA_4 */
+
+#ifdef BSP_USING_TMRA_5
+#ifndef TMRA_5_CONFIG
+#define TMRA_5_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_5,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_5,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_5_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_5_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_5"                          \
+    }
+#endif /* TMRA_5_CONFIG */
+#endif /* BSP_USING_TMRA_5 */
+
+#ifdef BSP_USING_TMRA_6
+#ifndef TMRA_6_CONFIG
+#define TMRA_6_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_6,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_6,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_6_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_6_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_6"                          \
+    }
+#endif /* TMRA_6_CONFIG */
+#endif /* BSP_USING_TMRA_6 */
+
+#ifdef BSP_USING_TMRA_7
+#ifndef TMRA_7_CONFIG
+#define TMRA_7_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_7,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_7,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_7_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_7_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_7"                          \
+    }
+#endif /* TMRA_7_CONFIG */
+#endif /* BSP_USING_TMRA_7 */
+
+#ifdef BSP_USING_TMRA_8
+#ifndef TMRA_8_CONFIG
+#define TMRA_8_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_8,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_8,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_8_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_8_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_8"                          \
+    }
+#endif /* TMRA_8_CONFIG */
+#endif /* BSP_USING_TMRA_8 */
+
+#ifdef BSP_USING_TMRA_9
+#ifndef TMRA_9_CONFIG
+#define TMRA_9_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_9,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_9,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_9_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_9_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_9"                          \
+    }
+#endif /* TMRA_9_CONFIG */
+#endif /* BSP_USING_TMRA_9 */
+
+#ifdef BSP_USING_TMRA_10
+#ifndef TMRA_10_CONFIG
+#define TMRA_10_CONFIG                                      \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_10,                       \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_10,              \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_10_OVF,              \
+            .enIRQn     = BSP_USING_TMRA_10_IRQ_NUM,        \
+            .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO,       \
+       },                                                   \
+       .name            = "tmra_10"                         \
+    }
+#endif /* TMRA_10_CONFIG */
+#endif /* BSP_USING_TMRA_10 */
+
+#ifdef BSP_USING_TMRA_11
+#ifndef TMRA_11_CONFIG
+#define TMRA_11_CONFIG                                      \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_11,                       \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_11,              \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_11_OVF,              \
+            .enIRQn     = BSP_USING_TMRA_11_IRQ_NUM,        \
+            .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO,       \
+       },                                                   \
+       .name            = "tmra_11"                         \
+    }
+#endif /* TMRA_11_CONFIG */
+#endif /* BSP_USING_TMRA_11 */
+
+#ifdef BSP_USING_TMRA_12
+#ifndef TMRA_12_CONFIG
+#define TMRA_12_CONFIG                                      \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_12,                       \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_12,              \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_12_OVF,              \
+            .enIRQn     = BSP_USING_TMRA_12_IRQ_NUM,        \
+            .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO,       \
+       },                                                   \
+       .name            = "tmra_12"                         \
+    }
+#endif /* TMRA_12_CONFIG */
+#endif /* BSP_USING_TMRA_12 */
+#endif /* __TMR_CONFIG_H__ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __USB_APP_CONF_H__
+#define __USB_APP_CONF_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include "rtconfig.h"
+
+/* USB MODE CONFIGURATION */
+/*
+USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment
+(1) If only defined USB_FS_MODE:
+    MCU USBFS core work in full speed using internal PHY.
+(2) If only defined USB_HS_MODE:
+    MCU USBHS core work in full speed using internal PHY.
+(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY
+    MCU USBHS core work in high speed using external PHY.
+(4) Other combination:
+    Not support, forbid!!
+*/
+
+#if defined(BSP_USING_USBHS)
+#define USB_HS_MODE
+#elif defined(BSP_USING_USBFS)
+#define USB_FS_MODE
+#else
+#define USB_FS_MODE
+#endif
+
+#if defined(BSP_USING_USBD)
+#define USE_DEVICE_MODE
+#elif defined(BSP_USING_USBH)
+#define USE_HOST_MODE
+#else
+#define USE_DEVICE_MODE
+#endif
+
+#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN)
+#define USB_HS_EXTERNAL_PHY
+#endif
+
+#ifndef USB_HS_MODE
+#ifndef USB_FS_MODE
+#error  "USB_HS_MODE or USB_FS_MODE should be defined"
+#endif
+#endif
+
+#ifndef USE_DEVICE_MODE
+#ifndef USE_HOST_MODE
+#error  "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
+#endif
+#endif
+
+#if defined(BSP_USING_USBD)
+/* USB DEVICE FIFO CONFIGURATION */
+#ifdef USB_FS_MODE
+#define RX_FIFO_FS_SIZE                         (128U)
+#define TX0_FIFO_FS_SIZE                        (32U)
+#define TX1_FIFO_FS_SIZE                        (32U)
+#define TX2_FIFO_FS_SIZE                        (32U)
+#define TX3_FIFO_FS_SIZE                        (32U)
+#define TX4_FIFO_FS_SIZE                        (32U)
+#define TX5_FIFO_FS_SIZE                        (32U)
+#define TX6_FIFO_FS_SIZE                        (32U)
+#define TX7_FIFO_FS_SIZE                        (32U)
+#define TX8_FIFO_FS_SIZE                        (32U)
+#define TX9_FIFO_FS_SIZE                        (32U)
+#define TX10_FIFO_FS_SIZE                       (32U)
+#define TX11_FIFO_FS_SIZE                       (32U)
+#define TX12_FIFO_FS_SIZE                       (32U)
+#define TX13_FIFO_FS_SIZE                       (32U)
+#define TX14_FIFO_FS_SIZE                       (32U)
+#define TX15_FIFO_FS_SIZE                       (32U)
+
+#if ((RX_FIFO_FS_SIZE + \
+      TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \
+      TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \
+      TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \
+      TX15_FIFO_FS_SIZE) > 640U)
+#error  "The USB max FIFO size is 640 x 4 Bytes!"
+#endif
+#endif
+
+#ifdef USB_HS_MODE
+#define RX_FIFO_HS_SIZE                         (512U)
+#define TX0_FIFO_HS_SIZE                        (64U)
+#define TX1_FIFO_HS_SIZE                        (64U)
+#define TX2_FIFO_HS_SIZE                        (64U)
+#define TX3_FIFO_HS_SIZE                        (64U)
+#define TX4_FIFO_HS_SIZE                        (64U)
+#define TX5_FIFO_HS_SIZE                        (64U)
+#define TX6_FIFO_HS_SIZE                        (64U)
+#define TX7_FIFO_HS_SIZE                        (64U)
+#define TX8_FIFO_HS_SIZE                        (64U)
+#define TX9_FIFO_HS_SIZE                        (64U)
+#define TX10_FIFO_HS_SIZE                       (64U)
+#define TX11_FIFO_HS_SIZE                       (64U)
+#define TX12_FIFO_HS_SIZE                       (64U)
+#define TX13_FIFO_HS_SIZE                       (64U)
+#define TX14_FIFO_HS_SIZE                       (64U)
+#define TX15_FIFO_HS_SIZE                       (64U)
+
+#if ((RX_FIFO_HS_SIZE + \
+      TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \
+      TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \
+      TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \
+      TX15_FIFO_HS_SIZE) > 2048U)
+#error  "The USB max FIFO size is 2048 x 4 Bytes!"
+#endif
+#endif
+
+#if defined(BSP_USING_USBD_VBUS_SENSING)
+#define VBUS_SENSING_ENABLED
+#endif
+#endif
+
+#if defined(BSP_USING_USBH)
+/* USB HOST FIFO CONFIGURATION */
+#ifdef USB_FS_MODE
+#define RX_FIFO_FS_SIZE                          (128U)
+#define TXH_NP_FS_FIFOSIZ                        (32U)
+#define TXH_P_FS_FIFOSIZ                         (64U)
+
+#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U)
+#error  "The USB max FIFO size is 640 x 4 Bytes!"
+#endif
+#endif
+
+#ifdef USB_HS_MODE
+#define RX_FIFO_HS_SIZE                          (512U)
+#define TXH_NP_HS_FIFOSIZ                        (128U)
+#define TXH_P_HS_FIFOSIZ                         (256U)
+
+#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U)
+#error  "The USB max FIFO size is 2048 x 4 Bytes!"
+#endif
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_APP_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-14     CDT          first version
+ */
+
+#ifndef __USB_BSP_H__
+#define __USB_BSP_H__
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "hc32_ll_utility.h"
+
+extern void usb_udelay(const uint32_t usec);
+extern void usb_mdelay(const uint32_t msec);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __USB_BSP_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/drv_config.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/drv_config.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dma_config.h"
+#include "uart_config.h"
+#include "spi_config.h"
+#include "adc_config.h"
+#include "dac_config.h"
+#include "gpio_config.h"
+#include "eth_config.h"
+#include "can_config.h"
+#include "sdio_config.h"
+#include "pm_config.h"
+#include "i2c_config.h"
+#include "qspi_config.h"
+#include "pulse_encoder_config.h"
+#include "timer_config.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h
@@ -0,0 +1,204 @@
+/**
+ *******************************************************************************
+ * @file  template/source/hc32f4xx_conf.h
+ * @brief This file contains HC32 Series Device Driver Library usage management.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2022-03-31       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32F4XX_CONF_H__
+#define __HC32F4XX_CONF_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include <rtconfig.h>
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @brief This is the list of modules to be used in the Device Driver Library.
+ * Select the modules you need to use to DDL_ON.
+ * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
+ * properly.
+ * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
+ * Library.
+ * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
+ */
+#define LL_ICG_ENABLE                               (DDL_ON)
+#define LL_UTILITY_ENABLE                           (DDL_ON)
+#define LL_PRINT_ENABLE                             (DDL_OFF)
+
+#define LL_ADC_ENABLE                               (DDL_ON)
+#define LL_AES_ENABLE                               (DDL_ON)
+#define LL_AOS_ENABLE                               (DDL_ON)
+#define LL_CAN_ENABLE                               (DDL_ON)
+#define LL_CLK_ENABLE                               (DDL_ON)
+#define LL_CMP_ENABLE                               (DDL_ON)
+#define LL_CRC_ENABLE                               (DDL_ON)
+#define LL_CTC_ENABLE                               (DDL_ON)
+#define LL_DAC_ENABLE                               (DDL_ON)
+#define LL_DBGC_ENABLE                              (DDL_OFF)
+#define LL_DCU_ENABLE                               (DDL_ON)
+#define LL_DMA_ENABLE                               (DDL_ON)
+#define LL_DMC_ENABLE                               (DDL_ON)
+#define LL_DVP_ENABLE                               (DDL_ON)
+#define LL_EFM_ENABLE                               (DDL_ON)
+#define LL_EMB_ENABLE                               (DDL_ON)
+#define LL_ETH_ENABLE                               (DDL_ON)
+#define LL_EVENT_PORT_ENABLE                        (DDL_OFF)
+#define LL_FCG_ENABLE                               (DDL_ON)
+#define LL_FCM_ENABLE                               (DDL_ON)
+#define LL_FMAC_ENABLE                              (DDL_ON)
+#define LL_GPIO_ENABLE                              (DDL_ON)
+#define LL_HASH_ENABLE                              (DDL_ON)
+#define LL_HRPWM_ENABLE                             (DDL_ON)
+#define LL_I2C_ENABLE                               (DDL_ON)
+#define LL_I2S_ENABLE                               (DDL_ON)
+#define LL_INTERRUPTS_ENABLE                        (DDL_ON)
+#define LL_INTERRUPTS_SHARE_ENABLE                  (DDL_ON)
+#define LL_KEYSCAN_ENABLE                           (DDL_ON)
+#define LL_MAU_ENABLE                               (DDL_ON)
+#define LL_MPU_ENABLE                               (DDL_ON)
+#define LL_NFC_ENABLE                               (DDL_ON)
+#define LL_OTS_ENABLE                               (DDL_ON)
+#define LL_PWC_ENABLE                               (DDL_ON)
+#define LL_QSPI_ENABLE                              (DDL_ON)
+#define LL_RMU_ENABLE                               (DDL_ON)
+#define LL_RTC_ENABLE                               (DDL_ON)
+#define LL_SDIOC_ENABLE                             (DDL_ON)
+#define LL_SMC_ENABLE                               (DDL_ON)
+#define LL_SPI_ENABLE                               (DDL_ON)
+#define LL_SRAM_ENABLE                              (DDL_ON)
+#define LL_SWDT_ENABLE                              (DDL_ON)
+#define LL_TMR0_ENABLE                              (DDL_ON)
+#define LL_TMR2_ENABLE                              (DDL_ON)
+#define LL_TMR4_ENABLE                              (DDL_ON)
+#define LL_TMR6_ENABLE                              (DDL_ON)
+#define LL_TMRA_ENABLE                              (DDL_ON)
+#define LL_TRNG_ENABLE                              (DDL_ON)
+#define LL_USART_ENABLE                             (DDL_ON)
+#define LL_USB_ENABLE                               (DDL_ON)
+#define LL_WDT_ENABLE                               (DDL_ON)
+
+/**
+ * @brief The following is a list of currently supported BSP boards.
+ */
+#define BSP_EV_HC32F4A0_LQFP176                     (1U)
+
+/**
+ * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
+ * in use.
+ * The value should be set to one of the list of currently supported BSP boards.
+ * @note  If there is no supported BSP board or the BSP function is not used,
+ * the value needs to be set to 0U.
+ */
+#define BSP_EV_HC32F4XX                             (BSP_EV_HC32F4A0_LQFP176)
+
+/**
+ * @brief This is the list of BSP components to be used.
+ * Select the components you need to use to DDL_ON.
+ */
+#define BSP_24CXX_ENABLE                            (DDL_OFF)
+#define BSP_GT9XX_ENABLE                            (DDL_OFF)
+#define BSP_IS42S16400J7TLI_ENABLE                  (DDL_OFF)
+#define BSP_IS62WV51216_ENABLE                      (DDL_OFF)
+#define BSP_MT29F2G08AB_ENABLE                      (DDL_OFF)
+#define BSP_NT35510_ENABLE                          (DDL_OFF)
+#define BSP_OV5640_ENABLE                           (DDL_OFF)
+#define BSP_TCA9539_ENABLE                          (DDL_OFF)
+#define BSP_W25QXX_ENABLE                           (DDL_OFF)
+#define BSP_WM8731_ENABLE                           (DDL_OFF)
+
+/**
+ * @brief Ethernet and PHY Configuration.
+ */
+/* MAC ADDRESS */
+#define ETH_MAC_ADDR0                               (0x02U)
+#define ETH_MAC_ADDR1                               (0x00U)
+#define ETH_MAC_ADDR2                               (0x00U)
+#define ETH_MAC_ADDR3                               (0x00U)
+#define ETH_MAC_ADDR4                               (0x00U)
+#define ETH_MAC_ADDR5                               (0x00U)
+
+/* Common PHY Registers */
+#define PHY_BCR                                     (0x00U)     /*!< Basic Control Register               */
+#define PHY_BSR                                     (0x01U)     /*!< Basic Status Register                */
+
+#define PHY_SOFT_RESET                              (0x8000U)   /*!< PHY Soft Reset                       */
+#define PHY_LOOPBACK                                (0x4000U)   /*!< Select loop-back mode                */
+#define PHY_FULLDUPLEX_100M                         (0x2100U)   /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M                         (0x2000U)   /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M                          (0x0100U)   /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M                          (0x0000U)   /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION                         (0x1000U)   /*!< Enable auto-negotiation function     */
+#define PHY_POWERDOWN                               (0x0800U)   /*!< Select the power down mode           */
+#define PHY_ISOLATE                                 (0x0400U)   /*!< Isolate PHY from MII                 */
+#define PHY_RESTART_AUTONEGOTIATION                 (0x0200U)   /*!< Restart auto-negotiation function    */
+
+#define PHY_100BASE_TX_FD                           (0x4000U)   /*!< 100Base-TX full duplex support       */
+#define PHY_100BASE_TX_HD                           (0x2000U)   /*!< 100Base-TX half duplex support       */
+#define PHY_10BASE_T_FD                             (0x1000U)   /*!< 10Base-T full duplex support         */
+#define PHY_10BASE_T_HD                             (0x0800U)   /*!< 10Base-T half duplex support         */
+#define PHY_AUTONEGO_COMPLETE                       (0x0020U)   /*!< Auto-Negotiation process completed   */
+#define PHY_LINK_STATUS                             (0x0004U)   /*!< Valid link established               */
+#define PHY_JABBER_DETECTION                        (0x0002U)   /*!< Jabber condition detected            */
+
+#if defined (ETH_PHY_USING_RTL8201F)
+/* PHY(RTL8201F) Address*/
+#define ETH_PHY_ADDR                                (0x00U)
+
+/* PHY Configuration delay(ms) */
+#define ETH_PHY_RST_DELAY                           (0x0080UL)
+#define ETH_PHY_CONFIG_DELAY                        (0x0800UL)
+#define ETH_PHY_RD_TIMEOUT                          (0x0005UL)
+#define ETH_PHY_WR_TIMEOUT                          (0x0005UL)
+
+/* PHY Status Register */
+#define PHY_SR                                      (PHY_BCR)   /*!< PHY status register            */
+
+#define PHY_DUPLEX_STATUS                           (PHY_FULLDUPLEX_10M)    /*!< PHY Duplex mask    */
+#define PHY_SPEED_STATUS                            (PHY_HALFDUPLEX_100M)   /*!< PHY Speed mask     */
+
+#endif
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32F4XX_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.icf
@@ -0,0 +1,115 @@
+/***************************************************************************//**
+ * \file HC32F4A0.icf
+ * \version 1.0
+ *
+ * \brief Linker file for the IAR compiler.
+ *
+********************************************************************************
+* \copyright
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+*******************************************************************************/
+/*###ICF### Section handled by ICF editor, don't touch! *****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+// Check that necessary symbols have been passed to linker via command line interface
+if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
+  error "Link location not defined or not supported!";
+}
+if((!isdefinedsymbol(_HC32F4A0_2M_)) && (!isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) && (!isdefinedsymbol(_HC32F4A0_1M_DUAL_))) {
+  error "Mcu type or size not defined or not supported!";
+}
+
+/*******************************************************************************
+ * Memory address and size definitions
+ ******************************************************************************/
+define symbol ram1_base_address = 0x1FFE0000;
+define symbol ram1_end_address  = 0x2005FFFF;
+
+if(isdefinedsymbol(_LINK_RAM_)) {
+  define symbol ram_start_reserve = 0x20000;
+  define symbol rom1_base_address = ram1_base_address;
+  define symbol rom1_end_address  = rom1_base_address + ram_start_reserve - 0x01;
+  define symbol rom2_base_address = 0x0;
+  define symbol rom2_end_address  = 0x0;
+  define symbol rom3_base_address = 0x0;
+  define symbol rom3_end_address = 0x0;
+} else {
+  define symbol ram_start_reserve = 0x0;
+  define symbol rom1_base_address = 0x0;
+  define symbol rom3_base_address = 0x03000000;
+  define symbol rom3_end_address = 0x030017FF;
+  if (isdefinedsymbol(_HC32F4A0_2M_)) {
+    define symbol rom1_end_address  = 0x001FFFFF;
+    define symbol rom2_base_address = 0x0;
+    define symbol rom2_end_address  = 0x0;
+  } else if (isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) {
+    define symbol rom1_end_address  = 0x000FFFFF;
+    define symbol rom2_base_address = 0x0;
+    define symbol rom2_end_address  = 0x0;
+  } else if (isdefinedsymbol(_HC32F4A0_1M_DUAL_)) {
+    define symbol rom1_end_address  = 0x0007FFFF;
+    define symbol rom2_base_address = 0x00100000;
+    define symbol rom2_end_address  = 0x0017FFFF;
+  }
+}
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
+define symbol __ICFEDIT_region_IROM1_end__   = rom1_end_address;
+define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
+define symbol __ICFEDIT_region_IROM2_end__   = rom2_end_address;
+define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
+define symbol __ICFEDIT_region_IROM3_end__   = rom3_end_address;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__   = ram1_end_address;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__     = 0x2000;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__       = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+/*******************************************************************************
+ * Memory definitions
+ ******************************************************************************/
+define memory mem with size = 4G;
+define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
+                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
+define region OTP_region       =   mem:[from __ICFEDIT_region_IROM3_start__   to __ICFEDIT_region_IROM3_end__];
+define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
+                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in OTP_region   { readonly section .otp_data };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.ld
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.ld
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ */
+/*****************************************************************************/
+/*  File        HC32F4A0xI.ld                                                */
+/*  Abstract    Linker script for HC32F4A0 Device with                       */
+/*              2MByte FLASH, 516KByte RAM                                   */
+/*  Version     V1.0                                                         */
+/*  Date        2022-03-31                                                   */
+/*****************************************************************************/
+
+/* Custom defines, according to section 7.7 of the user manual.
+   Take OTP sector 16 for example. */
+__OTP_DATA_START = 0x03000000;
+__OTP_DATA_SIZE  = 2048;
+__OTP_LOCK_START = 0x03001840;
+__OTP_LOCK_SIZE  = 4;
+
+/* Use contiguous memory regions for simple. */
+MEMORY
+{
+    FLASH       (rx): ORIGIN = 0x00000000, LENGTH = 2M
+    OTP_DATA    (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
+    OTP_LOCK    (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
+    RAM        (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K
+    RAMB       (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        . = ALIGN(4);
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+    } >FLASH
+
+    .icg_sec 0x00000400 :
+    {
+        KEEP(*(.icg_sec))
+    } >FLASH
+
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } >FLASH
+
+    .rodata :
+    {
+        . = ALIGN(4);
+        *(.rodata)
+        *(.rodata*)
+        . = ALIGN(4);
+    } >FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } >FLASH
+    __exidx_end = .;
+
+    .preinit_array :
+    {
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .init_array :
+    {
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .fini_array :
+    {
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    __etext = ALIGN(4);
+
+    .otp_data_sec :
+    {
+        KEEP(*(.otp_data_sec))
+    } >OTP_DATA
+
+    .otp_lock_sec :
+    {
+        KEEP(*(.otp_lock_sec))
+    } >OTP_LOCK
+
+    .data : AT (__etext)
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+        *(vtable)
+        *(.data)
+        *(.data*)
+        *(.gnu.linkonce.d*)
+        . = ALIGN(4);
+        *(.ramfunc)
+        *(.ramfunc*)
+        . = ALIGN(4);
+        __data_end__ = .;
+    } >RAM
+
+    .heap_stack (COPY) :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        *(.heap*)
+        . = ALIGN(8);
+        __HeapLimit = .;
+
+        __StackLimit = .;
+        *(.stack*)
+        . = ALIGN(8);
+        __StackTop = .;
+    } >RAM
+
+    __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
+    .ramb_data : AT (__etext_ramb)
+    {
+        . = ALIGN(4);
+        __data_start_ramb__ = .;
+        *(.ramb_data)
+        *(.ramb_data*)
+        . = ALIGN(4);
+        __data_end_ramb__ = .;
+    } >RAMB
+
+    __bss_start = .;
+    .bss __StackTop (NOLOAD):
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        __bss_start__ = _sbss;
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+        __bss_end__ = _ebss;
+        . = ALIGN(4);
+        *(.noinit*)
+        . = ALIGN(4);
+    } >RAM
+    __bss_end = .;
+
+    .ramb_bss :
+    {
+        . = ALIGN(4);
+        __bss_start_ramb__ = .;
+        *(.ramb_bss)
+        *(.ramb_bss*)
+        . = ALIGN(4);
+        __bss_end_ramb__ = .;
+    } >RAMB
+
+    /DISCARD/ :
+    {
+        libc.a (*)
+        libm.a (*)
+        libgcc.a (*)
+    }
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+
+    PROVIDE(_stack = __StackTop);
+    PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
+    PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
+
+    __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
+    ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.sct
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/linker_scripts/link.sct
@@ -0,0 +1,22 @@
+; ****************************************************************
+; Scatter-Loading Description File
+; ****************************************************************
+LR_IROM1 0x00000000 0x00200000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x00200000  {  ; load address = execution address
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+        .ANY (+XO)
+    }
+    RW_IRAM1 0x1FFE0000 UNINIT 0x00000008  {  ; RW data
+        *(.bss.noinit)
+    }
+    RW_IRAM2 0x1FFE0008 0x0007FFF8  {  ; RW data
+        .ANY (+RW +ZI)
+        .ANY (RAMCODE)
+    }
+    RW_IRAMB 0x200F0000 0x00001000  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+}
+
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/SConscript
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/SConscript
@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/drv_spi_flash.c
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/drv_spi_flash.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <board.h>
+#include <drv_spi.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <finsh.h>
+#include <dfs_fs.h>
+#include <fal.h>
+
+#ifdef BSP_USING_SPI_FLASH
+
+#include "spi_flash.h"
+#ifdef RT_USING_SFUD
+    #include "spi_flash_sfud.h"
+#endif
+
+#define SPI_BUS_NAME                    "spi1"
+#define SPI_FLASH_DEVICE_NAME           "spi10"
+#define SPI_FLASH_CHIP                  "w25q64"
+#define SPI_FLASH_SS_PORT               GPIO_PORT_A
+#define SPI_FLASH_SS_PIN                GPIO_PIN_04
+/* Partition Name */
+#define FS_PARTITION_NAME              "filesystem"
+
+#ifdef RT_USING_SFUD
+static void rt_hw_spi_flash_reset(char *spi_dev_name)
+{
+    struct rt_spi_device *spi_dev_w25;
+    rt_uint8_t w25_en_reset = 0x66;
+    rt_uint8_t w25_reset_dev = 0x99;
+
+    spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
+    if (!spi_dev_w25)
+    {
+        rt_kprintf("Can't find %s device!\n", spi_dev_name);
+    }
+    else
+    {
+        rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
+        rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
+        DDL_DelayMS(1U);
+        rt_kprintf("Reset ext flash!\n");
+    }
+}
+
+static int rt_hw_spi_flash_with_sfud_init(void)
+{
+    rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN);
+
+    if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+    {
+        rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
+        if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
+        {
+            return -RT_ERROR;
+        }
+    }
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
+
+static int rt_hw_fs_init(void)
+{
+    struct rt_device *mtd_dev = RT_NULL;
+
+    /* 初始化 fal */
+    fal_init();
+    /* 生成 mtd 设备 */
+    mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
+    if (!mtd_dev)
+    {
+        LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
+        return -RT_ERROR;
+    }
+    else
+    {
+        /* 挂载 littlefs */
+        if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+        {
+            LOG_I("Filesystem initialized!");
+            return RT_EOK;
+        }
+        else
+        {
+            /* 格式化文件系统 */
+            if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
+            {
+                /* 挂载 littlefs */
+                if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
+                {
+                    LOG_I("Filesystem initialized!");
+                    return RT_EOK;
+                }
+                else
+                {
+                    LOG_E("Failed to initialize filesystem!");
+                    return -RT_ERROR;
+                }
+            }
+            else
+            {
+                LOG_E("Failed to Format fs!");
+                return -RT_ERROR;
+            }
+        }
+    }
+}
+INIT_APP_EXPORT(rt_hw_fs_init);
+
+#endif /* RT_USING_SFUD */
+
+#endif /* BSP_USING_SPI_FLASH */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/SConscript
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/SConscript
@@ -0,0 +1,20 @@
+
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src = []
+
+src     += Glob('*.c')
+CPPPATH = [cwd]
+LOCAL_CFLAGS = ''
+
+if rtconfig.PLATFORM in ['gcc', 'armclang']:
+    LOCAL_CFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM in ['armcc']:
+    LOCAL_CFLAGS += ' --c99'
+
+group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_cfg.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_cfg.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+/* enable hc32f4 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_HC32F4
+/* enable SFUD flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev hc32_onchip_flash;
+extern struct fal_flash_dev ext_nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &hc32_onchip_flash,                                              \
+    &ext_nor_flash0,                                                 \
+}
+
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                                 \
+{                                                                                      \
+    {FAL_PART_MAGIC_WROD,          "app",   "onchip_flash",   0,  2 * 1024 * 1024, 0}, \
+    {FAL_PART_MAGIC_WROD,   "filesystem",         "w25q64",   0,  8 * 1024 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_flash_sfud_port.c
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal/fal_flash_sfud_port.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <fal.h>
+
+#include <sfud.h>
+#ifdef RT_USING_SFUD
+    #include <spi_flash_sfud.h>
+#endif
+
+#ifndef FAL_USING_NOR_FLASH_DEV_NAME
+    #define FAL_USING_NOR_FLASH_DEV_NAME            "w25q64"
+#endif
+
+static int init(void);
+static int read(long offset, uint8_t *buf, size_t size);
+static int write(long offset, const uint8_t *buf, size_t size);
+static int erase(long offset, size_t size);
+
+static sfud_flash_t sfud_dev = NULL;
+struct fal_flash_dev ext_nor_flash0 =
+{
+    .name       = FAL_USING_NOR_FLASH_DEV_NAME,
+    .addr       = 0,
+    .len        = 8 * 1024 * 1024,
+    .blk_size   = 4096,
+    .ops        = {init, read, write, erase},
+    .write_gran = 1
+};
+
+static int init(void)
+{
+    /* RT-Thread RTOS platform */
+    sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
+    if (NULL == sfud_dev)
+    {
+        return -1;
+    }
+    /* update the flash chip information */
+    ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
+    ext_nor_flash0.len      = sfud_dev->chip.capacity;
+
+    return 0;
+}
+
+static int read(long offset, uint8_t *buf, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
+
+    return size;
+}
+
+static int write(long offset, const uint8_t *buf, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}
+
+static int erase(long offset, size_t size)
+{
+    assert(sfud_dev);
+    assert(sfud_dev->init_ok);
+    if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
+    {
+        return -1;
+    }
+
+    return size;
+}
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-03-01     CDT          first version
+ */
+
+#ifndef __NAND_PORT_H__
+#define __NAND_PORT_H__
+
+/******************** NAND chip information ***********************************/
+#define NAND_BYTES_PER_PAGE             2048UL
+#define NAND_SPARE_AREA_SIZE            64UL
+#define NAND_PAGES_PER_BLOCK            64UL
+#define NAND_BYTES_PER_BLOCK            (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE)
+#define NAND_BLOCKS_PER_PLANE           1024UL
+#define NAND_PLANE_PER_DEVICE           2UL
+#define NAND_DEVICE_BLOCKS              (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE)
+#define NAND_DEVICE_PAGES               (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK)
+
+/******************** EXMC_NFC configure **************************************/
+/* chip: EXMC_NFC_BANK0~7 */
+#define NAND_EXMC_NFC_BANK              EXMC_NFC_BANK0
+
+/* density:2Gbit */
+#define NAND_EXMC_NFC_BANK_CAPACITY     EXMC_NFC_BANK_CAPACITY_2GBIT
+
+/* device width: 8-bit */
+#define NAND_EXMC_NFC_MEMORY_WIDTH      EXMC_NFC_MEMORY_WIDTH_8BIT
+
+/* page size: 2KByte */
+#define NAND_EXMC_NFC_PAGE_SIZE         EXMC_NFC_PAGE_SIZE_2KBYTE
+
+/* row address cycle: 3 */
+#define NAND_EXMC_NFC_ROW_ADDR_CYCLE    EXMC_NFC_3_ROW_ADDR_CYCLE
+
+/* ECC mode */
+#define NAND_EXMC_NFC_ECC_MD            EXMC_NFC_1BIT_ECC
+
+/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */
+/* TS: ALE/CLE/CE setup time(min=10ns) */
+#define NAND_TS                         1U
+
+/* TWP: WE# pulse width (min=10ns) */
+#define NAND_TWP                        1U
+
+/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */
+#define NAND_TRP                        2U
+
+/* TTH: ALE/CLE/CE hold time (min=5ns) */
+#define NAND_TH                         1U
+
+/* TWH: WE# pulse width HIGH (min=10ns) */
+#define NAND_TWH                        1U
+
+/* TRH: RE# pulse width HIGH (min=7ns) */
+#define NAND_TRH                        1U
+
+/* TRR: Ready to RE# LOW (min=20ns) */
+#define NAND_TRR                        2U
+
+/* TWB: WE# HIGH to busy (max=100ns) */
+#define NAND_TWB                        1U
+
+/* TWB: WE# HIGH to busy (max=100ns) */
+#define NAND_TRB                        1U
+
+/* TCCS: Change read column and Change write column delay */
+#define NAND_TCCS                       5U
+
+/* TWTR: WE# HIGH to RE# LOW (min=60ns) */
+#define NAND_TWTR                       4U
+
+/* TRTW: RE# HIGH to WE# LOW (min=100ns) */
+#define NAND_TRTW                       7U
+
+/* TADL: ALE to data start (min=70ns) */
+#define NAND_TADL                       5U
+
+#endif
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-02-24     CDT          first version
+ * 2024-02-20     CDT          modify timing configuration for using exclk clock frequency 30MHz
+ *                             add t_rcd/t_rfc/t_rp configuration macros-definition
+ */
+
+#ifndef __SDRAM_PORT_H__
+#define __SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+
+/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */
+#define SDRAM_CHIP                      EXMC_DMC_CHIP1
+/* bank address */
+#define SDRAM_BANK_ADDR                 (0x80000000UL)
+/* size(kbyte):8MB = 8*1024*1KBytes */
+#define SDRAM_SIZE                      (8UL * 1024UL * 1024UL)
+/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */
+#define SDRAM_AUTO_PRECHARGE_PIN        EXMC_DMC_AUTO_PRECHARGE_A10
+/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */
+#define SDRAM_DATA_WIDTH                EXMC_DMC_MEMORY_WIDTH_16BIT
+/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */
+#define SDRAM_COLUMN_BITS               EXMC_DMC_COLUMN_BITS_NUM8
+/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */
+#define SDRAM_ROW_BITS                  EXMC_DMC_ROW_BITS_NUM12
+/* cas latency clock number: 2, 3 */
+#define SDRAM_CAS_LATENCY               2UL
+/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */
+#define SDRAM_BURST_LENGTH              EXMC_DMC_BURST_1BEAT
+
+/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */
+#define SDRAM_MODEREG_OPERATING_MODE    SDRAM_MODEREG_OPERATING_MODE_STANDARD
+/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */
+#define SDRAM_MODEREG_BURST_TYPE        SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL
+/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */
+#define SDRAM_MODEREG_WRITEBURST_MODE   SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED
+
+/* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */
+/* refresh rate counter (EXCLK clock) */
+#define SDRAM_REFRESH_COUNT             (450U)
+/* TMDR: mode register command time (EXCLK clock) */
+#define SDRAM_TMDR                      2U
+/* TRAS: RAS to precharge delay time (EXCLK clock) */
+#define SDRAM_TRAS                      2U
+/* TRC:  active bank x to active bank x delay time (EXCLK clock) */
+#define SDRAM_TRC                       2U
+/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */
+#define SDRAM_TRCD_B                    3U
+#define SDRAM_TRCD_P                    0U
+/* TRFC: autorefresh command time (EXCLK clock) */
+#define SDRAM_TRFC_B                    3U
+#define SDRAM_TRFC_P                    0U
+/* TRP:  precharge to RAS delay time (EXCLK clock) */
+#define SDRAM_TRP_B                     3U
+#define SDRAM_TRP_P                     0U
+/* TRRD: active bank x to active bank y delay time (EXCLK clock) */
+#define SDRAM_TRRD                      1U
+/* TWR: write to precharge delay time (EXCLK clock). */
+#define SDRAM_TWR                       2U
+/* TWTR: write to read delay time (EXCLK clock). */
+#define SDRAM_TWTR                      1U
+/* TXP: exit power-down command time (EXCLK clock). */
+#define SDRAM_TXP                       1U
+/* TXSR: exit self-refresh command time (EXCLK clock). */
+#define SDRAM_TXSR                      5U
+/* TESR: self-refresh command time (EXCLK clock). */
+#define SDRAM_TESR                      5U
+
+/* memory mode register */
+#define SDRAM_MODEREG_BURST_LENGTH_1              (0x0000U)
+#define SDRAM_MODEREG_BURST_LENGTH_2              (0x0001U)
+#define SDRAM_MODEREG_BURST_LENGTH_4              (0x0002U)
+#define SDRAM_MODEREG_BURST_LENGTH_8              (0x0004U)
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL       (0x0000U)
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED      (0x0008U)
+#define SDRAM_MODEREG_CAS_LATENCY_2               (0x0020U)
+#define SDRAM_MODEREG_CAS_LATENCY_3               (0x0030U)
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD     (0x0000U)
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED  (0x0000U)
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE      (0x0200U)
+
+#endif
--- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.c
+++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rtdbg.h>
+
+#ifdef BSP_USING_TCA9539
+
+#include "tca9539.h"
+
+/*******************************************************************************
+ * Local type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+/* Define for TCA9539 */
+#define BSP_TCA9539_I2C_BUS_NAME        "i2c1"
+#define BSP_TCA9539_DEV_ADDR            (0x74U)
+
+#define TCA9539_RST_PIN                 (45)    /* PC13 */
+
+/*******************************************************************************
+ * Global variable definitions (declared in header file with 'extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local function prototypes ('static')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Local variable definitions ('static')
+ ******************************************************************************/
+static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
+
+/*******************************************************************************
+ * Function implementation - global ('extern') and local ('static')
+ ******************************************************************************/
+/**
+ * @brief  BSP TCA9539 write data.
+ * @param  [in] bus:                    Pointer to the i2c bus device.
+ * @param  [in] reg:                    Register to be written.
+ * @param  [in] data:                   The pointer to the buffer contains the data to be written.
+ * @param  [in] len:                    Buffer size in byte.
+ * @retval rt_err_t:
+ *           - RT_EOK
+ *           - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+    struct rt_i2c_msg msgs;
+    rt_uint8_t buf[6];
+
+    buf[0] = reg;
+    if (len > 0)
+    {
+        if (len < 6)
+        {
+            rt_memcpy(buf + 1, data, len);
+        }
+        else
+        {
+            return -RT_ERROR;
+        }
+    }
+    msgs.addr   = BSP_TCA9539_DEV_ADDR;
+    msgs.flags  = RT_I2C_WR;
+    msgs.buf    = buf;
+    msgs.len    = len + 1;
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+}
+
+/**
+ * @brief  BSP TCA9539 Read data.
+ * @param  [in] bus:                    Pointer to the i2c bus device.
+ * @param  [in] reg:                    Register to be read.
+ * @param  [out] data:                  The pointer to the buffer contains the data to be read.
+ * @param  [in] len:                    Buffer size in byte.
+ * @retval rt_err_t:
+ *           - RT_EOK
+ *           - -RT_ERROR
+ */
+static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
+{
+    struct rt_i2c_msg msgs;
+
+    if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0))
+    {
+        return -RT_ERROR;
+    }
+    msgs.addr   = BSP_TCA9539_DEV_ADDR;
+    msgs.flags  = RT_I2C_RD;
+    msgs.buf    = data;
+    msgs.len    = len;
+    if (rt_i2c_transfer(bus, &msgs, 1) == 1)
+    {
+        return RT_EOK;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+}
+
+
+/**
+ * @brief  Reset TCA9539.
+ * @param  [in] None
+ * @retval None
+ */
+static void TCA9539_Reset(void)
+{
+    rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT);
+    /* Reset the device */
+    rt_pin_write(TCA9539_RST_PIN, PIN_LOW);
+    rt_thread_mdelay(3U);
+    rt_pin_write(TCA9539_RST_PIN, PIN_HIGH);
+}
+
+/**
+ * @brief  Write TCA9539 pin output value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8PinState              Pin state to be written.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    if (0U == u8PinState)
+    {
+        u8TempData[1] &= (uint8_t)(~u8Pin);
+    }
+    else
+    {
+        u8TempData[1] |= u8Pin;
+    }
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Read TCA9539 pin input value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8PinState              Pin state to be written.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Pin_State_Definition
+ * @retval rt_err_t:
+ *           - RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    if (0U != (u8TempData[1] & u8Pin))
+    {
+        *pu8PinState = TCA9539_PIN_SET;
+    }
+    else
+    {
+        *pu8PinState = TCA9539_PIN_RESET;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Toggle TCA9539 pin output value.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @retval rt_err_t:
+ *           - -RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    u8TempData[1] ^= u8Pin;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Configuration TCA9539 pin.
+ * @param  [in] u8Port                  Port number.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Port_Definition
+ * @param  [in] u8Pin                   Pin number.
+ *         This parameter can be one or any combination of the following values:
+ *           @arg @ref TCA9539_Pin_Definition
+ * @param  [in] u8Dir                   Pin output direction.
+ *         This parameter can be one of the following values:
+ *           @arg @ref TCA9539_Direction_Definition
+ * @retval rt_err_t:
+ *           - -RT_ERROR
+ *           - RT_EOK
+ */
+rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
+{
+    uint8_t u8TempData[2];
+
+    u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
+    if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    if (TCA9539_DIR_OUT == u8Dir)
+    {
+        u8TempData[1] &= (uint8_t)(~u8Pin);
+    }
+    else
+    {
+        u8TempData[1] |= u8Pin;
+    }
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * @brief  Initialize TCA9539.
+ * @param  [in] None
+ * @retval rt_err_t:
+ *           - -RT_ERROR
+ *           - RT_EOK
+ */
+int TCA9539_Init(void)
+{
+    char name[RT_NAME_MAX];
+    uint8_t u8TempData[2];
+
+    TCA9539_Reset();
+    rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX);
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
+    if (i2c_bus == RT_NULL)
+    {
+        rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME);
+        return -RT_ERROR;
+    }
+    /* All Pins are input as default */
+    u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
+    u8TempData[1] = 0xFFU;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+    u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
+    if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+INIT_PREV_EXPORT(TCA9539_Init);
+
+#endif /* BSP_USING_TCA9539 */
--- a/Show More
+++ b/Show More