mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-02 14:23:19 +08:00
[BSP][HC32]add lckfb-hc32f4a0-lqfp100 (#9119)
* -以ev_hc32f4a0_lqfp176为模板进行修改 * -修改对应引脚 * -更新readme * -update readme * -添加 lckfb-hc32f4a0-lqfp100
This commit is contained in:
yuanzihao
@@ -87,6 +87,7 @@ jobs:
|
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- "hc32/ev_hc32f448_lqfp80"
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- "hc32/ev_hc32f460_lqfp100_v2"
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- "hc32/ev_hc32f472_lqfp100"
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- "hc32/lckfb-hc32f4a0-lqfp100"
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- "hc32l196"
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- "mm32/mm32f3270-100ask-pitaya"
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- "mm32f327x"
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@@ -11,6 +11,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
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| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
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| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 |
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| [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 |
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| [lckfb-hc32f4a0-lqfp100](lckfb-hc32f4a0-lqfp100) | 立创开发板 天空星-HC32F4A0PITB |
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| **M1 系列** | |
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| **M4 系列** | |
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File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,42 @@
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*.pyc
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||||
*.map
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*.dblite
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*.elf
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*.bin
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||||
*.hex
|
||||
*.axf
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||||
*.exe
|
||||
*.pdb
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*.idb
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*.ilk
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*.old
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build
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Debug
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documentation/html
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packages/
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*~
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*.o
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||||
*.obj
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||||
*.out
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*.bak
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*.dep
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||||
*.lib
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||||
*.i
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*.d
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.DS_Stor*
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.config 3
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.config 4
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.config 5
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||||
Midea-X1
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*.uimg
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GPATH
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GRTAGS
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GTAGS
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.vscode
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JLinkLog.txt
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JLinkSettings.ini
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DebugConfig/
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RTE/
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settings/
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*.uvguix*
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cconfig.h
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@@ -0,0 +1,68 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>project</name>
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<comment />
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<projects>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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<triggers>clean,full,incremental,</triggers>
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||||
<arguments>
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||||
</arguments>
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</buildCommand>
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<buildCommand>
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||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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<triggers>full,incremental,</triggers>
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||||
<arguments>
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||||
</arguments>
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</buildCommand>
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</buildSpec>
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<natures>
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||||
<nature>org.eclipse.cdt.core.cnature</nature>
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<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
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<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
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</natures>
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<linkedResources>
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<link>
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<name>rt-thread</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/components</name>
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<type>2</type>
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<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
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</link>
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<link>
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<name>rt-thread/include</name>
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<type>2</type>
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<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
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</link>
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<link>
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<name>rt-thread/libcpu</name>
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<type>2</type>
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<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
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</link>
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<link>
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<name>rt-thread/src</name>
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<type>2</type>
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<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/libraries</name>
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<type>2</type>
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||||
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
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||||
</link>
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</linkedResources>
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</projectDescription>
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@@ -0,0 +1,12 @@
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mainmenu "RT-Thread Configuration"
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BSP_DIR := .
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RTT_DIR := ../../..
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PKGS_DIR := packages
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source "$(RTT_DIR)/Kconfig"
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osource "$PKGS_DIR/Kconfig"
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rsource "../libraries/Kconfig"
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rsource "board/Kconfig"
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@@ -0,0 +1,97 @@
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# lckfb-hc32f4a0-lqfp100立创天空星开发板BSP说明
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## 简介
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该开发板是由立创开发板精心打造的一款高性价比的开发工具，**软硬件全开源**。设计上充分考虑了与多种100脚封装的单片机的兼容性。这种设计使得它不仅适用于特定的芯片，还能够适配市场上多种不同厂家生产的100脚微控制器，极大地提高了适用范围和灵活性。该BSP适配立创梁山派·天空星开发板的主控芯片为**HC32F4A0PITB**。
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为了最大限度的方便开发者和爱好者，该核心板通过排针将所有可用的IO（输入/输出）引脚都引出，这样大家就可以轻松地连接各种外部模块和设备，无需进行复杂的焊接工作。这一特点特别适合那些需要快速原型制作和迭代的场合，如学生电子竞赛、创客活动以及个人DIY项目。
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此外，这款核心板的设计考虑到了大家在电子竞赛中对于稳定性和可靠性的需求，以及在小型项目开发中对低成本的追求。具体请看硬件设计手册。
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](figures/board.png)
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## 资料罗列：
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* [硬件开源地址](https://oshwhub.com/li-chuang-kai-fa-ban/li-chuang-liang-shan-pai-tian-kong-xing-kai-fa-ban)
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* [硬件文档](https://lceda001.feishu.cn/wiki/D4cqwUkiTi6723knO2cczSThnYb)
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||||
* [入门手册](https://lceda001.feishu.cn/wiki/MqcKwTiJ2isvASk5xQzcdeUJnOb)
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||||
* [模块移植手册](https://lceda001.feishu.cn/wiki/RvtIwNuQ6iVhqvk4cELcr1vPncQ)
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* [购买地址](https://lckfb.com/project/detail/lckfb-lspi-skystar-hc32f4a0pitb-lite?param=baseInfo)
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## 外设支持
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本 BSP 目前对外设的支持情况如下：
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| **片上外设** | **支持情况** | **备注** |
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| :----------- | :----------: | :------------------------------ |
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| GPIO | 支持 | PA0, PA1... ---> PIN: 0, 1...81 |
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| UART | 支持 | UART0 - UART6 |
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| I2C | 支持 | I2C1 |
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| SPI | 支持 | SPI0 - SPI2 |
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| ADC | 支持 | ADC0 - ADC2 |
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| TF CARD | 支持 | SDIO1 |
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| SPI FLASH | 暂不支持 | |
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| **扩展模块** | **支持情况** | **备注** |
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| 暂无 | 暂不支持 | 暂不支持 |
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## 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 快速上手
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本 BSP 为开发者提供 MDK4、MDK5 工程，并且支持 GCC 开发环境，也可使用RT-Thread Studio开发。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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#### 硬件连接
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使用数据线连接开发板到 PC，使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)，上电。
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#### 编译下载
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双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
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> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板
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#### 运行结果
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下载程序成功之后，系统会自动运行，LED 闪烁。
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连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
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```bash
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\ | /
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||||
- RT - Thread Operating System
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/ | \ 5.2.0 build Jun 28 2024 16:55:59
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2006 - 2024 Copyright by RT-Thread team
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```
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### 进阶使用
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此 BSP 默认只开启了 GPIO 和 串口0的功能，如果需使用高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
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1. 在 bsp 下打开 env 工具。
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2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
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3. 输入`pkgs --update`命令更新软件包。
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4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
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## 注意事项
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暂无
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||||
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## 联系人信息
|
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|
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维护人:
|
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|
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- [yuanzihao](https://github.com/zihao-yuan/), 邮箱：[y@yzh.email](mailto:y@yzh.email)
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@@ -0,0 +1,15 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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|
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,62 @@
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import os
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import sys
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import rtconfig
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|
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
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|
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
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exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
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||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
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|
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Export('RTT_ROOT')
|
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Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
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|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
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libraries_path_prefix = SDK_ROOT + '/libraries'
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else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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||||
|
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# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
hc32_library = 'hc32f4a0_ddl'
|
||||
rtconfig.BSP_LIBRARY_TYPE = hc32_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
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@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
* 2024-06-28 yuanzihao adaptation for SkyStar HC32F4A0PITB version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED_GREEN pin: PB2 */
|
||||
#define LED_GREEN_PIN GET_PIN(B, 2)
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED_GREEN_PIN pin mode to output */
|
||||
rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-10-27 CDT first version
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
* This thread only runs once after the system starts.
|
||||
* When stability is detected or 2s times out, the thread will end.
|
||||
* (When a timeout occurs it will be prompted via rt_kprintf)
|
||||
*/
|
||||
void xtal32_fcm_thread_entry(void *parameter)
|
||||
{
|
||||
stc_fcm_init_t stcFcmInit;
|
||||
uint32_t u32TimeOut = 0UL;
|
||||
uint32_t u32Time = 200UL; /* 200*10ms = 2s */
|
||||
|
||||
/* FCM config */
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
|
||||
(void)FCM_StructInit(&stcFcmInit);
|
||||
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
|
||||
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
}
|
||||
}
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
int xtal32_fcm_thread_create(void)
|
||||
{
|
||||
rt_thread_t tid;
|
||||
|
||||
tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
|
||||
XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("create xtal32_fcm thread err!");
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_APP_EXPORT(xtal32_fcm_thread_create);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,38 @@
|
||||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
if GetDepend(['BSP_USING_TCA9539']):
|
||||
src += Glob('ports/tca9539.c')
|
||||
|
||||
if GetDepend(['BSP_USING_SPI_FLASH']):
|
||||
src += Glob('ports/drv_spi_flash.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
path += [cwd + '/config/usb_config']
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f4a0.S']
|
||||
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f4a0.s']
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src += [startup_path_prefix + '/hc32f4a0_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f4a0.s']
|
||||
|
||||
CPPDEFINES = ['HC32F4A0', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,165 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "board_config.h"
|
||||
|
||||
/* unlock/lock peripheral */
|
||||
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
|
||||
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
|
||||
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
/**
|
||||
* @brief Switch clock stable time
|
||||
* @note Approx. 30us
|
||||
*/
|
||||
#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL)
|
||||
/**
|
||||
* @brief Clk delay function
|
||||
* @param [in] u32Delay count
|
||||
* @retval when switch clock source, should be delay some time to wait stable.
|
||||
*/
|
||||
static void CLK_Delay(uint32_t u32Delay)
|
||||
{
|
||||
__IO uint32_t u32Timeout = 0UL;
|
||||
|
||||
while (u32Timeout < u32Delay)
|
||||
{
|
||||
u32Timeout++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/** System Base Configuration
|
||||
*/
|
||||
void SystemBase_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
|
||||
EFM_ICacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
|
||||
EFM_DCacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
|
||||
EFM_PrefetchCmd(ENABLE);
|
||||
#endif
|
||||
/* Reset the VBAT area */
|
||||
PWC_VBAT_Reset();
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
stc_clock_xtal_init_t stcXtalInit;
|
||||
stc_clock_pll_init_t stcPLLHInit;
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
stc_clock_pllx_init_t stcPLLAInit;
|
||||
#endif
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
stc_clock_xtal32_init_t stcXtal32Init;
|
||||
#endif
|
||||
|
||||
/* PCLK0, HCLK Max 240MHz */
|
||||
/* PCLK1, PCLK4 Max 120MHz */
|
||||
/* PCLK2, PCLK3 Max 60MHz */
|
||||
/* EX BUS Max 120MHz */
|
||||
CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
|
||||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
|
||||
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
|
||||
CLK_HCLK_DIV1));
|
||||
|
||||
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
|
||||
(void)CLK_XtalStructInit(&stcXtalInit);
|
||||
/* Config Xtal and enable Xtal */
|
||||
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
|
||||
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
|
||||
stcXtalInit.u8State = CLK_XTAL_ON;
|
||||
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
|
||||
(void)CLK_XtalInit(&stcXtalInit);
|
||||
|
||||
(void)CLK_PLLStructInit(&stcPLLHInit);
|
||||
/* VCO = (8/1)*120 = 960MHz*/
|
||||
stcPLLHInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLHInit.PLLCFGR = 0UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
|
||||
(void)CLK_PLLInit(&stcPLLHInit);
|
||||
|
||||
/* Highspeed SRAM set to 0 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
|
||||
/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
|
||||
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
|
||||
/* 0-wait @ 40MHz */
|
||||
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
|
||||
/* 4 cycles for 200 ~ 250MHz */
|
||||
GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
/* PLLX for USB */
|
||||
(void)CLK_PLLxStructInit(&stcPLLAInit);
|
||||
/* VCO = (8/2)*120 = 480MHz*/
|
||||
stcPLLAInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLAInit.PLLCFGR = 0UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
(void)CLK_PLLxInit(&stcPLLAInit);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
/* Xtal32 config */
|
||||
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
|
||||
(void)CLK_Xtal32StructInit(&stcXtal32Init);
|
||||
stcXtal32Init.u8State = CLK_XTAL32_ON;
|
||||
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
|
||||
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
|
||||
(void)CLK_Xtal32Init(&stcXtal32Init);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Clock Configuration
|
||||
*/
|
||||
void PeripheralClock_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1)
|
||||
CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
#if defined(BSP_USING_CAN2)
|
||||
CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
|
||||
CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP);
|
||||
/* Wait stable here, since the current DDL API does not include this */
|
||||
CLK_Delay(CLK_SYSCLK_SW_STB);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Registers Unlock
|
||||
*/
|
||||
void PeripheralRegister_Unlock(void)
|
||||
{
|
||||
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_SIZE (2 * 1024 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
||||
#define HC32_SRAM_SIZE (512)
|
||||
#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM2$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
void PeripheralRegister_Unlock(void);
|
||||
void PeripheralClock_Config(void);
|
||||
void SystemBase_Config(void);
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_INIT_PARAMS
|
||||
#define ADC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_INIT_PARAMS
|
||||
#define ADC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_INIT_PARAMS
|
||||
#define ADC3_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_MAX, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC3_INIT_PARAMS */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
@@ -0,0 +1,136 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __CAN_CONFIG_H__
|
||||
#define __CAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN1_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN2_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN2_NAME ("can2")
|
||||
#ifndef CAN2_INIT_PARAMS
|
||||
#define CAN2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN2_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
/* Bit time config
|
||||
Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
|
||||
|
||||
Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
|
||||
TQ = u32Prescaler / CANClock.
|
||||
Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
|
||||
|
||||
The following bit time configures are based on CAN Clock 40M
|
||||
*/
|
||||
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 20, \
|
||||
.u32TimeSeg2 = 5, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 8, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 16, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 20, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 40, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 100, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 200, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CAN_CONFIG_H__ */
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-05-12 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DAC_CONFIG_H__
|
||||
#define __DAC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC1
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef BSP_USING_DAC2
|
||||
#ifndef DAC2_INIT_PARAMS
|
||||
#define DAC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac2", \
|
||||
}
|
||||
#endif /* DAC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DAC_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ETH_CONFIG_H__
|
||||
#define __ETH_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_ETH)
|
||||
|
||||
#ifndef ETH_IRQ_CONFIG
|
||||
#define ETH_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_ETH_IRQ_NUM, \
|
||||
.irq_prio = BSP_ETH_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_ETH_GLB_INT, \
|
||||
}
|
||||
#endif /* ETH_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ETH_CONFIG_H__ */
|
||||
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_CONFIG_H__
|
||||
#define __GPIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(RT_USING_PIN)
|
||||
|
||||
#ifndef EXTINT0_IRQ_CONFIG
|
||||
#define EXTINT0_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT0_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ0, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT1_IRQ_CONFIG
|
||||
#define EXTINT1_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT1_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ1, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT2_IRQ_CONFIG
|
||||
#define EXTINT2_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT2_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ2, \
|
||||
}
|
||||
#endif /* EXTINT2_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT3_IRQ_CONFIG
|
||||
#define EXTINT3_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT3_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ3, \
|
||||
}
|
||||
#endif /* EXTINT3_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT4_IRQ_CONFIG
|
||||
#define EXTINT4_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT4_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ4, \
|
||||
}
|
||||
#endif /* EXTINT4_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT5_IRQ_CONFIG
|
||||
#define EXTINT5_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT5_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ5, \
|
||||
}
|
||||
#endif /* EXTINT5_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT6_IRQ_CONFIG
|
||||
#define EXTINT6_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT6_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ6, \
|
||||
}
|
||||
#endif /* EXTINT6_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT7_IRQ_CONFIG
|
||||
#define EXTINT7_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT7_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ7, \
|
||||
}
|
||||
#endif /* EXTINT7_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT8_IRQ_CONFIG
|
||||
#define EXTINT8_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT8_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ8, \
|
||||
}
|
||||
#endif /* EXTINT8_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT9_IRQ_CONFIG
|
||||
#define EXTINT9_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT9_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ9, \
|
||||
}
|
||||
#endif /* EXTINT9_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT10_IRQ_CONFIG
|
||||
#define EXTINT10_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT10_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ10, \
|
||||
}
|
||||
#endif /* EXTINT10_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT11_IRQ_CONFIG
|
||||
#define EXTINT11_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT11_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ11, \
|
||||
}
|
||||
#endif /* EXTINT11_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT12_IRQ_CONFIG
|
||||
#define EXTINT12_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT12_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ12, \
|
||||
}
|
||||
#endif /* EXTINT12_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT13_IRQ_CONFIG
|
||||
#define EXTINT13_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT13_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ13, \
|
||||
}
|
||||
#endif /* EXTINT13_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT14_IRQ_CONFIG
|
||||
#define EXTINT14_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT14_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ14, \
|
||||
}
|
||||
#endif /* EXTINT14_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT15_IRQ_CONFIG
|
||||
#define EXTINT15_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT15_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ15, \
|
||||
}
|
||||
#endif /* EXTINT15_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GPIO_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-05-12 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PM_CONFIG_H__
|
||||
#define __PM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PM
|
||||
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
|
||||
|
||||
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
|
||||
#define PM_TICKLESS_TIMER_ENABLE_MASK \
|
||||
( (1UL << PM_SLEEP_MODE_IDLE) | \
|
||||
(1UL << PM_SLEEP_MODE_DEEP))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief run mode config @ref pm_run_mode_config structure
|
||||
*/
|
||||
#ifndef PM_RUN_MODE_CFG
|
||||
#define PM_RUN_MODE_CFG \
|
||||
{ \
|
||||
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
|
||||
}
|
||||
#endif /* PM_RUN_MODE_CFG */
|
||||
|
||||
/**
|
||||
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_IDLE_CFG
|
||||
#define PM_SLEEP_IDLE_CFG \
|
||||
{ \
|
||||
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_IDLE_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_DEEP_CFG
|
||||
#define PM_SLEEP_DEEP_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u16Clock = PWC_STOP_CLK_KEEP, \
|
||||
.u8StopDrv = PWC_STOP_DRV_HIGH, \
|
||||
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
|
||||
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
|
||||
}, \
|
||||
.pwc_stop_type = PWC_STOP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_DEEP_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_STANDBY_CFG
|
||||
#define PM_SLEEP_STANDBY_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD1, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_STANDBY_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_SHUTDOWN_CFG
|
||||
#define PM_SLEEP_SHUTDOWN_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD3, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
|
||||
|
||||
#endif /* BSP_USING_PM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PM_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-06-15 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_QSPI, \
|
||||
.clock = FCG1_PERIPH_QSPI, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_QSPI_INTR, \
|
||||
}, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
|
||||
#ifndef QSPI_INIT_PARAMS
|
||||
#define QSPI_INIT_PARAMS \
|
||||
{ \
|
||||
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
|
||||
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
|
||||
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
|
||||
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
|
||||
}
|
||||
#endif /* QSPI_INIT_PARAMS */
|
||||
|
||||
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = QSPI_DMA_INSTANCE, \
|
||||
.channel = QSPI_DMA_CHANNEL, \
|
||||
.clock = QSPI_DMA_CLOCK, \
|
||||
.trigger_select = QSPI_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_AOS_STRG, \
|
||||
.flag = QSPI_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = QSPI_DMA_IRQn, \
|
||||
.irq_prio = QSPI_DMA_INT_PRIO, \
|
||||
.int_src = QSPI_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__QSPI_CONFIG_H__ */
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_CONFIG_H__
|
||||
#define __SDIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_SDIO1)
|
||||
#ifndef SDIO1_BUS_CONFIG
|
||||
#define SDIO1_BUS_CONFIG \
|
||||
{ \
|
||||
.name = "sdio1", \
|
||||
.instance = CM_SDIOC1, \
|
||||
.clock = FCG1_PERIPH_SDIOC1, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SDIO1_IRQ_NUM, \
|
||||
.irq_prio = BSP_SDIO1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SDIOC1_SD, \
|
||||
}, \
|
||||
.dma_rx = \
|
||||
{ \
|
||||
.Instance = SDIO1_RX_DMA_INSTANCE, \
|
||||
.channel = SDIO1_RX_DMA_CHANNEL, \
|
||||
.clock = SDIO1_RX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC1_DMAR, \
|
||||
}, \
|
||||
.dma_tx = \
|
||||
{ \
|
||||
.Instance = SDIO1_TX_DMA_INSTANCE, \
|
||||
.channel = SDIO1_TX_DMA_CHANNEL, \
|
||||
.clock = SDIO1_TX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC1_DMAW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SDIO1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SDIO1 */
|
||||
|
||||
#if defined(BSP_USING_SDIO2)
|
||||
#ifndef SDIO2_BUS_CONFIG
|
||||
#define SDIO2_BUS_CONFIG \
|
||||
{ \
|
||||
.name = "sdio2", \
|
||||
.instance = CM_SDIOC2, \
|
||||
.clock = FCG1_PERIPH_SDIOC2, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SDIO2_IRQ_NUM, \
|
||||
.irq_prio = BSP_SDIO2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SDIOC2_SD, \
|
||||
}, \
|
||||
.dma_rx = \
|
||||
{ \
|
||||
.Instance = SDIO2_RX_DMA_INSTANCE, \
|
||||
.channel = SDIO2_RX_DMA_CHANNEL, \
|
||||
.clock = SDIO2_RX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC2_DMAR, \
|
||||
}, \
|
||||
.dma_tx = \
|
||||
{ \
|
||||
.Instance = SDIO2_TX_DMA_INSTANCE, \
|
||||
.channel = SDIO2_TX_DMA_CHANNEL, \
|
||||
.clock = SDIO2_TX_DMA_CLOCK, \
|
||||
.trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SDIOC2_DMAW, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SDIO2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SDIO2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __USB_APP_CONF_H__
|
||||
#define __USB_APP_CONF_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "rtconfig.h"
|
||||
|
||||
/* USB MODE CONFIGURATION */
|
||||
/*
|
||||
USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment
|
||||
(1) If only defined USB_FS_MODE:
|
||||
MCU USBFS core work in full speed using internal PHY.
|
||||
(2) If only defined USB_HS_MODE:
|
||||
MCU USBHS core work in full speed using internal PHY.
|
||||
(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY
|
||||
MCU USBHS core work in high speed using external PHY.
|
||||
(4) Other combination:
|
||||
Not support, forbid!!
|
||||
*/
|
||||
|
||||
#if defined(BSP_USING_USBHS)
|
||||
#define USB_HS_MODE
|
||||
#elif defined(BSP_USING_USBFS)
|
||||
#define USB_FS_MODE
|
||||
#else
|
||||
#define USB_FS_MODE
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD)
|
||||
#define USE_DEVICE_MODE
|
||||
#elif defined(BSP_USING_USBH)
|
||||
#define USE_HOST_MODE
|
||||
#else
|
||||
#define USE_DEVICE_MODE
|
||||
#endif
|
||||
|
||||
#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN)
|
||||
#define USB_HS_EXTERNAL_PHY
|
||||
#endif
|
||||
|
||||
#ifndef USB_HS_MODE
|
||||
#ifndef USB_FS_MODE
|
||||
#error "USB_HS_MODE or USB_FS_MODE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef USE_DEVICE_MODE
|
||||
#ifndef USE_HOST_MODE
|
||||
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD)
|
||||
/* USB DEVICE FIFO CONFIGURATION */
|
||||
#ifdef USB_FS_MODE
|
||||
#define RX_FIFO_FS_SIZE (128U)
|
||||
#define TX0_FIFO_FS_SIZE (32U)
|
||||
#define TX1_FIFO_FS_SIZE (32U)
|
||||
#define TX2_FIFO_FS_SIZE (32U)
|
||||
#define TX3_FIFO_FS_SIZE (32U)
|
||||
#define TX4_FIFO_FS_SIZE (32U)
|
||||
#define TX5_FIFO_FS_SIZE (32U)
|
||||
#define TX6_FIFO_FS_SIZE (32U)
|
||||
#define TX7_FIFO_FS_SIZE (32U)
|
||||
#define TX8_FIFO_FS_SIZE (32U)
|
||||
#define TX9_FIFO_FS_SIZE (32U)
|
||||
#define TX10_FIFO_FS_SIZE (32U)
|
||||
#define TX11_FIFO_FS_SIZE (32U)
|
||||
#define TX12_FIFO_FS_SIZE (32U)
|
||||
#define TX13_FIFO_FS_SIZE (32U)
|
||||
#define TX14_FIFO_FS_SIZE (32U)
|
||||
#define TX15_FIFO_FS_SIZE (32U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + \
|
||||
TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \
|
||||
TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \
|
||||
TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \
|
||||
TX15_FIFO_FS_SIZE) > 640U)
|
||||
#error "The USB max FIFO size is 640 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef USB_HS_MODE
|
||||
#define RX_FIFO_HS_SIZE (512U)
|
||||
#define TX0_FIFO_HS_SIZE (64U)
|
||||
#define TX1_FIFO_HS_SIZE (64U)
|
||||
#define TX2_FIFO_HS_SIZE (64U)
|
||||
#define TX3_FIFO_HS_SIZE (64U)
|
||||
#define TX4_FIFO_HS_SIZE (64U)
|
||||
#define TX5_FIFO_HS_SIZE (64U)
|
||||
#define TX6_FIFO_HS_SIZE (64U)
|
||||
#define TX7_FIFO_HS_SIZE (64U)
|
||||
#define TX8_FIFO_HS_SIZE (64U)
|
||||
#define TX9_FIFO_HS_SIZE (64U)
|
||||
#define TX10_FIFO_HS_SIZE (64U)
|
||||
#define TX11_FIFO_HS_SIZE (64U)
|
||||
#define TX12_FIFO_HS_SIZE (64U)
|
||||
#define TX13_FIFO_HS_SIZE (64U)
|
||||
#define TX14_FIFO_HS_SIZE (64U)
|
||||
#define TX15_FIFO_HS_SIZE (64U)
|
||||
|
||||
#if ((RX_FIFO_HS_SIZE + \
|
||||
TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \
|
||||
TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \
|
||||
TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \
|
||||
TX15_FIFO_HS_SIZE) > 2048U)
|
||||
#error "The USB max FIFO size is 2048 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBD_VBUS_SENSING)
|
||||
#define VBUS_SENSING_ENABLED
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_USBH)
|
||||
/* USB HOST FIFO CONFIGURATION */
|
||||
#ifdef USB_FS_MODE
|
||||
#define RX_FIFO_FS_SIZE (128U)
|
||||
#define TXH_NP_FS_FIFOSIZ (32U)
|
||||
#define TXH_P_FS_FIFOSIZ (64U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U)
|
||||
#error "The USB max FIFO size is 640 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef USB_HS_MODE
|
||||
#define RX_FIFO_HS_SIZE (512U)
|
||||
#define TXH_NP_HS_FIFOSIZ (128U)
|
||||
#define TXH_P_HS_FIFOSIZ (256U)
|
||||
|
||||
#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U)
|
||||
#error "The USB max FIFO size is 2048 x 4 Bytes!"
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_APP_CONF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-14 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __USB_BSP_H__
|
||||
#define __USB_BSP_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "hc32_ll_utility.h"
|
||||
|
||||
extern void usb_udelay(const uint32_t usec);
|
||||
extern void usb_mdelay(const uint32_t msec);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __USB_BSP_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "dma_config.h"
|
||||
#include "uart_config.h"
|
||||
#include "spi_config.h"
|
||||
#include "adc_config.h"
|
||||
#include "dac_config.h"
|
||||
#include "gpio_config.h"
|
||||
#include "eth_config.h"
|
||||
#include "can_config.h"
|
||||
#include "sdio_config.h"
|
||||
#include "pm_config.h"
|
||||
#include "i2c_config.h"
|
||||
#include "qspi_config.h"
|
||||
#include "pulse_encoder_config.h"
|
||||
#include "timer_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,115 @@
|
||||
/***************************************************************************//**
|
||||
* \file HC32F4A0.icf
|
||||
* \version 1.0
|
||||
*
|
||||
* \brief Linker file for the IAR compiler.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*******************************************************************************/
|
||||
/*###ICF### Section handled by ICF editor, don't touch! *****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
// Check that necessary symbols have been passed to linker via command line interface
|
||||
if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
|
||||
error "Link location not defined or not supported!";
|
||||
}
|
||||
if((!isdefinedsymbol(_HC32F4A0_2M_)) && (!isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) && (!isdefinedsymbol(_HC32F4A0_1M_DUAL_))) {
|
||||
error "Mcu type or size not defined or not supported!";
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory address and size definitions
|
||||
******************************************************************************/
|
||||
define symbol ram1_base_address = 0x1FFE0000;
|
||||
define symbol ram1_end_address = 0x2005FFFF;
|
||||
|
||||
if(isdefinedsymbol(_LINK_RAM_)) {
|
||||
define symbol ram_start_reserve = 0x20000;
|
||||
define symbol rom1_base_address = ram1_base_address;
|
||||
define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
define symbol rom3_base_address = 0x0;
|
||||
define symbol rom3_end_address = 0x0;
|
||||
} else {
|
||||
define symbol ram_start_reserve = 0x0;
|
||||
define symbol rom1_base_address = 0x0;
|
||||
define symbol rom3_base_address = 0x03000000;
|
||||
define symbol rom3_end_address = 0x030017FF;
|
||||
if (isdefinedsymbol(_HC32F4A0_2M_)) {
|
||||
define symbol rom1_end_address = 0x001FFFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else if (isdefinedsymbol(_HC32F4A0_1M_SINGLE_)) {
|
||||
define symbol rom1_end_address = 0x000FFFFF;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else if (isdefinedsymbol(_HC32F4A0_1M_DUAL_)) {
|
||||
define symbol rom1_end_address = 0x0007FFFF;
|
||||
define symbol rom2_base_address = 0x00100000;
|
||||
define symbol rom2_end_address = 0x0017FFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
|
||||
define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
|
||||
define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x2000;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory definitions
|
||||
******************************************************************************/
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in OTP_region { readonly section .otp_data };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,22 @@
|
||||
; ****************************************************************
|
||||
; Scatter-Loading Description File
|
||||
; ****************************************************************
|
||||
LR_IROM1 0x00000000 0x00200000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00200000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFE0000 UNINIT 0x00000008 { ; RW data
|
||||
*(.bss.noinit)
|
||||
}
|
||||
RW_IRAM2 0x1FFE0008 0x0007FFF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
.ANY (RAMCODE)
|
||||
}
|
||||
RW_IRAMB 0x200F0000 0x00001000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <drv_spi.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rthw.h>
|
||||
#include <finsh.h>
|
||||
#include <dfs_fs.h>
|
||||
#include <fal.h>
|
||||
|
||||
#ifdef BSP_USING_SPI_FLASH
|
||||
|
||||
#include "spi_flash.h"
|
||||
#ifdef RT_USING_SFUD
|
||||
#include "spi_flash_sfud.h"
|
||||
#endif
|
||||
|
||||
#define SPI_BUS_NAME "spi1"
|
||||
#define SPI_FLASH_DEVICE_NAME "spi10"
|
||||
#define SPI_FLASH_CHIP "w25q64"
|
||||
#define SPI_FLASH_SS_PORT GPIO_PORT_A
|
||||
#define SPI_FLASH_SS_PIN GPIO_PIN_04
|
||||
/* Partition Name */
|
||||
#define FS_PARTITION_NAME "filesystem"
|
||||
|
||||
#ifdef RT_USING_SFUD
|
||||
static void rt_hw_spi_flash_reset(char *spi_dev_name)
|
||||
{
|
||||
struct rt_spi_device *spi_dev_w25;
|
||||
rt_uint8_t w25_en_reset = 0x66;
|
||||
rt_uint8_t w25_reset_dev = 0x99;
|
||||
|
||||
spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
|
||||
if (!spi_dev_w25)
|
||||
{
|
||||
rt_kprintf("Can't find %s device!\n", spi_dev_name);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
|
||||
rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
|
||||
DDL_DelayMS(1U);
|
||||
rt_kprintf("Reset ext flash!\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int rt_hw_spi_flash_with_sfud_init(void)
|
||||
{
|
||||
rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN);
|
||||
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
|
||||
|
||||
static int rt_hw_fs_init(void)
|
||||
{
|
||||
struct rt_device *mtd_dev = RT_NULL;
|
||||
|
||||
/* 初始化 fal */
|
||||
fal_init();
|
||||
/* 生成 mtd 设备 */
|
||||
mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
|
||||
if (!mtd_dev)
|
||||
{
|
||||
LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 格式化文件系统 */
|
||||
if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to initialize filesystem!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to Format fs!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
INIT_APP_EXPORT(rt_hw_fs_init);
|
||||
|
||||
#endif /* RT_USING_SFUD */
|
||||
|
||||
#endif /* BSP_USING_SPI_FLASH */
|
||||
@@ -0,0 +1,20 @@
|
||||
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = []
|
||||
|
||||
src += Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
LOCAL_CFLAGS = ''
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||
LOCAL_CFLAGS += ' -std=c99'
|
||||
elif rtconfig.PLATFORM in ['armcc']:
|
||||
LOCAL_CFLAGS += ' --c99'
|
||||
|
||||
group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/* enable hc32f4 onchip flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_HC32F4
|
||||
/* enable SFUD flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_SFUD
|
||||
|
||||
extern const struct fal_flash_dev hc32_onchip_flash;
|
||||
extern struct fal_flash_dev ext_nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&hc32_onchip_flash, \
|
||||
&ext_nor_flash0, \
|
||||
}
|
||||
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0}, \
|
||||
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#include <fal.h>
|
||||
|
||||
#include <sfud.h>
|
||||
#ifdef RT_USING_SFUD
|
||||
#include <spi_flash_sfud.h>
|
||||
#endif
|
||||
|
||||
#ifndef FAL_USING_NOR_FLASH_DEV_NAME
|
||||
#define FAL_USING_NOR_FLASH_DEV_NAME "w25q64"
|
||||
#endif
|
||||
|
||||
static int init(void);
|
||||
static int read(long offset, uint8_t *buf, size_t size);
|
||||
static int write(long offset, const uint8_t *buf, size_t size);
|
||||
static int erase(long offset, size_t size);
|
||||
|
||||
static sfud_flash_t sfud_dev = NULL;
|
||||
struct fal_flash_dev ext_nor_flash0 =
|
||||
{
|
||||
.name = FAL_USING_NOR_FLASH_DEV_NAME,
|
||||
.addr = 0,
|
||||
.len = 8 * 1024 * 1024,
|
||||
.blk_size = 4096,
|
||||
.ops = {init, read, write, erase},
|
||||
.write_gran = 1
|
||||
};
|
||||
|
||||
static int init(void)
|
||||
{
|
||||
/* RT-Thread RTOS platform */
|
||||
sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
|
||||
if (NULL == sfud_dev)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
/* update the flash chip information */
|
||||
ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
|
||||
ext_nor_flash0.len = sfud_dev->chip.capacity;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read(long offset, uint8_t *buf, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int write(long offset, const uint8_t *buf, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int erase(long offset, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
@@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-03-01 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __NAND_PORT_H__
|
||||
#define __NAND_PORT_H__
|
||||
|
||||
/******************** NAND chip information ***********************************/
|
||||
#define NAND_BYTES_PER_PAGE 2048UL
|
||||
#define NAND_SPARE_AREA_SIZE 64UL
|
||||
#define NAND_PAGES_PER_BLOCK 64UL
|
||||
#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE)
|
||||
#define NAND_BLOCKS_PER_PLANE 1024UL
|
||||
#define NAND_PLANE_PER_DEVICE 2UL
|
||||
#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE)
|
||||
#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK)
|
||||
|
||||
/******************** EXMC_NFC configure **************************************/
|
||||
/* chip: EXMC_NFC_BANK0~7 */
|
||||
#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0
|
||||
|
||||
/* density:2Gbit */
|
||||
#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT
|
||||
|
||||
/* device width: 8-bit */
|
||||
#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT
|
||||
|
||||
/* page size: 2KByte */
|
||||
#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE
|
||||
|
||||
/* row address cycle: 3 */
|
||||
#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE
|
||||
|
||||
/* ECC mode */
|
||||
#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC
|
||||
|
||||
/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */
|
||||
/* TS: ALE/CLE/CE setup time(min=10ns) */
|
||||
#define NAND_TS 1U
|
||||
|
||||
/* TWP: WE# pulse width (min=10ns) */
|
||||
#define NAND_TWP 1U
|
||||
|
||||
/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */
|
||||
#define NAND_TRP 2U
|
||||
|
||||
/* TTH: ALE/CLE/CE hold time (min=5ns) */
|
||||
#define NAND_TH 1U
|
||||
|
||||
/* TWH: WE# pulse width HIGH (min=10ns) */
|
||||
#define NAND_TWH 1U
|
||||
|
||||
/* TRH: RE# pulse width HIGH (min=7ns) */
|
||||
#define NAND_TRH 1U
|
||||
|
||||
/* TRR: Ready to RE# LOW (min=20ns) */
|
||||
#define NAND_TRR 2U
|
||||
|
||||
/* TWB: WE# HIGH to busy (max=100ns) */
|
||||
#define NAND_TWB 1U
|
||||
|
||||
/* TWB: WE# HIGH to busy (max=100ns) */
|
||||
#define NAND_TRB 1U
|
||||
|
||||
/* TCCS: Change read column and Change write column delay */
|
||||
#define NAND_TCCS 5U
|
||||
|
||||
/* TWTR: WE# HIGH to RE# LOW (min=60ns) */
|
||||
#define NAND_TWTR 4U
|
||||
|
||||
/* TRTW: RE# HIGH to WE# LOW (min=100ns) */
|
||||
#define NAND_TRTW 7U
|
||||
|
||||
/* TADL: ALE to data start (min=70ns) */
|
||||
#define NAND_TADL 5U
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,88 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-02-24 CDT first version
|
||||
* 2024-02-20 CDT modify timing configuration for using exclk clock frequency 30MHz
|
||||
* add t_rcd/t_rfc/t_rp configuration macros-definition
|
||||
*/
|
||||
|
||||
#ifndef __SDRAM_PORT_H__
|
||||
#define __SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
|
||||
/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */
|
||||
#define SDRAM_CHIP EXMC_DMC_CHIP1
|
||||
/* bank address */
|
||||
#define SDRAM_BANK_ADDR (0x80000000UL)
|
||||
/* size(kbyte):8MB = 8*1024*1KBytes */
|
||||
#define SDRAM_SIZE (8UL * 1024UL * 1024UL)
|
||||
/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */
|
||||
#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10
|
||||
/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */
|
||||
#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT
|
||||
/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */
|
||||
#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8
|
||||
/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */
|
||||
#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12
|
||||
/* cas latency clock number: 2, 3 */
|
||||
#define SDRAM_CAS_LATENCY 2UL
|
||||
/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */
|
||||
#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT
|
||||
|
||||
/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */
|
||||
#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD
|
||||
/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */
|
||||
#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL
|
||||
/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED
|
||||
|
||||
/* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */
|
||||
/* refresh rate counter (EXCLK clock) */
|
||||
#define SDRAM_REFRESH_COUNT (450U)
|
||||
/* TMDR: mode register command time (EXCLK clock) */
|
||||
#define SDRAM_TMDR 2U
|
||||
/* TRAS: RAS to precharge delay time (EXCLK clock) */
|
||||
#define SDRAM_TRAS 2U
|
||||
/* TRC: active bank x to active bank x delay time (EXCLK clock) */
|
||||
#define SDRAM_TRC 2U
|
||||
/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */
|
||||
#define SDRAM_TRCD_B 3U
|
||||
#define SDRAM_TRCD_P 0U
|
||||
/* TRFC: autorefresh command time (EXCLK clock) */
|
||||
#define SDRAM_TRFC_B 3U
|
||||
#define SDRAM_TRFC_P 0U
|
||||
/* TRP: precharge to RAS delay time (EXCLK clock) */
|
||||
#define SDRAM_TRP_B 3U
|
||||
#define SDRAM_TRP_P 0U
|
||||
/* TRRD: active bank x to active bank y delay time (EXCLK clock) */
|
||||
#define SDRAM_TRRD 1U
|
||||
/* TWR: write to precharge delay time (EXCLK clock). */
|
||||
#define SDRAM_TWR 2U
|
||||
/* TWTR: write to read delay time (EXCLK clock). */
|
||||
#define SDRAM_TWTR 1U
|
||||
/* TXP: exit power-down command time (EXCLK clock). */
|
||||
#define SDRAM_TXP 1U
|
||||
/* TXSR: exit self-refresh command time (EXCLK clock). */
|
||||
#define SDRAM_TXSR 5U
|
||||
/* TESR: self-refresh command time (EXCLK clock). */
|
||||
#define SDRAM_TESR 5U
|
||||
|
||||
/* memory mode register */
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-04-28 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TCA9539_H__
|
||||
#define __TCA9539_H__
|
||||
|
||||
#include <rtdevice.h>
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_REG_INPUT_PORT0 (0x00U)
|
||||
#define TCA9539_REG_INPUT_PORT1 (0x01U)
|
||||
#define TCA9539_REG_OUTPUT_PORT0 (0x02U)
|
||||
#define TCA9539_REG_OUTPUT_PORT1 (0x03U)
|
||||
#define TCA9539_REG_INVERT_PORT0 (0x04U)
|
||||
#define TCA9539_REG_INVERT_PORT1 (0x05U)
|
||||
#define TCA9539_REG_CONFIG_PORT0 (0x06U)
|
||||
#define TCA9539_REG_CONFIG_PORT1 (0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Port_Definition TCA9539 Port Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PORT0 (0x00U)
|
||||
#define TCA9539_IO_PORT1 (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PIN0 (0x01U)
|
||||
#define TCA9539_IO_PIN1 (0x02U)
|
||||
#define TCA9539_IO_PIN2 (0x04U)
|
||||
#define TCA9539_IO_PIN3 (0x08U)
|
||||
#define TCA9539_IO_PIN4 (0x10U)
|
||||
#define TCA9539_IO_PIN5 (0x20U)
|
||||
#define TCA9539_IO_PIN6 (0x40U)
|
||||
#define TCA9539_IO_PIN7 (0x80U)
|
||||
#define TCA9539_IO_PIN_ALL (0xFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_DIR_OUT (0x00U)
|
||||
#define TCA9539_DIR_IN (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_PIN_RESET (0x00U)
|
||||
#define TCA9539_PIN_SET (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition
|
||||
* @{
|
||||
*/
|
||||
#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */
|
||||
#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */
|
||||
#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */
|
||||
#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */
|
||||
#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */
|
||||
#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */
|
||||
#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
|
||||
#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */
|
||||
|
||||
#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */
|
||||
#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */
|
||||
#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */
|
||||
#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */
|
||||
#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */
|
||||
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
|
||||
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
|
||||
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define LED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PIN (EIO_LED_RED)
|
||||
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
|
||||
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_BLUE_PIN (EIO_LED_BLUE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP CAN PHY STB port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN_STB_PIN (EIO_CAN_STB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
int TCA9539_Init(void);
|
||||
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
|
||||
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
|
||||
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
|
||||
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
|
||||
|
||||
#endif
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 851 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,150 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
else:
|
||||
EXEC_PATH = r'C:/Users/XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iccarm':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD1FFE0000 -FF0HC32F4A0_2M -FF1HC32F4A0_otp -FL0200000 -FL11800 -FS00 -FS13000000 -FP0($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_2M.FLM) -FP1($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"LCKFB-CMSIS-DAP" -ULCKFB-V1.0.0-8437443312050767921 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F4A0_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_2M.FLM) -FF1HC32F4A0_otp.FLM -FS13000000 -FL11800 -FP1($$Device:HC32F4A0PITB$FlashARM\HC32F4A0_otp.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>0</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>1000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user