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Merge pull request #1515 from TanekLiang/ch802-fpga
[bsp] add ck802 bsp support
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@@ -0,0 +1,30 @@
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mainmenu "RT-Thread Configuration"
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config $BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config $RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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# you can change the RTT_ROOT default "../.." to your rtthread_root,
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# example : default "F:/git_repositories/rt-thread"
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config $PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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if RT_USING_SERIAL
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config RT_USING_UART1
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bool "Using uart1"
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default y
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endif
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@@ -0,0 +1,84 @@
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CK802
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## 简介
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CK802是杭州中天微系统有限公司自主开发的极低功耗、极低成本嵌入式CPU核产品，它以8位CPU的成本获得32位CPU的运行效率与性能。 BSP基于中天微提供的一块FPGA开发板完成。
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| 介绍 | 描述 |
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| ---- | ---- |
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| 主CPU平台 | CK802 |
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| 最高频率 | 600MHz |
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| SRAM | 128K |
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| FLASH | 256K |
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## 编译说明
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CK802板级包支持CDK集成开发环境和Scons编译。使用的编译器是csky-abiv2-elf-toolchain。
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| IDE/编译器 | 已测试版本 |
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| ---------- | --------- |
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| CDK | CDK 1.6.0 |
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| GCC | (C-SKY Tools V2.10.00(Minilibc), ABIV2, B20161206) 4.5.1 |
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使用scons编译，需要指定环境变量RTT_EXEC_PATH为正确的编译器路径，例如：
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Windows：
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```shell
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RTT_EXEC_PATH=r'D:\c-sky\CSKY\MinGW\csky-abiv2-elf-toolchain\bin'
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```
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Linux：
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```shell
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RTT_EXEC_PATH=r'/opt/csky-abiv2-elf-tools-x86_64-minilibc-20161211/bin'
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```
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## BSP使用
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### CDK
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#### 编译仿真
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打开project.cdkproj工程，点击菜单栏的`Project->Build Active Project`进行编译，编译完成后点击`Debug->Start/Stop Debugger`，就可以进入仿真。点击`Debug->Continue Debugger`全速运行。
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#### 更新工程
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在需要添加或者删除组件的时候，可以使用`menuconfig`进行配置。配置完成后输入`scons --target=cdk`更新工程
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### Scons
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#### 编译
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配置好环境变量`RTT_EXEC_PATH`后，使用[env工具][https://www.rt-thread.org/page/download.html]，可以在console下进入到bsp目录中，运行以下命令就可以编译该BSP：
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```
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scons
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```
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#### 仿真
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Windows平台打开CSkyDebugServer.exe，该软件会连接到仿真器并且提供一个gdb server。使用DebugServerConsole.exe在命令行下进行调试。
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Linux平台使用CSkyDebugServer.elf来连接仿真器，使用DebugServerConsole.exe在命令行下进行调试。
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### 运行结果
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如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 3.0.4 build Jun 5 2018
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2006 - 2018 Copyright by rt-thread team
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msh >
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```
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## 4. 驱动支持情况及计划
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| 驱动 | 支持情况 | 备注 |
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| ------ | ---- | ------ |
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| UART | 支持 | UART 1 |
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## 5. 联系人信息
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维护人：
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- [tanek](https://github.com/TanekLiang)
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@@ -0,0 +1,14 @@
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# for module compiling
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,35 @@
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import os
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import sys
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import rtconfig
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# if os.getenv('RTT_ROOT'):
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# RTT_ROOT = os.getenv('RTT_ROOT')
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# else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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print RTT_ROOT
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-ck802.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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# add --start-group and --end-group for GNU GCC
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env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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# make a building
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DoBuilding(TARGET, objs)
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@@ -0,0 +1,13 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'applications')
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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CCFLAGS = ' -c -mistack -ffunction-sections'
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CCFLAGS=CCFLAGS)
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Return('group')
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@@ -0,0 +1,33 @@
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/*
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* File : clock.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
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||||
* Change Logs:
|
||||
* Date Author Notes
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||||
* 2017-10-10 Tanek first version
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*/
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#include <rtthread.h>
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int main(void)
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{
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return 0;
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}
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/*@}*/
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@@ -0,0 +1,14 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'drivers')
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# add the general drivers.
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src = Glob("*.c") + Glob("*.cpp")
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CPPPATH = [cwd]
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,60 @@
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2018, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-08-10 Urey first implementation
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||||
*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "csi_core.h"
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#include "pinmux.h"
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extern int __bss_end__;
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#define SYS_HEAP_BEGIN (&__bss_end__)
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#include "core_ck802.h"
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/**
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* This function will initial CK802 board.
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*/
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void rt_hw_board_init(void)
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{
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phobos_ioreuse_initial();
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/* NVIC Configuration */
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drv_nvic_init(2);
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)SYS_HEAP_BEGIN, (void *)CK802_IRAM_END);
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#endif
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}
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/*@}*/
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@@ -0,0 +1,32 @@
|
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/*
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* File : board.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2018, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-08-10 Urey first implementation
|
||||
*/
|
||||
|
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#ifndef __BOARD_H__
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#define __BOARD_H__
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|
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#define APB_DEFAULT_FREQ 20000000 /* Hz */
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#define CK802_IRAM_SIZE 94
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#define CK802_IRAM_END (0x20000000 + CK802_IRAM_SIZE * 1024)
|
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|
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#endif /* __BOARD_H__ */
|
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@@ -0,0 +1,81 @@
|
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/*
|
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* File : board_coretimer.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-01-01 Urey first version
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "board_coretimer.h"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
static inline unsigned int readreg32(volatile unsigned int *addr)
|
||||
{
|
||||
return *(volatile unsigned int *)addr;
|
||||
}
|
||||
|
||||
static inline void writereg32(unsigned int b, volatile unsigned int *addr)
|
||||
{
|
||||
*(volatile unsigned int *)addr = b;
|
||||
}
|
||||
|
||||
void CKTimerInit(uint32_t timer_id, uint32_t freq)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
writereg32(APB_DEFAULT_FREQ / freq, CORET_RVR);
|
||||
writereg32(0, CORET_CVR);
|
||||
|
||||
reg = readreg32(CORET_CSR);
|
||||
reg |= CORETIM_TXCONTROL_ENABLE;
|
||||
reg |= CORETIM_TXCONTROL_INTMASK;
|
||||
writereg32(reg, CORET_CSR);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void CKTimerClear(uint32_t timer_id)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = readreg32(CORET_CSR);
|
||||
reg |= ~CORETIM_TXCONTROL_MODE;
|
||||
writereg32(reg, CORET_CSR);
|
||||
}
|
||||
|
||||
uint32_t CKTimer_CurrentValue(void)
|
||||
{
|
||||
return readreg32(CORET_CVR);
|
||||
}
|
||||
|
||||
void __attribute__((isr)) SysTick_Handler(void)
|
||||
{
|
||||
CKTimerClear(0x1);
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* File : board_coretimer.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-01-01 Urey first version
|
||||
*/
|
||||
#ifndef _BOARD_CORETIMER_H_
|
||||
#define _BOARD_CORETIMER_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define CK_TIMER_BASE (0xE000E000)
|
||||
|
||||
#define CORET_CSR (volatile unsigned int *)(CK_TIMER_BASE + 0x10)
|
||||
#define CORET_RVR (volatile unsigned int *)(CK_TIMER_BASE + 0x14)
|
||||
#define CORET_CVR (volatile unsigned int *)(CK_TIMER_BASE + 0x18)
|
||||
#define CORET_CALIB (volatile unsigned int *)(CK_TIMER_BASE + 0x1c)
|
||||
|
||||
/*
|
||||
* define the bits for TxControl
|
||||
*/
|
||||
#define CORETIM_TXCONTROL_ENABLE (1UL << 0)
|
||||
#define CORETIM_TXCONTROL_INTMASK (1UL << 1)
|
||||
#define CORETIM_TXCONTROL_MODE (1UL << 16)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BOARD_CORETIMER_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,44 @@
|
||||
/* config.h -- Autogenerated! Do not edit. */
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_KERNEL_NONE 1
|
||||
//#define CONFIG_AES 1
|
||||
//#define CONFIG_SPI 1
|
||||
//#define CONFIG_SPI_DMA 1
|
||||
//#define CONFIG_DMAC 1
|
||||
//#define CONFIG_GPIO 1
|
||||
//#define CONFIG_IIC 1
|
||||
//#define CONFIG_SHA 1
|
||||
//#define CONFIG_RSA 1
|
||||
//#define CONFIG_TIMER 1
|
||||
#define CONFIG_USART 1
|
||||
//#define CONFIG_TRNG 1
|
||||
//#define CONFIG_CRC 1
|
||||
//#define CONFIG_EFLASH 1
|
||||
//#define CONFIG_WDT 1
|
||||
//#define CONFIG_RTC 1
|
||||
//#define CONFIG_PWM 1
|
||||
//#define CONFIG_TEST 1
|
||||
//#define CONFIG_ETH 1
|
||||
//#define CONFIG_TEST_DRIVER 1
|
||||
//#define CONFIG_TEST_AES 1
|
||||
//#define CONFIG_TEST_ETH 1
|
||||
//#define CONFIG_TEST_DMAC 1
|
||||
//#define CONFIG_TEST_GPIO 1
|
||||
//#define CONFIG_TEST_IIC 1
|
||||
//#define CONFIG_TEST_SHA 1
|
||||
//#define CONFIG_TEST_RSA 1
|
||||
//#define CONFIG_TEST_TIMER 1
|
||||
//#define CONFIG_TEST_USART 1
|
||||
//#define CONFIG_TEST_TRNG 1
|
||||
//#define CONFIG_TEST_CRC 1
|
||||
//#define CONFIG_TEST_EFLASH 1
|
||||
//#define CONFIG_TEST_SPI 1
|
||||
//#define CONFIG_TEST_WDT 1
|
||||
//#define CONFIG_TEST_RTC 1
|
||||
//#define CONFIG_TEST_PWM 1
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@@ -0,0 +1,174 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file isr.c
|
||||
* @brief source file for the interrupt server route
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#include <drv_common.h>
|
||||
#include "config.h"
|
||||
#include "soc.h"
|
||||
|
||||
extern void dw_usart_irqhandler(int32_t idx);
|
||||
extern void dw_timer_irqhandler(int32_t idx);
|
||||
extern void dw_gpio_irqhandler(int32_t idx);
|
||||
extern void dw_iic_irqhandler(int32_t idx);
|
||||
extern void ck_rtc_irqhandler(int32_t idx);
|
||||
extern void dw_spi_irqhandler(int32_t idx);
|
||||
extern void dw_wdt_irqhandler(int32_t idx);
|
||||
extern void ck_dma_irqhandler(int32_t idx);
|
||||
extern void ck_aes_irqhandler(int32_t idx);
|
||||
extern void ck_sha_irqhandler(int32_t idx);
|
||||
#ifdef CONFIG_KERNEL_FREERTOS
|
||||
extern void CKTimer1Isr(void);
|
||||
extern void CKPendSVIsr(void);
|
||||
#endif
|
||||
|
||||
#define readl(addr) \
|
||||
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
|
||||
|
||||
__attribute__((isr)) void CORET_IRQHandler(void)
|
||||
{
|
||||
readl(0xE000E010);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_USART)
|
||||
/*
|
||||
__attribute__((isr)) void USART0_IRQHandler(void)
|
||||
{
|
||||
dw_usart_irqhandler(0);
|
||||
}
|
||||
|
||||
|
||||
__attribute__((isr)) void USART1_IRQHandler(void)
|
||||
{
|
||||
dw_usart_irqhandler(1);
|
||||
}
|
||||
|
||||
|
||||
__attribute__((isr)) void USART2_IRQHandler(void)
|
||||
{
|
||||
dw_usart_irqhandler(2);
|
||||
}
|
||||
|
||||
__attribute__((isr)) void USART3_IRQHandler(void)
|
||||
{
|
||||
dw_usart_irqhandler(3);
|
||||
}
|
||||
*/
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TIMER)
|
||||
__attribute__((isr)) void TIMA0_IRQHandler(void)
|
||||
{
|
||||
dw_timer_irqhandler(0);
|
||||
}
|
||||
|
||||
__attribute__((isr)) void TIMA1_IRQHandler(void)
|
||||
{
|
||||
dw_timer_irqhandler(1);
|
||||
}
|
||||
__attribute__((isr)) void TIMB0_IRQHandler(void)
|
||||
{
|
||||
dw_timer_irqhandler(2);
|
||||
}
|
||||
|
||||
__attribute__((isr)) void TIMB1_IRQHandler(void)
|
||||
{
|
||||
dw_timer_irqhandler(3);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_GPIO)
|
||||
|
||||
__attribute__((isr)) void GPIOA_IRQHandler(void)
|
||||
{
|
||||
dw_gpio_irqhandler(0);
|
||||
}
|
||||
|
||||
__attribute__((isr)) void GPIOB_IRQHandler(void)
|
||||
{
|
||||
dw_gpio_irqhandler(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_IIC)
|
||||
__attribute__((isr)) void I2C0_IRQHandler(void)
|
||||
{
|
||||
dw_iic_irqhandler(0);
|
||||
}
|
||||
|
||||
__attribute__((isr)) void I2C1_IRQHandler(void)
|
||||
{
|
||||
dw_iic_irqhandler(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC)
|
||||
|
||||
__attribute__((isr)) void RTC_IRQHandler(void)
|
||||
{
|
||||
ck_rtc_irqhandler(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_AES)
|
||||
|
||||
__attribute__((isr)) void AES_IRQHandler(void)
|
||||
{
|
||||
ck_aes_irqhandler(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SHA)
|
||||
|
||||
__attribute__((isr)) void SHA_IRQHandler(void)
|
||||
{
|
||||
ck_sha_irqhandler(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPI) && defined(CONFIG_GPIO)
|
||||
__attribute__((isr)) void SPI0_IRQHandler(void)
|
||||
{
|
||||
dw_spi_irqhandler(0);
|
||||
}
|
||||
|
||||
__attribute__((isr)) void SPI1_IRQHandler(void)
|
||||
{
|
||||
dw_spi_irqhandler(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_WDT)
|
||||
__attribute__((isr)) void WDT_IRQHandler(void)
|
||||
{
|
||||
dw_wdt_irqhandler(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DMAC)
|
||||
__attribute__((isr)) void DMAC_IRQHandler(void)
|
||||
{
|
||||
ck_dma_irqhandler(0);
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,88 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file pn_name.h
|
||||
* @brief header file for the pin_name
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _PINNAMES_H
|
||||
#define _PINNAMES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PA0_TXD0_PWM0_XX_SIROUT0 = 0,
|
||||
PA1_RXD0_PWM1_XX_SIRIN0,
|
||||
PA2_CTS0_PWM2_SPI0CLK_XX,
|
||||
PA3_RTS0_PWM3_SPI0TX_XX,
|
||||
PA4_SCL0_PWM4_SPI0RX_XX,
|
||||
PA5_SDA0_PWM5_SPI0CS_XX,
|
||||
PA6_SPI0CLK_PWMTRIG0_SCL0_XX,
|
||||
PA7_SPI0TX_PWMTRIG1_SDA0_XX,
|
||||
PA8_SPI0RX_TRIGFAULT_SCL1_XX,
|
||||
PA9_SPI0CS_PWM0_SDA1_XX,
|
||||
PA10_TXD1_PWM1_XX_SIROUT1,
|
||||
PA11_RXD1_PWM2_XX_SIRIN1,
|
||||
PA12_CTS1_PWM3_SPI1CLK_XX,
|
||||
PA13_RTS1_PWM4_SPI1TX_XX,
|
||||
PA14_SCL1_PWM5_SPI1RX_XX,
|
||||
PA15_SDA1_PWMTRIG0_SPI1CS0_XX,
|
||||
PA16_SPI1CLK_PWMTRIG1_XX_XX,
|
||||
PA17_SPI1TX_PWMFAULT_XX_XX,
|
||||
PA18_SPI1RX_PWM0_XX_XX,
|
||||
PA19_SPI1CS0_PWM1_XX_XX,
|
||||
PA20_SPI1CS1_PWM2_XX_XX,
|
||||
PA21_SPI1CS2_PWM3_XX_XX,
|
||||
PA22_RXD2_PWM4_XX_SIRIN2,
|
||||
PA23_TXD2_PWM5_XX_SIROUT2,
|
||||
PA24_CTS2_PWMTRIG0_SPI1CS1_XX,
|
||||
PA25_XX_PWMTRIG1_SPI1CS2_XX,
|
||||
PA26_TXD3_PWMFAULT_XX_SIROUT3,
|
||||
PA27_RXD3_PWM0_XX_SIRIN3,
|
||||
PA28_I2SMCLK_PWM1_XX_XX,
|
||||
PA29_I2SSCLK_PWM2_XX_XX,
|
||||
PA30_I2SWSCLK_PWM3_XX_XX,
|
||||
PA31_I2SSDA__SCL0_PWM4_XX,
|
||||
PB0_ADC0_SDA0_PWM5_XX,
|
||||
PB1_ADC1_SCL1_USISCLK_XX,
|
||||
PB2_ADC2_SDA1_USISD0_XX,
|
||||
PB3_ADC3_SPI1CLK_USISD1_XX,
|
||||
PB4_ADC4_SPI1TX_USINSS_XX,
|
||||
PB5_ADC5_SPI1RX_USISCLK_XX,
|
||||
PB6_ADC6_SPI1CS0_USISD0_XX,
|
||||
PB7_ADC7_SPI1CS1_USISD1_XX,
|
||||
PB8_PWMTRIG0_SPI1CS2_USINSS_XX,
|
||||
PB9_PWMTRIG1_CTS3_XX_XX,
|
||||
PB10_PWMFAULT_RTS3_XX_XX
|
||||
}
|
||||
pin_name_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PORTA = 0,
|
||||
PORTB = 1
|
||||
} port_name_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,158 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file pinmux.c
|
||||
* @brief source file for the pinmux
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "pinmux.h"
|
||||
#include "pin_name.h"
|
||||
|
||||
#define readl(addr) \
|
||||
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
|
||||
|
||||
#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
|
||||
|
||||
/*******************************************************************************
|
||||
* function: phobos_ioreuse_inital
|
||||
*
|
||||
* description:
|
||||
* initial phobos_pinmux
|
||||
*******************************************************************************/
|
||||
|
||||
void phobos_ioreuse_initial(void)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
/* gpio data source select */
|
||||
value = readl(PHOBOS_GIPO0_PORTCTL_REG);
|
||||
value |= GPIO0_REUSE_EN;
|
||||
writel(value, PHOBOS_GIPO0_PORTCTL_REG);
|
||||
|
||||
value = readl(PHOBOS_GIPO1_PORTCTL_REG);
|
||||
value |= GPIO1_REUSE_EN;
|
||||
writel(value, PHOBOS_GIPO1_PORTCTL_REG);
|
||||
|
||||
/* reuse function select */
|
||||
value = readl(PHOBOS_IOMUX0L_REG);
|
||||
value |= IOMUX0L_FUNCTION_SEL;
|
||||
writel(value, PHOBOS_IOMUX0L_REG);
|
||||
|
||||
value = readl(PHOBOS_IOMUX0H_REG);
|
||||
value |= IOMUX1L_FUNCTION_SEL;
|
||||
writel(value, PHOBOS_IOMUX0H_REG);
|
||||
|
||||
value = readl(PHOBOS_IOMUX1L_REG);
|
||||
value |= IOMUX1L_FUNCTION_SEL;
|
||||
writel(value, PHOBOS_IOMUX1L_REG);
|
||||
}
|
||||
|
||||
void phobos_pwm_ioreuse(void)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
/* gpio data source select */
|
||||
value = readl(PHOBOS_GIPO0_PORTCTL_REG);
|
||||
value |= PWM_GPIO0_REUSE_EN;
|
||||
writel(value, PHOBOS_GIPO0_PORTCTL_REG);
|
||||
|
||||
/* reuse function select */
|
||||
value = readl(PHOBOS_IOMUX0L_REG);
|
||||
value |= PWM_IOMUX0L_FUNCTION_SEL;
|
||||
writel(value, PHOBOS_IOMUX0L_REG);
|
||||
}
|
||||
|
||||
|
||||
int32_t pin_mux(pin_name_t pin, uint16_t function)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
unsigned int reg_val = 0;
|
||||
|
||||
uint8_t offset;
|
||||
|
||||
if (function > 3)
|
||||
{
|
||||
if (pin < PB0_ADC0_SDA0_PWM5_XX)
|
||||
{
|
||||
offset = pin;
|
||||
/* gpio data source select */
|
||||
val = readl(PHOBOS_GIPO0_PORTCTL_REG);
|
||||
val &= ~(1 << offset);
|
||||
writel(val, PHOBOS_GIPO0_PORTCTL_REG);
|
||||
return 0;
|
||||
}
|
||||
else if (pin >= PB0_ADC0_SDA0_PWM5_XX)
|
||||
{
|
||||
offset = pin - 32;
|
||||
/* gpio data source select */
|
||||
val = readl(PHOBOS_GIPO1_PORTCTL_REG);
|
||||
val &= ~(1 << offset);
|
||||
writel(val, PHOBOS_GIPO1_PORTCTL_REG);
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (pin >= PB0_ADC0_SDA0_PWM5_XX)
|
||||
{
|
||||
offset = pin - 32;
|
||||
|
||||
/* gpio data source select */
|
||||
val = readl(PHOBOS_GIPO1_PORTCTL_REG);
|
||||
val |= (1 << offset);
|
||||
writel(val, PHOBOS_GIPO1_PORTCTL_REG);
|
||||
|
||||
reg_val = (0x3 << (offset * 2));
|
||||
/* reuse function select */
|
||||
val = readl(PHOBOS_IOMUX1L_REG);
|
||||
val &= ~(reg_val);
|
||||
val |= (function << (2 * offset));
|
||||
writel(val, PHOBOS_IOMUX1L_REG);
|
||||
return 0;
|
||||
}
|
||||
|
||||
offset = pin;
|
||||
/* gpio data source select */
|
||||
val = readl(PHOBOS_GIPO0_PORTCTL_REG);
|
||||
val |= (1 << offset);
|
||||
writel(val, PHOBOS_GIPO0_PORTCTL_REG);
|
||||
|
||||
if (pin >= PA16_SPI1CLK_PWMTRIG1_XX_XX)
|
||||
{
|
||||
offset = pin - 16;
|
||||
reg_val = (0x3 << (offset * 2));
|
||||
/* reuse function select */
|
||||
val = readl(PHOBOS_IOMUX0H_REG);
|
||||
val &= ~(reg_val);
|
||||
val |= (function << (2 * offset));
|
||||
writel(val, PHOBOS_IOMUX0H_REG);
|
||||
return 0;
|
||||
}
|
||||
|
||||
reg_val = (0x3 << (offset * 2));
|
||||
/* reuse function select */
|
||||
val = readl(PHOBOS_IOMUX0L_REG);
|
||||
val &= ~(reg_val);
|
||||
val |= (function << (2 * offset));
|
||||
writel(val, PHOBOS_IOMUX0L_REG);
|
||||
return 0;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file system_PHOBOS.c
|
||||
* @brief CSI Device System Source File for PHOBOS
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#include "soc.h"
|
||||
#include "csi_core.h"
|
||||
#include "config.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock Variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
int SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
|
||||
|
||||
extern int __Vectors;
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize the system
|
||||
* Initialize the psr and vbr.
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Here we may setting exception vector, MGU, cache, and so on. */
|
||||
#ifdef CONFIG_SYSTEM_SECURE
|
||||
__set_PSR(0xc0000140);
|
||||
#else
|
||||
__set_PSR(0x80000140);
|
||||
#endif
|
||||
__set_VBR((uint32_t) & (__Vectors));
|
||||
|
||||
drv_coret_config(200 * 1000, CORET_IRQn); //10ms
|
||||
drv_nvic_enable_irq(CORET_IRQn);
|
||||
|
||||
SystemCoreClock = SYSTEM_CLOCK;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,48 @@
|
||||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
startup_gcc.S
|
||||
common/aes/ck_aes.c
|
||||
common/crc/ck_crc.c
|
||||
common/dmac/ck_dmac.c
|
||||
common/eflash/ck_eflash.c
|
||||
common/pwm/ck_pwm.c
|
||||
common/rsa/ck_rsa.c
|
||||
common/sha/ck_sha.c
|
||||
common/trng/ck_trng.c
|
||||
common/timer/dw_timer.c
|
||||
common/gpio/dw_gpio.c
|
||||
common/spi/dw_spi.c
|
||||
common/iic/dw_iic.c
|
||||
common/usart/dw_usart.c
|
||||
common/wdt/dw_wdt.c
|
||||
""")
|
||||
|
||||
path = [cwd + '/include',
|
||||
cwd + '/common/aes',
|
||||
cwd + '/common/aes',
|
||||
cwd + '/common/crc',
|
||||
cwd + '/common/dmac',
|
||||
cwd + '/common/eflash',
|
||||
cwd + '/common/gpio',
|
||||
cwd + '/common/iic',
|
||||
cwd + '/common/pwm',
|
||||
cwd + '/common/rsa',
|
||||
cwd + '/common/rtc',
|
||||
cwd + '/common/sha',
|
||||
cwd + '/common/spi',
|
||||
cwd + '/common/timer',
|
||||
cwd + '/common/trng',
|
||||
cwd + '/common/usart',
|
||||
cwd + '/common/wdt'
|
||||
]
|
||||
|
||||
group = DefineGroup('libraries', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file ck_aes.h
|
||||
* @brief header file for aes driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CK_AES_H_
|
||||
#define _CK_AES_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include "drv_aes.h"
|
||||
#include "soc.h"
|
||||
|
||||
#define AES_LITTLE_ENDIAN 0x00000100
|
||||
|
||||
#define AES_MAX_KEY_LENGTH 32
|
||||
#define AES_IT_DATAINT 0x4
|
||||
#define AES_IT_KEYINT 0x2
|
||||
#define AES_IT_BUSY 0x1
|
||||
#define AES_IT_ALL 0x7
|
||||
#define AES_CRYPTO_KEYEXP 0x2
|
||||
|
||||
#define AES_WORK_ENABLE_OFFSET 0
|
||||
#define AES_INT_ENABLE_OFFSET 2
|
||||
#define AES_MODE_OFFSET 3
|
||||
#define AES_KEY_LEN_OFFSET 4
|
||||
#define AES_OPCODE_OFFSET 6
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t datain[4]; /* Offset: 0x000 (R/W) Data input 0~127 */
|
||||
__IOM uint32_t key[8]; /* Offset: 0x010 (R/W) Key 0~255 */
|
||||
__IOM uint32_t iv[4]; /* Offset: 0x030 (R/W) Initial Vector: 0~127 */
|
||||
__IOM uint32_t ctrl; /* Offset: 0x040 (R/W) AES Control Register */
|
||||
__IOM uint32_t state; /* Offset: 0x044 (R/W) AES State Register */
|
||||
__IOM uint32_t dataout[4]; /* Offset: 0x048 (R/W) Data Output 0~31 */
|
||||
} ck_aes_reg_t;
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_crc.h
|
||||
* @brief header file for crc driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CK_CRC_H_
|
||||
#define _CK_CRC_H_
|
||||
|
||||
#include "stdint.h"
|
||||
#include "soc.h"
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t CRC_DATA; /* Offset: 0x000 (W/R) data register */
|
||||
__IOM uint32_t CRC_SEL; /* Offset: 0x004 (W/R) mode select register for CRC */
|
||||
__OM uint32_t CRC_INIT; /* Offset: 0x008 (W) initial value register */
|
||||
|
||||
} ck_crc_reg_t;
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_dmac.h
|
||||
* @brief header file for DMAC Driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __CK_DMA_H
|
||||
#define __CK_DMA_H
|
||||
#include <stdio.h>
|
||||
#include "soc.h"
|
||||
|
||||
#define CK_DMA_MAXCHANNEL 2
|
||||
#define CK_DMA_INT_EN 1
|
||||
#define CK_DMA_CH_EN 1
|
||||
#define CK_DMA_TFR 0x0002
|
||||
#define CK_DMA_ERR 0x0001
|
||||
#define CK_DMA_INTC 0x03
|
||||
#define CK_DMA_MASK 0x03
|
||||
|
||||
typedef enum {
|
||||
DMA_ADDR_INCREMENT = 0,
|
||||
DMA_ADDR_DECREMENT = 1,
|
||||
DMA_ADDR_NOCHANGE = 2
|
||||
} enum_addr_state_e;
|
||||
|
||||
typedef enum {
|
||||
DMA_DATAWIDTH_SIZE8 = 1,
|
||||
DMA_DATAWIDTH_SIZE16 = 2,
|
||||
DMA_DATAWIDTH_SIZE32 = 4
|
||||
} dma_datawidth_e;
|
||||
|
||||
typedef enum {
|
||||
DMA_HANDSHAKING_HARDWARE = 0,
|
||||
DMA_HANDSHAKING_SOFTWARE = 1,
|
||||
} dma_handshaking_select_e;
|
||||
|
||||
typedef enum {
|
||||
DMA_PRIORITY0 = 0,
|
||||
DMA_PRIORITY1 = 1,
|
||||
DMA_PRIOTITY2 = 2,
|
||||
DMA_PRIOTITY3 = 3
|
||||
} dma_priority_t;
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t SAR; /* offset: 0x00 (R/W) Channel Source Address Register */
|
||||
__IOM uint32_t DAR; /* offset: 0x04 (R/W) Channel Destination Address Register */
|
||||
__IOM uint32_t CHCTRLA; /* offset: 0x08 (R/W) Channel Control Register A */
|
||||
__IOM uint32_t CHCTRLB; /* offset: 0x0C (R/W) Channel Control Register B */
|
||||
__IOM uint8_t CHINTM:2; /* offset: 0x10 (R/W) Channel Interrupt Mask Register */
|
||||
uint8_t RESERVED0[3];
|
||||
__IM uint8_t CHINTS:2; /* offset: 0x14 (R/ ) Channel Interrupt Status Register */
|
||||
uint8_t RESERVED1[3];
|
||||
__IOM uint8_t CHINTC:2; /* offset: 0x18 (R/W) Channel Interrupt Clear Register */
|
||||
uint8_t RESERVED2[3];
|
||||
__IOM uint8_t CHSREQ:1; /* offset: 0x1C (R/W) Channel Software Request Register */
|
||||
uint8_t RESERVED3[3];
|
||||
__IOM uint8_t CHEN:1; /* offset: 0x20 (R/W) Channel Enable Register */
|
||||
uint8_t RESERVED4[3];
|
||||
} ck_dma_reg_t;
|
||||
#endif /* __CK_DMA_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_eflash.h
|
||||
* @brief head file for ck eflash
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CK_EFLASH_H_
|
||||
#define _CK_EFLASH_H_
|
||||
|
||||
#include "drv_eflash.h"
|
||||
#include "soc.h"
|
||||
|
||||
#define EFLASH_ADDR_START 0x10000000
|
||||
#define EFLASH_ADDR_END 0x1003f7ff
|
||||
#define EFLASH_SECTOR_SIZE 0x200
|
||||
#define EFLASH_ERASED_VALUE 0xff
|
||||
#define EFLASH_PROGRAM_UINT 0x4
|
||||
#define EFLASH_PAGE_SIZE 0
|
||||
#define BLOCK_SIZE 0x200
|
||||
#define IS_EFLASH_ADDR(addr) \
|
||||
((addr >= EFLASH_ADDR_START) && (addr <= EFLASH_ADDR_END))
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file dw_gpio.h
|
||||
* @brief header file for GPIO Driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _DW_GPIO_H_
|
||||
#define _DW_GPIO_H_
|
||||
|
||||
#include "drv_gpio.h"
|
||||
#include "soc.h"
|
||||
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t SWPORT_DR; /* Offset: 0x000 (W/R) PortA data register */
|
||||
__IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (W/R) PortA data direction register */
|
||||
__IOM uint32_t PORT_CTL; /* Offset: 0x008 (W/R) PortA source register */
|
||||
|
||||
} dw_gpio_reg_t;
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t INTEN; /* Offset: 0x000 (W/R) Interrupt enable register */
|
||||
__IOM uint32_t INTMASK; /* Offset: 0x004 (W/R) Interrupt mask register */
|
||||
__IOM uint32_t INTTYPE_LEVEL; /* Offset: 0x008 (W/R) Interrupt level register */
|
||||
__IOM uint32_t INT_POLARITY; /* Offset: 0x00c (W/R) Interrupt polarity register */
|
||||
__IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */
|
||||
__IM uint32_t RAWINTSTATUS; /* Offset: 0x014 (W/R) Raw interrupt status of Port */
|
||||
__IOM uint32_t revreg1; /* Offset: 0x018 (W/R) Reserve register */
|
||||
__OM uint32_t PORTA_EOI; /* Offset: 0x01c (W/R) Port clear interrupt register */
|
||||
__IM uint32_t EXT_PORTA; /* Offset: 0x020 (W/R) PortA external port register */
|
||||
__IM uint32_t EXT_PORTB; /* Offset: 0x024 (W/R) PortB external port register */
|
||||
__IOM uint32_t revreg2[2]; /* Offset: 0x028 (W/R) Reserve register */
|
||||
__IOM uint32_t LS_SYNC; /* Offset: 0x030 (W/R) Level-sensitive synchronization enable register */
|
||||
|
||||
} dw_gpio_control_reg_t;
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file dw_iic.h
|
||||
* @brief header File for IIC Driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __DW_IIC_H
|
||||
#define __DW_IIC_H
|
||||
#include "soc.h"
|
||||
|
||||
/*
|
||||
* Define the speed of I2C
|
||||
*/
|
||||
typedef enum {
|
||||
DW_IIC_STANDARDSPEED = 1,
|
||||
DW_IIC_FASTSPEED = 2,
|
||||
DW_IIC_HIGHSPEED = 3
|
||||
} DWENUM_IIC_SPEED;
|
||||
|
||||
enum i2c_state_e {
|
||||
IIC_STATE_NONE = 0, /* Send start + (first part of) address. */
|
||||
IIC_STATE_DATASEND, /* Send data. */
|
||||
IIC_STATE_WFDATA, /* Wait for data. */
|
||||
IIC_STATE_WFSTOPSENT, /* Wait for STOP to have been transmitted. */
|
||||
IIC_STATE_DONE, /* Transfer completed successfully. */
|
||||
IIC_STATE_ERROR /* Transfer error. */
|
||||
};
|
||||
/*
|
||||
* Define the interrupt type of I2C
|
||||
*/
|
||||
typedef enum {
|
||||
DW_IIC_RX_UNDER = 0,
|
||||
DW_IIC_RX_OVER = 1,
|
||||
DW_IIC_RX_FULL = 2,
|
||||
DW_IIC_TX_OVER = 3,
|
||||
DW_IIC_TX_EMPTY = 4,
|
||||
DW_IIC_RD_REQ = 5,
|
||||
DW_IIC_TX_ABRT = 6,
|
||||
DW_IIC_RX_DONE = 7,
|
||||
DW_IIC_ACTIVITY = 8,
|
||||
DW_IIC_STOP_DET = 9,
|
||||
DW_IIC_START_DET = 10,
|
||||
DW_IIC_GEN_CALL = 11
|
||||
} DWENUM_IIC_INTERRUPT_TYPE;
|
||||
|
||||
/*
|
||||
* I2C register bit definitions
|
||||
*/
|
||||
#define DW_IIC_DISABLE 0
|
||||
#define DW_IIC_ENABLE 1
|
||||
#define DW_IIC_FIFO_MAX_LV 0x8
|
||||
#define DW_IIC_TXFIFO_LV 0x2
|
||||
#define DW_IIC_RXFIFO_LV 0x0
|
||||
|
||||
#define DW_IIC_RXFIFO_FULL (0x1 << 4)
|
||||
#define DW_IIC_RXFIFO_NOT_EMPTY (0x1 << 3)
|
||||
#define DW_IIC_TXFIFO_EMPTY (0x1 << 2)
|
||||
#define DW_IIC_TXFIFO_NOT_FULL (0x1 << 1)
|
||||
#define DW_IIC_STATUS_ACTIVITY 0x1
|
||||
|
||||
#define DW_IIC_CON_DEFAUL 0x23
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t IC_CON; /* Offset: 0x000 (R/W) Receive buffer register */
|
||||
__IOM uint32_t IC_TAR; /* Offset: 0x004 (R/W) Transmission hold register */
|
||||
__IOM uint32_t IC_SAR; /* Offset: 0x008 (R/W) Clock frequency division low section register */
|
||||
__IOM uint32_t IC_HS_MADDR; /* Offset: 0x00c (R/W) Clock frequency division high section register */
|
||||
__IOM uint32_t IC_DATA_CMD; /* Offset: 0x010 (R/W) Interrupt enable register */
|
||||
__IOM uint32_t IC_SS_SCL_HCNT; /* Offset: 0x014 (R/W) Interrupt indicia register */
|
||||
__IOM uint32_t IC_SS_SCL_LCNT; /* Offset: 0x018 (R/W) Transmission control register */
|
||||
__IOM uint32_t IC_FS_SCL_HCNT; /* Offset: 0x01c (R/W) Modem control register */
|
||||
__IOM uint32_t IC_FS_SCL_LCNT; /* Offset: 0x020 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_HS_SCL_HCNT; /* Offset: 0x024 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_HS_SCL_LCNT; /* Offset: 0x028 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_INTR_STAT; /* Offset: 0x02c (R) Transmission state register */
|
||||
__IOM uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_RAW_INTR_STAT; /* Offset: 0x034 (R) Transmission state register */
|
||||
__IOM uint32_t IC_RX_TL; /* Offset: 0x038 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_TX_TL; /* Offset: 0x03c (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_INTR; /* Offset: 0x040 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_RX_UNDER; /* Offset: 0x044 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_RX_OVER; /* Offset: 0x048 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_TX_OVER; /* Offset: 0x04c (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_RD_REQ; /* Offset: 0x050 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_TX_ABRT; /* Offset: 0x054 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_RX_DONE; /* Offset: 0x058 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_ACTIVITY; /* Offset: 0x05c (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_STOP_DET; /* Offset: 0x060 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_START_DET; /* Offset: 0x064 (R) Transmission state register */
|
||||
__IOM uint32_t IC_CLR_GEN_CALL; /* Offset: 0x068 (R) Transmission state register */
|
||||
__IOM uint32_t IC_ENABLE; /* Offset: 0x06c (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_STATUS; /* Offset: 0x070 (R) Transmission state register */
|
||||
__IOM uint32_t IC_TXFLR; /* Offset: 0x074 (R) Transmission state register */
|
||||
__IOM uint32_t IC_RXFLR; /* Offset: 0x078 (R) Transmission state register */
|
||||
uint32_t RESERVED; /* Offset: 0x014 (R/ ) Transmission state register */
|
||||
__IOM uint32_t IC_TX_ABRT_SOURCE; /* Offset: 0x080 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_SAR1; /* Offset: 0x084 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_DMA_CR; /* Offset: 0x088 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_DMA_TDLR; /* Offset: 0x08c (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_DMA_RDLR; /* Offset: 0x090 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_SAR2; /* Offset: 0x094 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_SAR3; /* Offset: 0x098 (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_MULTI_SLAVE; /* Offset: 0x09c (R/W) Transmission state register */
|
||||
__IOM uint32_t IC_GEN_CALL_EN; /* Offset: 0x0a0 (R/W) Transmission state register */
|
||||
} dw_iic_reg_t;
|
||||
|
||||
#endif /* __DW_IIC_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_pwm.h
|
||||
* @brief header file for pwm driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __CK_PWM_H
|
||||
#define __CK_PWM_H
|
||||
#include <stdio.h>
|
||||
#include "soc.h"
|
||||
|
||||
typedef enum {
|
||||
CKENUM_PWM_CH0 = 0,
|
||||
CKENUM_PWM_CH1 = 1,
|
||||
CKENUM_PWM_CH2 = 2,
|
||||
CKENUM_PWM_CH3 = 3,
|
||||
CKENUM_PWM_CH4 = 4,
|
||||
CKENUM_PWM_CH5 = 5,
|
||||
CKENUM_PWM_CH6 = 6,
|
||||
CKENUM_PWM_CH7 = 7,
|
||||
CKENUM_PWM_CH8 = 8,
|
||||
CKENUM_PWM_CH9 = 9,
|
||||
CKENUM_PWM_CH10 = 10,
|
||||
CKENUM_PWM_CH11 = 11
|
||||
} CKENUM_PWM_CHANNEL;
|
||||
|
||||
typedef enum {
|
||||
CKENUM_PWM_COUNT_UP = 0,
|
||||
CKENUM_PWM_COUNT_UP_DOWN = 1
|
||||
} CKENUM_PWM_COUNTER_MODE;
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t PWMCFG; /* Offset: 0x000 (R/W) PWM configure register */
|
||||
__IOM uint32_t PWMINVERTTRIG; /* Offset: 0x004 (R/W) PWM signal is inverted register */
|
||||
__IOM uint32_t PWM01TRIG; /* Offset: 0x008 (R/W) contain the trigger generate compare value */
|
||||
__IOM uint32_t PWM23TRIG; /* Offset: 0x00C (R/W) contain the trigger generate compare value */
|
||||
__IOM uint32_t PWM45TRIG; /* Offset: 0x010 (N/A) contain the trigger generate compare value */
|
||||
__IOM uint32_t PWMINTEN1; /* Offset: 0x014 (R/W) interrupt enable */
|
||||
__IM uint32_t PWMINTEN2; /* Offset: 0x018 (N/A) interrupt enable */
|
||||
__IOM uint32_t PWMRIS1; /* Offset: 0x01C (R/ ) raw interrupt status */
|
||||
__IOM uint32_t PWMRIS2; /* Offset: 0x020 (N/A) raw interrupt status */
|
||||
__IOM uint32_t PWMIC1; /* Offset: 0x024 (R/W) interrupt clear */
|
||||
__IOM uint32_t PWMIC2; /* Offset: 0x028 (R/W) interrupt clear */
|
||||
__IOM uint32_t PWMIS1; /* Offset: 0x02C (R/W) interrupt status */
|
||||
__IOM uint32_t PWMIS2; /* Offset: 0x030 (R/W) interrupt status */
|
||||
__IOM uint32_t PWMCTL; /* Offset: 0x034 (R/W) configure the pwm generation blocks */
|
||||
__IOM uint32_t PWM01LOAD; /* Offset: 0x038 (R/W) contain the load value of the PWM count */
|
||||
__IOM uint32_t PWM23LOAD; /* Offset: 0x03C (R/W) contain the load value of the PWM count */
|
||||
__IOM uint32_t PWM45LOAD; /* Offset: 0x040 (N/A) contain the load value of the PWM count */
|
||||
__IM uint32_t PWM01COUNT; /* Offset: 0x044 (R/ ) contain the current value of the PWM count */
|
||||
__IM uint32_t PWM23COUNT; /* Offset: 0x048 (R/ ) contain the current value of the PWM count */
|
||||
__IOM uint32_t PWM45COUNT; /* Offset: 0x04C (N/A) contain the current value of the PWM count */
|
||||
__IOM uint32_t PWM0CMP; /* Offset: 0x050 (R/W) contain a value to be compared against the counter */
|
||||
__IOM uint32_t PWM1CMP; /* Offset: 0x054 (R/W) contain a value to be compared against the counter */
|
||||
__IOM uint32_t PWM2CMP; /* Offset: 0x058 (R/W) contain a value to be compared against the counter */
|
||||
__IOM uint32_t PWM3CMP; /* Offset: 0x05C (N/A) contain a value to be compared against the counter */
|
||||
__IOM uint32_t PWM4CMP; /* Offset: 0x060 (N/A) contain a value to be compared against the counter */
|
||||
__IOM uint32_t PWM5CMP; /* Offset: 0x064 (N/A) contain a value to be compared against the counter */
|
||||
__IOM uint32_t PWM01DB; /* Offset: 0x068 (R/W) contain the number of clock ticks to delay */
|
||||
__IOM uint32_t PWM23DB; /* Offset: 0x06C (R/W) contain the number of clock ticks to delayr */
|
||||
__IOM uint32_t PWM45DB; /* Offset: 0x070 (N/A) contain the number of clock ticks to delay */
|
||||
__IOM uint32_t CAPCTL; /* Offset: 0x074 (R/W) input capture control */
|
||||
__IOM uint32_t CAPINTEN; /* Offset: 0x078 (R/W) input capture interrupt enable */
|
||||
__IM uint32_t CAPRIS; /* Offset: 0x07C (R/ ) input capture raw interrupt status */
|
||||
__IOM uint32_t CAPIC; /* Offset: 0x080 (R/W) input capture interrupt clear */
|
||||
__IM uint32_t CAPIS; /* Offset: 0x084 (R/ ) input capture interrupt status */
|
||||
__IM uint32_t CAP01T; /* Offset: 0x088 (R/ ) input capture count value */
|
||||
__IM uint32_t CAP23T; /* Offset: 0x08C (R/ ) input capture count value */
|
||||
__IOM uint32_t CAP45T; /* Offset: 0x090 (N/A) input capture count value */
|
||||
__IOM uint32_t CAP01MATCH; /* Offset: 0x094 (R/W) input capture match value */
|
||||
__IOM uint32_t CAP23MATCH; /* Offset: 0x098 (R/W) input capture match value */
|
||||
__IOM uint32_t CAP45MATCH; /* Offset: 0x09C (N/A) input capture match value */
|
||||
__IOM uint32_t TIMINTEN; /* Offset: 0x0A0 (R/W) time interrupt enable */
|
||||
__IM uint32_t TIMRIS; /* Offset: 0x0A4 (R/ ) time raw interrupt stats */
|
||||
__IOM uint32_t TIMIC; /* Offset: 0x0A8 (R/W) time interrupt clear */
|
||||
__IM uint32_t TIMIS; /* Offset: 0x0AC (R/ ) time interrupt status */
|
||||
__IOM uint32_t TIM01LOAD; /* Offset: 0x0B0 (R/W) time load value */
|
||||
__IOM uint32_t TIM23LOAD; /* Offset: 0x0B4 (R/W) time load value */
|
||||
__IOM uint32_t TIM45LOAD; /* Offset: 0x0B8 (N/A) time load value */
|
||||
__IOM uint32_t TIM01COUNT; /* Offset: 0x0BC (R/W) time current count time */
|
||||
__IOM uint32_t TIM23COUNT; /* Offset: 0x0C0 (R/W) time current count time */
|
||||
__IOM uint32_t TIM45COUNT; /* Offset: 0x0C4 (R/W) time current count time */
|
||||
} ck_pwm_reg_t;
|
||||
|
||||
#endif /* __CK_PWM_H */
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_rsa.h
|
||||
* @brief header file for rsa driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CK_RSA_H_
|
||||
#define _CK_RSA_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include "drv_rsa.h"
|
||||
#include "soc.h"
|
||||
|
||||
#define RSA_KEY_LEN 1024
|
||||
#define RSA_KEY_BYTE (RSA_KEY_LEN >> 3)
|
||||
#define RSA_KEY_WORD (RSA_KEY_LEN >> 5)
|
||||
|
||||
#define BN_MAX_BITS ((RSA_KEY_LEN << 1) + 32)
|
||||
#define BN_MAX_BYTES ((BN_MAX_BITS + 7) >> 3)
|
||||
#define BN_MAX_WORDS ((BN_MAX_BYTES + 3) >> 2)
|
||||
|
||||
#define MAX_RSA_LP_CNT 10000
|
||||
|
||||
#define UINT32_TO_UINT64(data) ((uint64_t)(((uint64_t)(data)) & 0x00000000ffffffffU))
|
||||
#define UINT64L_TO_UINT32(data) ((uint32_t)(((uint64_t)(data)) & 0x00000000ffffffffU))
|
||||
#define UINT64H_TO_UINT32(data) ((uint32_t)((((uint64_t)(data)) >> 32) & 0x00000000ffffffffU))
|
||||
|
||||
#define PKCS1_PADDING 0x01
|
||||
#define NO_PADDING 0x02
|
||||
|
||||
#define MD5_PADDING 0x00
|
||||
#define SHA1_PADDING 0x01
|
||||
|
||||
#define MD5_HASH_SZ 16
|
||||
#define SHA1_HASH_SZ 20
|
||||
|
||||
#define RAS_CALCULATE_Q 0x6
|
||||
#define RSA_ENABLE_MODULE 0x3
|
||||
#define RSA_ENDIAN_MODE 0x8
|
||||
#define RSA_RESET 0x1
|
||||
#define RSA_CAL_Q_DONE_OFFSET 0x5
|
||||
|
||||
typedef struct bignum {
|
||||
uint32_t pdata[BN_MAX_WORDS];
|
||||
uint32_t words;
|
||||
} bignum_t;
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t rsa_mwid; /* Offset: 0x000 (R/W) Width of M register */
|
||||
__IOM uint32_t rsa_ckid; /* Offset: 0x004 (R/W) Width of D register */
|
||||
__IOM uint32_t rsa_bwid; /* Offset: 0x008 (R/W) Width of B register */
|
||||
__IOM uint32_t rsa_ctrl; /* Offset: 0x00c (R/W) RSA control register */
|
||||
__OM uint32_t rsa_rst; /* Offset: 0x010 (W) RSA reset register */
|
||||
__IM uint32_t rsa_lp_cnt; /* Offset: 0x014 (R) Loop counter for inquiry register*/
|
||||
__IM uint32_t rsa_q0; /* Offset: 0x018 (R) High-radix MM algorithm assistant register,part 1*/
|
||||
__IM uint32_t rsa_q1; /* Offset: 0x01c (R) High-radix MM algorithm assistant register,part 2*/
|
||||
__IOM uint32_t rsa_isr; /* Offset: 0x020 (W/R) Interrupt raw status register */
|
||||
__IOM uint32_t rsa_imr; /* Offset: 0x024 (W/R) Interrupt mask register */
|
||||
__IOM uint32_t rev1[54]; /* Reserve regiser */
|
||||
__IOM uint32_t rsa_rfm; /* Offset: 0x100 (W/R) Register file for modulus M */
|
||||
__IOM uint32_t rev2[63]; /* Reserve regiser */
|
||||
__IOM uint32_t rsa_rfd; /* Offset: 0x200 (W/R) Register file for exponent D */
|
||||
__IOM uint32_t rev3[63]; /* Reserve regiser */
|
||||
__IOM uint32_t rsa_rfc; /* Offset: 0x300 (W/R) Register file for hard C */
|
||||
__IOM uint32_t rev4[63]; /* Reserve regiser */
|
||||
__IOM uint32_t rsa_rfb; /* Offset: 0x400 (W/R) Register file for data B */
|
||||
__IOM uint32_t rev5[63]; /* Reserve regiser */
|
||||
__IM uint32_t rsa_rfr; /* Offset: 0x500 (R) Register file for storing the result */
|
||||
} ck_rsa_reg_t;
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_rtc.h
|
||||
* @brief header file for rtc driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __CK_RTC_H
|
||||
#define __CK_RTC_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include "soc.h"
|
||||
|
||||
#define SEC_PER_MIN ((time_t)60)
|
||||
#define SEC_PER_HOUR ((time_t)60 * SEC_PER_MIN)
|
||||
#define SEC_PER_DAY ((time_t)24 * SEC_PER_HOUR)
|
||||
|
||||
typedef struct {
|
||||
__IM uint32_t RTC_CCVR; /* Offset: 0x000 (R/ ) current count value register */
|
||||
__IOM uint32_t RTC_CMR; /* Offset: 0x004 (R/W) count match register */
|
||||
__IOM uint32_t RTC_CLR; /* Offset: 0x008 (R/W) count load register */
|
||||
__IOM uint32_t RTC_CCR; /* Offset: 0x00c (R/W) count control register */
|
||||
__IM uint32_t RTC_STAT; /* Offset: 0x010 (R/ ) interrupt status register */
|
||||
__IM uint32_t RTC_RSTAT; /* Offset: 0x014 (R/ ) interrupt raw status register */
|
||||
__IM uint32_t RTC_EOI; /* Offset: 0x018 (R/ ) end of interrupt register */
|
||||
__IM uint32_t RTC_COMP_VERSION; /* Offset: 0x01c (R/ ) component version register */
|
||||
} ck_rtc_reg_t;
|
||||
|
||||
#endif /* __CK_RTC_H */
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_sha.h
|
||||
* @brief header file for sha driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CK_SHA_H_
|
||||
#define _CK_SHA_H_
|
||||
|
||||
#include <stdio.h>
|
||||
#include "drv_sha.h"
|
||||
#include "soc.h"
|
||||
|
||||
#define SHA_INIT_OFFSET 3
|
||||
#define SHA_INT_ENABLE_OFFSET 4
|
||||
#define SHA_ENDIAN_OFFSET 5
|
||||
#define SHA_CAL_OFFSET 6
|
||||
typedef struct {
|
||||
__IOM uint32_t SHA_CON; /* Offset: 0x000 (R/W) Control register */
|
||||
__IOM uint32_t SHA_INTSTATE; /* Offset: 0x004 (R/W) Instatus register */
|
||||
__IOM uint32_t SHA_H0L; /* Offset: 0x008 (R/W) H0L register */
|
||||
__IOM uint32_t SHA_H1L; /* Offset: 0x00c (R/W) H1L register */
|
||||
__IOM uint32_t SHA_H2L; /* Offset: 0x010 (R/W) H2L register */
|
||||
__IOM uint32_t SHA_H3L; /* Offset: 0x014 (R/W) H3L register */
|
||||
__IOM uint32_t SHA_H4L; /* Offset: 0x018 (R/W) H4L register */
|
||||
__IOM uint32_t SHA_H5L; /* Offset: 0x01c (R/W) H5L register */
|
||||
__IOM uint32_t SHA_H6L; /* Offset: 0x020 (R/W) H6L register */
|
||||
__IOM uint32_t SHA_H7L; /* Offset: 0x024 (R/W) H7L register */
|
||||
__IOM uint32_t SHA_H0H; /* Offset: 0x028 (R/W) H0H register */
|
||||
__IOM uint32_t SHA_H1H; /* Offset: 0x02c (R/W) H1H register */
|
||||
__IOM uint32_t SHA_H2H; /* Offset: 0x030 (R/W) H2H register */
|
||||
__IOM uint32_t SHA_H3H; /* Offset: 0x034 (R/W) H3H register */
|
||||
__IOM uint32_t SHA_H4H; /* Offset: 0x038 (R/W) H4H register */
|
||||
__IOM uint32_t SHA_H5H; /* Offset: 0x03c (R/W) H5H register */
|
||||
__IOM uint32_t SHA_H6H; /* Offset: 0x040 (R/W) H6H register */
|
||||
__IOM uint32_t SHA_H7H; /* Offset: 0x044 (R/W) H7H register */
|
||||
__IOM uint32_t SHA_DATA1; /* Offset: 0x048 (R/W) DATA1 register */
|
||||
uint32_t REV[15];
|
||||
__IOM uint32_t SHA_DATA2; /* Offset: 0x088 (R/W) DATA2 register */
|
||||
} ck_sha_reg_t;
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
SHA_STATUS_START_END = 0, /* the one time count mode */
|
||||
SHA_STATUS_START = 1, /* the first time of the cal */
|
||||
SHA_STATUS_CONTINUE = 2, /* the middle stage of the cal */
|
||||
SHA_STATUS_END = 3 /* the last time of the cal*/
|
||||
} enum_sha_status;
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,159 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file dw_spi.h
|
||||
* @brief header file for spi driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __DW_SPI_H
|
||||
#define __DW_SPI_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include "soc.h"
|
||||
|
||||
/*
|
||||
* SPI register bit definitions
|
||||
*/
|
||||
#define DW_SPI_ENABLE 0x01
|
||||
#define DW_SPI_DISABLE 0x00
|
||||
#define DW_SPI_TMOD_BIT8 0x0100
|
||||
#define DW_SPI_TMOD_BIT9 0x0200
|
||||
#define DW_SPI_POLARITY 0x80
|
||||
#define DW_SPI_PHASE 0x40
|
||||
#define DW_SPI_BUSY 0x01
|
||||
#define DW_SPI_TFE 0x04
|
||||
#define DW_SPI_RFNE 0x08
|
||||
#define DW_SPI_INT_EN 0x19
|
||||
#define DW_SPI_RINT_EN 0x3e
|
||||
#define DW_SPI_TINT_EN 0x3f
|
||||
#define DW_SPI_INT_DISABLE 0x00
|
||||
#define DW_SPI_INT_MASK_RX 0x27
|
||||
#define DW_SPI_INT_MASKTX 0x3e
|
||||
#define DW_SPI_RDMAE 0x1
|
||||
#define DW_SPI_TDMAE 0x2
|
||||
#define DW_SPI_TXFIFO_LV 0x0
|
||||
#define DW_SPI_RXFIFO_LV 0x1d
|
||||
#define DW_SPI_RXFIFO_NOT_EMPTY 0x08
|
||||
#define DW_SPI_START_RX 0x0
|
||||
#define DW_SPI_FIFO_MAX_LV 0x20
|
||||
#define DW_SPI_FIFO_OVER_LV 0x18
|
||||
#define DW_SPI_RXFIFO_OVERFLOW 0x08
|
||||
#define DW_SPI_RXFIFO_FULL 0x10
|
||||
#define DW_SPI_TXFIFO_EMPTY 0x01
|
||||
#define SPI_CS_SELECTED 0x0
|
||||
#define DW_SPI_IMR_TXEIM 0x01 /* Transmit FIFO Empty Interrupt Mask */
|
||||
#define DW_SPI_IMR_RXFIM 0x10 /* Receive FIFO Full Interrupt Mask */
|
||||
|
||||
|
||||
/* some infoermationgs of SPI for special MCU */
|
||||
#define DW_SPI_DEFAULT_BAUDR 10000000 /* 10M */
|
||||
#define DW_SPI_MAXID 0x1
|
||||
|
||||
#define SPI_INITIALIZED ((uint8_t)(1U)) // SPI initalized
|
||||
#define SPI_POWERED ((uint8_t)(1U<< 1)) // SPI powered on
|
||||
#define SPI_CONFIGURED ((uint8_t)(1U << 2)) // SPI configured
|
||||
#define SPI_DATA_LOST ((uint8_t)(1U << 3)) // SPI data lost occurred
|
||||
#define SPI_MODE_FAULT ((uint8_t)(1U << 4)) // SPI mode fault occurred
|
||||
|
||||
|
||||
typedef enum {
|
||||
DWENUM_SPI_DMACR_RXE = 0,
|
||||
DWENUM_SPI_DMACR_TXE = 1,
|
||||
} DWENUM_SPI_DMACR;
|
||||
|
||||
|
||||
typedef enum {
|
||||
DWENUM_SPI_TXRX = 0,
|
||||
DWENUM_SPI_TX = 1,
|
||||
DWENUM_SPI_RX = 2,
|
||||
DWENUM_SPI_EERX = 3
|
||||
} DWENUM_SPI_MODE;
|
||||
|
||||
typedef enum {
|
||||
DWENUM_SPI_CLOCK_POLARITY_LOW = 0,
|
||||
DWENUM_SPI_CLOCK_POLARITY_HIGH = 1
|
||||
} DWENUM_SPI_POLARITY;
|
||||
|
||||
typedef enum {
|
||||
DWENUM_SPI_CLOCK_PHASE_MIDDLE = 0,
|
||||
DWENUM_SPI_CLOCK_PHASE_START = 1
|
||||
} DWENUM_SPI_PHASE;
|
||||
|
||||
typedef enum {
|
||||
DWENUM_SPI_DATASIZE_4 = 3,
|
||||
DWENUM_SPI_DATASIZE_5 = 4,
|
||||
DWENUM_SPI_DATASIZE_6 = 5,
|
||||
DWENUM_SPI_DATASIZE_7 = 6,
|
||||
DWENUM_SPI_DATASIZE_8 = 7,
|
||||
DWENUM_SPI_DATASIZE_9 = 8,
|
||||
DWENUM_SPI_DATASIZE_10 = 9,
|
||||
DWENUM_SPI_DATASIZE_11 = 10,
|
||||
DWENUM_SPI_DATASIZE_12 = 11,
|
||||
DWENUM_SPI_DATASIZE_13 = 12,
|
||||
DWENUM_SPI_DATASIZE_14 = 13,
|
||||
DWENUM_SPI_DATASIZE_15 = 14,
|
||||
DWENUM_SPI_DATASIZE_16 = 15
|
||||
} DWENUM_SPI_DATAWIDTH;
|
||||
|
||||
typedef enum {
|
||||
DWENUM_SPI_CS0 = 1,
|
||||
DWENUM_SPI_CS1 = 2
|
||||
} DWENUM_SPI_SLAVE;
|
||||
|
||||
typedef struct {
|
||||
__IOM uint16_t CTRLR0; /* Offset: 0x000 (R/W) Control register 0 */
|
||||
uint16_t RESERVED0;
|
||||
__IOM uint16_t CTRLR1; /* Offset: 0x004 (R/W) Control register 1 */
|
||||
uint16_t RESERVED1;
|
||||
__IOM uint8_t SPIENR; /* Offset: 0x008 (R/W) SSI enable regiseter */
|
||||
uint8_t RESERVED2[7];
|
||||
__IOM uint32_t SER; /* Offset: 0x010 (R/W) Slave enable register */
|
||||
__IOM uint16_t BAUDR; /* Offset: 0x014 (R/W) Baud rate select */
|
||||
uint16_t RESERVED3;
|
||||
__IOM uint32_t TXFTLR; /* Offset: 0x018 (R/W) Transmit FIFO Threshold Level */
|
||||
__IOM uint32_t RXFTLR; /* Offset: 0x01c (R/W) Receive FIFO Threshold Level */
|
||||
__IOM uint32_t TXFLR; /* Offset: 0x020 (R/W) Transmit FIFO Level register */
|
||||
__IOM uint32_t RXFLR; /* Offset: 0x024 (R/W) Receive FIFO Level Register */
|
||||
__IOM uint8_t SR; /* Offset: 0x028 (R/W) status register */
|
||||
uint8_t RESERVED4[3];
|
||||
__IOM uint32_t IMR; /* Offset: 0x02C (R/W) Interrupt Mask Register */
|
||||
__IM uint32_t ISR; /* Offset: 0x030 (R/W) interrupt status register */
|
||||
__IM uint32_t RISR; /* Offset: 0x034 (R/W) Raw Interrupt Status Register */
|
||||
__IM uint8_t TXOICR; /* Offset: 0x038 (R/W) Transmit FIFO Overflow Interrupt Clear Register */
|
||||
uint8_t RESERVED5[3];
|
||||
__IM uint8_t RXOICR; /* Offset: 0x03C (R/W) Receive FIFO Overflow Interrupt Clear Register*/
|
||||
uint8_t RESERVED6[3];
|
||||
__IM uint8_t RXUICR; /* Offset: 0x040 (R/W) Receive FIFO Underflow Interrupt Clear Register */
|
||||
uint8_t RESERVED7[3];
|
||||
__IM uint8_t MSTICR; /* Offset: 0x044 (R/W) Multi-Master Interrupt Clear Register */
|
||||
uint8_t RESERVED8[3];
|
||||
__IM uint8_t ICR; /* Offset: 0x048 (R/W) Interrupt Clear Register */
|
||||
uint8_t RESERVED9[3];
|
||||
__IOM uint8_t DMACR; /* Offset: 0x04C (R/W) DMA Control Register */
|
||||
uint8_t RESERVED10[3];
|
||||
__IOM uint8_t DMATDLR; /* Offset: 0x050 (R/W) DMA Transmoit Data Level */
|
||||
uint8_t RESERVED11[3];
|
||||
__IOM uint8_t DMARDLR; /* Offset: 0x054 (R/W) DMA Receive Data Level */
|
||||
uint8_t RESERVED12[3];
|
||||
__IM uint32_t IDR; /* Offset: 0x058 (R/W) identification register */
|
||||
uint32_t RESERVED13;
|
||||
__IOM uint16_t DR; /* Offset: 0x060 (R/W) Data Register */
|
||||
uint16_t RESERVED14[17];
|
||||
__IOM uint8_t WR; /* Offset: 0x0A0 (R/W) SPI is Master or Slave Select Register */
|
||||
} dw_spi_reg_t;
|
||||
|
||||
#endif /* __DW_SPI_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file dw_timer.h
|
||||
* @brief header file for timer driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __DW_TIMER_H
|
||||
#define __DW_TIMER_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include "soc.h"
|
||||
|
||||
/*
|
||||
* define the bits for TxControl
|
||||
*/
|
||||
#define DW_TIMER_TXCONTROL_ENABLE (1UL << 0)
|
||||
#define DW_TIMER_TXCONTROL_MODE (1UL << 1)
|
||||
#define DW_TIMER_TXCONTROL_INTMASK (1UL << 2)
|
||||
|
||||
#define DW_TIMER_INIT_DEFAULT_VALUE 0x7ffffff
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */
|
||||
__IM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */
|
||||
__IOM uint8_t TxControl: 4; /* Offset: 0x008 (R/W) Clock frequency division low section register */
|
||||
uint8_t RESERVED0[3];
|
||||
__IM uint8_t TxEOI: 1; /* Offset: 0x00c (R) Clock frequency division high section register */
|
||||
uint8_t RESERVED1[3];
|
||||
__IM uint8_t TxIntStatus: 1; /* Offset: 0x010 (R) Interrupt enable register */
|
||||
uint8_t RESERVED2[3];
|
||||
} dw_timer_reg_t;
|
||||
|
||||
#endif /* __DW_TIMER_H */
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file ck_trng.h
|
||||
* @brief header file for trng driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CK_TRNG_H_
|
||||
#define _CK_TRNG_H_
|
||||
|
||||
#include "drv_trng.h"
|
||||
#include "soc.h"
|
||||
|
||||
/*
|
||||
* define the bits for TCR
|
||||
*/
|
||||
#define TRNG_EN (1UL << 1)
|
||||
#define TRNG_LOWPER_MODE (1UL << 2)
|
||||
#define TRNG_DATA_READY 1
|
||||
|
||||
typedef struct {
|
||||
__IOM uint32_t TCR; /* Offset: 0x000 (W/R) TRNG control register */
|
||||
__IM uint32_t TDR; /* Offset: 0x004 (R) TRNG Data register */
|
||||
|
||||
} ck_trng_reg_t;
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file dw_usart.h
|
||||
* @brief header file for usart driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __DW_USART_H
|
||||
#define __DW_USART_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include "errno.h"
|
||||
#include "soc.h"
|
||||
|
||||
#define BAUDRATE_DEFAULT 19200
|
||||
#define UART_BUSY_TIMEOUT 1000000
|
||||
#define UART_RECEIVE_TIMEOUT 1000
|
||||
#define UART_TRANSMIT_TIMEOUT 1000
|
||||
#define UART_MAX_FIFO 0x10
|
||||
/* UART register bit definitions */
|
||||
|
||||
#define USR_UART_BUSY 0x01
|
||||
#define USR_UART_TFE 0x04
|
||||
#define USR_UART_RFNE 0x08
|
||||
#define LSR_DATA_READY 0x01
|
||||
#define LSR_THR_EMPTY 0x20
|
||||
#define IER_RDA_INT_ENABLE 0x01
|
||||
#define IER_THRE_INT_ENABLE 0x02
|
||||
#define IIR_NO_ISQ_PEND 0x01
|
||||
|
||||
#define LCR_SET_DLAB 0x80 /* enable r/w DLR to set the baud rate */
|
||||
#define LCR_PARITY_ENABLE 0x08 /* parity enabled */
|
||||
#define LCR_PARITY_EVEN 0x10 /* Even parity enabled */
|
||||
#define LCR_PARITY_ODD 0xef /* Odd parity enabled */
|
||||
#define LCR_WORD_SIZE_5 0xfc /* the data length is 5 bits */
|
||||
#define LCR_WORD_SIZE_6 0x01 /* the data length is 6 bits */
|
||||
#define LCR_WORD_SIZE_7 0x02 /* the data length is 7 bits */
|
||||
#define LCR_WORD_SIZE_8 0x03 /* the data length is 8 bits */
|
||||
#define LCR_STOP_BIT1 0xfb /* 1 stop bit */
|
||||
#define LCR_STOP_BIT2 0x04 /* 1.5 stop bit */
|
||||
|
||||
#define DW_LSR_PFE 0x80
|
||||
#define DW_LSR_TEMT 0x40
|
||||
#define DW_LSR_THRE 0x40
|
||||
#define DW_LSR_BI 0x10
|
||||
#define DW_LSR_FE 0x08
|
||||
#define DW_LSR_PE 0x04
|
||||
#define DW_LSR_OE 0x02
|
||||
#define DW_LSR_DR 0x01
|
||||
#define DW_LSR_TRANS_EMPTY 0x20
|
||||
|
||||
#define DW_FCR_FIFOE 0x01
|
||||
#define DW_FCR_RFIFOR 0x02
|
||||
#define DW_FCR_XFIFOR 0x04
|
||||
#define DW_FCR_RT_FIFO_SINGLE 0x00 /* rcvr trigger 1 character in the FIFO */
|
||||
#define DW_FCR_RT_FIFO_QUARTER 0x01 /* rcvr trigger FIFO 1/4 full */
|
||||
#define DW_FCR_RT_FIFO_HALF 0x10 /* rcvr trigger FIFO 1/2 full */
|
||||
#define DW_FCR_RT_FIFO_LESSTWO 0x11 /* rcvr trigger FIFO 2 less than full */
|
||||
#define DW_FCR_TET_FIFO_EMPTY 0x00 /* tx empty trigger FIFO empty */
|
||||
#define DW_FCR_TET_FIFO_TWO 0x01 /* tx empty trigger 2 characters in the FIFO */
|
||||
#define DW_FCR_TET_FIFO_QUARTER 0x10 /* tx empty trigger FIFO 1/4 full */
|
||||
#define DW_FCR_TET_FIFO_HALF 0x11 /* tx empty trigger FIFO 1/2 full*/
|
||||
|
||||
#define DW_IIR_THR_EMPTY 0x02 /* threshold empty */
|
||||
#define DW_IIR_RECV_DATA 0x04 /* received data available */
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
__IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */
|
||||
__OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */
|
||||
__IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */
|
||||
};
|
||||
union {
|
||||
__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */
|
||||
__IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */
|
||||
};
|
||||
union {
|
||||
__IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt indicia register */
|
||||
__OM uint32_t FCR; /* Offset: 0x008 ( /W) FIFO control register */
|
||||
};
|
||||
__IOM uint32_t LCR; /* Offset: 0x00C (R/W) Transmission control register */
|
||||
__IOM uint32_t MCR; /* Offset: 0x010 (R/W) Modem control register */
|
||||
__IM uint32_t LSR; /* Offset: 0x014 (R/ ) Transmission state register */
|
||||
__IM uint32_t MSR; /* Offset: 0x018 (R/ ) Modem state register */
|
||||
uint32_t RESERVED1[21];
|
||||
__IOM uint32_t FAR; /* Offset: 0x070 (R/W) FIFO accesss register */
|
||||
__IM uint32_t TFR; /* Offset: 0x074 (R/ ) transmit FIFO read */
|
||||
__OM uint32_t RFW; /* Offset: 0x078 ( /W) receive FIFO write */
|
||||
__IM uint32_t USR; /* Offset: 0x07c (R/ ) UART state register */
|
||||
__IM uint32_t TFL; /* Offset: 0x080 (R/ ) transmit FIFO level */
|
||||
__IM uint32_t RFL; /* Offset: 0x084 (R/ ) receive FIFO level */
|
||||
} dw_usart_reg_t;
|
||||
|
||||
|
||||
#endif /* __DW_USART_H */
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file dw_wdt.h
|
||||
* @brief header file for wdt driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef __DW_WDT_H
|
||||
#define __DW_WDT_H
|
||||
|
||||
#include <stdio.h>
|
||||
#include "soc.h"
|
||||
|
||||
#define DW_WDT_CRR_RESET 0x76
|
||||
typedef struct {
|
||||
__IOM uint8_t WDT_CR:5; /* Offset: 0x000 (R/W) WDT control register */
|
||||
uint8_t RESERVED0[3];
|
||||
__IOM uint8_t WDT_TORR; /* Offset: 0x004 (R/W) WDT timeout range register */
|
||||
uint8_t RESERVED1[3];
|
||||
__IM uint32_t WDT_CCVR; /* Offset: 0x008 (R/ ) WDT current counter value register */
|
||||
__OM uint8_t WDT_CRR:8; /* Offset: 0x00C ( /W) WDT count restart register */
|
||||
uint8_t RESERVED2[3];
|
||||
__IM uint8_t WDT_STAT:1; /* Offset: 0x010 (R/ ) WDT interrupt status register */
|
||||
uint8_t RESERVED3[3];
|
||||
__IM uint8_t WDT_EOI:1; /* Offset: 0x014 (R/ ) WDT interrupt clear register */
|
||||
uint8_t RESERVED4[3];
|
||||
} dw_wdt_reg_t;
|
||||
|
||||
#endif /* __DW_WDT_H */
|
||||
|
||||
@@ -0,0 +1,189 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file drv_aes.h
|
||||
* @brief Header File for AES Driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CSI_AES_H_
|
||||
#define _CSI_AES_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
#include <drv_errno.h>
|
||||
|
||||
|
||||
/// definition for aes handle.
|
||||
typedef void *aes_handle_t;
|
||||
|
||||
/****** AES specific error codes *****/
|
||||
typedef enum {
|
||||
AES_ERROR_MODE = (EDRV_SPECIFIC + 1) , ///< Specified Mode not supported
|
||||
AES_ERROR_DATA_BITS , ///< Specified number of Data bits not supported
|
||||
AES_ERROR_ENDIAN ///< Specified endian not supported
|
||||
} drv_aes_error_e;
|
||||
|
||||
/*----- AES Control Codes: Mode -----*/
|
||||
typedef enum {
|
||||
AES_MODE_ECB = 0, ///< ECB Mode
|
||||
AES_MODE_CBC , ///< CBC Mode
|
||||
AES_MODE_CFB , ///< CFB Mode
|
||||
AES_MODE_OFB , ///< OFB Mode
|
||||
AES_MODE_CTR ///< CTR Mode
|
||||
} aes_mode_e;
|
||||
|
||||
/*----- AES Control Codes: Crypto Mode -----*/
|
||||
typedef enum {
|
||||
AES_CRYPTO_MODE_ENCRYPT = 0, ///< encrypt Mode
|
||||
AES_CRYPTO_MODE_DECRYPT , ///< decrypt Mode
|
||||
} aes_crypto_mode_e;
|
||||
|
||||
/*----- AES Control Codes: Padding Mode -----*/
|
||||
typedef enum {
|
||||
AES_PADDING_MODE_NO = 0, ///< NO-PADDING
|
||||
AES_PADDING_MODE_ZERO , ///< ZERO-PADDING
|
||||
AES_PADDING_MODE_PKCS5 ///< PKCS5-PADDING
|
||||
} aes_padding_mode_e;
|
||||
|
||||
/*----- AES Control Codes: Mode Parameters: Key length -----*/
|
||||
typedef enum {
|
||||
AES_KEY_LEN_BITS_128 = 0, ///< 128 Data bits
|
||||
AES_KEY_LEN_BITS_192 , ///< 192 Data bits
|
||||
AES_KEY_LEN_BITS_256 ///< 256 Data bits
|
||||
} aes_key_len_bits_e;
|
||||
|
||||
/*----- AES Control Codes: Mode Parameters: Endian -----*/
|
||||
typedef enum {
|
||||
AES_ENDIAN_LITTLE = 0, ///< Little Endian
|
||||
AES_ENDIAN_BIG ///< Big Endian
|
||||
} aes_endian_mode_e;
|
||||
|
||||
/**
|
||||
\brief AES Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t busy : 1; ///< busy flag
|
||||
} aes_status_t;
|
||||
|
||||
/****** AES Event *****/
|
||||
typedef enum {
|
||||
AES_EVENT_CRYPTO_COMPLETE = 0 ///< Encrypt completed
|
||||
} aes_event_e;
|
||||
typedef void (*aes_event_cb_t)(aes_event_e event); ///< Pointer to \ref aes_event_cb_t : AES Event call back.
|
||||
|
||||
|
||||
/**
|
||||
\brief AES Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ecb_mode : 1; ///< supports ECB mode
|
||||
uint32_t cbc_mode : 1; ///< supports CBC mode
|
||||
uint32_t cfb_mode : 1; ///< supports CFB mode
|
||||
uint32_t ofb_mode : 1; ///< supports OFB mode
|
||||
uint32_t ctr_mode : 1; ///< supports CTR mode
|
||||
uint32_t bits_128 : 1; ///< supports 128bits key length
|
||||
uint32_t bits_192 : 1; ///< supports 192bits key length
|
||||
uint32_t bits_256 : 1; ///< supports 256bits key length
|
||||
} aes_capabilities_t;
|
||||
|
||||
|
||||
// Function documentation
|
||||
|
||||
/**
|
||||
\brief get aes instance count.
|
||||
\return aes handle count
|
||||
*/
|
||||
int32_t csi_aes_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize AES Interface. 1. Initializes the resources needed for the AES interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_aes_get_instance_count().
|
||||
\param[in] cb_event Pointer to \ref aes_event_cb_t
|
||||
\return return aes handle if success
|
||||
*/
|
||||
aes_handle_t csi_aes_initialize(int32_t idx, aes_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize AES Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle aes handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_aes_uninitialize(aes_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle aes handle to operate.
|
||||
\return \ref aes_capabilities_t
|
||||
*/
|
||||
aes_capabilities_t csi_aes_get_capabilities(aes_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config aes mode.
|
||||
\param[in] handle aes handle to operate.
|
||||
\param[in] mode \ref aes_mode_e
|
||||
\param[in] keylen_bits \ref aes_key_len_bits_e
|
||||
\param[in] endian \ref aes_endian_mode_e
|
||||
\param[in] arg Pointer to the iv address when mode is cbc_mode
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_aes_config(aes_handle_t handle,
|
||||
aes_mode_e mode,
|
||||
aes_key_len_bits_e keylen_bits,
|
||||
aes_endian_mode_e endian,
|
||||
uint32_t arg
|
||||
);
|
||||
|
||||
/**
|
||||
\brief set crypto key.
|
||||
\param[in] handle aes handle to operate.
|
||||
\param[in] context aes information context(NULL when hardware implementation)
|
||||
\param[in] key Pointer to the key buf
|
||||
\param[in] key_len the key len
|
||||
\param[in] enc \ref aes_crypto_mode_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_aes_set_key(aes_handle_t handle, void *context, void *key, uint32_t key_len, aes_crypto_mode_e enc);
|
||||
|
||||
/**
|
||||
\brief encrypt or decrypt
|
||||
\param[in] handle aes handle to operate.
|
||||
\param[in] context aes information context(NULL when hardware implementation)
|
||||
\param[in] in Pointer to the Source data
|
||||
\param[out] out Pointer to the Result data.
|
||||
\param[in] len the Source data len.
|
||||
\param[in] padding \ref aes_padding_mode_e.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_aes_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, aes_padding_mode_e padding);
|
||||
|
||||
/**
|
||||
\brief Get AES status.
|
||||
\param[in] handle aes handle to operate.
|
||||
\return AES status \ref aes_status_t
|
||||
*/
|
||||
aes_status_t csi_aes_get_status(aes_handle_t handle);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_AES_H_ */
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file drv_common.h
|
||||
* @brief Header File for Common Driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _DRV_COMMON_H_
|
||||
#define _DRV_COMMON_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_errno.h>
|
||||
#include "config.h"
|
||||
|
||||
/** pin definition */
|
||||
typedef int32_t pin_t;
|
||||
|
||||
/// \details driver handle
|
||||
typedef void *drv_handle_t;
|
||||
|
||||
/**
|
||||
\brief General power states
|
||||
*/
|
||||
typedef enum {
|
||||
DRV_POWER_OFF, ///< Power off: no operation possible
|
||||
DRV_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
|
||||
DRV_POWER_FULL ///< Power on: full operation at maximum performance
|
||||
} drv_power_stat_e;
|
||||
|
||||
#endif /* _DRV_COMMON_H */
|
||||
|
||||
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file drv_crc.h
|
||||
* @brief Header File for CRC Driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CSI_CRC_H_
|
||||
#define _CSI_CRC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_errno.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
|
||||
/****** CRC specific error codes *****/
|
||||
#define CRC_ERROR_MODE (EDRV_SPECIFIC + 1) ///< Specified Mode not supported
|
||||
|
||||
/// definition for crc handle.
|
||||
typedef void *crc_handle_t;
|
||||
|
||||
/*----- CRC Control Codes: Mode -----*/
|
||||
typedef enum {
|
||||
CRC_MODE_CRC8 = 0, ///< Mode CRC8
|
||||
CRC_MODE_CRC16 , ///< Mode CRC16
|
||||
CRC_MODE_CRC32 ///< Mode CRC32
|
||||
} crc_mode_e;
|
||||
|
||||
/*----- CRC Control Codes: Mode Parameters: Key length -----*/
|
||||
typedef enum {
|
||||
CRC_STANDARD_CRC_ROHC = 0, ///< Standard CRC RHOC
|
||||
CRC_STANDARD_CRC_MAXIM , ///< Standard CRC MAXIAM
|
||||
CRC_STANDARD_CRC_X25 , ///< Standard CRC X25
|
||||
CRC_STANDARD_CRC_CCITT , ///< Standard CRC CCITT
|
||||
CRC_STANDARD_CRC_USB , ///< Standard CRC USB
|
||||
CRC_STANDARD_CRC_IBM , ///< Standard CRC IBM
|
||||
CRC_STANDARD_CRC_MODBUS ///< Standard CRC MODBUS
|
||||
} crc_standard_crc_e;
|
||||
|
||||
/**
|
||||
\brief CRC Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t busy : 1; ///< busy flag
|
||||
} crc_status_t;
|
||||
|
||||
/****** CRC Event *****/
|
||||
typedef enum {
|
||||
CRC_EVENT_CALCULATE_COMPLETE = 0, ///< Calculate completed
|
||||
} crc_event_e;
|
||||
|
||||
typedef void (*crc_event_cb_t)(crc_event_e event); ///< Pointer to \ref crc_event_cb_t : CRC Event call back.
|
||||
|
||||
/**
|
||||
\brief CRC Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ROHC : 1; ///< supports ROHC mode
|
||||
uint32_t MAXIM : 1; ///< supports MAXIM mode
|
||||
uint32_t X25 : 1; ///< supports X25 mode
|
||||
uint32_t CCITT : 1; ///< supports CCITT mode
|
||||
uint32_t USB : 1; ///< supports USB mode
|
||||
uint32_t IBM : 1; ///< supports IBM mode
|
||||
uint32_t MODBUS : 1; ///< supports MODBUS mode
|
||||
} crc_capabilities_t;
|
||||
|
||||
// Function documentation
|
||||
|
||||
/**
|
||||
\brief get crc handle count.
|
||||
\return crc handle count
|
||||
*/
|
||||
int32_t csi_crc_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize CRC Interface. 1. Initializes the resources needed for the CRC interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_crc_get_handle_count()
|
||||
\param[in] cb_event Pointer to \ref crc_event_cb_t
|
||||
\return return crc handle if success
|
||||
*/
|
||||
crc_handle_t csi_crc_initialize(int32_t idx, crc_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize CRC Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle crc handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_crc_uninitialize(crc_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle crc handle to operate.
|
||||
\return \ref crc_capabilities_t
|
||||
*/
|
||||
crc_capabilities_t csi_crc_get_capabilities(crc_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config crc mode.
|
||||
\param[in] handle crc handle to operate.
|
||||
\param[in] mode \ref crc_mode_e
|
||||
\param[in] standard \ref crc_standard_crc_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_crc_config(crc_handle_t handle,
|
||||
crc_mode_e mode,
|
||||
crc_standard_crc_e standard
|
||||
);
|
||||
|
||||
/**
|
||||
\brief calculate crc.
|
||||
\param[in] handle crc handle to operate.
|
||||
\param[in] in Pointer to the input data
|
||||
\param[out] out Pointer to the result.
|
||||
\param[in] len intpu data len.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_crc_calculate(crc_handle_t handle, const void *in, void *out, uint32_t len);
|
||||
|
||||
/**
|
||||
\brief Get CRC status.
|
||||
\param[in] handle crc handle to operate.
|
||||
\return CRC status \ref crc_status_t
|
||||
*/
|
||||
crc_status_t csi_crc_get_status(crc_handle_t handle);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_CRC_H_ */
|
||||
@@ -0,0 +1,171 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_dmac.h
|
||||
* @brief header file for dmac driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CSI_DMA_H_
|
||||
#define _CSI_DMA_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
/// definition for dmac handle.
|
||||
typedef void *dmac_handle_t;
|
||||
|
||||
/**
|
||||
\brief DMA Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t unalign_addr : 1; ///< support for unalign address transfer when memory is source
|
||||
} dma_capabilities_t;
|
||||
|
||||
typedef enum {
|
||||
DMA_STATE_FREE = 0, ///< DMA not yet initialized or disabled
|
||||
DMA_STATE_READY, ///< DMA process success and ready for use, but not start yet
|
||||
DMA_STATE_BUSY, ///< DMA process is ongoing
|
||||
DMA_STATE_ERROR, ///< DMA transfer error
|
||||
DMA_STATE_DONE, ///< DMA transfer done
|
||||
} dma_status_e;
|
||||
|
||||
/****** DMA specific error codes *****/
|
||||
typedef enum {
|
||||
EDRV_DMA_MODE = (EDRV_SPECIFIC + 1), ///< Specified Mode not supported
|
||||
} dma_error_e;
|
||||
|
||||
/****** DMA Event *****/
|
||||
typedef enum {
|
||||
DMA_EVENT_TRANSFER_DONE = 0, ///< transfer complete
|
||||
DMA_EVENT_TRANSFER_ERROR = 1, ///< transfer error
|
||||
} dma_event_e;
|
||||
|
||||
typedef enum {
|
||||
DMA_ADDR_INC = 0,
|
||||
DMA_ADDR_DEC,
|
||||
DMA_ADDR_CONSTANT
|
||||
} dma_addr_inc_e;
|
||||
|
||||
typedef enum {
|
||||
DMA_MEM2MEM = 0,
|
||||
DMA_MEM2PERH,
|
||||
DMA_PERH2MEM,
|
||||
DMA_PERH2PERH,
|
||||
} dma_trans_type_e;
|
||||
|
||||
typedef struct {
|
||||
dma_addr_inc_e src_inc; ///< source address increment
|
||||
dma_addr_inc_e dst_inc; ///< destination address increment
|
||||
uint8_t src_tw; ///< source transfer width in byte
|
||||
uint8_t dst_tw; ///< destination transfer width in byte
|
||||
uint8_t hs_if; ///< a hardware handshaking interface
|
||||
dma_trans_type_e type; ///< transfer type
|
||||
} dma_config_t;
|
||||
|
||||
typedef void (*dma_event_cb_t)(dma_event_e event, int32_t ch); ///< Pointer to \ref dma_event_cb_t : CRC Event call back.
|
||||
|
||||
/**
|
||||
\brief get dma instance count.
|
||||
\return dma instance count
|
||||
*/
|
||||
int32_t csi_dma_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize DMA Interface. 1. Initializes the resources needed for the DMA interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_dma_get_instance_count()
|
||||
\return pointer to dma instances
|
||||
*/
|
||||
dmac_handle_t csi_dma_initialize(int32_t idx);
|
||||
|
||||
/**
|
||||
\brief De-initialize DMA Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle damc handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_dma_uninitialize(dmac_handle_t handle);
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle damc handle to operate.
|
||||
\return \ref dma_capabilities_t
|
||||
*/
|
||||
dma_capabilities_t csi_dma_get_capabilities(dmac_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief get one free dma channel
|
||||
\param[in] handle damc handle to operate.
|
||||
\param[in] ch channel num. if -1 then allocate a free channal in this dma
|
||||
\return -1 - no channel can be used, other - channel index
|
||||
*/
|
||||
int32_t csi_dma_alloc_channel(dmac_handle_t handle, int32_t ch);
|
||||
|
||||
/**
|
||||
\brief release dma channel and related resources
|
||||
\param[in] handle damc handle to operate.
|
||||
\param[in] ch channel num.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_dma_release_channel(dmac_handle_t handle, int32_t ch);
|
||||
|
||||
/**
|
||||
\brief
|
||||
\param[in] handle damc handle to operate.
|
||||
\param[in] ch channel num. if -1 then allocate a free channal in this dma
|
||||
\param[in] psrcaddr dma transfer source address
|
||||
\param[in] pstdaddr dma transfer source address
|
||||
\param[in] length dma transfer length
|
||||
\param[in] config dma transfer configure
|
||||
\param[in] cb_event Pointer to \ref dma_event_cb_t
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_dma_config(dmac_handle_t handle, int32_t ch,
|
||||
void *psrcaddr, void *pstdaddr,
|
||||
uint32_t length, dma_config_t *config, dma_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief start generate dma signal.
|
||||
\param[in] handle damc handle to operate.
|
||||
\param[in] ch channel num.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_dma_start(dmac_handle_t handle, int32_t ch);
|
||||
|
||||
/**
|
||||
\brief Stop generate dma signal.
|
||||
\param[in] handle damc handle to operate.
|
||||
\param[in] ch channel num.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_dma_stop(dmac_handle_t handle, int32_t ch);
|
||||
|
||||
/**
|
||||
\brief Get DMA status.
|
||||
\param[in] handle damc handle to operate.
|
||||
\param[in] ch channel num.
|
||||
\return DMA status \ref dma_status_e
|
||||
*/
|
||||
dma_status_e csi_dma_get_status(dmac_handle_t handle, int32_t ch);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_DMA_H_ */
|
||||
|
||||
@@ -0,0 +1,157 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_eflash.h
|
||||
* @brief header file for eflash driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CSI_EFLASH_H_
|
||||
#define _CSI_EFLASH_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
|
||||
/// definition for eflash handle.
|
||||
typedef void *eflash_handle_t;
|
||||
|
||||
/**
|
||||
\brief Flash information
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t start; ///< Chip Start address
|
||||
uint32_t end; ///< Chip End address (start+size-1)
|
||||
uint32_t sector_count; ///< Number of sectors
|
||||
uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used)
|
||||
uint32_t page_size; ///< Optimal programming page size in bytes
|
||||
uint32_t program_unit; ///< Smallest programmable unit in bytes
|
||||
uint8_t erased_value; ///< Contents of erased memory (usually 0xFF)
|
||||
} eflash_info;
|
||||
|
||||
/**
|
||||
\brief Flash Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t busy : 1; ///< Flash busy flag
|
||||
uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
|
||||
} eflash_status_t;
|
||||
|
||||
/****** EFLASH Event *****/
|
||||
typedef enum {
|
||||
EFLASH_EVENT_READY = 0, ///< Flash Ready
|
||||
EFLASH_EVENT_ERROR , ///< Read/Program/Erase Error
|
||||
} eflash_event_e;
|
||||
|
||||
typedef void (*eflash_event_cb_t)(eflash_event_e event); ///< Pointer to \ref eflash_event_cb_t : EFLASH Event call back.
|
||||
|
||||
/**
|
||||
\brief Flash Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t event_ready : 1; ///< Signal Flash Ready event
|
||||
uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
|
||||
uint32_t erase_chip : 1; ///< Supports EraseChip operation
|
||||
} eflash_capabilities_t;
|
||||
|
||||
// Function documentation
|
||||
|
||||
/**
|
||||
\brief get eflash handle count.
|
||||
\return eflash handle count
|
||||
*/
|
||||
int32_t csi_eflash_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize EFLASH Interface. 1. Initializes the resources needed for the EFLASH interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_eflash_get_instance_count()
|
||||
\param[in] cb_event Pointer to \ref eflash_event_cb_t
|
||||
\return pointer to eflash handle
|
||||
*/
|
||||
eflash_handle_t csi_eflash_initialize(int32_t idx, eflash_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize EFLASH Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle eflash handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_eflash_uninitialize(eflash_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle eflash handle to operate.
|
||||
\return \ref eflash_capabilities_t
|
||||
*/
|
||||
eflash_capabilities_t csi_eflash_get_capabilities(eflash_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Read data from Flash.
|
||||
\param[in] handle eflash handle to operate.
|
||||
\param[in] addr Data address.
|
||||
\param[out] data Pointer to a buffer storing the data read from Flash.
|
||||
\param[in] cnt Number of data items to read.
|
||||
\return number of data items read or error code
|
||||
*/
|
||||
int32_t csi_eflash_read(eflash_handle_t handle, uint32_t addr, void *data, uint32_t cnt);
|
||||
|
||||
/**
|
||||
\brief Program data to Flash.
|
||||
\param[in] handle eflash handle to operate.
|
||||
\param[in] addr Data address.
|
||||
\param[in] data Pointer to a buffer containing the data to be programmed to Flash..
|
||||
\param[in] cnt Number of data items to program.
|
||||
\return number of data items programmed or error code
|
||||
*/
|
||||
int32_t csi_eflash_program(eflash_handle_t handle, uint32_t addr, const void *data, uint32_t cnt);
|
||||
|
||||
/**
|
||||
\brief Erase Flash Sector.
|
||||
\param[in] handle eflash handle to operate.
|
||||
\param[in] addr Sector address
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_eflash_erase_sector(eflash_handle_t handle, uint32_t addr);
|
||||
|
||||
/**
|
||||
\brief Erase complete Flash.
|
||||
\param[in] handle eflash handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_eflash_erase_chip(eflash_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get Flash information.
|
||||
\param[in] handle eflash handle to operate.
|
||||
\return Pointer to Flash information \ref eflash_info
|
||||
*/
|
||||
eflash_info *csi_eflash_get_info(eflash_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get EFLASH status.
|
||||
\param[in] handle eflash handle to operate.
|
||||
\return EFLASH status \ref eflash_status_t
|
||||
*/
|
||||
eflash_status_t csi_eflash_get_status(eflash_handle_t handle);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_EFLASH_H_ */
|
||||
@@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_errno.h
|
||||
* @brief header file for error num
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* @file
|
||||
* @details Error code field difination
|
||||
* Error number is devided into 4 field:
|
||||
* 0x8******* : 8 : means < 0
|
||||
* 0x*A****** : A : means type number: bsp(1), driver(2), hal(3), app(4)...
|
||||
* 0x**AB**** : AB : means module number: timer(1), rtc(2), ....
|
||||
* 0x****AB** : AB : means API number: module API's definition
|
||||
* 0x******AB : AB : means sub error number
|
||||
* 0 ~ 0x80 is common error such as EPERM, refer to errno.h
|
||||
* 0x80 ~ 0xFF is specific error, can difine in module
|
||||
*
|
||||
* For example 0x81020113 means:
|
||||
* 1. 0x8*******: value < 0, means error happened
|
||||
* 2. 0x*1******: type number is 1, means bsp error
|
||||
* 3. 0x**02****: module number is 02, means RTC error
|
||||
* 4. 0x****01**: module API is 01, means RTC's init
|
||||
* 5. 0x******13: specific error is 0x13=19=ENODEV, means no such device
|
||||
*
|
||||
* For special bsp module example, you can return:
|
||||
* (BSP_ERRNO_TIMER_BASE | BSP_API_RTC_INIT | EPERM) for rtc init error
|
||||
* (BSP_ERRNO_TIMER_BASE | BSP_API_RTC_SETTIME | ENXIO) for rtc settime error
|
||||
*
|
||||
* Here list the common sub error number (0x******AB) below(0~127 defined in errno.h as standard err code):
|
||||
* Code Hex Deci Meaning
|
||||
* -------------------------------------------------------
|
||||
* EPERM 0x01 1 Operation not permitted
|
||||
* EIO 0x05 5 I/O error
|
||||
* ENXIO 0x06 6 No such device or address
|
||||
* ENOMEM 0x0C 12 Out of memory
|
||||
* EACCES 0x0D 13 Permission denied
|
||||
* EINVAL 0x16 22 Invalid argument
|
||||
* ...
|
||||
* SPEC_ERR_BASE 0x80 128 module special error number base
|
||||
* ...
|
||||
* ERRNO_MAX 0xFF -- Max sub error number
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _DRV_ERRNO_H_
|
||||
#define _DRV_ERRNO_H_
|
||||
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#define ERRNO_DRV_START 0X80
|
||||
|
||||
/* drvier General return codes */
|
||||
typedef enum {
|
||||
EDRV = ERRNO_DRV_START, ///< Unspecified error
|
||||
EDRV_BUSY, ///< Driver is busy
|
||||
EDRV_TIMEOUT, ///< Timeout occurred
|
||||
EDRV_UNSUPPORTED, ///< Operation not supported
|
||||
EDRV_PARAMETER, ///< Parameter error
|
||||
EDRV_SPECIFIC ///< Start of driver specific errors
|
||||
} drv_common_err_e;
|
||||
|
||||
|
||||
/** Get error type */
|
||||
#define GET_ERROR_TYPE(errno) \
|
||||
(error & 0xFF000000 >> 24)
|
||||
/** Get error module */
|
||||
#define GET_ERROR_MODULE(error) \
|
||||
(error & 0x00FF0000 >> 16)
|
||||
/** Get error API */
|
||||
#define GET_ERROR_API(error) \
|
||||
(error & 0x0000FF00 >> 8)
|
||||
/** Get errno */
|
||||
#define GET_ERROR_NUM(error) \
|
||||
(error & 0x000000FF)
|
||||
|
||||
#ifndef CSI_DRV_ERRNO_BASE
|
||||
/** means bsp errors */
|
||||
#define CSI_DRV_ERRNO_BASE 0x81000000
|
||||
#endif
|
||||
|
||||
/** driver module id definition*/
|
||||
#define CSI_DRV_ERRNO_GPIO_BASE 0x81010000
|
||||
#define CSI_DRV_ERRNO_USART_BASE 0x81020000
|
||||
#define CSI_DRV_ERRNO_SPI_BASE 0x81030000
|
||||
#define CSI_DRV_ERRNO_I2C_BASE 0x81040000
|
||||
#define CSI_DRV_ERRNO_FLASH_BASE 0x81050000
|
||||
#define CSI_DRV_ERRNO_PWM_BASE 0x81060000
|
||||
#define CSI_DRV_ERRNO_RTC_BASE 0x81070000
|
||||
#define CSI_DRV_ERRNO_TIMER_BASE 0x81080000
|
||||
#define CSI_DRV_ERRNO_WDT_BASE 0x81090000
|
||||
#define CSI_DRV_ERRNO_AES_BASE 0x810A0000
|
||||
#define CSI_DRV_ERRNO_CRC_BASE 0x810B0000
|
||||
#define CSI_DRV_ERRNO_RSA_BASE 0x810C0000
|
||||
#define CSI_DRV_ERRNO_SHA_BASE 0x810D0000
|
||||
#define CSI_DRV_ERRNO_TRNG_BASE 0x810E0000
|
||||
#define CSI_DRV_ERRNO_EFLASH_BASE 0x810F0000
|
||||
#define CSI_DRV_ERRNO_DMA_BASE 0x81100000
|
||||
|
||||
#endif /* CSI_DRV_ERRNO_H */
|
||||
@@ -0,0 +1,105 @@
|
||||
/**
|
||||
* Copyright (C) 2016 CSI Project. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CSI_NET_H_
|
||||
#define _CSI_NET_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define CSI_ETH_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
|
||||
|
||||
/**
|
||||
\brief Driver Version
|
||||
*/
|
||||
typedef struct csi_driver_version {
|
||||
uint16_t api; ///< API version
|
||||
uint16_t drv; ///< Driver version
|
||||
} csi_drv_version_t;
|
||||
|
||||
/* General return codes */
|
||||
#define CSI_ETH_OK 0 ///< Operation succeeded
|
||||
#define CSI_ETH_ERROR CSI_DRV_ERRNO_ETH_BASE+1 ///< Unspecified error
|
||||
#define CSI_ETH_ERROR_BUSY CSI_DRV_ERRNO_ETH_BASE+2 ///< Driver is busy
|
||||
#define CSI_ETH_ERROR_TIMEOUT CSI_DRV_ERRNO_ETH_BASE+3 ///< Timeout occurred
|
||||
#define CSI_ETH_ERROR_UNSUPPORTED CSI_DRV_ERRNO_ETH_BASE+4 ///< Operation not supported
|
||||
#define CSI_ETH_ERROR_PARAMETER CSI_DRV_ERRNO_ETH_BASE+5 ///< Parameter error
|
||||
#define CSI_ETH_ERROR_SPECIFIC CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors
|
||||
|
||||
/**
|
||||
\brief General power states
|
||||
*/
|
||||
typedef enum eth_power_state {
|
||||
CSI_ETH_POWER_OFF, ///< Power off: no operation possible
|
||||
CSI_ETH_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
|
||||
CSI_ETH_POWER_FULL ///< Power on: full operation at maximum performance
|
||||
} eth_power_state_t;
|
||||
|
||||
/**
|
||||
\brief Ethernet Media Interface type
|
||||
*/
|
||||
#define CSI_ETH_INTERFACE_MII (0) ///< Media Independent Interface (MII)
|
||||
#define CSI_ETH_INTERFACE_RMII (1) ///< Reduced Media Independent Interface (RMII)
|
||||
#define CSI_ETH_INTERFACE_SMII (2) ///< Serial Media Independent Interface (SMII)
|
||||
|
||||
/**
|
||||
\brief Ethernet link speed
|
||||
*/
|
||||
#define CSI_ETH_SPEED_10M (0) ///< 10 Mbps link speed
|
||||
#define CSI_ETH_SPEED_100M (1) ///< 100 Mbps link speed
|
||||
#define CSI_ETH_SPEED_1G (2) ///< 1 Gpbs link speed
|
||||
|
||||
/**
|
||||
\brief Ethernet duplex mode
|
||||
*/
|
||||
#define CSI_ETH_DUPLEX_HALF (0) ///< Half duplex link
|
||||
#define CSI_ETH_DUPLEX_FULL (1) ///< Full duplex link
|
||||
|
||||
/**
|
||||
\brief Ethernet link state
|
||||
*/
|
||||
typedef enum eth_link_state {
|
||||
ETH_LINK_DOWN, ///< Link is down
|
||||
ETH_LINK_UP ///< Link is up
|
||||
} eth_link_state_t;
|
||||
|
||||
/**
|
||||
\brief Ethernet link information
|
||||
*/
|
||||
typedef volatile struct eth_link_info {
|
||||
uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
|
||||
uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full
|
||||
uint32_t Autonegotiation : 1; ///< Set the interface to Auto Negotiation mode of transmission parameters
|
||||
uint32_t Loopback : 1; ///< Set the interface into a Loop-back test mode
|
||||
uint32_t Isolation : 1; ///< Set to indicate electrical isolation of PHY interface from MII/RMII interface
|
||||
uint32_t reserved : 26;
|
||||
} eth_link_info_t;
|
||||
|
||||
/**
|
||||
\brief Ethernet MAC Address
|
||||
*/
|
||||
typedef struct eth_mac_addr {
|
||||
uint8_t b[6]; ///< MAC Address (6 bytes), MSB first
|
||||
} eth_mac_addr_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CSI_NET_H_ */
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,124 @@
|
||||
/**
|
||||
* Copyright (C) 2016 CSI Project. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _CSI_ETH_PHY_H_
|
||||
#define _CSI_ETH_PHY_H_
|
||||
|
||||
#include "drv_eth.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef void *eth_phy_handle_t;
|
||||
|
||||
#define CSI_ETH_PHY_API_VERSION CSI_ETH_VERSION_MAJOR_MINOR(2,1) /* API version */
|
||||
|
||||
|
||||
#define _CSI_Driver_ETH_PHY_(n) Driver_ETH_PHY##n
|
||||
#define CSI_Driver_ETH_PHY_(n) _CSI_Driver_ETH_PHY_(n)
|
||||
|
||||
|
||||
/****** Ethernet PHY Mode *****/
|
||||
#define CSI_ETH_PHY_SPEED_Pos 0
|
||||
#define CSI_ETH_PHY_SPEED_Msk (3UL << CSI_ETH_PHY_SPEED_Pos)
|
||||
#define CSI_ETH_PHY_SPEED_10M (CSI_ETH_SPEED_10M << CSI_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed
|
||||
#define CSI_ETH_PHY_SPEED_100M (CSI_ETH_SPEED_100M << CSI_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed
|
||||
#define CSI_ETH_PHY_SPEED_1G (CSI_ETH_SPEED_1G << CSI_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed
|
||||
#define CSI_ETH_PHY_DUPLEX_Pos 2
|
||||
#define CSI_ETH_PHY_DUPLEX_Msk (1UL << CSI_ETH_PHY_DUPLEX_Pos)
|
||||
#define CSI_ETH_PHY_DUPLEX_HALF (CSI_ETH_DUPLEX_HALF << CSI_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
|
||||
#define CSI_ETH_PHY_DUPLEX_FULL (CSI_ETH_DUPLEX_FULL << CSI_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
|
||||
#define CSI_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode
|
||||
#define CSI_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode
|
||||
#define CSI_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface
|
||||
|
||||
typedef int32_t (*csi_eth_phy_read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Read Ethernet PHY Register.
|
||||
typedef int32_t (*csi_eth_phy_write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Write Ethernet PHY Register.
|
||||
|
||||
typedef struct {
|
||||
csi_eth_phy_read_t phy_read;
|
||||
csi_eth_phy_write_t phy_write;
|
||||
eth_link_info_t link_info;
|
||||
}eth_phy_priv_t;
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\brief Get driver version.
|
||||
\param[in] handle ethernet phy handle
|
||||
\return driver version
|
||||
*/
|
||||
csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Initialize Ethernet PHY Device.
|
||||
\param[in] fn_read
|
||||
\param[in] fn_write
|
||||
\return ethernet phy handle
|
||||
*/
|
||||
eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write);
|
||||
|
||||
/**
|
||||
\brief De-initialize Ethernet PHY Device.
|
||||
\param[in] handle ethernet phy handle
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_eth_phy_uninitialize(eth_phy_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Control Ethernet PHY Device Power.
|
||||
\param[in] handle ethernet phy handle
|
||||
\param[in] state Power state
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_eth_phy_power_control(eth_phy_handle_t handle, eth_power_state_t state);
|
||||
|
||||
/**
|
||||
\brief Set Ethernet Media Interface.
|
||||
\param[in] handle ethernet phy handle
|
||||
\param[in] interface Media Interface type
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_eth_phy_set_interface(eth_phy_handle_t handle, uint32_t interface);
|
||||
|
||||
/**
|
||||
\brief Set Ethernet PHY Device Operation mode.
|
||||
\param[in] handle ethernet phy handle
|
||||
\param[in] mode Operation Mode
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_eth_phy_set_mode(eth_phy_handle_t handle, uint32_t mode);
|
||||
|
||||
/**
|
||||
\brief Get Ethernet PHY Device Link state.
|
||||
\param[in] handle ethernet phy handle
|
||||
\return current link status \ref eth_link_state_t
|
||||
*/
|
||||
eth_link_state_t csi_eth_phy_get_linkstate(eth_phy_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get Ethernet PHY Device Link information.
|
||||
\param[in] handle ethernet phy handle
|
||||
\return current link parameters \ref eth_link_info_t
|
||||
*/
|
||||
eth_link_info_t csi_eth_phy_get_linkinfo(eth_phy_handle_t handle);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,183 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_gpio.h
|
||||
* @brief header file for gpio driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CSI_GPIO_H_
|
||||
#define _CSI_GPIO_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <drv_common.h>
|
||||
#include <pin_name.h>
|
||||
|
||||
/// definition for gpio port handle.
|
||||
typedef void *gpio_port_handle_t;
|
||||
/// definition for gpio pin handle.
|
||||
typedef void *gpio_pin_handle_t;
|
||||
|
||||
/****** GPIO specific error codes *****/
|
||||
typedef enum {
|
||||
GPIO_ERROR_MODE = (EDRV_SPECIFIC + 1), ///< Specified Mode not suphandleed
|
||||
GPIO_ERROR_DIRECTION, ///< Specified direction not suphandleed
|
||||
GPIO_ERROR_IRQ_MODE, ///< Specified irq mode not suphandleed
|
||||
} drv_gpio_error_e;
|
||||
|
||||
/*----- GPIO Control Codes: Mode -----*/
|
||||
typedef enum {
|
||||
GPIO_MODE_PULLNONE = 0, ///< pull none for input
|
||||
GPIO_MODE_PULLUP , ///< pull up for input
|
||||
GPIO_MODE_PULLDOWM , ///< pull down for input
|
||||
GPIO_MODE_OPEN_DRAIN , ///< open drain mode for output
|
||||
GPIO_MODE_PUSH_PULL ///< push-pull mode for output
|
||||
} gpio_mode_e;
|
||||
|
||||
/*----- GPIO Control Codes: Mode Parameters: Data Bits -----*/
|
||||
typedef enum {
|
||||
GPIO_DIRECTION_INPUT = 0, ///< gpio as input
|
||||
GPIO_DIRECTION_OUTPUT , ///< gpio as output
|
||||
} gpio_direction_e;
|
||||
|
||||
/*----- GPIO Control Codes: Mode Parameters: Parity -----*/
|
||||
typedef enum {
|
||||
GPIO_IRQ_MODE_RISING_EDGE = 0, ///< interrupt mode for rising edge
|
||||
GPIO_IRQ_MODE_FALLING_EDGE , ///< interrupt mode for falling edge
|
||||
GPIO_IRQ_MODE_DOUBLE_EDGE , ///< interrupt mode for double edge
|
||||
GPIO_IRQ_MODE_LOW_LEVEL , ///< interrupt mode for low level
|
||||
GPIO_IRQ_MODE_HIGH_LEVEL , ///< interrupt mode for high level
|
||||
} gpio_irq_mode_e;
|
||||
|
||||
/**
|
||||
\brief GPIO Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t interrupt_mode : 1; ///< suphandles GPIO interrupt mode
|
||||
uint32_t pull_mode : 1;
|
||||
} gpio_capabilities_t;
|
||||
|
||||
|
||||
typedef void (*gpio_event_cb_t)(gpio_pin_handle_t io); ///< gpio Event call back.
|
||||
|
||||
/**
|
||||
\brief Initialize GPIO module. 1. Initializes the resources needed for the GPIO handle 2.registers event callback function
|
||||
3.get gpio_port_handle
|
||||
\param[in] port port_name.
|
||||
\param[in] cb_event Pointer to \ref gpio_event_cb_t
|
||||
\return gpio_port_handle
|
||||
*/
|
||||
gpio_port_handle_t csi_gpio_port_initialize(port_name_t port, gpio_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize GPIO handle. stops operation and releases the software resources used by the handle
|
||||
\param[in] handle gpio port handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_port_uninitialize(gpio_port_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get gpio capabilities.all pins have same capabilities in one handle
|
||||
\param[in] handle handle instance to operate.
|
||||
\return \ref gpio_capabilities_t
|
||||
*/
|
||||
gpio_capabilities_t csi_gpio_get_io_capabilities(gpio_port_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config multiple pin within one handle
|
||||
\param[in] handle gpio port handle to operate.
|
||||
\param[in] mask the bitmask to identify which bits in the handle should be included (0 - ignore)
|
||||
\param[in] mode \ref gpio_mode_e
|
||||
\param[in] dir \ref gpio_direction_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_port_config(gpio_port_handle_t handle,
|
||||
uint32_t mask,
|
||||
gpio_mode_e mode,
|
||||
gpio_direction_e dir);
|
||||
|
||||
/**
|
||||
\brief Write value to the handle(write value to multiple pins on one handle at the same time)
|
||||
\param[in] handle gpio port handle to operate.
|
||||
\param[in] mask The bitmask to identify which bits in the handle should be included (0 - ignore)
|
||||
\param[in] value the value to be set
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_port_write(gpio_port_handle_t handle, uint32_t mask, uint32_t value);
|
||||
|
||||
/**
|
||||
\brief Read the current value on the handle(read value of multiple pins on one handle at the same time)
|
||||
\param[in] handle gpio port handle to operate.
|
||||
\param[in] mask The bitmask to identify which bits in the handle should be included (0 - ignore)
|
||||
\param[out] value an integer with each bit corresponding to an associated handle pin setting
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_port_read(gpio_port_handle_t handle, uint32_t mask, uint32_t *value);
|
||||
|
||||
/**
|
||||
\brief Initialize GPIO handle.
|
||||
\param[in] gpio_pin Pointer to the pin_t.
|
||||
\return gpio_pin_handle
|
||||
*/
|
||||
gpio_pin_handle_t csi_gpio_pin_initialize(pin_t gpio_pin);
|
||||
/**
|
||||
\brief config pin
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] mode \ref gpio_mode_e
|
||||
\param[in] dir \ref gpio_direction_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_config(gpio_pin_handle_t pin,
|
||||
gpio_mode_e mode,
|
||||
gpio_direction_e dir);
|
||||
|
||||
/**
|
||||
\brief Set one or zero to the selected GPIO pin.
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] value the value to be set
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_write(gpio_pin_handle_t pin, bool value);
|
||||
|
||||
/**
|
||||
\brief Get the value of selected GPIO pin.
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[out] value buf to store the pin value
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_read(gpio_pin_handle_t pin, bool *value);
|
||||
|
||||
/**
|
||||
\brief set GPIO interrupt mode.
|
||||
\param[in] pin gpio pin handle to operate.
|
||||
\param[in] mode the irq mode to be set
|
||||
\param[in] enable the enable flag
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_gpio_pin_irq_set(gpio_pin_handle_t pin, gpio_irq_mode_e mode, bool enable);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_GPIO_H_ */
|
||||
@@ -0,0 +1,195 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_iic.h
|
||||
* @brief header file for iic driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CSI_IIC_H_
|
||||
#define _CSI_IIC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
/// definition for iic handle.
|
||||
typedef void *iic_handle_t;
|
||||
|
||||
/*----- IIC Control Codes: Mode -----*/
|
||||
typedef enum {
|
||||
IIC_MODE_MASTER, ///< IIC Master
|
||||
IIC_MODE_SLAVE ///< IIC Slave
|
||||
} iic_mode_e;
|
||||
|
||||
/*----- IIC Control Codes: IIC Bus Speed -----*/
|
||||
typedef enum {
|
||||
I2C_BUS_SPEED_STANDARD = 0, ///< Standard Speed (100kHz)
|
||||
I2C_BUS_SPEED_FAST = 1, ///< Fast Speed (400kHz)
|
||||
I2C_BUS_SPEED_FAST_PLUS = 2, ///< Fast+ Speed ( 1MHz)
|
||||
I2C_BUS_SPEED_HIGH = 3 ///< High Speed (3.4MHz)
|
||||
} iic_speed_e;
|
||||
|
||||
/*----- IIC Control Codes: IIC Address Mode -----*/
|
||||
typedef enum {
|
||||
I2C_ADDRESS_7BIT = 0, ///< 7-bit address mode
|
||||
I2C_ADDRESS_10BIT = 1 ///< 10-bit address mode
|
||||
} iic_address_mode_e;
|
||||
|
||||
/**
|
||||
\brief IIC Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
|
||||
uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master
|
||||
uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver
|
||||
uint32_t general_call : 1; ///< General Call(address 0) indication (cleared on start of next Slave operation)
|
||||
uint32_t arbitration_lost : 1; ///< Master lost arbitration(in case of multi-masters) (cleared on start of next Master operation)
|
||||
uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation)
|
||||
} iic_status_t;
|
||||
|
||||
/****** IIC Event *****/
|
||||
typedef enum {
|
||||
I2C_EVENT_TRANSFER_DONE = 0, ///< Master/Slave Transmit/Receive finished
|
||||
I2C_EVENT_TRANSFER_INCOMPLETE = 1, ///< Master/Slave Transmit/Receive incomplete transfer
|
||||
I2C_EVENT_SLAVE_TRANSMIT = 2, ///< Slave Transmit operation requested
|
||||
I2C_EVENT_SLAVE_RECEIVE = 3, ///< Slave Receive operation requested
|
||||
I2C_EVENT_ADDRESS_NACK = 4, ///< Address not acknowledged from Slave
|
||||
I2C_EVENT_GENERAL_CALL = 5, ///< General Call indication
|
||||
I2C_EVENT_ARBITRATION_LOST = 6, ///< Master lost arbitration
|
||||
I2C_EVENT_BUS_ERROR = 7, ///< Bus error detected (START/STOP at illegal position)
|
||||
I2C_EVENT_BUS_CLEAR = 8 ///< Bus clear finished
|
||||
} iic_event_e;
|
||||
|
||||
typedef void (*iic_event_cb_t)(iic_event_e event, void *arg); ///< Pointer to \ref iic_event_cb_t : IIC Event call back.
|
||||
|
||||
/**
|
||||
\brief IIC Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t address_10_bit : 1; ///< supports 10-bit addressing
|
||||
} iic_capabilities_t;
|
||||
|
||||
/**
|
||||
\brief Initialize IIC Interface specified by pins. \n
|
||||
1. Initializes the resources needed for the IIC interface 2.registers event callback function
|
||||
\param[in] scl scl pin of iic.
|
||||
\param[in] sda sda pin of iic.
|
||||
\param[in] cb_event Pointer to \ref iic_event_cb_t
|
||||
\param[in] cb_arg argument for call back function
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
iic_handle_t csi_iic_initialize(pin_t scl, pin_t sda, iic_event_cb_t cb_event, void *cb_arg);
|
||||
|
||||
/**
|
||||
\brief De-initialize IIC Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle iic handle to operate.
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
int32_t csi_iic_uninitialize(iic_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle iic handle to operate.
|
||||
\return \ref iic_capabilities_t
|
||||
*/
|
||||
iic_capabilities_t csi_iic_get_capabilities(iic_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config iic attributes.
|
||||
\param[in] handle iic handle to operate.
|
||||
\param[in] mode iic mode \ref iic_mode_e. if negative, then this attribute not changed.
|
||||
\param[in] speed iic speed \ref iic_speed_e. if negative, then this attribute not changed.
|
||||
\param[in] addr_mode iic address mode \ref iic_address_mode_e. if negative, then this attribute not changed.
|
||||
\param[in] slave_addr iic address of slave. if negative, then this attribute not changed.
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
int32_t csi_iic_config(iic_handle_t handle,
|
||||
iic_mode_e mode,
|
||||
iic_speed_e speed,
|
||||
iic_address_mode_e addr_mode,
|
||||
int32_t slave_addr);
|
||||
|
||||
/**
|
||||
\brief Start transmitting data as I2C Master.
|
||||
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
|
||||
\ref csi_iic_get_status can indicates transmission status.
|
||||
\param[in] handle iic handle to operate.
|
||||
\param[in] data data to send to I2C Slave
|
||||
\param[in] num Number of data items to send
|
||||
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
int32_t csi_iic_master_send(iic_handle_t handle, const void *data, uint32_t num, bool xfer_pending);
|
||||
|
||||
/**
|
||||
\brief Start receiving data as I2C Master.
|
||||
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
|
||||
\ref csi_iic_get_status can indicates transmission status.
|
||||
\param[in] handle iic handle to operate.
|
||||
\param[out] data Pointer to buffer for data to receive from IIC receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
int32_t csi_iic_master_receive(iic_handle_t handle, const void *data, uint32_t num, bool xfer_pending);
|
||||
|
||||
/**
|
||||
\brief Start transmitting data as I2C Slave.
|
||||
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
|
||||
\ref csi_iic_get_status can indicates transmission status.
|
||||
\param[in] handle iic handle to operate.
|
||||
\param[in] data Pointer to buffer with data to transmit to I2C Master
|
||||
\param[in] num Number of data items to send
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
int32_t csi_iic_slave_send(iic_handle_t handle, const void *data, uint32_t num);
|
||||
|
||||
/**
|
||||
\brief Start receiving data as I2C Slave.
|
||||
This function is non-blocking,\ref iic_event_e is signaled when transfer completes or error happens.
|
||||
\ref csi_iic_get_status can indicates transmission status.
|
||||
\param[in] handle iic handle to operate.
|
||||
\param[out] data Pointer to buffer for data to receive from I2C Master
|
||||
\param[in] num Number of data items to receive
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
int32_t csi_iic_slave_receive(iic_handle_t handle, const void *data, uint32_t num);
|
||||
|
||||
/**
|
||||
\brief abort transfer.
|
||||
\param[in] handle iic handle to operate.
|
||||
\return 0 for success, negative for error code
|
||||
*/
|
||||
int32_t csi_iic_abort_transfer(iic_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get IIC status.
|
||||
\param[in] handle iic handle to operate.
|
||||
\return IIC status \ref iic_status_t
|
||||
*/
|
||||
iic_status_t csi_iic_get_status(iic_handle_t handle);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_IIC_H_ */
|
||||
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_pwm.h
|
||||
* @brief header file for pwm driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CSI_PWM_H_
|
||||
#define _CSI_PWM_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
|
||||
/// definition for pwm handle.
|
||||
typedef void *pwm_handle_t;
|
||||
|
||||
/****** PWM specific error codes *****/
|
||||
typedef enum {
|
||||
EDRV_PWM_MODE = (EDRV_SPECIFIC + 1), ///< Specified Mode not supported
|
||||
} drv_pwm_error_e;
|
||||
|
||||
|
||||
/**
|
||||
\brief Initialize PWM Interface. 1. Initializes the resources needed for the PWM interface 2.registers event callback function
|
||||
\param[in] pwm_pin pin name of pwm
|
||||
\return handle pwm handle to operate.
|
||||
*/
|
||||
pwm_handle_t drv_pwm_initialize(pin_t pwm_pin);
|
||||
|
||||
/**
|
||||
\brief De-initialize PWM Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle pwm handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t drv_pwm_uninitialize(pwm_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config pwm mode.
|
||||
\param[in] handle pwm handle to operate.
|
||||
\param[in] sysclk configured system clock.
|
||||
\param[in] period_us the PWM period in us
|
||||
\param[in] duty the PMW duty. ( 0 - 10000 represents 0% - 100% ,other values are invalid)
|
||||
\return error code
|
||||
*/
|
||||
int32_t drv_pwm_config(pwm_handle_t handle,
|
||||
uint32_t sysclk,
|
||||
uint32_t period_us,
|
||||
uint32_t duty);
|
||||
|
||||
/**
|
||||
\brief start generate pwm signal.
|
||||
\param[in] handle pwm handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t drv_pwm_start(pwm_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Stop generate pwm signal.
|
||||
\param[in] handle pwm handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t drv_pwm_stop(pwm_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get PWM status.
|
||||
\param[in] handle pwm handle to operate.
|
||||
\return PWM status \ref pwm_status_t
|
||||
pwm_status_t drv_pwm_get_status(pwm_handle_t handle);
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_PWM_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,161 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_rtc.h
|
||||
* @brief header file for rtc driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CSI_RTC_H_
|
||||
#define _CSI_RTC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
#include <time.h>
|
||||
|
||||
/// definition for rtc handle.
|
||||
typedef void *rtc_handle_t;
|
||||
|
||||
/****** rtc specific error codes *****/
|
||||
typedef enum {
|
||||
EDRV_RTC_TIME = (EDRV_SPECIFIC + 1), ///< timer data not supported
|
||||
} drv_rtc_error_e;
|
||||
|
||||
/**
|
||||
\brief RTC Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t active : 1; ///< rtc is running or not
|
||||
} rtc_status_t;
|
||||
|
||||
/****** RTC Event *****/
|
||||
typedef enum {
|
||||
RTC_EVENT_TIMER_INTRERRUPT = 0 ///< generate interrupt
|
||||
} rtc_event_e;
|
||||
|
||||
typedef void (*rtc_event_cb_t)(rtc_event_e event); ///< Pointer to \ref rtc_event_cb_t : RTC Event call back.
|
||||
|
||||
/**
|
||||
\brief RTC Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t interrupt_mode : 1; ///< supports Interrupt mode
|
||||
uint32_t wrap_mode : 1; ///< supports wrap mode
|
||||
} rtc_capabilities_t;
|
||||
|
||||
/**
|
||||
\brief get rtc instance count.
|
||||
\return rtc instance count
|
||||
*/
|
||||
int32_t csi_rtc_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize RTC Interface. 1. Initializes the resources needed for the RTC interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_rtc_get_instance_count()
|
||||
\param[in] cb_event Pointer to \ref rtc_event_cb_t
|
||||
\return pointer to rtc instance
|
||||
*/
|
||||
rtc_handle_t csi_rtc_initialize(int32_t idx, rtc_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize RTC Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle rtc handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_rtc_uninitialize(rtc_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\return \ref rtc_capabilities_t
|
||||
*/
|
||||
rtc_capabilities_t csi_rtc_get_capabilities(rtc_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Set RTC timer.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\param[in] rtctime pointer to rtc time
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_rtc_set_time(rtc_handle_t handle, const struct tm *rtctime);
|
||||
|
||||
/**
|
||||
\brief Get RTC timer.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\param[in] rtctime pointer to rtc time
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_rtc_get_time(rtc_handle_t handle, struct tm *rtctime);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Start RTC timer.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_rtc_start(rtc_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Stop RTC timer.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_rtc_stop(rtc_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config rtc mode.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
//int32_t drv_rtc_config (rtc_handle_t handle/*,rtc_mode_e mode*/);
|
||||
|
||||
/**
|
||||
\brief Get RTC status.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\return RTC status \ref rtc_status_t
|
||||
*/
|
||||
rtc_status_t csi_rtc_get_status(rtc_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config RTC timer.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\param[in] rtctime time to wake up
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_rtc_timer_config(rtc_handle_t handle, const struct tm *rtctime);
|
||||
|
||||
/**
|
||||
\brief disable or enable RTC timer.
|
||||
\param[in] handle rtc handle to operate.
|
||||
\param[in] en set 1 enable for rtc timer
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_rtc_timer_enable(rtc_handle_t handle, uint8_t en);
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_RTC_H_ */
|
||||
@@ -0,0 +1,172 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_sha.h
|
||||
* @brief header file for sha driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CSI_SHA_H_
|
||||
#define _CSI_SHA_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
#include <drv_errno.h>
|
||||
|
||||
|
||||
/// definition for sha handle.
|
||||
typedef void *sha_handle_t;
|
||||
|
||||
/****** SHA specific error codes *****/
|
||||
typedef enum {
|
||||
SHA_ERROR_MODE = (EDRV_SPECIFIC + 1), ///< Specified Mode not supported
|
||||
SHA_ERROR_ENDIAN ///< Specified endian not supported
|
||||
} drv_sha_error_e;
|
||||
|
||||
/*----- SHA Control Codes: Mode -----*/
|
||||
typedef enum {
|
||||
SHA_MODE_1 = 1, ///< SHA_1 mode
|
||||
SHA_MODE_256 , ///< SHA_256 mode
|
||||
SHA_MODE_224 , ///< SHA_224 mode
|
||||
SHA_MODE_512 , ///< SHA_512 mode
|
||||
SHA_MODE_384 , ///< SHA_384 mode
|
||||
SHA_MODE_512_256 , ///< SHA_512_256 mode
|
||||
SHA_MODE_512_224 ///< SHA_512_224 mode
|
||||
} sha_mode_e;
|
||||
|
||||
/*----- SHA Control Codes: Mode Parameters: Endian -----*/
|
||||
typedef enum {
|
||||
SHA_ENDIAN_MODE_BIG = 0, ///< Big Endian Mode
|
||||
SHA_ENDIAN_MODE_LITTLE , ///< Little Endian Mode
|
||||
} sha_endian_mode_e;
|
||||
|
||||
/**
|
||||
\brief SHA Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t busy : 1; ///< calculate busy flag
|
||||
} sha_status_t;
|
||||
|
||||
/****** SHA Event *****/
|
||||
typedef enum {
|
||||
SHA_EVENT_COMPLETE = 0 ///< calculate completed
|
||||
} sha_event_e;
|
||||
|
||||
typedef void (*sha_event_cb_t)(sha_event_e event); ///< Pointer to \ref sha_event_cb_t : SHA Event call back.
|
||||
|
||||
|
||||
/**
|
||||
\brief SHA Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t sha1 : 1; ///< supports sha1 mode
|
||||
uint32_t sha224 : 1; ///< supports sha224 mode
|
||||
uint32_t sha256 : 1; ///< supports sha256 mode
|
||||
uint32_t sha384 : 1; ///< supports sha384 mode
|
||||
uint32_t sha512 : 1; ///< supports sha512 mode
|
||||
uint32_t sha512_224 : 1; ///< supports sha512_224 mode
|
||||
uint32_t sha512_256 : 1; ///< supports sha512_256 mode
|
||||
uint32_t endianmode : 1; ///< supports endian mode control
|
||||
uint32_t interruptmode : 1; ///< supports interrupt mode
|
||||
} sha_capabilities_t;
|
||||
|
||||
|
||||
// Function documentation
|
||||
|
||||
/**
|
||||
\brief get sha handle count.
|
||||
\return sha handle count
|
||||
*/
|
||||
int32_t csi_sha_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize SHA Interface. 1. Initializes the resources needed for the SHA interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_sha_get_instance_count()
|
||||
\param[in] cb_event Pointer to \ref sha_event_cb_t
|
||||
\return return sha handle if success
|
||||
*/
|
||||
sha_handle_t csi_sha_initialize(int32_t idx, sha_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize SHA Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle sha handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_sha_uninitialize(sha_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle sha handle to operate.
|
||||
\return \ref sha_capabilities_t
|
||||
*/
|
||||
sha_capabilities_t csi_sha_get_capabilities(sha_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config sha mode.
|
||||
\param[in] handle sha handle to operate.
|
||||
\param[in] mode \ref sha_mode_e
|
||||
\param[in] endian \ref sha_endian_mode_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_sha_config(sha_handle_t handle,
|
||||
sha_mode_e mode,
|
||||
sha_endian_mode_e endian
|
||||
);
|
||||
|
||||
/**
|
||||
\brief start the engine
|
||||
\param[in] handle sha handle to operate.
|
||||
\param[in] context Pointer to the sha context.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_sha_starts(sha_handle_t handle, void *context);
|
||||
|
||||
/**
|
||||
\brief updata the engine
|
||||
\param[in] handle sha handle to operate.
|
||||
\param[in] context Pointer to the sha context.
|
||||
\param[in] input Pointer to the Source data
|
||||
\param[in] len the data len
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_sha_update(sha_handle_t handle, void *context, const void *input, uint32_t len);
|
||||
|
||||
/**
|
||||
\brief finish the engine
|
||||
\param[in] handle sha handle to operate.
|
||||
\param[in] context Pointer to the sha context.
|
||||
\param[out] output Pointer to the dest data
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_sha_finish(sha_handle_t handle, void *context, void *output);
|
||||
|
||||
/**
|
||||
\brief Get SHA status.
|
||||
\param[in] handle sha handle to operate.
|
||||
\return SHA status \ref sha_status_t
|
||||
*/
|
||||
sha_status_t csi_sha_get_status(sha_handle_t handle);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_SHA_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,160 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_timer.h
|
||||
* @brief header file for timer driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CSI_TIMER_H_
|
||||
#define _CSI_TIMER_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
/// definition for timer handle.
|
||||
typedef void *timer_handle_t;
|
||||
|
||||
/*----- TIMER Control Codes: Mode -----*/
|
||||
typedef enum {
|
||||
TIMER_MODE_FREE_RUNNING = 0, ///< free running mode
|
||||
TIMER_MODE_RELOAD ///< reload mode
|
||||
} timer_mode_e;
|
||||
|
||||
/**
|
||||
\brief TIMER Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t active : 1; ///< timer active flag
|
||||
uint32_t timeout : 1; ///< timeout flag
|
||||
} timer_status_t;
|
||||
|
||||
/**
|
||||
\brief TIMER Event
|
||||
*/
|
||||
typedef enum {
|
||||
TIMER_EVENT_TIMEOUT = 0 ///< time out event
|
||||
} timer_event_e;
|
||||
|
||||
typedef void (*timer_event_cb_t)(timer_event_e event, void *arg); ///< Pointer to \ref timer_event_cb_t : TIMER Event call back.
|
||||
|
||||
/**
|
||||
\brief TIMER Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t interrupt_mode : 1; ///< supports Interrupt mode
|
||||
} timer_capabilities_t;
|
||||
|
||||
/**
|
||||
\brief get timer instance count.
|
||||
\return timer instance count
|
||||
*/
|
||||
int32_t csi_timer_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function
|
||||
\param[in] idx instance timer index
|
||||
\param[in] cb_event Pointer to \ref timer_event_cb_t
|
||||
\param[in] cb_arg arguments of cb_event
|
||||
\return pointer to timer instance
|
||||
*/
|
||||
timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event, void *cb_arg);
|
||||
|
||||
/**
|
||||
\brief De-initialize TIMER Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_uninitialize(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return \ref timer_capabilities_t
|
||||
*/
|
||||
timer_capabilities_t csi_timer_get_capabilities(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief config timer mode.
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[in] mode \ref timer_mode_e
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode);
|
||||
|
||||
/**
|
||||
\brief Set timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[in] timeout the timeout value in microseconds(us).
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout);
|
||||
|
||||
/**
|
||||
\brief Start timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[in] apbfreq APB frequency
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_start(timer_handle_t handle, uint32_t apbfreq);
|
||||
|
||||
/**
|
||||
\brief Stop timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_stop(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief suspend timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_suspend(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief resume timer.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_resume(timer_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief get timer current value
|
||||
\param[in] handle timer handle to operate.
|
||||
\param[in] value timer current value
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value);
|
||||
|
||||
/**
|
||||
\brief Get TIMER status.
|
||||
\param[in] handle timer handle to operate.
|
||||
\return TIMER status \ref timer_status_t
|
||||
*/
|
||||
timer_status_t csi_timer_get_status(timer_handle_t handle);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_TIMER_H_ */
|
||||
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_trng.h
|
||||
* @brief header file for trng driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
#ifndef _CSI_TRNG_H_
|
||||
#define _CSI_TRNG_H_
|
||||
|
||||
#include "drv_common.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/// definition for trng handle.
|
||||
typedef void *trng_handle_t;
|
||||
/****** TRNG specific error codes *****/
|
||||
typedef enum {
|
||||
TRNG_ERROR_MODE = 0, ///< Specified Mode not supported
|
||||
} drv_trng_error_e;
|
||||
|
||||
/*----- TRNG Control Codes: Mode -----*/
|
||||
typedef enum {
|
||||
TRNG_MODE_LOWPOWER = 0, ///< TRNG Low power Mode
|
||||
TRNG_MODE_NORMAL ///< TRNG Normal Mode
|
||||
} trng_mode_e;
|
||||
|
||||
/**
|
||||
\brief TRNG Status
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t busy : 1;
|
||||
uint32_t data_valid : 1; ///< Data is valid flag
|
||||
} trng_status_t;
|
||||
|
||||
/****** TRNG Event *****/
|
||||
typedef enum {
|
||||
TRNG_EVENT_DATA_GENERATE_COMPLETE = 0 ///< Get data from TRNG success
|
||||
} trng_event_e;
|
||||
typedef void (*trng_event_cb_t)(trng_event_e event); ///< Pointer to \ref trng_event_cb_t : TRNG Event call back.
|
||||
|
||||
/**
|
||||
\brief TRNG Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t lowper_mode : 1; ///< supports low power mode
|
||||
} trng_capabilities_t;
|
||||
|
||||
// Function documentation
|
||||
|
||||
/**
|
||||
\brief get trng handle count.
|
||||
\return trng handle count
|
||||
*/
|
||||
int32_t csi_trng_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize TRNG Interface. 1. Initializes the resources needed for the TRNG interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_trng_get_instance_count()
|
||||
\param[in] cb_event Pointer to \ref trng_event_cb_t
|
||||
\return pointer to trng handle
|
||||
*/
|
||||
trng_handle_t csi_trng_initialize(int32_t idx, trng_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize TRNG Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle trng handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_trng_uninitialize(trng_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle trng handle to operate.
|
||||
\return \ref trng_capabilities_t
|
||||
*/
|
||||
trng_capabilities_t csi_trng_get_capabilities(trng_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get data from the TRNG.
|
||||
\param[in] handle trng handle to operate.
|
||||
\param[out] data Pointer to buffer with data get from TRNG
|
||||
\param[in] num Number of data items to obtain
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_trng_get_data(trng_handle_t handle, void *data, uint32_t num);
|
||||
|
||||
/**
|
||||
\brief Get TRNG status.
|
||||
\param[in] handle trng handle to operate.
|
||||
\return TRNG status \ref trng_status_t
|
||||
*/
|
||||
trng_status_t csi_trng_get_status(trng_handle_t handle);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_TRNG_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,119 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/******************************************************************************
|
||||
* @file drv_wdt.h
|
||||
* @brief header file for wdt driver
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CSI_WDT_H_
|
||||
#define _CSI_WDT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
/// definition for wdt handle.
|
||||
typedef void *wdt_handle_t;
|
||||
|
||||
/****** WDT Event *****/
|
||||
typedef enum {
|
||||
WDT_EVENT_TIMEOUT = 0 ///< generate the interrupt
|
||||
} wdt_event_e;
|
||||
|
||||
typedef void (*wdt_event_cb_t)(wdt_event_e event); ///< Pointer to \ref wdt_event_cb_t : WDT Event call back.
|
||||
|
||||
/**
|
||||
\brief WDT Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t interrupt : 1; ///< supports interrupt
|
||||
} wdt_capabilities_t;
|
||||
|
||||
/**
|
||||
\brief get wdt instance count.
|
||||
\return wdt instance count
|
||||
*/
|
||||
int32_t csi_wdt_get_instance_count(void);
|
||||
|
||||
/**
|
||||
\brief Initialize WDT Interface. 1. Initializes the resources needed for the WDT interface 2.registers event callback function
|
||||
\param[in] idx must not exceed return value of csi_wdt_get_instance_count()
|
||||
\param[in] cb_event Pointer to \ref wdt_event_cb_t
|
||||
\return pointer to wdt instance
|
||||
*/
|
||||
wdt_handle_t csi_wdt_initialize(int32_t idx, wdt_event_cb_t cb_event);
|
||||
|
||||
/**
|
||||
\brief De-initialize WDT Interface. stops operation and releases the software resources used by the interface
|
||||
\param[in] handle wdt handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_wdt_uninitialize(wdt_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Get driver capabilities.
|
||||
\param[in] handle wdt handle to operate.
|
||||
\return \ref wdt_capabilities_t
|
||||
*/
|
||||
wdt_capabilities_t csi_wdt_get_capabilities(wdt_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Set the WDT value.
|
||||
\param[in] handle wdt handle to operate.
|
||||
\param[in] value the timeout value(ms).
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_wdt_set_timeout(wdt_handle_t handle, uint32_t value);
|
||||
|
||||
/**
|
||||
\brief Start the WDT.
|
||||
\param[in] handle wdt handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_wdt_start(wdt_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Stop the WDT.
|
||||
\param[in] handle wdt handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_wdt_stop(wdt_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Restart the WDT.
|
||||
\param[in] handle wdt handle to operate.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_wdt_restart(wdt_handle_t handle);
|
||||
|
||||
/**
|
||||
\brief Read the WDT Current value.
|
||||
\param[in] handle wdt handle to operate.
|
||||
\param[in] value Pointer to the Value.
|
||||
\return error code
|
||||
*/
|
||||
int32_t csi_wdt_read_current_value(wdt_handle_t handle, uint32_t *value);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _CSI_WDT_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,145 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_DEBUG
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_DEBUG_INIT 0
|
||||
#define RT_DEBUG_THREAD 0
|
||||
#define RT_USING_HOOK
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
|
||||
/* C++ features */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 1
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 512
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_USING_MSH_ONLY
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
|
||||
/* Network stack */
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
|
||||
/* Modbus master and slave stack */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* RT-Thread GUI Engine */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
|
||||
/* sample package */
|
||||
|
||||
|
||||
/* example package: hello */
|
||||
|
||||
|
||||
/* Privated Packages of RealThread */
|
||||
|
||||
|
||||
/* Network Utilities */
|
||||
|
||||
#define RT_USING_UART1
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,63 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH ='c-sky'
|
||||
CPU ='ck802'
|
||||
CROSS_TOOL ='gcc'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'F:\c-sky\CSKY\MinGW\csky-abiv2-elf-toolchain\bin'
|
||||
# EXEC_PATH = r'/home/tanek/c-sky/CK802/toolchain/csky-abiv2-elf-tools-x86_64-minilibc-20161211/bin'
|
||||
else:
|
||||
print 'Please make sure your toolchains is GNU GCC!'
|
||||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
# BUILD = 'debug'
|
||||
BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'csky-abiv2-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'g++'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
if CPU == 'ck802':
|
||||
DEVICE = ' -mcpu=ck802'
|
||||
|
||||
CFLAGS = DEVICE + ' -DCONFIG_CPU_CK802 -c -g -ffunction-sections -Wall -mistack -mlittle-endian'
|
||||
AFLAGS = ' -c' + DEVICE + ' -EL -x assembler-with-cpp -save-temps=ojb'
|
||||
LFLAGS = DEVICE + ' -EL -Wl,--gc-sections,-Map=rtthread_ck802.map,-cref,-u,Reset_Handler -T gcc_csky.ld'
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
M_CFLAGS = DEVICE + ' -EL -G0 -O2 -mno-abicalls -fno-common -fno-exceptions -fno-omit-frame-pointer -mlong-calls -fno-pic '
|
||||
M_CXXFLAGS = M_CFLAGS
|
||||
M_LFLAGS = DEVICE + ' -EL -r -Wl,--gc-sections,-z,max-page-size=0x4' +\
|
||||
' -nostartfiles -static-libgcc'
|
||||
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
@@ -0,0 +1,176 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Project Name="rt-thread" Version="1">
|
||||
<Dependencies Name="Debug"/>
|
||||
<Description/>
|
||||
<Dependencies Name="BuildSet"/>
|
||||
<BuildConfigs>
|
||||
<BuildConfig Name="BuildSet">
|
||||
<Target>
|
||||
<ROMBank Selected="1">
|
||||
<ROM1>
|
||||
<InUse>yes</InUse>
|
||||
<Start>0x10000000</Start>
|
||||
<Size>0x40000</Size>
|
||||
</ROM1>
|
||||
<ROM2>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
</ROM2>
|
||||
<ROM3>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
</ROM3>
|
||||
<ROM4>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
</ROM4>
|
||||
<ROM5>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
</ROM5>
|
||||
</ROMBank>
|
||||
<RAMBank>
|
||||
<RAM1>
|
||||
<InUse>yes</InUse>
|
||||
<Start>0x20000000</Start>
|
||||
<Size>0x18000</Size>
|
||||
<Init>yes</Init>
|
||||
</RAM1>
|
||||
<RAM2>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
<Init>yes</Init>
|
||||
</RAM2>
|
||||
<RAM3>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
<Init>yes</Init>
|
||||
</RAM3>
|
||||
<RAM4>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
<Init>yes</Init>
|
||||
</RAM4>
|
||||
<RAM5>
|
||||
<InUse>no</InUse>
|
||||
<Start/>
|
||||
<Size/>
|
||||
<Init>yes</Init>
|
||||
</RAM5>
|
||||
</RAMBank>
|
||||
<CPU>ck802</CPU>
|
||||
<UseMiniLib>yes</UseMiniLib>
|
||||
<Endian>little</Endian>
|
||||
<UseHardFloat>no</UseHardFloat>
|
||||
<UseEnhancedLRW>no</UseEnhancedLRW>
|
||||
</Target>
|
||||
<Output>
|
||||
<OutputName>$(ProjectName)</OutputName>
|
||||
<Type>Executable</Type>
|
||||
<CreateHexFile>yes</CreateHexFile>
|
||||
<Preprocessor>yes</Preprocessor>
|
||||
<Disasm>yes</Disasm>
|
||||
<CallGraph>yes</CallGraph>
|
||||
<Map>yes</Map>
|
||||
</Output>
|
||||
<User>
|
||||
<BeforeCompile>
|
||||
<RunUserProg>no</RunUserProg>
|
||||
<UserProgName/>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg>no</RunUserProg>
|
||||
<UserProgName/>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg>no</RunUserProg>
|
||||
<UserProgName/>
|
||||
</AfterMake>
|
||||
</User>
|
||||
<Compiler>
|
||||
<Define/>
|
||||
<Undefine/>
|
||||
<Optim>None (-O0)</Optim>
|
||||
<DebugLevel>Maximum (-g3)</DebugLevel>
|
||||
<IncludePath/>
|
||||
<OtherFlags></OtherFlags>
|
||||
<Verbose>no</Verbose>
|
||||
<Ansi>no</Ansi>
|
||||
<Syntax>no</Syntax>
|
||||
<Pedantic>no</Pedantic>
|
||||
<PedanticErr>no</PedanticErr>
|
||||
<InhibitWarn>no</InhibitWarn>
|
||||
<AllWarn>yes</AllWarn>
|
||||
<WarnErr>no</WarnErr>
|
||||
<OneElfS>no</OneElfS>
|
||||
<Fstrict>no</Fstrict>
|
||||
</Compiler>
|
||||
<Asm>
|
||||
<Define>CONFIG_CKCPU_MMU=0</Define>
|
||||
<Undefine/>
|
||||
<IncludePath></IncludePath>
|
||||
<OtherFlags/>
|
||||
<DebugLevel>gdwarf2</DebugLevel>
|
||||
</Asm>
|
||||
<Linker>
|
||||
<Garbage>yes</Garbage>
|
||||
<LDFile>$(ProjectPath)\gcc_csky.ld</LDFile>
|
||||
<LibName/>
|
||||
<LibPath/>
|
||||
<OtherFlags/>
|
||||
<AutoLDFile>no</AutoLDFile>
|
||||
</Linker>
|
||||
<Debug>
|
||||
<LoadApplicationAtStartup>yes</LoadApplicationAtStartup>
|
||||
<Connector>ICE</Connector>
|
||||
<StopAt>yes</StopAt>
|
||||
<StopAtText>main</StopAtText>
|
||||
<InitFile/>
|
||||
<AutoRun>no</AutoRun>
|
||||
<ResetType>Hard Reset</ResetType>
|
||||
<SoftResetVal>0</SoftResetVal>
|
||||
<ResetAfterLoad>no</ResetAfterLoad>
|
||||
<ConfigICE>
|
||||
<IP>localhost</IP>
|
||||
<PORT>1025</PORT>
|
||||
<Clock>12000</Clock>
|
||||
<Delay>10</Delay>
|
||||
<DDC>yes</DDC>
|
||||
<TRST>no</TRST>
|
||||
<Connect>Normal</Connect>
|
||||
<ResetType>Soft Reset</ResetType>
|
||||
<SoftResetVal>0</SoftResetVal>
|
||||
<RTOSType>Bare Metal</RTOSType>
|
||||
<DownloadToFlash>no</DownloadToFlash>
|
||||
<ResetAfterConnect>yes</ResetAfterConnect>
|
||||
</ConfigICE>
|
||||
<ConfigSIM>
|
||||
<SIMTarget>soccfg/cskyv2/smart_v3_802_cfg.xml</SIMTarget>
|
||||
<OtherFlags/>
|
||||
<NoGraphic>no</NoGraphic>
|
||||
<Log>yes</Log>
|
||||
</ConfigSIM>
|
||||
</Debug>
|
||||
<Flash>
|
||||
<InitFile/>
|
||||
<Erase>Erase Sectors</Erase>
|
||||
<Algorithms Path=""/>
|
||||
<Program>yes</Program>
|
||||
<Verify>no</Verify>
|
||||
<ResetAndRun>no</ResetAndRun>
|
||||
</Flash>
|
||||
</BuildConfig>
|
||||
</BuildConfigs>
|
||||
<DebugSessions>
|
||||
<watchExpressions/>
|
||||
<memoryExpressions>;;;</memoryExpressions>
|
||||
<statistics>;;MHZ</statistics>
|
||||
</DebugSessions>
|
||||
</Project>
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,152 @@
|
||||
/*
|
||||
* File : contex_ck802.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-01-01 Urey first version
|
||||
* 2018-06-05 tanek clean code
|
||||
*/
|
||||
|
||||
.file "contex_ck802.S"
|
||||
|
||||
#undef VIC_TSPDR
|
||||
#define VIC_TSPDR 0XE000EC08
|
||||
|
||||
.global rt_thread_switch_interrupt_flag
|
||||
.global rt_interrupt_from_thread
|
||||
.global rt_interrupt_to_thread
|
||||
|
||||
.text
|
||||
.align 2
|
||||
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable(void);
|
||||
*/
|
||||
.global rt_hw_interrupt_disable
|
||||
.type rt_hw_interrupt_disable, %function
|
||||
rt_hw_interrupt_disable:
|
||||
mfcr r0, psr
|
||||
psrclr ie
|
||||
rts
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t psr);
|
||||
*/
|
||||
.global rt_hw_interrupt_enable
|
||||
.type rt_hw_interrupt_enable, %function
|
||||
rt_hw_interrupt_enable:
|
||||
mtcr r0, psr
|
||||
rts
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to);
|
||||
* R0 --> to
|
||||
*/
|
||||
.global rt_hw_context_switch_to
|
||||
.type rt_hw_context_switch_to, %function
|
||||
rt_hw_context_switch_to:
|
||||
lrw r2, rt_interrupt_to_thread
|
||||
stw r0, (r2)
|
||||
|
||||
/* set form thread = 0 */
|
||||
lrw r2, rt_interrupt_from_thread
|
||||
movi r0, 0
|
||||
stw r0, (r2)
|
||||
|
||||
psrclr ie
|
||||
jbr __tspend_handler_nosave
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
|
||||
* r0 --> from
|
||||
* r1 --> to
|
||||
*/
|
||||
.global rt_hw_context_switch_interrupt
|
||||
.type rt_hw_context_switch_interrupt, %function
|
||||
rt_hw_context_switch_interrupt:
|
||||
lrw r2, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
|
||||
stw r0, (r2)
|
||||
|
||||
lrw r2, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
|
||||
stw r1, (r2)
|
||||
|
||||
lrw r0, VIC_TSPDR
|
||||
bgeni r1, 0
|
||||
stw r1, (r0)
|
||||
rts
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
|
||||
* r0 --> from
|
||||
* r1 --> to
|
||||
*/
|
||||
.global rt_hw_context_switch
|
||||
.type rt_hw_context_switch, %function
|
||||
rt_hw_context_switch:
|
||||
lrw r2, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
|
||||
stw r0, (r2)
|
||||
|
||||
lrw r2, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
|
||||
stw r1, (r2)
|
||||
|
||||
lrw r0, VIC_TSPDR
|
||||
bgeni r1, 0
|
||||
stw r1, (r0)
|
||||
rts
|
||||
|
||||
.global PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
subi sp, 68
|
||||
stm r0-r13, (sp)
|
||||
stw r15, (sp, 56)
|
||||
mfcr r0, epsr
|
||||
stw r0, (sp, 60)
|
||||
mfcr r0, epc
|
||||
stw r0, (sp, 64)
|
||||
|
||||
lrw r0, rt_interrupt_from_thread
|
||||
ldw r1, (r0)
|
||||
stw sp, (r1)
|
||||
|
||||
__tspend_handler_nosave:
|
||||
lrw r6, rt_interrupt_to_thread
|
||||
lrw r7, rt_interrupt_from_thread
|
||||
ldw r8, (r6)
|
||||
stw r8, (r7)
|
||||
|
||||
ldw sp, (r8)
|
||||
|
||||
#ifdef CONFIG_STACK_GUARD
|
||||
mfcr r3, cr<0, 4>
|
||||
bseti r3, 0
|
||||
bseti r3, 1
|
||||
mtcr r3, cr<0, 4>
|
||||
#endif
|
||||
|
||||
ldw r0, (sp, 64)
|
||||
mtcr r0, epc
|
||||
ldw r0, (sp, 60)
|
||||
bseti r0, 6
|
||||
mtcr r0, epsr
|
||||
ldw r15, (sp, 56)
|
||||
ldm r0-r13, (sp)
|
||||
addi sp, 68
|
||||
rte
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* File : stack_ck802.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-01-01 Urey first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk = (rt_uint32_t *)stack_addr;
|
||||
|
||||
stk = (rt_uint32_t *)(stack_addr + sizeof(rt_uint32_t));
|
||||
stk = (rt_uint32_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
|
||||
|
||||
*(--stk) = (rt_uint32_t)tentry; /* Entry Point */
|
||||
*(--stk) = (rt_uint32_t)0x80000150L; /* PSR */
|
||||
*(--stk) = (rt_uint32_t)texit; /* R15 (LR) (init value will cause fault if ever used) */
|
||||
*(--stk) = (rt_uint32_t)0x13131313L; /* R13 */
|
||||
*(--stk) = (rt_uint32_t)0x12121212L; /* R12 */
|
||||
*(--stk) = (rt_uint32_t)0x11111111L; /* R11 */
|
||||
*(--stk) = (rt_uint32_t)0x10101010L; /* R10 */
|
||||
*(--stk) = (rt_uint32_t)0x09090909L; /* R9 */
|
||||
*(--stk) = (rt_uint32_t)0x08080808L; /* R8 */
|
||||
*(--stk) = (rt_uint32_t)0x07070707L; /* R7 */
|
||||
*(--stk) = (rt_uint32_t)0x06060606L; /* R6 */
|
||||
*(--stk) = (rt_uint32_t)0x05050505L; /* R5 */
|
||||
*(--stk) = (rt_uint32_t)0x04040404L; /* R4 */
|
||||
*(--stk) = (rt_uint32_t)0x03030303L; /* R3 */
|
||||
*(--stk) = (rt_uint32_t)0x02020202L; /* R2 */
|
||||
*(--stk) = (rt_uint32_t)0x01010101L; /* R1 */
|
||||
*(--stk) = (rt_uint32_t)parameter; /* R0 : argument */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file csi_gcc.h
|
||||
* @brief CSI Header File for GCC.
|
||||
* @version V1.0
|
||||
* @date 02. June 2017
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _CSI_GCC_H_
|
||||
#define _CSI_GCC_H_
|
||||
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __ALWAYS_INLINE __attribute__((always_inline)) static inline
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "csi_reg.h"
|
||||
#include "csi_instr.h"
|
||||
#include "csi_simd.h"
|
||||
|
||||
#endif /* _CSI_GCC_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
+8
-2
@@ -264,7 +264,7 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [
|
||||
AddOption('--target',
|
||||
dest='target',
|
||||
type='string',
|
||||
help='set target project: mdk/mdk4/mdk5/iar/vs/vsc/ua')
|
||||
help='set target project: mdk/mdk4/mdk5/iar/vs/vsc/ua/cdk')
|
||||
|
||||
#{target_name:(CROSS_TOOL, PLATFORM)}
|
||||
tgt_dict = {'mdk':('keil', 'armcc'),
|
||||
@@ -275,8 +275,10 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [
|
||||
'vs2012':('msvc', 'cl'),
|
||||
'vsc' : ('gcc', 'gcc'),
|
||||
'cb':('keil', 'armcc'),
|
||||
'ua':('gcc', 'gcc')}
|
||||
'ua':('gcc', 'gcc'),
|
||||
'cdk':('gcc', 'gcc')}
|
||||
tgt_name = GetOption('target')
|
||||
|
||||
if tgt_name:
|
||||
# --target will change the toolchain settings which clang-analyzer is
|
||||
# depend on
|
||||
@@ -770,6 +772,10 @@ def EndBuilding(target, program = None):
|
||||
if GetOption('target') == 'vsc':
|
||||
from vsc import GenerateVSCode
|
||||
GenerateVSCode(Env)
|
||||
|
||||
if GetOption('target') == 'cdk':
|
||||
from cdk import CDKProject
|
||||
CDKProject('project.cdkproj', Projects)
|
||||
|
||||
BSP_ROOT = Dir('#').abspath
|
||||
if GetOption('copy') and program != None:
|
||||
|
||||
+128
@@ -0,0 +1,128 @@
|
||||
#
|
||||
# File : keil.py
|
||||
# This file is part of RT-Thread RTOS
|
||||
# COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License along
|
||||
# with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
# 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
#
|
||||
# Change Logs:
|
||||
# Date Author Notes
|
||||
# 2017-10-16 Tanek Add CDK IDE support
|
||||
#
|
||||
|
||||
import os
|
||||
import sys
|
||||
import string
|
||||
|
||||
import xml.etree.ElementTree as etree
|
||||
from xml.etree.ElementTree import SubElement
|
||||
from utils import _make_path_relative
|
||||
from utils import xml_indent
|
||||
|
||||
def SDKAddGroup(ProjectFiles, parent, name, files, project_path):
|
||||
# don't add an empty group
|
||||
if len(files) == 0:
|
||||
return
|
||||
|
||||
group = SubElement(parent, 'VirtualDirectory', attrib={'Name': name})
|
||||
|
||||
for f in files:
|
||||
fn = f.rfile()
|
||||
name = fn.name
|
||||
path = os.path.dirname(fn.abspath)
|
||||
|
||||
basename = os.path.basename(path)
|
||||
path = _make_path_relative(project_path, path)
|
||||
elm_attr_name = os.path.join(path, name)
|
||||
|
||||
file = SubElement(group, 'File', attrib={'Name': elm_attr_name})
|
||||
|
||||
return group
|
||||
|
||||
def _CDKProject(tree, target, script):
|
||||
|
||||
project_path = os.path.dirname(os.path.abspath(target))
|
||||
|
||||
root = tree.getroot()
|
||||
out = file(target, 'wb')
|
||||
out.write('<?xml version="1.0" encoding="UTF-8"?>\n')
|
||||
|
||||
CPPPATH = []
|
||||
CPPDEFINES = []
|
||||
LINKFLAGS = ''
|
||||
CCFLAGS = ''
|
||||
ProjectFiles = []
|
||||
|
||||
for child in root:
|
||||
if child.tag == 'VirtualDirectory':
|
||||
root.remove(child)
|
||||
|
||||
for group in script:
|
||||
group_tree = SDKAddGroup(ProjectFiles, root, group['name'], group['src'], project_path)
|
||||
|
||||
# get each include path
|
||||
if group.has_key('CPPPATH') and group['CPPPATH']:
|
||||
if CPPPATH:
|
||||
CPPPATH += group['CPPPATH']
|
||||
else:
|
||||
CPPPATH += group['CPPPATH']
|
||||
|
||||
# get each group's definitions
|
||||
if group.has_key('CPPDEFINES') and group['CPPDEFINES']:
|
||||
if CPPDEFINES:
|
||||
CPPDEFINES += group['CPPDEFINES']
|
||||
else:
|
||||
CPPDEFINES += group['CPPDEFINES']
|
||||
|
||||
# get each group's cc flags
|
||||
if group.has_key('CCFLAGS') and group['CCFLAGS']:
|
||||
if CCFLAGS:
|
||||
CCFLAGS += ' ' + group['CCFLAGS']
|
||||
else:
|
||||
CCFLAGS += group['CCFLAGS']
|
||||
|
||||
# get each group's link flags
|
||||
if group.has_key('LINKFLAGS') and group['LINKFLAGS']:
|
||||
if LINKFLAGS:
|
||||
LINKFLAGS += ' ' + group['LINKFLAGS']
|
||||
else:
|
||||
LINKFLAGS += group['LINKFLAGS']
|
||||
|
||||
# todo: cdk add lib
|
||||
|
||||
# write include path, definitions and link flags
|
||||
text = ';'.join([_make_path_relative(project_path, os.path.normpath(i)) for i in CPPPATH])
|
||||
IncludePath = tree.find('BuildConfigs/BuildConfig/Compiler/IncludePath')
|
||||
IncludePath.text = text
|
||||
IncludePath = tree.find('BuildConfigs/BuildConfig/Asm/IncludePath')
|
||||
IncludePath.text = text
|
||||
|
||||
Define = tree.find('BuildConfigs/BuildConfig/Compiler/Define')
|
||||
Define.text = ', '.join(set(CPPDEFINES))
|
||||
|
||||
CC_Misc = tree.find('BuildConfigs/BuildConfig/Compiler/OtherFlags')
|
||||
CC_Misc.text = CCFLAGS
|
||||
|
||||
LK_Misc = tree.find('BuildConfigs/BuildConfig/Linker/OtherFlags')
|
||||
LK_Misc.text = LINKFLAGS
|
||||
|
||||
xml_indent(root)
|
||||
out.write(etree.tostring(root, encoding='utf-8'))
|
||||
out.close()
|
||||
|
||||
def CDKProject(target, script):
|
||||
template_tree = etree.parse('template.cdkproj')
|
||||
|
||||
_CDKProject(template_tree, target, script)
|
||||
Reference in new issue
Block a user