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remove old CMSIS
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@683 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
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||||
;/*****************************************************************************
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||||
; * @file: startup_LPC17xx.s
|
||||
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
|
||||
; * for the NXP LPC17xx Device Series
|
||||
; * @version: V1.0
|
||||
; * @date: 25. Nov. 2008
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000200
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||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
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||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 16: Watchdog Timer
|
||||
DCD TIMER0_IRQHandler ; 17: Timer0
|
||||
DCD TIMER1_IRQHandler ; 18: Timer1
|
||||
DCD TIMER2_IRQHandler ; 19: Timer2
|
||||
DCD TIMER3_IRQHandler ; 20: Timer3
|
||||
DCD UART0_IRQHandler ; 21: UART0
|
||||
DCD UART1_IRQHandler ; 22: UART1
|
||||
DCD UART2_IRQHandler ; 23: UART2
|
||||
DCD UART3_IRQHandler ; 24: UART3
|
||||
DCD PWM1_IRQHandler ; 25: PWM1
|
||||
DCD I2C0_IRQHandler ; 26: I2C0
|
||||
DCD I2C1_IRQHandler ; 27: I2C1
|
||||
DCD I2C2_IRQHandler ; 28: I2C2
|
||||
DCD SPI_IRQHandler ; 29: SPI
|
||||
DCD SSP0_IRQHandler ; 30: SSP0
|
||||
DCD SSP1_IRQHandler ; 31: SSP1
|
||||
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
||||
DCD RTC_IRQHandler ; 33: Real Time Clock
|
||||
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
||||
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
||||
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
||||
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
||||
DCD ADC_IRQHandler ; 38: A/D Converter
|
||||
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
||||
DCD USB_IRQHandler ; 40: USB
|
||||
DCD CAN_IRQHandler ; 41: CAN
|
||||
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
||||
DCD I2S_IRQHandler ; 43: I2S
|
||||
DCD ENET_IRQHandler ; 44: Ethernet
|
||||
DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
|
||||
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
||||
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
||||
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
||||
DCD USBActivity_IRQHandler ; USB Activity interrupt to wakeup
|
||||
DCD CANActivity_IRQHandler ; CAN Activity interrupt to wakeup
|
||||
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
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||||
EXPORT Reset_Handler [WEAK]
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||||
IMPORT __main
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||||
LDR R0, =__main
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||||
BX R0
|
||||
ENDP
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||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
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||||
EXPORT NMI_Handler [WEAK]
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||||
B .
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||||
ENDP
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||||
HardFault_Handler\
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||||
PROC
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||||
EXPORT HardFault_Handler [WEAK]
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||||
B .
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||||
ENDP
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||||
MemManage_Handler\
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||||
PROC
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||||
EXPORT MemManage_Handler [WEAK]
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||||
B .
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||||
ENDP
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||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
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||||
B .
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||||
ENDP
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||||
UsageFault_Handler\
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||||
PROC
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||||
EXPORT UsageFault_Handler [WEAK]
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||||
B .
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||||
ENDP
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||||
SVC_Handler PROC
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||||
EXPORT SVC_Handler [WEAK]
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||||
B .
|
||||
ENDP
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||||
DebugMon_Handler\
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||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT I2C2_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
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||||
EXPORT PLL0_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT EINT0_IRQHandler [WEAK]
|
||||
EXPORT EINT1_IRQHandler [WEAK]
|
||||
EXPORT EINT2_IRQHandler [WEAK]
|
||||
EXPORT EINT3_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT RIT_IRQHandler [WEAK]
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||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
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||||
EXPORT PLL1_IRQHandler [WEAK]
|
||||
EXPORT USBActivity_IRQHandler [WEAK]
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||||
EXPORT CANActivity_IRQHandler [WEAK]
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||||
|
||||
WDT_IRQHandler
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||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
I2C2_IRQHandler
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||||
SPI_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
PLL0_IRQHandler
|
||||
RTC_IRQHandler
|
||||
EINT0_IRQHandler
|
||||
EINT1_IRQHandler
|
||||
EINT2_IRQHandler
|
||||
EINT3_IRQHandler
|
||||
ADC_IRQHandler
|
||||
BOD_IRQHandler
|
||||
USB_IRQHandler
|
||||
CAN_IRQHandler
|
||||
DMA_IRQHandler
|
||||
I2S_IRQHandler
|
||||
ENET_IRQHandler
|
||||
RIT_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
QEI_IRQHandler
|
||||
PLL1_IRQHandler
|
||||
USBActivity_IRQHandler
|
||||
CANActivity_IRQHandler
|
||||
|
||||
B .
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||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
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||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
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||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
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||||
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||||
IMPORT __use_two_region_memory
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||||
EXPORT __user_initial_stackheap
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||||
__user_initial_stackheap
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||||
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||||
LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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||||
LDR R2, = (Heap_Mem + Heap_Size)
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||||
LDR R3, = Stack_Mem
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||||
BX LR
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||||
|
||||
ALIGN
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||||
|
||||
ENDIF
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||||
|
||||
|
||||
END
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||||
@@ -1,495 +0,0 @@
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||||
/******************************************************************************
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||||
* @file: system_LPC17xx.c
|
||||
* @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC17xx Device Series
|
||||
* @version: V1.1
|
||||
* @date: 18th May 2009
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
*
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#include <stdint.h>
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||||
#include "LPC17xx.h"
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
*/
|
||||
|
||||
/*--------------------- Clock Configuration ----------------------------------
|
||||
//
|
||||
// <e> Clock Configuration
|
||||
// <h> System Controls and Status Register (SCS)
|
||||
// <o1.4> OSCRANGE: Main Oscillator Range Select
|
||||
// <0=> 1 MHz to 20 MHz
|
||||
// <1=> 15 MHz to 24 MHz
|
||||
// <e1.5> OSCEN: Main Oscillator Enable
|
||||
// </e>
|
||||
// </h>
|
||||
//
|
||||
// <h> Clock Source Select Register (CLKSRCSEL)
|
||||
// <o2.0..1> CLKSRC: PLL Clock Source Selection
|
||||
// <0=> Internal RC oscillator
|
||||
// <1=> Main oscillator
|
||||
// <2=> RTC oscillator
|
||||
// </h>
|
||||
//
|
||||
// <e3> PLL0 Configuration (Main PLL)
|
||||
// <h> PLL0 Configuration Register (PLL0CFG)
|
||||
// <i> F_cco0 = (2 * M * F_in) / N
|
||||
// <i> F_in must be in the range of 32 kHz to 50 MHz
|
||||
// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
|
||||
// <o4.0..14> MSEL: PLL Multiplier Selection
|
||||
// <6-32768><#-1>
|
||||
// <i> M Value
|
||||
// <o4.16..23> NSEL: PLL Divider Selection
|
||||
// <1-256><#-1>
|
||||
// <i> N Value
|
||||
// </h>
|
||||
// </e>
|
||||
//
|
||||
// <e5> PLL1 Configuration (USB PLL)
|
||||
// <h> PLL1 Configuration Register (PLL1CFG)
|
||||
// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
|
||||
// <i> F_cco1 = F_osc * M * 2 * P
|
||||
// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
|
||||
// <o6.0..4> MSEL: PLL Multiplier Selection
|
||||
// <1-32><#-1>
|
||||
// <i> M Value (for USB maximum value is 4)
|
||||
// <o6.5..6> PSEL: PLL Divider Selection
|
||||
// <0=> 1
|
||||
// <1=> 2
|
||||
// <2=> 4
|
||||
// <3=> 8
|
||||
// <i> P Value
|
||||
// </h>
|
||||
// </e>
|
||||
//
|
||||
// <h> CPU Clock Configuration Register (CCLKCFG)
|
||||
// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
|
||||
// <3-256><#-1>
|
||||
// </h>
|
||||
//
|
||||
// <h> USB Clock Configuration Register (USBCLKCFG)
|
||||
// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL1
|
||||
// <0-15>
|
||||
// <i> Divide is USBSEL + 1
|
||||
// </h>
|
||||
//
|
||||
// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
|
||||
// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 6
|
||||
// </h>
|
||||
//
|
||||
// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
|
||||
// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
|
||||
// <0=> Pclk = Cclk / 4
|
||||
// <1=> Pclk = Cclk
|
||||
// <2=> Pclk = Cclk / 2
|
||||
// <3=> Pclk = Hclk / 8
|
||||
// </h>
|
||||
//
|
||||
// <h> Power Control for Peripherals Register (PCONP)
|
||||
// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
|
||||
// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
|
||||
// <o11.3> PCUART0: UART 0 power/clock enable
|
||||
// <o11.4> PCUART1: UART 1 power/clock enable
|
||||
// <o11.6> PCPWM1: PWM 1 power/clock enable
|
||||
// <o11.7> PCI2C0: I2C interface 0 power/clock enable
|
||||
// <o11.8> PCSPI: SPI interface power/clock enable
|
||||
// <o11.9> PCRTC: RTC power/clock enable
|
||||
// <o11.10> PCSSP1: SSP interface 1 power/clock enable
|
||||
// <o11.12> PCAD: A/D converter power/clock enable
|
||||
// <o11.13> PCCAN1: CAN controller 1 power/clock enable
|
||||
// <o11.14> PCCAN2: CAN controller 2 power/clock enable
|
||||
// <o11.15> PCGPIO: GPIOs power/clock enable
|
||||
// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
|
||||
// <o11.17> PCMC: Motor control PWM power/clock enable
|
||||
// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
|
||||
// <o11.19> PCI2C1: I2C interface 1 power/clock enable
|
||||
// <o11.21> PCSSP0: SSP interface 0 power/clock enable
|
||||
// <o11.22> PCTIM2: Timer 2 power/clock enable
|
||||
// <o11.23> PCTIM3: Timer 3 power/clock enable
|
||||
// <o11.24> PCUART2: UART 2 power/clock enable
|
||||
// <o11.25> PCUART3: UART 3 power/clock enable
|
||||
// <o11.26> PCI2C2: I2C interface 2 power/clock enable
|
||||
// <o11.27> PCI2S: I2S interface power/clock enable
|
||||
// <o11.29> PCGPDMA: GP DMA function power/clock enable
|
||||
// <o11.30> PCENET: Ethernet block power/clock enable
|
||||
// <o11.31> PCUSB: USB interface power/clock enable
|
||||
// </h>
|
||||
//
|
||||
// <h> Clock Output Configuration Register (CLKOUTCFG)
|
||||
// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
|
||||
// <0=> CPU clock
|
||||
// <1=> Main oscillator
|
||||
// <2=> Internal RC oscillator
|
||||
// <3=> USB clock
|
||||
// <4=> RTC oscillator
|
||||
// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
|
||||
// <1-16><#-1>
|
||||
// <o12.8> CLKOUT_EN: CLKOUT enable control
|
||||
// </h>
|
||||
//
|
||||
// </e>
|
||||
*/
|
||||
#define CLOCK_SETUP 1
|
||||
#define SCS_Val 0x00000020
|
||||
#define CLKSRCSEL_Val 0x00000001
|
||||
#define PLL0_SETUP 1
|
||||
#define PLL0CFG_Val 0x0000000B
|
||||
#define PLL1_SETUP 1
|
||||
#define PLL1CFG_Val 0x00000023
|
||||
#define CCLKCFG_Val 0x00000003
|
||||
#define USBCLKCFG_Val 0x00000000
|
||||
#define PCLKSEL0_Val 0x00000000
|
||||
#define PCLKSEL1_Val 0x00000000
|
||||
#define PCONP_Val 0x042887DE
|
||||
#define CLKOUTCFG_Val 0x00000000
|
||||
|
||||
|
||||
/*--------------------- Flash Accelerator Configuration ----------------------
|
||||
//
|
||||
// <e> Flash Accelerator Configuration
|
||||
// <o1.0..1> FETCHCFG: Fetch Configuration
|
||||
// <0=> Instruction fetches from flash are not buffered
|
||||
// <1=> One buffer is used for all instruction fetch buffering
|
||||
// <2=> All buffers may be used for instruction fetch buffering
|
||||
// <3=> Reserved (do not use this setting)
|
||||
// <o1.2..3> DATACFG: Data Configuration
|
||||
// <0=> Data accesses from flash are not buffered
|
||||
// <1=> One buffer is used for all data access buffering
|
||||
// <2=> All buffers may be used for data access buffering
|
||||
// <3=> Reserved (do not use this setting)
|
||||
// <o1.4> ACCEL: Acceleration Enable
|
||||
// <o1.5> PREFEN: Prefetch Enable
|
||||
// <o1.6> PREFOVR: Prefetch Override
|
||||
// <o1.12..15> FLASHTIM: Flash Access Time
|
||||
// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
|
||||
// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
|
||||
// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
|
||||
// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
|
||||
// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
|
||||
// <5=> 6 CPU clocks (for any CPU clock)
|
||||
// </e>
|
||||
*/
|
||||
#define FLASH_SETUP 1
|
||||
#define FLASHCFG_Val 0x0000303A
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Check the register settings
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
|
||||
#define CHECK_RSVD(val, mask) (val & mask)
|
||||
|
||||
/* Clock Configuration -------------------------------------------------------*/
|
||||
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
|
||||
#error "SCS: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
|
||||
#error "CLKSRCSEL: Value out of range!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
|
||||
#error "PLL0CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
|
||||
#error "PLL1CFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
|
||||
#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
|
||||
#error "USBCLKCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
|
||||
#error "PCLKSEL0: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
|
||||
#error "PCLKSEL1: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
|
||||
#error "PCONP: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
|
||||
#error "CLKOUTCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
/* Flash Accelerator Configuration -------------------------------------------*/
|
||||
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
|
||||
#error "FLASHCFG: Invalid values of reserved bits!"
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
DEFINES
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
|
||||
#define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemFrequency = IRC_OSC; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemFrequency variable.
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if (CLOCK_SETUP) /* Clock Setup */
|
||||
LPC_SC->SCS = SCS_Val;
|
||||
if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
|
||||
while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
|
||||
}
|
||||
|
||||
LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
|
||||
|
||||
LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
|
||||
LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
|
||||
|
||||
#if (PLL0_SETUP)
|
||||
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
|
||||
LPC_SC->PLL0CFG = PLL0CFG_Val;
|
||||
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
|
||||
|
||||
LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
|
||||
LPC_SC->PLL0FEED = 0xAA;
|
||||
LPC_SC->PLL0FEED = 0x55;
|
||||
#endif
|
||||
|
||||
#if (PLL1_SETUP)
|
||||
LPC_SC->PLL1CFG = PLL1CFG_Val;
|
||||
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
|
||||
|
||||
LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
|
||||
LPC_SC->PLL1FEED = 0xAA;
|
||||
LPC_SC->PLL1FEED = 0x55;
|
||||
#else
|
||||
LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
|
||||
#endif
|
||||
|
||||
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
|
||||
|
||||
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
|
||||
#endif
|
||||
|
||||
/* Determine clock frequency according to clock register values */
|
||||
if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Internal RC */
|
||||
SystemFrequency = (IRC_OSC *
|
||||
(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
SystemFrequency = (OSC_CLK *
|
||||
(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
SystemFrequency = (RTC_CLK *
|
||||
(((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
|
||||
(((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
|
||||
((LPC_SC->CCLKCFG & 0xFF)+ 1));
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (LPC_SC->CLKSRCSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator => PLL0 */
|
||||
case 3: /* Reserved, default to Internal RC */
|
||||
SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
case 1: /* Main oscillator => PLL0 */
|
||||
SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
case 2: /* RTC oscillator => PLL0 */
|
||||
SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
|
||||
LPC_SC->FLASHCFG = FLASHCFG_Val;
|
||||
#endif
|
||||
}
|
||||
@@ -1,49 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file: system_LPC17xx.h
|
||||
* @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
|
||||
* for the NXP LPC17xx Device Series
|
||||
* @version: V1.01
|
||||
* @date: 22. Jul. 2009
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (C) 2009 ARM Limited. All rights reserved.
|
||||
*
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_LPC17xx_H
|
||||
#define __SYSTEM_LPC17xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemFrequency variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC17xx_H */
|
||||
@@ -1,33 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* type.h: Type definition Header file for NXP LPC17xx Family
|
||||
* Microprocessors
|
||||
*
|
||||
* Copyright(C) 2009, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* History
|
||||
* 2009.05.25 ver 1.00 Prelimnary version, first Release
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef __TYPE_H__
|
||||
#define __TYPE_H__
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE (0)
|
||||
#endif
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE (1)
|
||||
#endif
|
||||
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
#endif /* __TYPE_H__ */
|
||||
Reference in New Issue
Block a user