[IFX]Add psoc6 bsp

2026-06-12 20:24:15 +08:00 · 2023-02-03 11:50:39 +08:00
parent 9fbf63441e
commit db5ed9c576
651 changed files with 85234 additions and 2567 deletions
@@ -52,6 +52,11 @@ jobs:
         - {RTT_BSP: "at91/at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062S2-43012", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062-BLE", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062s4", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8ckit-062-WIFI-BT", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-cy8cproto-062S3-4343W", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "Infineon/psoc6-evaluationkit-062S2", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "ft32/ft32f072xb-starter", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "n32/n32g43xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "n32/n32g45xcl-stb", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -8,6 +8,9 @@ PSOC6 系列 BSP 目前支持情况如下表所示：
 | [psoc6-cy8ckit-062S2-43012](psoc6-cy8ckit-062S2-43012)     | Infineon 官方 CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit 开发板 |
 | [psoc6-cy8cproto-062S3-4343W](psoc6-cy8cproto-062S3-4343W) | Infineon 官方 PSoC™ 62S3 Wi-Fi BT Prototyping Kit 开发板    |
 | [psoc6-evaluationkit-062S2](psoc6-evaluationkit-062S2)     | RT-Thread 联合 Infineon 推出的评估开发板                    |
+| [psoc6-cy8ckit-062-BLE](psoc6-cy8ckit-062-BLE)             | Infineon 官方 psoc6-cy8ckit-062-BLE 开发板                  |
+| [psoc6-cy8ckit-062-WIFI-BT](psoc6-cy8ckit-062-WIFI-BT)     | Infineon 官方 psoc6-cy8ckit-062-WIFI-BT 开发板              |
+| [psoc6-cy8ckit-062s4](psoc6-cy8ckit-062s4)                 | Infineon 官方 psoc6-cy8ckit-062s4 开发板                    |

 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

@@ -22,12 +22,12 @@
 static const struct pin_irq_map pin_irq_map[] =
 {
    {CYHAL_PORT_0,  ioss_interrupts_gpio_0_IRQn},
-#ifndef SOC_CY8C6245LQI_S3D72
+#if !defined(SOC_CY8C6245LQI_S3D72) && !defined(SOC_CY8C6244LQI_S4D92)
    {CYHAL_PORT_1,  ioss_interrupts_gpio_1_IRQn},
 #endif
    {CYHAL_PORT_2,  ioss_interrupts_gpio_2_IRQn},
    {CYHAL_PORT_3,  ioss_interrupts_gpio_3_IRQn},
-#ifndef SOC_CY8C6245LQI_S3D72
+#if !defined(SOC_CY8C6245LQI_S3D72) && !defined(SOC_CY8C6244LQI_S4D92)
    {CYHAL_PORT_4,  ioss_interrupts_gpio_4_IRQn},
 #endif
    {CYHAL_PORT_5,  ioss_interrupts_gpio_5_IRQn},
@@ -38,7 +38,7 @@ static const struct pin_irq_map pin_irq_map[] =
    {CYHAL_PORT_10,  ioss_interrupts_gpio_10_IRQn},
    {CYHAL_PORT_11,  ioss_interrupts_gpio_11_IRQn},
    {CYHAL_PORT_12,  ioss_interrupts_gpio_12_IRQn},
-#ifndef SOC_CY8C6245LQI_S3D72
+#if !defined(SOC_CY8C6245LQI_S3D72) && !defined(SOC_CY8C6244LQI_S4D92)
    {CYHAL_PORT_13,  ioss_interrupts_gpio_13_IRQn},
 #endif
    {CYHAL_PORT_14,  ioss_interrupts_gpio_14_IRQn},
@@ -20,12 +20,12 @@ extern "C"
 #endif

 #ifdef BSP_USING_UART0
-/* UART0 device driver structure */
-cy_stc_sysint_t UART0_SCB_IRQ_cfg =
-{
-    .intrSrc = (IRQn_Type) scb_0_interrupt_IRQn,
-    .intrPriority = (7u),
-};
+    /* UART0 device driver structure */
+    cy_stc_sysint_t UART0_SCB_IRQ_cfg =
+        {
+            .intrSrc = (IRQn_Type)scb_0_interrupt_IRQn,
+            .intrPriority = (7u),
+    };
 #endif
 #ifdef BSP_USING_UART1
    /* UART1 device driver structure */
@@ -102,6 +102,18 @@ cy_stc_sysint_t UART0_SCB_IRQ_cfg =

 #if defined(BSP_USING_UART2)
 #ifndef UART2_CONFIG
+#if defined(SOC_CY8C6244LQI_S4D92)
+#define UART2_CONFIG                            \
+    {                                           \
+        .name = "uart2",                        \
+        .tx_pin = P3_1,                         \
+        .rx_pin = P3_0,                         \
+        .usart_x = SCB2,                        \
+        .intrSrc = scb_2_interrupt_IRQn,        \
+        .userIsr = uart_isr_callback(uart2),    \
+        .UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
+    }
+#else
 #define UART2_CONFIG                            \
    {                                           \
        .name = "uart2",                        \
@@ -112,6 +124,7 @@ cy_stc_sysint_t UART0_SCB_IRQ_cfg =
        .userIsr = uart_isr_callback(uart2),    \
        .UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
    }
+#endif /* SOC_CY8C6244LQI_S4D92 */
    void uart2_isr_callback(void);
 #endif /* UART2_CONFIG */
 #endif /* BSP_USING_UART2 */
@@ -54,6 +54,29 @@ if GetDepend(['SOC_CY8C624ALQI_S2D42']):
    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_68_qfn.c']
    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')

+if GetDepend(['SOC_CY8C6247BZI_D54']):
+    src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_01.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
+    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+
+if GetDepend(['SOC_CY8C6347BZI_BLD53']):
+    src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_01.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_ble_clk.c']
+    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+
+if GetDepend(['SOC_CY8C6244LQI_S4D92']):
+    src += ['mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_04.c']
+    src += ['mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_68_qfn.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_ble_clk.c']
+    src += Glob('psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+
 if GetDepend(['RT_USING_SERIAL']):
    src += ['retarget-io/cy_retarget_io.c']
    src += ['mtb-hal-cat1/source/cyhal_uart.c']
@@ -149,6 +172,24 @@ if GetDepend(['SOC_CY8C624ALQI_S2D42']):
    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']

+if GetDepend(['SOC_CY8C6247BZI_D54']):
+    path += [cwd + '/psoc6cm0p']
+    path += [cwd + '/capsense']
+    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
+    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
+
+if GetDepend(['SOC_CY8C6347BZI_BLD53']):
+    path += [cwd + '/psoc6cm0p']
+    path += [cwd + '/capsense']
+    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
+    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
+
+if GetDepend(['SOC_CY8C6244LQI_S4D92']):
+    path += [cwd + '/psoc6cm0p']
+    path += [cwd + '/capsense']
+    path += [cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include']
+    path += [cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include']
+
 group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)

 Return('group')
@@ -1,181 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_dmas.c
-*
-* Description:
-* DMA configuration
-* This file was automatically generated and should not be modified.
-* Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.14850
-* personalities 6.0.0.0
-* udd 3.0.0.2024
-*
-********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_dmas.h"
-
-const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config =
-{
-    .retrigger = CY_DMA_RETRIG_4CYC,
-    .interruptType = CY_DMA_DESCR,
-    .triggerOutType = CY_DMA_1ELEMENT,
-    .channelState = CY_DMA_CHANNEL_ENABLED,
-    .triggerInType = CY_DMA_1ELEMENT,
-    .dataSize = CY_DMA_BYTE,
-    .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-    .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
-    .descriptorType = CY_DMA_SINGLE_TRANSFER,
-    .srcAddress = NULL,
-    .dstAddress = NULL,
-    .srcXincrement = 1,
-    .dstXincrement = 0,
-    .xCount = 1,
-    .srcYincrement = 1,
-    .dstYincrement = 1,
-    .yCount = 1,
-    .nextDescriptor = NULL,
-};
-cy_stc_dma_descriptor_t TxDma_Descriptor_0 =
-{
-    .ctl = 0UL,
-    .src = 0UL,
-    .dst = 0UL,
-    .xCtl = 0UL,
-    .yCtl = 0UL,
-    .nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t TxDma_channelConfig =
-{
-    .descriptor = &TxDma_Descriptor_0,
-    .preemptable = false,
-    .priority = 3,
-    .enable = false,
-    .bufferable = false,
-};
-const cy_stc_dma_crc_config_t TxDma_crcConfig =
-{
-    .dataReverse = false,
-    .dataXor = 0,
-    .reminderReverse = false,
-    .reminderXor = 0,
-    .polynomial = 79764919,
-};
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t TxDma_obj =
-    {
-        .type = CYHAL_RSC_DMA,
-        .block_num = 0U,
-        .channel_num = TxDma_CHANNEL,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config =
-{
-    .retrigger = CY_DMA_RETRIG_4CYC,
-    .interruptType = CY_DMA_1ELEMENT,
-    .triggerOutType = CY_DMA_1ELEMENT,
-    .channelState = CY_DMA_CHANNEL_ENABLED,
-    .triggerInType = CY_DMA_1ELEMENT,
-    .dataSize = CY_DMA_BYTE,
-    .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
-    .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-    .descriptorType = CY_DMA_SINGLE_TRANSFER,
-    .srcAddress = NULL,
-    .dstAddress = NULL,
-    .srcXincrement = 0,
-    .dstXincrement = 1,
-    .xCount = 1,
-    .srcYincrement = 1,
-    .dstYincrement = 1,
-    .yCount = 1,
-    .nextDescriptor = &RxDma_Descriptor_1,
-};
-const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config =
-{
-    .retrigger = CY_DMA_RETRIG_4CYC,
-    .interruptType = CY_DMA_DESCR,
-    .triggerOutType = CY_DMA_1ELEMENT,
-    .channelState = CY_DMA_CHANNEL_ENABLED,
-    .triggerInType = CY_DMA_1ELEMENT,
-    .dataSize = CY_DMA_BYTE,
-    .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
-    .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
-    .descriptorType = CY_DMA_SINGLE_TRANSFER,
-    .srcAddress = NULL,
-    .dstAddress = NULL,
-    .srcXincrement = 0,
-    .dstXincrement = 1,
-    .xCount = 1,
-    .srcYincrement = 1,
-    .dstYincrement = 1,
-    .yCount = 1,
-    .nextDescriptor = &RxDma_Descriptor_0,
-};
-cy_stc_dma_descriptor_t RxDma_Descriptor_0 =
-{
-    .ctl = 0UL,
-    .src = 0UL,
-    .dst = 0UL,
-    .xCtl = 0UL,
-    .yCtl = 0UL,
-    .nextPtr = 0UL,
-};
-cy_stc_dma_descriptor_t RxDma_Descriptor_1 =
-{
-    .ctl = 0UL,
-    .src = 0UL,
-    .dst = 0UL,
-    .xCtl = 0UL,
-    .yCtl = 0UL,
-    .nextPtr = 0UL,
-};
-const cy_stc_dma_channel_config_t RxDma_channelConfig =
-{
-    .descriptor = &RxDma_Descriptor_0,
-    .preemptable = false,
-    .priority = 3,
-    .enable = false,
-    .bufferable = false,
-};
-const cy_stc_dma_crc_config_t RxDma_crcConfig =
-{
-    .dataReverse = false,
-    .dataXor = 0,
-    .reminderReverse = false,
-    .reminderXor = 0,
-    .polynomial = 79764919,
-};
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t RxDma_obj =
-    {
-        .type = CYHAL_RSC_DMA,
-        .block_num = 0U,
-        .channel_num = RxDma_CHANNEL,
-    };
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_dmas(void)
-{
-#if defined (CY_USING_HAL)
-    cyhal_hwmgr_reserve(&TxDma_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-    cyhal_hwmgr_reserve(&RxDma_obj);
-#endif //defined (CY_USING_HAL)
-}
@@ -1,76 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_dmas.h
-*
-* Description:
-* DMA configuration
-* This file was automatically generated and should not be modified.
-* Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.14850
-* personalities 6.0.0.0
-* udd 3.0.0.2024
-*
-********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_DMAS_H)
-#define CYCFG_DMAS_H
-
-#include "cycfg_notices.h"
-#include "cy_dma.h"
-#if defined (CY_USING_HAL)
-    #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define TxDma_ENABLED 1U
-#define TxDma_HW DW0
-#define TxDma_CHANNEL 26U
-#define TxDma_IRQ cpuss_interrupts_dw0_26_IRQn
-#define RxDma_ENABLED 1U
-#define RxDma_HW DW0
-#define RxDma_CHANNEL 27U
-#define RxDma_IRQ cpuss_interrupts_dw0_27_IRQn
-
-extern const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config;
-extern cy_stc_dma_descriptor_t TxDma_Descriptor_0;
-extern const cy_stc_dma_channel_config_t TxDma_channelConfig;
-extern const cy_stc_dma_crc_config_t TxDma_crcConfig;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t TxDma_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config;
-extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config;
-extern cy_stc_dma_descriptor_t RxDma_Descriptor_0;
-extern cy_stc_dma_descriptor_t RxDma_Descriptor_1;
-extern const cy_stc_dma_channel_config_t RxDma_channelConfig;
-extern const cy_stc_dma_crc_config_t RxDma_crcConfig;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t RxDma_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_dmas(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_DMAS_H */
@@ -1,66 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_peripherals.c
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
-* personalities 6.0.0.0
-* udd 3.0.0.1974
-*
-********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-#include <rtthread.h>
-
-#include "cycfg_peripherals.h"
-
-cy_stc_csd_context_t cy_csd_0_context =
-{
-    .lockKey = CY_CSD_NONE_KEY,
-};
-
-void init_cycfg_peripherals(void)
-{
-    Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-
-#ifdef BSP_USING_UART0
-    /* UART0 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART1
-    /* UART1 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART2
-    /* UART2 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#if defined(BSP_USING_UART3) || defined(BSP_USING_HW_I2C3)
-    /* UART3 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART4
-    /* UART4 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART5
-    /* UART5 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-}
@@ -1,20 +0,0 @@
-[Device=CY8C624ABZI-S2D44]
-
-[Blocks]
-# WIFI
-# CYBSP_WIFI_SDIO
-sdhc[0]
-# CYBSP_WIFI_SDIO_D0
-ioss[0].port[2].pin[0]
-# CYBSP_WIFI_SDIO_D1
-ioss[0].port[2].pin[1]
-# CYBSP_WIFI_SDIO_D2
-ioss[0].port[2].pin[2]
-# CYBSP_WIFI_SDIO_D3
-ioss[0].port[2].pin[3]
-# CYBSP_WIFI_SDIO_CMD
-ioss[0].port[2].pin[4]
-# CYBSP_WIFI_SDIO_CLK
-ioss[0].port[2].pin[5]
-# CYBSP_WIFI_WL_REG_ON
-ioss[0].port[2].pin[6]
@@ -1,7 +0,0 @@
-capsense
-core-lib
-core-make
-mtb-hal-cat1
-mtb-pdl-cat1
-psoc6cm0p
-recipe-make-cat1a
@@ -1,7 +0,0 @@
-capsense
-core-lib
-core-make
-mtb-hal-cat1
-mtb-pdl-cat1
-psoc6cm0p
-recipe-make-cat1a
@@ -1,7 +0,0 @@
-capsense
-core-lib
-core-make
-mtb-hal-cat1
-mtb-pdl-cat1
-psoc6cm0p
-recipe-make-cat1a
@@ -1 +0,0 @@
-<version>3.1.0.27308</version>
@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>project</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>com.cypress.studio.app.cymodusnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1283879096433011140" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>
@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1
@@ -0,0 +1,20 @@
+#RT-Thread Studio Project Configuration
+#Thu Feb 02 15:45:05 CST 2023
+project_type=rt-thread
+chip_name=CY8C6347BZI_BLD53
+os_branch=full
+example_name=
+os_version=latest
+selected_rtt_version=latest
+cfg_version=v3.0
+board_base_nano_proj=False
+is_use_scons_build=True
+output_project_path=C\:\\Users\\Qianchen\\Downloads\\rt-thread-master\\rt-thread-master\\bsp\\Infineon\\psoc6-cy8ckit-062-BLE\\dist
+project_base_bsp=true
+hardware_adapter=KitProg3
+project_name=1111
+is_base_example_project=False
+board_name=psoc6-cy8ckit-062S2-43012
+device_vendor=Infineon 
+bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0
+bsp_version=1.0.0
@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.adapterName" value="DAP-LINK"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.binFlashStartAddress" value=""/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="12000000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerDeviceName" value="cy8c64xA_cm4"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="E:\software\RT-ThreadStudio\repo\Extract\Debugger_Support_Packages\openocd\bin\openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.programMode" value="HEX"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU PyOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/dist_ide_project"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-infineon_debugger_relative_path}/bin/openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s ../scripts -f interface/kitprog3.cfg -f target/psoc6.cfg -c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot; -c &quot;gdb_port 3332&quot; -c &quot;psoc6 sflash_restrictions 1&quot; -c &quot;init; reset init&quot;"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon psoc6 reset_halt sysresetreq&#13;&#10;flushregs&#13;&#10;mon gdb_sync&#13;&#10;stepi"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="entry"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/project"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
@@ -0,0 +1,210 @@
+CYPRESS END USER LICENSE AGREEMENT
+
+PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
+DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING
+DOCUMENTATION.  BY DOWNLOADING, INSTALLING, COPYING OR USING THE SOFTWARE,
+YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT.  IF YOU DO NOT AGREE TO ALL
+OF THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN AND DO NOT USE THE SOFTWARE.
+IF YOU HAVE PURCHASED THIS LICENSE TO THE SOFTWARE, YOUR RIGHT TO RETURN THE
+SOFTWARE EXPIRES 30 DAYS AFTER YOUR PURCHASE AND APPLIES ONLY TO THE ORIGINAL
+PURCHASER.
+
+1. Definitions.
+
+    "Software" means this software and any accompanying documentation,
+      including any upgrades, updates, bug fixes or modified versions provided
+      to you by Cypress.
+
+    "Source Code" means software in human-readable form.
+
+    "Binary Code" means the software in binary code form such as object code or
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+
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+
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+
+    "inf File" means a hardware setup information file (.inf file) created by
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+      the driver for a Cypress hardware product.
+
+2. License.  Subject to the terms and conditions of this Agreement, Cypress
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+
+    a. to use the Development Tools in object code form solely for the purpose
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+
+    b. (i) if provided in Source Code form, to copy, modify, and compile the
+           Firmware Source Code to create Firmware for execution on a Cypress
+           hardware product, and
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+
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+
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+
+7. Compliance With Law.  Each party agrees to comply with all applicable laws,
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+
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+Cypress product may reasonably be expected to result in significant property
+damage, injury or death ("High Risk Product").  If you include any Software or
+Cypress product in a High Risk Product, you assume all risk of such use and
+agree to indemnify Cypress and its suppliers against all liability.  No
+computing device can be absolutely secure.  Therefore, despite security
+measures implemented in Cypress hardware or software products, Cypress does
+not assume any liability arising out of any security breach, such as
+unauthorized access to or use of a Cypress product.
+
+9. Limitation of Liability.  TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE
+LAW, IN NO EVENT WILL CYPRESS OR ITS SUPPLIERS, RESELLERS, OR DISTRIBUTORS BE
+LIABLE FOR ANY LOST REVENUE, PROFIT, OR DATA, OR FOR SPECIAL, INDIRECT,
+CONSEQUENTIAL, INCIDENTAL, OR PUNITIVE DAMAGES HOWEVER CAUSED AND REGARDLESS
+OF THE THEORY OF LIABILITY, ARISING OUT OF OR RELATED TO THE USE OF OR
+INABILITY TO USE THE SOFTWARE EVEN IF CYPRESS OR ITS SUPPLIERS, RESELLERS, OR
+DISTRIBUTORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.  IN NO
+EVENT SHALL CYPRESS' OR ITS SUPPLIERS', RESELLERS', OR DISTRIBUTORS' TOTAL
+LIABILITY TO YOU, WHETHER IN CONTRACT, TORT (INCLUDING NEGLIGENCE), OR
+OTHERWISE, EXCEED THE GREATER OF US$500 OR THE PRICE PAID BY YOU FOR THE
+SOFTWARE.  THE FOREGOING LIMITATIONS SHALL APPLY EVEN IF THE ABOVE-STATED
+WARRANTY FAILS OF ITS ESSENTIAL PURPOSE.  BECAUSE SOME STATES OR JURISDICTIONS
+DO NOT ALLOW LIMITATION OR EXCLUSION OF CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ALL OR PORTIONS OF THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+
+10. Restricted Rights.  The Software is commercial computer software as that
+term is described in 48 C.F.R. 252.227-7014(a)(1).  If the Software is being
+acquired by or on behalf of the U.S. Government or by a U.S. Government prime
+contractor or subcontractor (at any tier), then the Government's rights in
+Software shall be only those set forth in this Agreement.
+
+11. Personal Information.  You agree that information you provide through your
+registration on Cypress IoT Community Forum or other Cypress websites,
+including contact information or other personal information, may be collected
+and used by Cypress consistent with its Data Privacy Policy
+(www.cypress.com/privacy-policy), as updated or revised from time to time, and
+may be provided to its third party sales representatives, distributors and
+other entities conducting sales activities for Cypress for sales-related and
+other business purposes.
+
+12. General.  This Agreement will bind and inure to the benefit of each
+party's successors and assigns, provided that you may not assign or transfer
+this Agreement, in whole or in part, without Cypress' written consent.  This
+Agreement shall be governed by and construed in accordance with the laws of
+the State of California, United States of America, as if performed wholly
+within the state and without giving effect to the principles of conflict of
+law.  The parties consent to personal and exclusive jurisdiction of and venue
+in, the state and federal courts within Santa Clara County, California;
+provided however, that nothing in this Agreement will limit Cypress' right to
+bring legal action in any venue in order to protect or enforce its
+intellectual property rights.  No failure of either party to exercise or
+enforce any of its rights under this Agreement will act as a waiver of such
+rights.  If any portion of this Agreement is found to be void or
+unenforceable, the remaining provisions of this Agreement shall remain in full
+force and effect.  This Agreement is the complete and exclusive agreement
+between the parties with respect to the subject matter hereof, superseding and
+replacing any and all prior agreements, communications, and understandings
+(both written and oral) regarding such subject matter.  Any notice to Cypress
+will be deemed effective when actually received and must be sent to Cypress
+Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San
+Jose, CA 95134 USA.
@@ -0,0 +1,104 @@
+# Infineon Psoc6-CY8ckit-062-BLE 说明
+
+## 简介
+
+本文档为 `RT-Thread` 为 ` Psoc6-CY8ckit-062-BLE`开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 `RT-Thread` 驱动更多板载资源。
+
+## 开发板介绍
+
+` Psoc6-CY8ckit-062-BLE` 是英飞凌推出的一款32位双核CPU子系统（ ARM Cortex-M4 和 ARM Cortex-M0）的开发板，具有单周期乘法的150-MHz Arm Cortex-M4F CPU (浮点和存储器保护单元)，100-MHz Cortex M0+ CPU，带单周期乘法和MPU，可以充分发挥 PSoC6 双核芯片性能。
+
+开发板外观详细信息：[CY8CKIT-062-BLE - Infineon Technologies](https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062-ble/)
+
+该开发板核心 **板载资源** 如下：
+
+- MCU：CY8C6347BZI_BLD53，Cortex-M4主频 150MHz，Cortex-M0主频 100MHz，1MB Flash 和 288KB SRAM
+	    MCU手册更多详细信息请参考文档 [PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet (infineon.com)](https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C62X8_CY8C62XA-DataSheet-v17_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee7d03a70b1)
+- 开发环境：ModusToolbox 2.0/MDK V5
+  	PSoC® Creator™ 下载链接 [ModusToolbox™ Software - Infineon Technologies](https://www.infineon.com/cms/en/design-support/tools/sdk/modustoolbox-software/)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+| :----------: | :----------: | :------: |
+|  USB 转串口  |     支持     |  UART5   |
+|     GPIO     |     支持     |    —     |
+|     UART     |     支持     | UART0-5  |
+
+## 快速上手
+
+本 BSP 是以 `MDK V5` 和 `RT-Thread Studio` 为开发环境（编译器：ARMClang / GCC），接下来介绍如何将系统运行起来。
+
+### 使用 MDK V5 开发
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC。
+
+#### 编译下载
+
+1、配置工程：
+
+首先打开 MDK ，若没有安装 `Infineon-PSoC6` 的芯片支持包会提示在线安装，根据提示安装即可。若受网络问题，可以进入 [keil](https://www.keil.com/dd2/pack) 官网下载安装包，离线安装。
+
+![mdk_package](./figures/mdk_package.png)
+
+2、 编译此工程：在安装好芯片支持包后，在 `MDK`工程中进行编译。
+
+3、下载此工程：
+
+工程默认配置使用板载 `DAP-LINK` 使用 `SWD` 方式下载程序，使用数据线连接开发板，编译之后直接点击下载按钮即可。
+
+### 使用 RT-Thread Studio 开发
+
+#### 导入工程
+
+* 首先打开  `RT-Thread Studio` 开发工具，点加左上角文件—>导入—> RT-Thread Studio项目到工作空间中。
+
+![](./figures/studio1.png)
+
+* 接着选择 `Psoc6-CY8ckit-062-BLE` 开发板支持包的目录，进行导入。
+
+![](./figures/studio2.png)
+
+#### 编译下载
+
+* 点击 IDE 左上角的构建选项进行工程的编译。
+
+![](./figures/studio3-build.png)
+
+* 当编译无错误警告时，点击 `Debug` 或 `Download` 选项进行调试/下载。
+
+  注：若点击下载并下载成功后串口终端无显示信息，请手动按下复位按键进行重启运行。
+
+  ![](./figures/studio4-download.png)
+
+## 运行结果
+
+下载程序成功之后，系统会自动运行。打开终端工具串口助手，选择波特率为 115200。复位设备后，LED 将会以 500HZ 的频率闪烁，而且在终端上可以看到 `RT-Thread` 的输出信息：
+
+注：推荐使用串口调试助手如：`MobaXterm`
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.1.1 build Jul 25 2022 18:03:35
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+
+## 联系人
+
+维护人:
+
+- [Rbb666](https://github.com/Rbb666)
@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,60 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+IFX_library = 'IFX_PSOC6_HAL'
+rtconfig.BSP_LIBRARY_TYPE = IFX_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, IFX_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,16 @@
+import rtconfig
+from building import *
+import os
+
+cwd  = GetCurrentDir()
+path = [cwd]
+src  = Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "drv_gpio.h"
+
+#define LED_PIN     GET_PIN(13, 7)
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    for (;;)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
@@ -0,0 +1,253 @@
+menu "Hardware Drivers Config"
+
+config SOC_CY8C6347BZI_BLD53
+    bool
+    select SOC_SERIES_IFX_PSOC63
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_USB_TO_USART
+        bool "Enable USB TO USART (uart5)"
+        select BSP_USING_UART
+        select BSP_USING_UART5
+        default y
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+            config BSP_USING_UART5
+                bool "Enable UART5"
+                default y
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+        menuconfig BSP_USING_PWM0
+            bool "Enable timer0 output pwm"
+            default n
+            if BSP_USING_PWM0
+                menuconfig BSP_USING_PWM0_CH3
+                    bool "Enable PWM0 channel3"
+                    default n
+                    if BSP_USING_PWM0_CH3
+                        config BSP_USING_PWM0_PORT13
+                        bool "Enable PWM0-PORT13 output pwm"
+                        default n
+                    endif
+                menuconfig BSP_USING_PWM0_CH7
+                    bool "Enable PWM0 channel7"
+                    default n
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT2
+                        bool "Enable PWM0-PORT2 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT5
+                        bool "Enable PWM0-PORT5 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT7
+                        bool "Enable PWM0-PORT7 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT9
+                        bool "Enable PWM0-PORT9 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT10
+                        bool "Enable PWM0-PORT10 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT12
+                        bool "Enable PWM0-PORT12 output pwm"
+                        default n
+                    endif
+            endif
+        endif
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        select RT_USING_SPI
+        default n
+        if BSP_USING_SPI
+            menuconfig BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_USING_SPI3_SAMPLE
+                        bool "Enable SPI3 BUS Sample"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+        endif
+
+    config BSP_USING_SDMMC
+        bool "Enable SDMMC (sd card)"
+        default n
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        if BSP_USING_SDMMC
+            config BSP_USING_SDIO1
+                bool "Enable SDIO1 (sd card)"
+                default n
+        endif
+
+    menuconfig BSP_USING_HW_I2C
+        bool "Enable Hardware I2C Bus"
+        default n
+        select RT_USING_I2C
+        select RT_USING_PIN
+        if BSP_USING_HW_I2C
+            config BSP_USING_HW_I2C3
+                bool "Enable I2C3 Bus (User I2C)"
+                default n
+                if BSP_USING_HW_I2C3
+                    comment "Notice: P6_0 --> 48; P6_1 --> 49"
+                    config BSP_I2C3_SCL_PIN
+                        int "i2c3 SCL pin number"
+                        range 1 113
+                        default 48
+                    config BSP_I2C3_SDA_PIN
+                        int "i2c3 SDA pin number"
+                        range 1 113
+                        default 49
+                endif
+            config BSP_USING_HW_I2C6
+                bool "Enable I2C6 Bus (User I2C)"
+                default n
+                if BSP_USING_HW_I2C6
+                    comment "Notice: P13_0 --> 48; P13_1 --> 49"
+                    config BSP_I2C6_SCL_PIN
+                        int "i2c6 SCL pin number"
+                        range 1 113
+                        default 104
+                    config BSP_I2C6_SDA_PIN
+                        int "i2c6 SDA pin number"
+                        range 1 113
+                        default 105
+                endif
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable Software I2C Bus"
+        default n
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        if BSP_USING_I2C
+            config BSP_USING_I2C1
+                bool "Enable I2C1 Bus (User I2C)"
+                default n
+                if BSP_USING_I2C1
+                    comment "Notice: P13_1 --> 105; P13_2 --> 106"
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 SCL pin number"
+                        range 1 113
+                        default 105
+                    config BSP_I2C1_SDA_PIN
+                        int "i2c1 SDA pin number"
+                        range 1 113
+                        default 106
+                endif
+        endif
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        if BSP_USING_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_LSE
+
+                config BSP_RTC_USING_LSE
+                    bool "RTC USING LSE"
+
+                config BSP_RTC_USING_LSI
+                    bool "RTC USING LSI"
+            endchoice
+        endif
+
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        default n
+        select RT_USING_DAC
+        if BSP_USING_DAC
+            config BSP_USING_DAC1
+                bool "Enable DAC1"
+                default n
+            config BSP_USING_DAC2
+                bool "Enable DAC2"
+                default n
+        endif
+
+    menuconfig BSP_USING_TIM
+        bool "Enable timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TIM
+            config BSP_USING_TIM1
+                bool "Enable TIM1"
+                default n
+            config BSP_USING_TIM2
+                bool "Enable TIM2"
+                default n
+        endif
+endmenu
+
+endmenu
@@ -0,0 +1,40 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+objs = []
+cwd = GetCurrentDir()
+list = os.listdir(cwd)
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+if GetDepend(['BSP_USING_SPI3_SAMPLE']):
+    src += Glob('ports/spi_sample.c')
+
+if GetDepend(['BSP_USING_RW007']):
+    src += Glob('ports/drv_rw007.c')
+
+if GetDepend(['BSP_USING_SLIDER']):
+    src += Glob('ports/slider_sample.c')
+
+path = [cwd]
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S']
+elif rtconfig.PLATFORM in ['armclang']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S']
+
+CPPDEFINES = ['CY8C6347BZI_BLD53', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
+group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
+
+Return('group')
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include "board.h"
+
+void cy_bsp_all_init(void)
+{
+    cy_rslt_t result;
+
+    /* Initialize the device and board peripherals */
+    result = cybsp_init();
+
+    /* Board init failed. Stop program execution */
+    if (result != CY_RSLT_SUCCESS)
+    {
+        CY_ASSERT(0);
+    }
+}
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ * 2022-07-26     Rbb666       Add Flash Config
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#include "cyhal.h"
+#include "cybsp.h"
+
+#ifdef BSP_USING_USBD
+    #include "cy_usb_dev.h"
+    #include "cy_usb_dev_hid.h"
+    #include "cycfg_usbdev.h"
+#endif
+
+/*SRAM CONFIG*/
+#define IFX_SRAM_SIZE                   (277)
+#define IFX_SRAM_END                    (0x08002000 + IFX_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+    #define HEAP_END        IFX_SRAM_END
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN    (__segment_end("HEAP"))
+#else
+    extern unsigned int __end__;
+    extern unsigned int __HeapLimit;
+    #define HEAP_BEGIN    (void*)&__end__
+    #define HEAP_END      (void*)&__HeapLimit
+#endif
+
+void cy_bsp_all_init(void);
+
+#endif
+
@@ -1,247 +1,247 @@
-/*******************************************************************************
-* \file cy8c6xxa_cm4_dual.icf
-* \version 2.91
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
-
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = 0x1000;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
- * More about CM0+ prebuilt images, see here:
- * https://github.com/cypresssemiconductorco/psoc6cm0p
- */
-/* The size of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE  = 0x2000;
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
-define block RO     {first section .intvec, readonly};
-
-define block cy_xip { section .cy_xip };
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application image */
-place at start of IROM1_region  { block CM0P_RO };
-
-/* Flash - Cortex-M4 application */
-place in          IROM1_region  { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-"cy_xip" : place at start of EROM1_region  { block cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in          IRAM1_region  { readwrite };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_m0p_image,
-        section .cy_app_signature,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x00200000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */
+/*******************************************************************************
+* \file cy8c6xx7_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x100FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00100000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */
@@ -1,5 +1,5 @@
 /***************************************************************************//**
-* \file cy8c6xxa_cm4_dual.ld
+* \file cy8c6xx7_cm4_dual.ld
 * \version 2.91
 *
 * Linker file for the GNU C compiler.
@@ -70,8 +70,8 @@ MEMORY
     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
     */
-    ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0xFD800
-    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x200000
+    ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0x45800
+    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x100000

    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
     * You can assign sections to this memory region for only one of the cores.
@@ -176,6 +176,35 @@ SECTIONS
        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)

        KEEP(*(.eh_frame*))
+        
+		/* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
    } > flash


@@ -195,7 +224,7 @@ SECTIONS

    /* To copy multiple ROM to RAM sections,
     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
+     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
    .copy.table :
    {
        . = ALIGN(4);
@@ -213,33 +242,11 @@ SECTIONS

        __copy_table_end__ = .;
    } > flash
-	/* setction information for finsh shell begin */
-    FSymTab : 
-    {
-        . = ALIGN(4);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-    } > flash
-    VSymTab : 
-    {
-        . = ALIGN(4);
-         __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-    } > flash
-    rti_fn : 
-    {
-        . = ALIGN(4);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-    } > flash
-    /* setction information for finsh shell end */
+

    /* To clear multiple BSS sections,
     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
    .zero.table :
    {
        . = ALIGN(4);
@@ -439,7 +446,7 @@ SECTIONS
 /* The following symbols used by the cymcuelftool. */
 /* Flash */
 __cy_memory_0_start    = 0x10000000;
-__cy_memory_0_length   = 0x00200000;
+__cy_memory_0_length   = 0x00100000;
 __cy_memory_0_row_size = 0x200;

 /* Emulated EEPROM Flash area */
@@ -0,0 +1,67 @@
+#include <rtthread.h>
+#include <rtdbg.h>
+#ifdef BSP_USING_RW007
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <board.h>
+#include <spi_wifi_rw007.h>
+
+extern void spi_wifi_isr(int vector);
+
+static void rw007_gpio_init(void)
+{
+    /* Configure IO */
+    rt_pin_mode(IFX_RW007_RST_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
+
+    /* Reset rw007 and config mode */
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_HIGH);
+
+    /* Wait rw007 ready(exit busy stat) */
+    while (!rt_pin_read(IFX_RW007_INT_BUSY_PIN))
+    {
+        rt_thread_delay(5);
+    }
+
+    rt_thread_delay(rt_tick_from_millisecond(200));
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+}
+
+static struct rt_spi_device rw007_dev;
+
+int wifi_spi_device_init(void)
+{
+    char sn_version[32];
+    uint32_t cs_pin = IFX_RW007_CS_PIN;
+
+    rw007_gpio_init();
+    rt_hw_spi_device_attach(IFX_RW007_SPI_BUS_NAME, "wspi", cs_pin);
+    rt_hw_wifi_init("wspi");
+
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+
+    rw007_sn_get(sn_version);
+    rt_kprintf("\nrw007  sn: [%s]\n", sn_version);
+    rw007_version_get(sn_version);
+    rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
+
+    return 0;
+}
+INIT_APP_EXPORT(wifi_spi_device_init);
+
+static void int_wifi_irq(void *p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_attach_irq(IFX_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(IFX_RW007_INT_BUSY_PIN, RT_TRUE);
+}
+
+#endif /* BSP_USING_RW007 */
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-27     Rbb666       first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev ifx_onchip_flash_32k;
+extern const struct fal_flash_dev ifx_onchip_flash_256k;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE         \
+    {                               \
+        &ifx_onchip_flash_32k,      \
+        &ifx_onchip_flash_256k,     \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                  \
+    {                                                                                   \
+        {FAL_PART_MAGIC_WROD, "param", "onchip_flash_32k", 0, IFX_EFLASH_SIZE, 0},      \
+        {FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0, IFX_FLASH_SIZE, 0},        \
+    }
+
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-28     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "drv_common.h"
+
+#ifdef BSP_USING_SLIDER
+#include "cycfg_capsense.h"
+
+#define CAPSENSE_INTR_PRIORITY      (7u)
+#define EZI2C_INTR_PRIORITY         (6u)
+
+/* Allowed duty cycle for maximum brightness */
+#define LED_MAX_BRIGHTNESS      (100u)
+
+/* Allowed duty cycle for minimum brightness*/
+#define LED_MIN_BRIGHTNESS      (0u)
+
+#define GET_DUTY_CYCLE(x)       (1 * 1000 * 1000 - x * 10 * 1000)
+
+typedef enum
+{
+    LED_OFF,
+    LED_ON
+} led_state_t;
+
+typedef struct
+{
+    led_state_t state;
+    uint32_t brightness;
+} led_data_t;
+
+static rt_sem_t trans_done_semphr = RT_NULL;
+
+#ifndef RT_USING_PWM
+    #error You need enable PWM to use this sample
+#else
+    #define PWM_DEV_NAME "pwm0"
+    #define PWM_DEV_CHANNEL 3
+    static struct rt_device_pwm *pwm_dev;
+#endif
+
+static void capsense_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    Cy_CapSense_InterruptHandler(CYBSP_CSD_HW, &cy_capsense_context);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void capsense_callback(cy_stc_active_scan_sns_t *ptrActiveScan)
+{
+    rt_sem_release(trans_done_semphr);
+}
+
+static uint32_t initialize_capsense(void)
+{
+    uint32_t status = CYRET_SUCCESS;
+
+    /* CapSense interrupt configuration parameters */
+    static const cy_stc_sysint_t capSense_intr_config =
+    {
+        .intrSrc = csd_interrupt_IRQn,
+        .intrPriority = CAPSENSE_INTR_PRIORITY,
+    };
+
+    /* Capture the CSD HW block and initialize it to the default state. */
+    status = Cy_CapSense_Init(&cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    /* Initialize CapSense interrupt */
+    cyhal_system_set_isr(csd_interrupt_IRQn, csd_interrupt_IRQn, CAPSENSE_INTR_PRIORITY, &capsense_isr);
+    NVIC_ClearPendingIRQ(capSense_intr_config.intrSrc);
+    NVIC_EnableIRQ(capSense_intr_config.intrSrc);
+
+    /* Initialize the CapSense firmware modules. */
+    status = Cy_CapSense_Enable(&cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    /* Assign a callback function to indicate end of CapSense scan. */
+    status = Cy_CapSense_RegisterCallback(CY_CAPSENSE_END_OF_SCAN_E,
+                                          capsense_callback, &cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    return status;
+}
+
+void Slider_Init(void)
+{
+    cy_rslt_t result;
+
+    result = initialize_capsense();
+
+    if (CYRET_SUCCESS != result)
+    {
+        /* Halt the CPU if CapSense initialization failed */
+        RT_ASSERT(0);
+    }
+
+    /* Initiate first scan */
+    Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
+
+    trans_done_semphr = rt_sem_create("slider_sem", 1, RT_IPC_FLAG_PRIO);
+    if (trans_done_semphr == RT_NULL)
+    {
+        rt_kprintf("create transform done semphr failed.\n");
+        RT_ASSERT(0);
+        return;
+    }
+
+#ifdef BSP_USING_PWM0_PORT13
+    /* Initiate PWM*/
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
+
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("PWM init failed! can't find %s device!\n", PWM_DEV_NAME);
+        RT_ASSERT(0);
+    }
+
+    /*default   period:1ms    pulse:0*/
+    rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, 1 * 1000 * 1000);
+    rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
+#endif
+}
+
+void update_led_state(led_data_t *ledData)
+{
+    if (ledData->brightness >= 0)
+    {
+        uint32_t brightness = (ledData->brightness < LED_MIN_BRIGHTNESS) ? LED_MIN_BRIGHTNESS : ledData->brightness;
+
+        /* Drive the LED with brightness */
+        rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, GET_DUTY_CYCLE(brightness));
+    }
+}
+
+static void process_touch(void)
+{
+    cy_stc_capsense_touch_t *slider_touch_info;
+    uint16_t slider_pos;
+    uint8_t slider_touch_status;
+    bool led_update_req = false;
+
+    static uint16_t slider_pos_prev;
+    static led_data_t led_data = {LED_ON, LED_MAX_BRIGHTNESS};
+
+    /* Get slider status */
+    slider_touch_info = Cy_CapSense_GetTouchInfo(
+                            CY_CAPSENSE_LINEARSLIDER0_WDGT_ID, &cy_capsense_context);
+    slider_touch_status = slider_touch_info->numPosition;
+    slider_pos = slider_touch_info->ptrPosition->x;
+
+    /* Detect the new touch on slider */
+    if ((RT_NULL != slider_touch_status) &&
+            (slider_pos != slider_pos_prev))
+    {
+        led_data.brightness = (slider_pos * 100)
+                              / cy_capsense_context.ptrWdConfig[CY_CAPSENSE_LINEARSLIDER0_WDGT_ID].xResolution;
+
+        led_update_req = true;
+    }
+
+#ifndef RT_USING_PWM
+#error You need enable PWM to use this sample
+#else
+    /* Update the LED state if requested */
+    if (led_update_req)
+    {
+        update_led_state(&led_data);
+    }
+#endif
+    slider_pos_prev = slider_pos;
+}
+
+static void Slider_thread_entry(void *parameter)
+{
+    Slider_Init();
+
+    for (;;)
+    {
+        rt_sem_take(trans_done_semphr, RT_WAITING_FOREVER);
+
+        /* Process all widgets */
+        Cy_CapSense_ProcessAllWidgets(&cy_capsense_context);
+
+        /* Process touch input */
+        process_touch();
+
+        /* Establishes synchronized operation between the CapSense
+         * middleware and the CapSense Tuner tool.
+         */
+        Cy_CapSense_RunTuner(&cy_capsense_context);
+
+        /* Initiate next scan */
+        Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
+
+        rt_thread_mdelay(50);
+    }
+}
+
+int Slider_ctrl_sample(void)
+{
+    rt_err_t ret = RT_EOK;
+
+    rt_thread_t thread = rt_thread_create("slider_th",
+                                          Slider_thread_entry,
+                                          RT_NULL,
+                                          1024,
+                                          25,
+                                          10);
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        ret = RT_ERROR;
+    }
+
+    return ret;
+}
+MSH_CMD_EXPORT(Slider_ctrl_sample, Slider sample to ctrl led);
+#endif
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-19     Rbbb666      first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_SPI3_SAMPLE)
+#include <drv_spi.h>
+
+#define SPI_NAME     "spi30"
+static struct rt_spi_device *spi_dev = RT_NULL;
+
+/* attach spi5 device */
+static int rt_spi_device_init(void)
+{
+    struct rt_spi_configuration cfg;
+
+    rt_hw_spi_device_attach("spi3", "spi30", NULL);
+
+    cfg.data_width = 8;
+    cfg.mode   = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS;
+    cfg.max_hz = 1 *1000 *1000;
+
+    spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
+
+    if (RT_NULL == spi_dev)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
+        return RT_ERROR;
+    }
+
+    rt_spi_configure(spi_dev, &cfg);
+
+    return RT_EOK;
+}
+INIT_APP_EXPORT(rt_spi_device_init);
+
+/* spi5 loopback mode test case */
+static int spi_sample(int argc, char **argv)
+{
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
+    static struct rt_spi_message msg1;
+
+    if (argc != 9)
+    {
+        rt_kprintf("Please Usage:\n");
+        rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
+        return -RT_ERROR;
+    }
+
+    for (i = 0; i < 8; i++)
+    {
+        t_buf[i] = atoi(argv[i+1]);
+    }
+
+    msg1.send_buf   = &t_buf;
+    msg1.recv_buf   = &r_buf;
+    msg1.length     = sizeof(t_buf);
+    msg1.cs_take    = 1;
+    msg1.cs_release = 0;
+    msg1.next       = RT_NULL;
+
+    rt_spi_transfer_message(spi_dev, &msg1);
+
+    rt_kprintf("spi rbuf : ");
+    for (i = 0; i < sizeof(t_buf); i++)
+    {
+        rt_kprintf("%x ", r_buf[i]);
+    }
+
+    rt_kprintf("\nspi loopback mode test over!\n");
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(spi_sample, spi loopback test);
+
+#endif /* BSP_USING_SPI3 */
@@ -0,0 +1,26 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    src += Glob(cwd + '/TARGET_CY8CKIT-062-BLE/*.c')
+    src += Glob(cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/*.c')
+    src += Glob(cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/*.c')
+
+    CPPPATH = [ cwd + '/TARGET_CY8CKIT-062-BLE',
+                cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+    if rtconfig.PLATFORM in ['gcc']:
+        src += [cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S']
+    elif rtconfig.PLATFORM in ['armclang']:
+        src += [cwd + '/TARGET_CY8CKIT-062-BLE/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S']
+
+group = DefineGroup('libs', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
@@ -0,0 +1 @@
+docs
@@ -4,13 +4,13 @@
 * Description:
 * Wrapper function to initialize all generated code.
 * This file was automatically generated and should not be modified.
-* Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
-* personalities 6.0.0.0
-* udd 3.0.0.1974
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -0,0 +1,52 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5721
+* mtb-pdl-cat1 3.0.0.10651
+* personalities 5.0.0.0
+* udd 3.0.0.1377
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */
--- a/Show More
+++ b/Show More