[BSP] Support YD-CH32V307VCT6 (#8473)

bsp/wch/risc-v/yd-ch32v307vct6/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../Libraries/Kconfig"
+source "board/Kconfig"

bsp/wch/risc-v/yd-ch32v307vct6/README.md

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+# YD-CH32V307VCT6 BSP Introduction
+
+## 1 Introduction
+
+YD-CH32V307VCT6 is a RISC-V core-based development board with a maximum main frequency of 144Mhz. It delivers the best value for developers to try and get started with RISC-V architecture.
+
+This document records the execution instruction of the BSP (board support package) provided by the RT-Thread community for the CH32V307V-R1 development board.
+
+The document is covered in three parts:
+
+- Board Resources Introduction
+- Compiling
+- Quickly Get Started
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board.
+
+![board](./figures/VCC-GND-Studio-CH32V307-RISC-V-Ethernet-board.jpg)
+
+**Features**
+
+- MCU: CH32V307VCT6, main frequency 144MHz，FLASH and RAM are available for configuration.
+- LED: 2, user LEDs (blue and red).
+- Button: 3, Reset, Boot, User.
+- SPI Flash: 32M-bit serial flash memory (W25Q32).
+- I2C EEPROM: 64k-bit serial EEPROM (24C64).
+- USB: 2, Type-C.
+- Network Port: 1, 10M PHY inside.
+- SDIO: microSD connector.
+- Debug interface: SWD.
+- 8 MHz external quartz oscillator (HSE).
+- 32,768 Hz external RTC quartz oscillator (LSE).
+
+For more details about this board, please refer to: 
+- [Board YD-CH32V307VCT6 VCC-GND Studio](http://152.32.187.208:8080/yd-data/YD-CH32V307VCT6/YD-CH32V307VCT6/)
+- [CH32V307](https://www.wch.cn/products/CH32V307.html)
+- [CH32V307 official document](https://github.com/openwch/ch32v307)
+
+## 2 Compiling
+
+The BSP supports the RISC-V GCC development environment, here's the specific version information:
+
+| IDE/Compiler | Version Tested       |
+| ------------ | -------------------- |
+| GCC          | WCH RISC-V GCC 8.2.0 |
+
+## 3 Quickly Get Started
+
+### 3.1 Using Linux to compile BSP
+
+This section is about to introduce how to compile the BSP in Linux.
+
+#### 3.1.1 Compile BSP
+
+1. [Download WCH Compile Toolchain](https://github.com/NanjingQinheng/sdk-toolchain-RISC-V-GCC-WCH/releases)
+2. [Download the RT-Thread latest code](https://github.com/RT-Thread/rt-thread/archive/refs/heads/master.zip)
+3. Install SCons construction tool (similar GNU Make): sudo apt install scons
+4. Edit the variable **EXEC_PATH** in file **rtconfig.py** to point to the directory with executable WCH Compile Toolchain (file riscv-none-embed-gcc).
+5. Configure RT-Thread and hardware board: scons --menuconfig
+6. Start compilation: scons
+7. After compilation, the **rtthread.bin** file will be generated
+
+#### 3.1.2 Download
+
+1. Clone source file: git clone https://github.com/jmaselbas/wch-isp.git
+2. Compile and install :
+- cd wch-isp
+- make && sudo make install && sudo make load
+3. Use a USB cable Type-C to connect board to the PC. Hold button **BOOT0**, press briefly button **RST** and release button **BOOT0**.
+4. Check board connection:
+```sh
+wch-isp list
+0: BTVER v2.9 UID 10-46-89-26-3b-38-d4-a4 [0x1770] CH32V307VCT6
+MCU current flash size: 256 Kbyte
+```
+
+> Note that Chip Mem here is set to 256K ROM + 64K RAM (see Table 2-1 of datasheet CH32V307, and chapter 32.6 "User Option Bytes" of Reference Manual CH32V2x_V3x).
+
+5. Download firmware to board:
+```
+wch-isp -p flash ./rtthread.bin && wch-isp reset 
+```
+
+#### 3.1.3 Running Result
+
+1. Connect USB-UART converter to board:
+- board pin A9 (UART1_TX) -> converter RX
+- board pin A10 (UART1_RX) -> converter TX (optional, for enter commands)
+2. In the terminal tool, open the converter serial port (default 115200-8-1-N), and after resetting the device, you can see the output information of RT-Thread on the serial port:
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.1.0 build Jan  6 2024 17:12:03
+ 2006 - 2022 Copyright by RT-Thread team
+SystemClk: 144000000 Hz
+msh >
+```
+On board LEDs (red and blue) blinking.

bsp/wch/risc-v/yd-ch32v307vct6/SConscript

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+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/wch/risc-v/yd-ch32v307vct6/SConstruct

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+import os
+import sys
+import rtconfig
+from SCons.Script import *
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/Libraries'):
+    libraries_path_prefix = SDK_ROOT + '/Libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+ch32_library = 'ch32v30x_libraries'
+rtconfig.BSP_LIBRARY_TYPE = ch32_library
+
+bsp_vdir = 'build'
+library_vdir = 'build/libraries'
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, ch32_library, 'SConscript'), variant_dir=library_vdir + '/ch32_library', duplicate=0))
+
+# common include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ch32_drivers', 'SConscript'), variant_dir=library_vdir + '/ch32_drivers', duplicate=0))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/wch/risc-v/yd-ch32v307vct6/applications/SConscript

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+from building import *
+import os
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+src = ['main.c']
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/wch/risc-v/yd-ch32v307vct6/applications/main.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-01-06     GSunwinder   first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "ch32v30x.h"
+#include "board.h"
+
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+
+int main(void)
+{
+    printf("SystemClk: %d Hz\r\n", SystemCoreClock);
+
+    rt_pin_mode(LED_BLUE, PIN_MODE_OUTPUT);
+    rt_pin_mode(LED_RED,  PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_RED,  PIN_LOW);
+        rt_pin_write(LED_BLUE, PIN_HIGH);
+        rt_thread_mdelay(1000);
+        rt_pin_write(LED_RED,  PIN_HIGH);
+        rt_pin_write(LED_BLUE, PIN_LOW);
+        rt_thread_mdelay(1000);
+    }
+}

bsp/wch/risc-v/yd-ch32v307vct6/board/SConscript

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+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+software_irq.c
+''')
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+Return('group')

bsp/wch/risc-v/yd-ch32v307vct6/board/board.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-08-23     liYony       first version
+ */
+
+#include "board.h"
+#include <stdint.h>
+#include "drv_usart.h"
+#include <rthw.h>
+#include <rtthread.h>
+
+extern uint32_t SystemCoreClock;
+
+static uint32_t _SysTick_Config(rt_uint32_t ticks)
+{
+    NVIC_SetPriority(SysTicK_IRQn, 0xf0);
+    NVIC_SetPriority(Software_IRQn, 0xf0);
+    NVIC_EnableIRQ(SysTicK_IRQn);
+    NVIC_EnableIRQ(Software_IRQn);
+    SysTick->CTLR = 0;
+    SysTick->SR = 0;
+    SysTick->CNT = 0;
+    SysTick->CMP = ticks - 1;
+    SysTick->CTLR = 0xF;
+    return 0;
+}
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init()
+{
+    /* System Tick Configuration */
+    _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+    rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+#ifdef RT_USING_PIN
+    /* pin must initialized before i2c */
+    rt_hw_pin_init();
+#endif
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void SysTick_Handler(void)
+{
+    GET_INT_SP();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    SysTick->SR = 0;
+    rt_tick_increase();
+    /* leave interrupt */
+    rt_interrupt_leave();
+    FREE_INT_SP();
+
+}

bsp/wch/risc-v/yd-ch32v307vct6/board/board.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-08-23     liYony       first version
+ * 2024-01-06     GSunwinder   add define LED pins
+ */
+
+/* <<< Use Configuration Wizard in Context Menu >>> */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "ch32v30x.h"
+#include "drv_gpio.h"
+#include "drv_pwm.h"
+
+/* board configuration */
+#define SRAM_SIZE  64
+#define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
+
+extern int _ebss, _susrstack;
+#define HEAP_BEGIN  ((void *)&_ebss)
+#define HEAP_END    ((void *)&_susrstack)
+
+/* defined the LED pin */
+#define LED_BLUE              rt_pin_get("PB.4")
+#define LED_RED               rt_pin_get("PA.15")
+
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */

bsp/wch/risc-v/yd-ch32v307vct6/board/linker_scripts/link.lds

@@ -0,0 +1,209 @@
+ENTRY( _start )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
+    RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+
+SECTIONS
+{
+
+    .init :
+    {
+        _sinit = .;
+        . = ALIGN(4);
+        KEEP(*(SORT_NONE(.init)))
+        . = ALIGN(4);
+        _einit = .;
+    } >FLASH AT>FLASH
+
+    .vector :
+    {
+        *(.vector);
+        . = ALIGN(64);
+    } >FLASH AT>FLASH
+
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text)
+        *(.text.*)
+        *(.rodata)
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t.*)
+
+         /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+            . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+
+    } >FLASH AT>FLASH
+
+    .fini :
+    {
+        KEEP(*(SORT_NONE(.fini)))
+        . = ALIGN(4);
+    } >FLASH AT>FLASH
+
+    PROVIDE( _etext = . );
+    PROVIDE( _eitcm = . );
+
+    .preinit_array  :
+    {
+      PROVIDE_HIDDEN (__preinit_array_start = .);
+      KEEP (*(.preinit_array))
+      PROVIDE_HIDDEN (__preinit_array_end = .);
+    } >FLASH AT>FLASH
+
+    .init_array     :
+    {
+      PROVIDE_HIDDEN (__init_array_start = .);
+      KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+      KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+      PROVIDE_HIDDEN (__init_array_end = .);
+    } >FLASH AT>FLASH
+
+    .fini_array     :
+    {
+      PROVIDE_HIDDEN (__fini_array_start = .);
+      KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+      KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+      PROVIDE_HIDDEN (__fini_array_end = .);
+    } >FLASH AT>FLASH
+
+    .ctors          :
+    {
+      /* gcc uses crtbegin.o to find the start of
+         the constructors, so we make sure it is
+         first.  Because this is a wildcard, it
+         doesn't matter if the user does not
+         actually link against crtbegin.o; the
+         linker won't look for a file to match a
+         wildcard.  The wildcard also means that it
+         doesn't matter which directory crtbegin.o
+         is in.  */
+      KEEP (*crtbegin.o(.ctors))
+      KEEP (*crtbegin?.o(.ctors))
+      /* We don't want to include the .ctor section from
+         the crtend.o file until after the sorted ctors.
+         The .ctor section from the crtend file contains the
+         end of ctors marker and it must be last */
+      KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+      KEEP (*(SORT(.ctors.*)))
+      KEEP (*(.ctors))
+    } >FLASH AT>FLASH
+
+    .dtors          :
+    {
+      KEEP (*crtbegin.o(.dtors))
+      KEEP (*crtbegin?.o(.dtors))
+      KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+      KEEP (*(SORT(.dtors.*)))
+      KEEP (*(.dtors))
+    } >FLASH AT>FLASH
+
+    .dalign :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data_vma = .);
+    } >RAM AT>FLASH
+
+    .dlalign :
+    {
+        . = ALIGN(4);
+        PROVIDE(_data_lma = .);
+    } >FLASH AT>FLASH
+
+    .data :
+    {
+        *(.gnu.linkonce.r.*)
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        . = ALIGN(8);
+        PROVIDE( __global_pointer$ = . + 0x800 );
+        *(.sdata .sdata.*)
+        *(.sdata2.*)
+        *(.gnu.linkonce.s.*)
+        . = ALIGN(8);
+        *(.srodata.cst16)
+        *(.srodata.cst8)
+        *(.srodata.cst4)
+        *(.srodata.cst2)
+        *(.srodata .srodata.*)
+        . = ALIGN(4);
+        PROVIDE( _edata = .);
+    } >RAM AT>FLASH
+
+    .bss :
+    {
+        . = ALIGN(4);
+        PROVIDE( _sbss = .);
+        *(.sbss*)
+        *(.gnu.linkonce.sb.*)
+        *(.bss*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON*)
+        . = ALIGN(4);
+        PROVIDE( _ebss = .);
+    } >RAM AT>FLASH
+
+    PROVIDE( _end = _ebss);
+    PROVIDE( end = . );
+
+    .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+    {
+        PROVIDE( _heap_end = . );
+        . = ALIGN(4);
+        PROVIDE(_susrstack = . );
+        . = . + __stack_size;
+        PROVIDE( _eusrstack = .);
+        PROVIDE( __rt_rvstack = . );
+    } >RAM
+
+}

bsp/wch/risc-v/yd-ch32v307vct6/board/software_irq.c

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WCH        the first version
+ * 2023-01-04     WangShun   Remove redundant files
+ */
+#include "rtconfig.h"
+#if defined (SOC_RISCV_SERIES_CH32V1)
+#include "ch32v10x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V2)
+#include "ch32v20x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V3)
+#include "ch32v30x.h"
+#else
+#error "CH32 architecture doesn't support!"
+#endif
+void rt_trigger_software_interrupt(void)
+{
+    /*CH32V103 does not support systick software interrupt*/
+#if defined(SOC_RISCV_SERIES_CH32V1)
+    NVIC_SetPendingIRQ(Software_IRQn);
+#else
+    SysTick->CTLR |= (1 << 31);
+#endif
+}
+
+void rt_hw_do_after_save_above(void)
+{
+    __asm volatile ("li t0,0x20" );
+    __asm volatile ("csrs 0x804, t0");
+    /*CH32V103 does not support systick software interrupt*/
+#if defined(SOC_RISCV_SERIES_CH32V1)
+    NVIC_ClearPendingIRQ(Software_IRQn);
+#else
+    SysTick->CTLR &= ~(1 << 31);
+#endif
+}

bsp/wch/risc-v/yd-ch32v307vct6/rtconfig.h

@@ -0,0 +1,262 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+#define RT_USING_HW_ATOMIC
+#define ARCH_RISCV
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 1024
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Memory protection */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_RISCV_FAMILY_CH32
+#define SOC_RISCV_SERIES_CH32V3
+
+/* Hardware Drivers Config */
+
+#define SOC_CH32V307VC
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+#define LSI_VALUE 39000
+
+/* Board extended module Drivers */
+
+
+#endif

bsp/wch/risc-v/yd-ch32v307vct6/rtconfig.py

@@ -0,0 +1,70 @@
+import os
+ARCH     = 'risc-v'
+CPU      = 'ch32'
+# toolchains options
+CROSS_TOOL  = 'gcc'
+
+#------- toolchains path -------------------------------------------------------
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/MRS_Toolchain_Linux_x64_V1.90/RISC-V_Embedded_GCC/bin/'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+	
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+CORE = 'risc-v'
+MAP_FILE = 'rtthread.map'
+LINK_FILE = './board/linker_scripts/link.lds'
+TARGET_NAME = 'rtthread.bin'
+
+#------- GCC settings ----------------------------------------------------------
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'riscv-none-embed-'
+    CC = PREFIX + 'gcc'
+    CXX= PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L.  -nostartfiles  -lc '
+    CFLAGS = DEVICE
+    CFLAGS += ' -save-temps=obj'
+    AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE
+    LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
+    LFLAGS += ' -T ' + LINK_FILE
+    AFLAGS += ' -I.'
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
+    POST_ACTION += SIZE + ' $TARGET\n'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)