mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-14 12:57:45 +08:00
Bernard Xiong
+95
-5
File diff suppressed because it is too large
Load Diff
+5
-195
File diff suppressed because it is too large
Load Diff
@@ -79,6 +79,10 @@ CONFIG_RT_VER_NUM=0x40004
|
||||
CONFIG_ARCH_ARM=y
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||||
# CONFIG_RT_USING_CPU_FFS is not set
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CONFIG_ARCH_ARM_CORTEX_A=y
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||||
# CONFIG_RT_SMP_AUTO_BOOT is not set
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||||
CONFIG_RT_USING_GIC_V2=y
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||||
# CONFIG_RT_USING_GIC_V3 is not set
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# CONFIG_RT_NO_USING_GIC is not set
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CONFIG_ARCH_ARM_CORTEX_A9=y
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# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
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@@ -26,10 +26,16 @@ static void rt_hw_timer2_isr(int vector, void *param)
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timer_clear_pending(0);
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}
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void set_secondary_cpu_boot_address(void)
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{
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extern void secondary_cpu_start(void);
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uint32_t *boot_address = (uint32_t *)0x10000030;
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*(boot_address + 1) = ~0ul;
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*boot_address = (uint32_t )&secondary_cpu_start;
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}
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void rt_hw_secondary_cpu_up(void)
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{
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extern void set_secondary_cpu_boot_address(void);
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set_secondary_cpu_boot_address();
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__asm__ volatile ("dsb":::"memory");
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rt_hw_ipi_send(0, 1 << 1);
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@@ -55,6 +55,7 @@
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||||
#define RT_VER_NUM 0x40004
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#define ARCH_ARM
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#define ARCH_ARM_CORTEX_A
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#define RT_USING_GIC_V2
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#define ARCH_ARM_CORTEX_A9
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/* RT-Thread Components */
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@@ -55,6 +55,7 @@
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#define RT_VER_NUM 0x40004
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#define ARCH_ARM
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#define ARCH_ARM_CORTEX_A
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#define RT_USING_GIC_V2
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#define ARCH_ARM_CORTEX_A9
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/* RT-Thread Components */
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@@ -58,6 +58,26 @@ config ARCH_ARM_CORTEX_A
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bool
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select ARCH_ARM
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if ARCH_ARM_CORTEX_A
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config RT_SMP_AUTO_BOOT
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bool
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default n
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choice
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prompt "GIC controller selection"
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default RT_USING_GIC_V2
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config RT_USING_GIC_V2
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bool " Gic version 2 "
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config RT_USING_GIC_V3
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bool " Gic version 3 "
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config RT_NO_USING_GIC
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bool " GIC controller is not used "
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endchoice
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endif
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config ARCH_ARM_CORTEX_A5
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bool
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select ARCH_ARM_CORTEX_A
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@@ -5,9 +5,27 @@ from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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src = Split('''
|
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cache.c
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cpu.c
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gtimer.c
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mmu.c
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pmu.c
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stack.c
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|
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''')
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CPPPATH = [cwd]
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if GetDepend('RT_USING_GIC_V2'):
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src += ['interrupt.c']
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src += ['gic.c']
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src += ['trap.c']
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if GetDepend('RT_USING_GIC_V3'):
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src += ['interrupt.c']
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src += ['gicv3.c']
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src += ['trap.c']
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if rtconfig.PLATFORM == 'armcc':
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src += Glob('*_rvds.S')
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@@ -18,6 +36,9 @@ if rtconfig.PLATFORM == 'gcc':
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if rtconfig.PLATFORM == 'iar':
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src += Glob('*_iar.S')
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if rtconfig.PLATFORM == 'iar':
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src += Glob('*_iar.S')
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group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -15,8 +15,7 @@
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#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
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#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
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unsigned long rt_cpu_get_smp_id(void);
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int rt_hw_cpu_id(void);
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void rt_cpu_mmu_disable(void);
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void rt_cpu_mmu_enable(void);
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void rt_cpu_tlb_set(volatile unsigned long*);
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@@ -8,9 +8,11 @@
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||||
* 2013-07-05 Bernard the first version
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*/
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.globl rt_cpu_get_smp_id
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rt_cpu_get_smp_id:
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mrc p15, #0, r0, c0, c0, #5
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.weak rt_hw_cpu_id
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rt_hw_cpu_id:
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mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register
|
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ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2
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and r0, r0, r1
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bx lr
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.globl rt_cpu_vector_set_base
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@@ -15,17 +15,6 @@
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#ifdef RT_USING_SMP
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int rt_hw_cpu_id(void)
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{
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int cpu_id;
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__asm__ volatile (
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"mrc p15, 0, %0, c0, c0, 5"
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:"=r"(cpu_id)
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);
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cpu_id &= 0xf;
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return cpu_id;
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};
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
|
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{
|
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lock->slock = 0;
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|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
*/
|
||||
|
||||
#ifndef __GIC_V3_H__
|
||||
#define __GIC_V3_H__
|
||||
|
||||
#include <rthw.h>
|
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#include <board.h>
|
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|
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#define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR \
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: "=r"(Rt) \
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: \
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: "memory")
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||||
#define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \
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||||
: \
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: "r"(Rt) \
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: "memory")
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||||
|
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|
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/* AArch32 System register interface to GICv3 */
|
||||
#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
|
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#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
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#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
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#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
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#define ICC_HPPIR0 "p15, 0, %0, c12, c8, 2"
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#define ICC_HPPIR1 "p15, 0, %0, c12, c12, 2"
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#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
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#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
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#define ICC_DIR "p15, 0, %0, c12, c11, 1"
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#define ICC_PMR "p15, 0, %0, c4, c6, 0"
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#define ICC_RPR "p15, 0, %0, c12, c11, 3"
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#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
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#define ICC_MCTLR "p15, 6, %0, c12, c12, 4"
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#define ICC_SRE "p15, 0, %0, c12, c12, 5"
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#define ICC_HSRE "p15, 4, %0, c12, c9, 5"
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#define ICC_MSRE "p15, 6, %0, c12, c12, 5"
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#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
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#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
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#define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7"
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#define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x)))
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#define ROUTED_TO_ALL (1)
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#define ROUTED_TO_SPEC (0)
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/** Macro to access the Distributor Control Register (GICD_CTLR)
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*/
|
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#define GICD_CTLR_RWP (1<<31)
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#define GICD_CTLR_E1NWF (1<<7)
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#define GICD_CTLR_DS (1<<6)
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#define GICD_CTLR_ARE_NS (1<<5)
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#define GICD_CTLR_ARE_S (1<<4)
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#define GICD_CTLR_ENGRP1S (1<<2)
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#define GICD_CTLR_ENGRP1NS (1<<1)
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#define GICD_CTLR_ENGRP0 (1<<0)
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/** Macro to access the Redistributor Control Register (GICR_CTLR)
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*/
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#define GICR_CTLR_UWP (1<<31)
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#define GICR_CTLR_DPG1S (1<<26)
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#define GICR_CTLR_DPG1NS (1<<25)
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#define GICR_CTLR_DPG0 (1<<24)
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#define GICR_CTLR_RWP (1<<3)
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#define GICR_CTLR_IR (1<<2)
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#define GICR_CTLR_CES (1<<1)
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#define GICR_CTLR_EnableLPI (1<<0)
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/** Macro to access the Generic Interrupt Controller Interface (GICC)
|
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*/
|
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#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U)
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#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U)
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#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U)
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#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU)
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#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U)
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#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U)
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#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U)
|
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#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU)
|
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|
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/** Macro to access the Generic Interrupt Controller Distributor (GICD)
|
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*/
|
||||
#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
|
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#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U)
|
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#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
|
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#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
|
||||
#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
|
||||
#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U)
|
||||
#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
|
||||
#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U)
|
||||
#define GIC_DIST_IROUTER_LOW(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U)
|
||||
#define GIC_DIST_IROUTER_HIGH(hw_base, n) __REG32((hw_base) + 0x6000U + (n)*8U + 4)
|
||||
|
||||
/* SGI base address is at 64K offset from Redistributor base address */
|
||||
#define GIC_RSGI_OFFSET 0x10000
|
||||
|
||||
/** Macro to access the Generic Interrupt Controller Redistributor (GICD)
|
||||
*/
|
||||
#define GIC_RDIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
|
||||
#define GIC_RDIST_IIDR(hw_base) __REG32((hw_base) + 0x004U)
|
||||
#define GIC_RDIST_TYPER(hw_base) __REG32((hw_base) + 0x008U)
|
||||
#define GIC_RDIST_TSTATUSR(hw_base) __REG32((hw_base) + 0x010U)
|
||||
#define GIC_RDIST_WAKER(hw_base) __REG32((hw_base) + 0x014U)
|
||||
#define GIC_RDIST_SETLPIR(hw_base) __REG32((hw_base) + 0x040U)
|
||||
#define GIC_RDIST_CLRLPIR(hw_base) __REG32((hw_base) + 0x048U)
|
||||
#define GIC_RDIST_PROPBASER(hw_base) __REG32((hw_base) + 0x070U)
|
||||
#define GIC_RDIST_PENDBASER(hw_base) __REG32((hw_base) + 0x078U)
|
||||
#define GIC_RDIST_INVLPIR(hw_base) __REG32((hw_base) + 0x0A0U)
|
||||
#define GIC_RDIST_INVALLR(hw_base) __REG32((hw_base) + 0x0B0U)
|
||||
#define GIC_RDIST_SYNCR(hw_base) __REG32((hw_base) + 0x0C0U)
|
||||
|
||||
#define GIC_RDISTSGI_IGROUPR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U)
|
||||
#define GIC_RDISTSGI_ISENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U)
|
||||
#define GIC_RDISTSGI_ICENABLER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U)
|
||||
#define GIC_RDISTSGI_ISPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U)
|
||||
#define GIC_RDISTSGI_ICPENDR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U)
|
||||
#define GIC_RDISTSGI_ISACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U)
|
||||
#define GIC_RDISTSGI_ICACTIVER0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U)
|
||||
#define GIC_RDISTSGI_IPRIORITYR(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U)
|
||||
#define GIC_RDISTSGI_ICFGR0(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U)
|
||||
#define GIC_RDISTSGI_ICFGR1(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U)
|
||||
#define GIC_RDISTSGI_IGRPMODR0(hw_base, n) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4)
|
||||
#define GIC_RDISTSGI_NSACR(hw_base) __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U)
|
||||
|
||||
#define GIC_RSGI_AFF1_OFFSET 16
|
||||
#define GIC_RSGI_AFF2_OFFSET 32
|
||||
#define GIC_RSGI_AFF3_OFFSET 48
|
||||
|
||||
rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list);
|
||||
rt_uint64_t get_main_cpu_affval(void);
|
||||
int arm_gic_get_active_irq(rt_uint32_t index);
|
||||
void arm_gic_ack(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_mask(rt_uint32_t index, int irq);
|
||||
void arm_gic_umask(rt_uint32_t index, int irq);
|
||||
|
||||
rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
|
||||
void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
|
||||
void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_configuration(rt_uint32_t index, int irq, uint32_t config);
|
||||
rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_clear_active(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
|
||||
rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority);
|
||||
rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority);
|
||||
rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index);
|
||||
|
||||
void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point);
|
||||
rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
|
||||
|
||||
rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq);
|
||||
|
||||
void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode);
|
||||
rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index);
|
||||
|
||||
rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
|
||||
|
||||
void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group);
|
||||
rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq);
|
||||
|
||||
int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id);
|
||||
int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id);
|
||||
int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
|
||||
int arm_gic_cpu_init(rt_uint32_t index);
|
||||
int arm_gic_redist_init(rt_uint32_t index);
|
||||
|
||||
void arm_gic_dump_type(rt_uint32_t index);
|
||||
void arm_gic_dump(rt_uint32_t index);
|
||||
|
||||
void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value);
|
||||
rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index);
|
||||
void arm_gic_secondary_cpu_init(void);
|
||||
#endif
|
||||
|
||||
@@ -110,6 +110,14 @@ void gtimer_set_counter_frequency(rt_uint32_t value)
|
||||
__asm__ volatile ("isb 0xF":::"memory");
|
||||
}
|
||||
|
||||
/** Get the frequency the timer shall run at.
|
||||
* return timer frequency in Hz.
|
||||
*/
|
||||
rt_uint32_t gtimer_get_counter_frequency(void)
|
||||
{
|
||||
return(__get_cntfrq());
|
||||
}
|
||||
|
||||
/** Sets the reset value of the timer.
|
||||
* param value: The value the timer is loaded with.
|
||||
*/
|
||||
|
||||
@@ -14,6 +14,7 @@
|
||||
#include <rtdef.h>
|
||||
|
||||
void gtimer_set_counter_frequency(rt_uint32_t value);
|
||||
rt_uint32_t gtimer_get_counter_frequency(void);
|
||||
void gtimer_set_load_value(rt_uint32_t value);
|
||||
rt_uint32_t gtimer_get_current_value(void);
|
||||
rt_uint64_t gtimer_get_current_physical_value(void);
|
||||
|
||||
@@ -12,8 +12,12 @@
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "interrupt.h"
|
||||
#include "gic.h"
|
||||
|
||||
#ifdef RT_USING_GIC_V2
|
||||
#include "gic.h"
|
||||
#else
|
||||
#include "gicv3.h"
|
||||
#endif
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
struct rt_irq_desc isr_table[MAX_HANDLERS];
|
||||
@@ -34,6 +38,7 @@ void rt_hw_vector_init(void)
|
||||
rt_cpu_vector_set_base((unsigned int)&system_vectors);
|
||||
}
|
||||
|
||||
#ifdef RT_USING_GIC_V2
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
@@ -58,6 +63,33 @@ void rt_hw_interrupt_init(void)
|
||||
arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
|
||||
arm_gic_cpu_init(0, gic_cpu_base);
|
||||
}
|
||||
#else
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
* Called by the primary cpu(cpu0)
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
rt_uint32_t gic_dist_base;
|
||||
rt_uint32_t gic_irq_start;
|
||||
|
||||
/* initialize vector table */
|
||||
rt_hw_vector_init();
|
||||
|
||||
/* initialize exceptions table */
|
||||
rt_memset(isr_table, 0x00, sizeof(isr_table));
|
||||
|
||||
/* initialize ARM GIC */
|
||||
gic_dist_base = platform_get_gic_dist_base();
|
||||
gic_irq_start = GIC_IRQ_START;
|
||||
|
||||
arm_gic_dist_init(0, gic_dist_base, gic_irq_start);
|
||||
|
||||
arm_gic_cpu_init(0);
|
||||
arm_gic_redist_init(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
@@ -245,7 +277,7 @@ unsigned int rt_hw_interrupt_get_prior_group_bits(void)
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
@@ -269,7 +301,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
#ifdef RT_USING_SMP
|
||||
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
|
||||
{
|
||||
#ifdef RT_USING_GIC_V2
|
||||
arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
|
||||
#else
|
||||
arm_gic_send_affinity_sgi(0, ipi_vector, cpu_mask, ROUTED_TO_SPEC);
|
||||
#endif
|
||||
}
|
||||
|
||||
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
|
||||
|
||||
@@ -22,20 +22,26 @@
|
||||
.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
|
||||
.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
|
||||
|
||||
#ifdef RT_USING_FPU
|
||||
.equ UND_Stack_Size, 0x00000400
|
||||
#else
|
||||
.equ UND_Stack_Size, 0x00000000
|
||||
#endif
|
||||
.equ SVC_Stack_Size, 0x00000400
|
||||
.equ ABT_Stack_Size, 0x00000000
|
||||
.equ ABT_Stack_Size, 0x00000400
|
||||
.equ RT_FIQ_STACK_PGSZ, 0x00000000
|
||||
.equ RT_IRQ_STACK_PGSZ, 0x00000800
|
||||
.equ USR_Stack_Size, 0x00000400
|
||||
|
||||
.equ SUB_UND_Stack_Size, 0x00000400
|
||||
.equ SUB_SVC_Stack_Size, 0x00000400
|
||||
.equ SUB_ABT_Stack_Size, 0x00000400
|
||||
.equ SUB_RT_FIQ_STACK_PGSZ, 0x00000000
|
||||
.equ SUB_RT_IRQ_STACK_PGSZ, 0x00000400
|
||||
.equ SUB_USR_Stack_Size, 0x00000400
|
||||
|
||||
#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
|
||||
RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
|
||||
|
||||
#define SUB_ISR_Stack_Size (SUB_UND_Stack_Size + SUB_SVC_Stack_Size + SUB_ABT_Stack_Size + \
|
||||
SUB_RT_FIQ_STACK_PGSZ + SUB_RT_IRQ_STACK_PGSZ)
|
||||
|
||||
.section .data.share.isr
|
||||
/* stack */
|
||||
.globl stack_start
|
||||
@@ -82,9 +88,40 @@ continue:
|
||||
|
||||
/* disable the data alignment check */
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
bic r1, #(1<<1)
|
||||
bic r1, #(1<<0) /* Disable MMU */
|
||||
bic r1, #(1<<1) /* Disable Alignment fault checking */
|
||||
bic r1, #(1<<2) /* Disable data cache */
|
||||
bic r1, #(1<<11) /* Disable program flow prediction */
|
||||
bic r1, #(1<<12) /* Disable instruction cache */
|
||||
bic r1, #(3<<19) /* bit[20:19] must be zero */
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
|
||||
@ get cpu id, and subtract the offset from the stacks base address
|
||||
bl rt_hw_cpu_id
|
||||
mov r5, r0
|
||||
|
||||
cmp r5, #0 @ cpu id == 0
|
||||
beq normal_setup
|
||||
|
||||
@ cpu id > 0, stop or wait
|
||||
#ifdef RT_SMP_AUTO_BOOT
|
||||
ldr r0, =secondary_cpu_entry
|
||||
mov r1, #0
|
||||
str r1, [r0] /* clean secondary_cpu_entry */
|
||||
#endif /* RT_SMP_AUTO_BOOT */
|
||||
|
||||
secondary_loop:
|
||||
@ cpu core 1 goes into sleep until core 0 wakeup it
|
||||
wfe
|
||||
#ifdef RT_SMP_AUTO_BOOT
|
||||
ldr r1, =secondary_cpu_entry
|
||||
ldr r0, [r1]
|
||||
cmp r0, #0
|
||||
blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */
|
||||
#endif /* RT_SMP_AUTO_BOOT */
|
||||
b secondary_loop
|
||||
|
||||
normal_setup:
|
||||
/* setup stack */
|
||||
bl stack_setup
|
||||
|
||||
@@ -105,6 +142,11 @@ bss_loop:
|
||||
mcr p15, 0, r1, c1, c0, 1 //enable smp
|
||||
#endif
|
||||
|
||||
/* enable branch prediction */
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #(1<<11)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
/* initialize the mmu table and enable mmu */
|
||||
ldr r0, =platform_mem_desc
|
||||
ldr r1, =platform_mem_desc_size
|
||||
@@ -137,6 +179,7 @@ stack_setup:
|
||||
|
||||
@ Set the startup stack for svc
|
||||
mov sp, r0
|
||||
sub r0, r0, #SVC_Stack_Size
|
||||
|
||||
@ Enter Undefined Instruction Mode and set its Stack Pointer
|
||||
msr cpsr_c, #Mode_UND|I_Bit|F_Bit
|
||||
@@ -378,16 +421,6 @@ vector_resv:
|
||||
b .
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
.global set_secondary_cpu_boot_address
|
||||
set_secondary_cpu_boot_address:
|
||||
ldr r0, =secondary_cpu_start
|
||||
|
||||
mvn r1, #0 //0xffffffff
|
||||
ldr r2, =0x10000034
|
||||
str r1, [r2]
|
||||
str r0, [r2, #-4]
|
||||
mov pc, lr
|
||||
|
||||
.global secondary_cpu_start
|
||||
secondary_cpu_start:
|
||||
|
||||
@@ -405,38 +438,52 @@ secondary_cpu_start:
|
||||
bic r0, #(1<<13)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
#ifdef RT_USING_FPU
|
||||
cps #Mode_UND
|
||||
ldr sp, =und_stack_2_limit
|
||||
#endif
|
||||
/* enable branch prediction */
|
||||
mrc p15, 0, r0, c1, c0, 0
|
||||
orr r0, r0, #(1<<11)
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
|
||||
cps #Mode_IRQ
|
||||
ldr sp, =irq_stack_2_limit
|
||||
@ get cpu id, and subtract the offset from the stacks base address
|
||||
bl rt_hw_cpu_id
|
||||
sub r5, r0, #1
|
||||
|
||||
cps #Mode_FIQ
|
||||
ldr sp, =irq_stack_2_limit
|
||||
ldr r0, =SUB_ISR_Stack_Size
|
||||
mul r0, r0, r5 @r0 = SUB_ISR_Stack_Size * (cpuid - 1)
|
||||
ldr r1, =sub_stack_top
|
||||
sub r0, r1, r0 @r0 = sub_stack_top - (SUB_ISR_Stack_Size * (cpuid - 1))
|
||||
|
||||
cps #Mode_SVC
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_SVC_Stack_Size
|
||||
|
||||
cps #Mode_UND
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_UND_Stack_Size
|
||||
|
||||
cps #Mode_ABT
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_ABT_Stack_Size
|
||||
|
||||
cps #Mode_FIQ
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_RT_FIQ_STACK_PGSZ
|
||||
|
||||
cps #Mode_IRQ
|
||||
mov sp, r0
|
||||
sub r0, r0, #SUB_RT_IRQ_STACK_PGSZ
|
||||
|
||||
cps #Mode_SVC
|
||||
ldr sp, =svc_stack_2_limit
|
||||
|
||||
/* initialize the mmu table and enable mmu */
|
||||
bl rt_hw_mmu_init
|
||||
|
||||
b secondary_cpu_c_start
|
||||
#endif
|
||||
|
||||
.bss
|
||||
.align 2 //align to 2~2=4
|
||||
svc_stack_2:
|
||||
.space (1 << 10)
|
||||
svc_stack_2_limit:
|
||||
|
||||
irq_stack_2:
|
||||
.space (1 << 10)
|
||||
irq_stack_2_limit:
|
||||
sub_stack_start:
|
||||
.space (SUB_ISR_Stack_Size * (RT_CPUS_NR-1))
|
||||
sub_stack_top:
|
||||
|
||||
#ifdef RT_USING_FPU
|
||||
und_stack_2:
|
||||
.space (1 << 10)
|
||||
und_stack_2_limit:
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user