[BSP][tms320f28379d] Add port for tms320f28379d

2026-09-21 10:36:04 +08:00 · 2018-09-02 18:44:28 +08:00
parent f7d19319ab
commit d85981a715
179 changed files with 102196 additions and 0 deletions
@@ -0,0 +1,17 @@
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+								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.OUTPUT_FILE.704940018" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.OUTPUT_FILE" value="${ProjName}.out" valueType="string"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.LIBRARY.28700764" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.LIBRARY" valueType="libs">
+									<listOptionValue builtIn="false" value="libc.a"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.SEARCH_PATH.1505417840" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.SEARCH_PATH" valueType="libPaths">
+									<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/lib"/>
+									<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
+								</option>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.DIAG_WRAP.229288789" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.DIAG_WRAP" value="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.DIAG_WRAP.off" valueType="enumerated"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.DISPLAY_ERROR_NUMBER.1105472030" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.DISPLAY_ERROR_NUMBER" value="true" valueType="boolean"/>
+								<option id="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.XML_LINK_INFO.1521574856" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.linkerID.XML_LINK_INFO" value="${ProjName}_linkInfo.xml" valueType="string"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_18.1.exeLinker.inputType__CMD_SRCS.1836678608" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.exeLinker.inputType__CMD_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_18.1.exeLinker.inputType__CMD2_SRCS.769850203" name="Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.exeLinker.inputType__CMD2_SRCS"/>
+								<inputType id="com.ti.ccstudio.buildDefinitions.C2000_18.1.exeLinker.inputType__GEN_CMDS.1509425120" name="Generated Linker Command Files" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.exeLinker.inputType__GEN_CMDS"/>
+							</tool>
+							<tool id="com.ti.ccstudio.buildDefinitions.C2000_18.1.hex.1247524530" name="C2000 Hex Utility" superClass="com.ti.ccstudio.buildDefinitions.C2000_18.1.hex"/>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.core.language.mapping">
+		<project-mappings>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.asmSource" language="com.ti.ccstudio.core.TIASMLanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cHeader" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cSource" language="com.ti.ccstudio.core.TIGCCLanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxHeader" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+			<content-type-mapping configuration="" content-type="org.eclipse.cdt.core.cxxSource" language="com.ti.ccstudio.core.TIGPPLanguage"/>
+		</project-mappings>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="rt-thread.com.ti.ccstudio.buildDefinitions.C2000.ProjectType.1837437567" name="C2000" projectType="com.ti.ccstudio.buildDefinitions.C2000.ProjectType"/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="scannerConfiguration"/>
+</cproject>
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>rt-thread</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.ti.ccstudio.core.ccsNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>C28X</name>
+			<type>2</type>
+			<locationURI>PARENT-2-PROJECT_LOC/libcpu/c28x</locationURI>
+		</link>
+		<link>
+			<name>Kernel</name>
+			<type>2</type>
+			<locationURI>PARENT-2-PROJECT_LOC/src</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
@@ -0,0 +1,22 @@
+eclipse.preferences.version=1
+encoding//Debug/C28X/subdir_rules.mk=UTF-8
+encoding//Debug/C28X/subdir_vars.mk=UTF-8
+encoding//Debug/Kernel/subdir_rules.mk=UTF-8
+encoding//Debug/Kernel/subdir_vars.mk=UTF-8
+encoding//Debug/applications/subdir_rules.mk=UTF-8
+encoding//Debug/applications/subdir_vars.mk=UTF-8
+encoding//Debug/drivers/subdir_rules.mk=UTF-8
+encoding//Debug/drivers/subdir_vars.mk=UTF-8
+encoding//Debug/libraries/common/source/subdir_rules.mk=UTF-8
+encoding//Debug/libraries/common/source/subdir_vars.mk=UTF-8
+encoding//Debug/libraries/headers/cmd/subdir_rules.mk=UTF-8
+encoding//Debug/libraries/headers/cmd/subdir_vars.mk=UTF-8
+encoding//Debug/libraries/headers/source/subdir_rules.mk=UTF-8
+encoding//Debug/libraries/headers/source/subdir_vars.mk=UTF-8
+encoding//Debug/libraries/subdir_rules.mk=UTF-8
+encoding//Debug/libraries/subdir_vars.mk=UTF-8
+encoding//Debug/makefile=UTF-8
+encoding//Debug/objects.mk=UTF-8
+encoding//Debug/sources.mk=UTF-8
+encoding//Debug/subdir_rules.mk=UTF-8
+encoding//Debug/subdir_vars.mk=UTF-8
@@ -0,0 +1,135 @@
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
+          /* BEGIN is used for the "boot to Flash" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000
+   RAMGS15          : origin = 0x01B000, length = 0x001000
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+   
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */   
+
+PAGE 1 : /* Data Memory */
+         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000
+   RAMGS13     : origin = 0x019000, length = 0x001000
+
+   
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)   
+   #endif
+#endif
+						 
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1        PAGE = 1
+   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
+   .esysmem            : >> RAMGS2 | RAMGS3 | RAMGS4 | RAMGS5 | RAMGS6 | RAMGS7 | RAMGS8 | RAMGS9 | RAMGS10 | RAMGS11 | RAMGS12 | RAMGS13    PAGE = 1
+
+   /* Initalized sections go in Flash */
+   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
+   
+   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
+   
+   SHARERAMGS0		: > RAMGS0,		PAGE = 1
+   SHARERAMGS1		: > RAMGS1,		PAGE = 1
+   
+   /* The following section definitions are required when using the IPC API Drivers */ 
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1 
+    {
+        PUTBUFFER 
+        PUTWRITEIDX 
+        GETREADIDX 
+    }
+    
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }  
+    
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,59 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2014-04-27     Bernard      make code cleanup. 
+ */
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef RT_USING_LWIP
+#include <lwip/sys.h>
+#include <lwip/api.h>
+#include <netif/ethernetif.h>
+#include "stm32f4xx_eth.h"
+#endif
+
+#ifdef RT_USING_FINSH
+#include <shell.h>
+#include <finsh.h>
+#endif
+
+#ifdef RT_USING_GDB
+#include <gdb_stub.h>
+#endif
+
+void rt_init_thread_entry(void* parameter)
+{
+    /* initialization RT-Thread Components */
+    rt_components_init();
+	
+    /* GDB STUB */
+#ifdef RT_USING_GDB
+    gdb_set_device("uart6");
+    gdb_start();
+#endif
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+        rt_init_thread_entry, RT_NULL,
+        2048, RT_THREAD_PRIORITY_MAX/3, 20);
+
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+
+    return 0;
+}
@@ -0,0 +1,98 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ * 2018-09-02     xuzhuoyi     modify for TMS320F28379D version
+ */
+
+#include <stdint.h>
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint16_t* file, uint32_t line)
+{
+    rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+    rt_kprintf("       file  %s\r\n", file);
+    rt_kprintf("       line  %d\r\n", line);
+
+    while (1) ;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init tick */
+    rt_system_tick_init();
+
+    /* init kernel object */
+    rt_system_object_init();
+
+    /* init timer system */
+    rt_system_timer_init();
+
+    //rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END);
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/
@@ -0,0 +1,70 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2018-09-02     xuzhuoyi     modify for TMS320F28379D version
+ */
+#include <rtthread.h>
+#include "board.h"
+#include "F28x_Project.h"
+
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+interrupt void cpu_timer2_isr (void)
+{
+    CpuTimer2Regs.TCR.all = 0x8000;
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+/**
+ * This function will initial STM32 board.
+ */
+void rt_hw_board_init()
+{
+    /* Configure the system clock @ 84 Mhz */
+    InitSysCtrl();
+
+    DINT;
+    InitPieCtrl();
+
+    IER = 0x0000;
+    IFR = 0x0000;
+
+    InitPieVectTable();
+
+    EALLOW;  // This is needed to write to EALLOW protected registers
+    PieVectTable.TIMER2_INT = &cpu_timer2_isr;
+    EDIS;
+
+    InitCpuTimers();
+    ConfigCpuTimer(&CpuTimer2, 200, 1000000 / RT_TICK_PER_SECOND);
+    CpuTimer2Regs.TCR.all = 0x4000;
+    IER |= M_INT14;
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
@@ -0,0 +1,26 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ */
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+#include <rtthread.h>
+
+#define C28X_SRAM_END          0x00020000
+
+
+#define HEAP_BEGIN  0x0000E000
+#define HEAP_END    C28X_SRAM_END
+extern void rt_hw_board_init(void);
+#endif
+
@@ -0,0 +1,178 @@
+// The user must define CLA_C in the project linker settings if using the
+// CLA C compiler
+// Project Properties -> C2000 Linker -> Advanced Options -> Command File
+// Preprocessing -> --define
+#ifdef CLA_C
+// Define a size for the CLA scratchpad area that will be used
+// by the CLA compiler for local symbols and temps
+// Also force references to the special symbols that mark the
+// scratchpad are.
+CLA_SCRATCHPAD_SIZE = 0x100;
+--undef_sym=__cla_scratchpad_end
+--undef_sym=__cla_scratchpad_start
+#endif //CLA_C
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000,   length = 0x000002
+   RAMM0           	: origin = 0x000122,   length = 0x0002DE
+   RAMD0           	: origin = 0x00B000,   length = 0x000800
+   RAMLS0          	: origin = 0x008000,   length = 0x000800
+   RAMLS1          	: origin = 0x008800,   length = 0x000800   
+   /* RAMLS4      	   : origin = 0x00A000, length = 0x000800 */
+   /* RAMLS5           : origin = 0x00A800, length = 0x000800 */
+   RAMLS4_5         : origin = 0x00A000,   length = 0x001000
+   
+   RAMGS14          : origin = 0x01A000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET           	: origin = 0x3FFFC0,   length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002,   length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000,   length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000,   length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000,   length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000,   length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000,   length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000,   length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000,   length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000,   length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000,   length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000,   length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000,   length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000,   length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000,   length = 0x002000	/* on-chip Flash */
+
+PAGE 1 :
+
+   BOOT_RSVD        : origin = 0x000002,   length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1            : origin = 0x000400,   length = 0x000400     /* on-chip RAM block M1 */
+
+   RAMLS2      		: origin = 0x009000,   length = 0x000800
+   RAMLS3      		: origin = 0x009800,   length = 0x000800
+
+   RAMGS0           : origin = 0x00C000,   length = 0x001000
+   RAMGS1           : origin = 0x00D000,   length = 0x001000
+   RAMGS2           : origin = 0x00E000,   length = 0x001000
+   RAMGS3           : origin = 0x00F000,   length = 0x001000
+   RAMGS4           : origin = 0x010000,   length = 0x001000
+   RAMGS5           : origin = 0x011000,   length = 0x001000
+   RAMGS6           : origin = 0x012000,   length = 0x001000
+   RAMGS7           : origin = 0x013000,   length = 0x001000
+   RAMGS8           : origin = 0x014000,   length = 0x001000
+   RAMGS9           : origin = 0x015000,   length = 0x001000
+   RAMGS10          : origin = 0x016000,   length = 0x001000
+   RAMGS11          : origin = 0x017000,   length = 0x001000
+   RAMGS12          : origin = 0x018000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13          : origin = 0x019000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   EMIF1_CS0n       : origin = 0x80000000, length = 0x10000000
+   EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000
+   EMIF1_CS3n       : origin = 0x00300000, length = 0x00080000
+   EMIF1_CS4n       : origin = 0x00380000, length = 0x00060000
+   EMIF2_CS0n       : origin = 0x90000000, length = 0x10000000
+   EMIF2_CS2n       : origin = 0x00002000, length = 0x00001000
+
+   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
+   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
+}
+
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit           : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit           : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text            : > FLASHB      PAGE = 0, ALIGN(4)
+   codestart        : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack           : > RAMM1        PAGE = 1
+   .ebss            : > RAMLS2       PAGE = 1
+   .esysmem         : > RAMLS2       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   .econst          : > FLASHB      PAGE = 0, ALIGN(4)
+   .switch          : > FLASHB      PAGE = 0, ALIGN(4)
+
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
+   
+   .em2_cs0         : > EMIF2_CS0n, PAGE = 1
+   .em2_cs2         : > EMIF2_CS2n, PAGE = 1
+
+    /* CLA specific sections */
+   Cla1Prog         : LOAD = FLASHD,
+                      RUN = RAMLS4_5,
+                      LOAD_START(_Cla1funcsLoadStart),
+                      LOAD_END(_Cla1funcsLoadEnd),
+                      RUN_START(_Cla1funcsRunStart),
+                      LOAD_SIZE(_Cla1funcsLoadSize),
+                      PAGE = 0, ALIGN(4)
+
+   CLADataLS0		: > RAMLS0, PAGE=0
+   CLADataLS1		: > RAMLS1, PAGE=0
+
+   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
+   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+						 RUN = RAMD0,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+						 PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs         : LOAD = FLASHD,
+                      RUN = RAMD0,
+                      LOAD_START(_RamfuncsLoadStart),
+                      LOAD_SIZE(_RamfuncsLoadSize),
+                      LOAD_END(_RamfuncsLoadEnd),
+                      RUN_START(_RamfuncsRunStart),
+                      RUN_SIZE(_RamfuncsRunSize),
+                      RUN_END(_RamfuncsRunEnd),
+                      PAGE = 0, ALIGN(4)
+   #endif
+#endif
+
+   /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+
+#ifdef CLA_C
+   /* CLA C compiler sections */
+   //
+   // Must be allocated to memory the CLA has write access to
+   //
+   CLAscratch       :
+                     { *.obj(CLAscratch)
+                     . += CLA_SCRATCHPAD_SIZE;
+                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 0
+
+   .scratchpad      : > RAMLS1,       PAGE = 0
+   .bss_cla		    : > RAMLS1,       PAGE = 0
+   .const_cla	    :  LOAD = FLASHB,
+                       RUN = RAMLS1,
+                       RUN_START(_Cla1ConstRunStart),
+                       LOAD_START(_Cla1ConstLoadStart),
+                       LOAD_SIZE(_Cla1ConstLoadSize),
+                       PAGE = 0
+#endif //CLA_C
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,134 @@
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
+          /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 : /* Data Memory */
+         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : > FLASHB      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1        PAGE = 1
+   .ebss               : > RAMLS5       PAGE = 1
+   .esysmem            : > RAMLS5       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   .econst             : > FLASHB      PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
+
+   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+   /* Allocate IQ math areas: */
+   IQmath			: > FLASHB, PAGE = 0, ALIGN(4)            /* Math Code */
+   IQmathTables		: > FLASHC, PAGE = 0, ALIGN(4)
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,147 @@
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
+          /* BEGIN is used for the "boot to Flash" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 : /* Data Memory */
+         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   FLASHN      : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)   
+   #endif
+#endif
+
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1        PAGE = 1
+   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
+   .esysmem            : > RAMLS5       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
+
+   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
+
+   ramgs0           : > RAMGS0,     PAGE = 1
+   ramgs1           : > RAMGS1,     PAGE = 1
+   .cio				: > RAMGS2,	   	PAGE = 1
+
+   /* Sine Table */
+   SINTBL			: > FLASHN,	   PAGE = 1
+
+   /* Data Log */
+   DLOG				: > RAMGS3,    PAGE = 1
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+   /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,136 @@
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
+          /* BEGIN is used for the "boot to Flash" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 : /* Data Memory */
+         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
+
+   BOOT_RSVD        : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1            : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1            : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1           : origin = 0x00D000, length = 0x001000
+   RAMGS2_GS4       : origin = 0x00E000, length = 0x003000
+   /*
+   RAMGS2           : origin = 0x00E000, length = 0x001000
+   RAMGS3           : origin = 0x00F000, length = 0x001000
+   RAMGS4           : origin = 0x010000, length = 0x001000
+   */
+   RAMGS5           : origin = 0x011000, length = 0x001000
+   RAMGS6           : origin = 0x012000, length = 0x001000
+   RAMGS7           : origin = 0x013000, length = 0x001000
+   RAMGS8           : origin = 0x014000, length = 0x001000
+   RAMGS9           : origin = 0x015000, length = 0x001000
+   RAMGS10          : origin = 0x016000, length = 0x001000
+   RAMGS11          : origin = 0x017000, length = 0x001000
+   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13          : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CPU2TOCPU1RAM    : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM    : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMGS1        PAGE = 1
+   .ebss               : > RAMGS2_GS4       PAGE = 1
+   .esysmem            : > RAMLS5       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
+
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
+
+   .sysmem          : > RAMGS1,    PAGE = 1
+   .cio             : > RAMGS1,    PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),                         
+                         PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,170 @@
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
+          /* BEGIN is used for the "boot to Flash" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x001800
+  // RAMLS3      		: origin = 0x009800, length = 0x000800
+ //  RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 : /* Data Memory */
+         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1        PAGE = 1
+   .ebss               : >> RAMGS0 | RAMGS1       PAGE = 1
+   .esysmem            : > RAMLS5       PAGE = 1
+   .cio                : > RAMLS5     PAGE = 1
+   
+   /* Initalized sections go in Flash */
+   .econst             : >> FLASHG | FLASHH      PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
+
+   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
+
+   SHARERAMGS0		: > RAMGS0,		PAGE = 1
+   SHARERAMGS1		: > RAMGS1,		PAGE = 1
+   ramgs0           : > RAMGS0,     PAGE = 1
+   ramgs1           : > RAMGS1,     PAGE = 1
+   ramls2           : > RAMLS2,     PAGE = 0
+//   SINETABLE        : > FLASHF      PAGE = 0, ALIGN(4)
+
+fsk_corr_lib_data : > RAMGS5		PAGE = 1	/* Flash block for lib data */
+
+#ifdef __TI_COMPILER_VERSION__
+	#if __TI_COMPILER_VERSION__ >= 15009000
+	.TI.ramfunc : {} LOAD = FLASHD,
+						 RUN = RAMLS0 | RAMLS1 | RAMLS2 ,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+						 PAGE = 0, ALIGN(4)
+	#else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)    
+    #endif
+#endif
+    #ifdef __TI_COMPILER_VERSION__
+	#if __TI_COMPILER_VERSION__ >= 15009000
+SINETABLE : {} LOAD = FLASHF,
+						 RUN = RAMLS2 ,
+                         LOAD_START(_SineTableLoadStart),
+                         LOAD_SIZE(_SineTableLoadSize),
+                         LOAD_END(_SineTableLoadEnd),
+                         RUN_START(_SineTableRunStart),
+                         RUN_SIZE(_SineTableRunSize),
+                         RUN_END(_SineTableRunEnd),
+						 PAGE = 0, ALIGN(4)
+
+	#else
+SINETABLE           :    LOAD = FLASHF,
+						 RUN = RAMLS2 ,
+                         LOAD_START(_SineTableLoadStart),
+                         LOAD_SIZE(_SineTableLoadSize),
+                         LOAD_END(_SineTableLoadEnd),
+                         RUN_START(_SineTableRunStart),
+                         RUN_SIZE(_SineTableRunSize),
+                         RUN_END(_SineTableRunEnd),
+						 PAGE = 0, ALIGN(4)
+
+    #endif
+#endif
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+   /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,142 @@
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
+          /* BEGIN is used for the "boot to Flash" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 : /* Data Memory */
+         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1        PAGE = 1
+   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
+   .esysmem            : > RAMLS5       PAGE = 1
+   .cio                : > RAMLS5     PAGE = 1
+   
+   /* Initalized sections go in Flash */
+   .econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
+
+   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
+
+   SHARERAMGS0		: > RAMGS0,		PAGE = 1
+   SHARERAMGS1		: > RAMGS1,		PAGE = 1
+   ramgs0           : > RAMGS0,     PAGE = 1
+   ramgs1           : > RAMGS1,     PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+	#if __TI_COMPILER_VERSION__ >= 15009000
+	.TI.ramfunc : {} LOAD = FLASHD,
+						 RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+						 PAGE = 0, ALIGN(4)
+	#else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)    
+    #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+   /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,156 @@
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
+          /* BEGIN is used for the "boot to Flash" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 : /* Data Memory */
+         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5          : origin = 0x00A800, length = 0x000800
+
+   RAMGS0          : origin = 0x00C000, length = 0x001000
+   RAMGS1          : origin = 0x00D000, length = 0x001000
+   RAMGS2          : origin = 0x00E000, length = 0x001000
+   RAMGS3          : origin = 0x00F000, length = 0x001000
+   RAMGS4          : origin = 0x010000, length = 0x001000
+   RAMGS5          : origin = 0x011000, length = 0x001000
+   RAMGS6          : origin = 0x012000, length = 0x001000
+   RAMGS7          : origin = 0x013000, length = 0x001000
+   RAMGS8          : origin = 0x014000, length = 0x001000
+   RAMGS9          : origin = 0x015000, length = 0x001000
+   RAMGS10         : origin = 0x016000, length = 0x001000
+   RAMGS11         : origin = 0x017000, length = 0x001000
+   RAMGS12         : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13         : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
+   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
+   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
+   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
+   EMIF2_CS0n      : origin = 0x90000000, length = 0x10000000
+   EMIF2_CS2n      : origin = 0x00002000, length = 0x00001000
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit           : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit           : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text            : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
+   codestart        : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack           : > RAMM1        PAGE = 1
+   .ebss            : >> RAMLS5 | RAMGS0 | RAMGS1       PAGE = 1
+   .esysmem         : > RAMLS5       PAGE = 1
+   .farbss          : > EMIF1_CS0n,  PAGE = 1
+
+   .em1_cs0         : > EMIF1_CS0n,      PAGE = 1
+   .em1_cs2         : > EMIF1_CS2n,      PAGE = 1
+   .em1_cs3         : > EMIF1_CS3n,      PAGE = 1
+   .em1_cs4         : > EMIF1_CS4n,      PAGE = 1
+   .em2_cs0         : > EMIF2_CS0n,      PAGE = 1
+   .em2_cs2         : > EMIF2_CS2n,      PAGE = 1
+
+   /* Initalized sections go in Flash */
+   .econst          : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)
+   .switch          : > FLASHB      PAGE = 0, ALIGN(4)
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+   .farconst        : > EMIF1_CS0n, PAGE = 1
+
+   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
+
+   SHARERAMGS0		: > RAMGS0,		PAGE = 1
+   SHARERAMGS1		: > RAMGS1,		PAGE = 1
+   ramgs0           : > RAMGS0,     PAGE = 1
+   ramgs1           : > RAMGS1,     PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+   /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,114 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000080, length = 0x000380
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET       		: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5          : origin = 0x00A800, length = 0x000800
+
+   RAMGS0          : origin = 0x00C000, length = 0x001000
+   RAMGS1          : origin = 0x00D000, length = 0x001000
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : > FLASHB      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1        PAGE = 1
+   .ebss               : > RAMLS5       PAGE = 1
+   .esysmem            : > RAMLS5       PAGE = 1
+
+   /* Initalized sections go in Flash */
+   .econst             : > FLASHB      PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   SHARERAMGS0		: > RAMGS0,		PAGE = 1
+   SHARERAMGS1		: > RAMGS1,		PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,120 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x080000, length = 0x000002
+   RAMM0           	: origin = 0x000080, length = 0x000380
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET       		: origin = 0x3FFFC0, length = 0x000002
+
+   /* Flash sectors */
+   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
+   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
+   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
+   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
+   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
+   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
+   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
+   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
+   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
+   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
+   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
+   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
+   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
+   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5          : origin = 0x00A800, length = 0x000800
+
+   RAMGS0          : origin = 0x00C000, length = 0x001000
+   RAMGS1          : origin = 0x00D000, length = 0x001000
+
+   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
+   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
+   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
+   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   /* Allocate program areas: */
+   .cinit              : > FLASHB      PAGE = 0, ALIGN(4)
+   .pinit              : > FLASHB,     PAGE = 0, ALIGN(4)
+   .text               : > FLASHB      PAGE = 0, ALIGN(4)
+   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
+
+   /* Allocate uninitalized data sections: */
+   .stack              : > RAMM1        PAGE = 1
+   .ebss               : > RAMLS5       PAGE = 1
+   .esysmem            : > RAMLS5       PAGE = 1
+   .farbss             : > EMIF1_CS0n,  PAGE = 1
+   /* Initalized sections go in Flash */
+   .econst             : > FLASHB       PAGE = 0, ALIGN(4)
+   .switch             : > FLASHB       PAGE = 0, ALIGN(4)
+   .reset              : > RESET,       PAGE = 0, TYPE = DSECT /* not used, */
+   .farconst           : > EMIF1_CS0n,  PAGE = 1
+   SHARERAMGS0		   : > RAMGS0,		PAGE = 1
+   SHARERAMGS1		   : > RAMGS1,		PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)
+   #else
+   ramfuncs            : LOAD = FLASHD,
+                         RUN = RAMLS0 | RAMLS1 | RAMLS2 |RAMLS3,
+                         LOAD_START(_RamfuncsLoadStart),
+                         LOAD_SIZE(_RamfuncsLoadSize),
+                         LOAD_END(_RamfuncsLoadEnd),
+                         RUN_START(_RamfuncsRunStart),
+                         RUN_SIZE(_RamfuncsRunSize),
+                         RUN_END(_RamfuncsRunEnd),
+                         PAGE = 0, ALIGN(4)   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,135 @@
+// The user must define CLA_C in the project linker settings if using the
+// CLA C compiler
+// Project Properties -> C2000 Linker -> Advanced Options -> Command File
+// Preprocessing -> --define
+#ifdef CLA_C
+// Define a size for the CLA scratchpad area that will be used
+// by the CLA compiler for local symbols and temps
+// Also force references to the special symbols that mark the
+// scratchpad are.
+CLA_SCRATCHPAD_SIZE = 0x100;
+--undef_sym=__cla_scratchpad_end
+--undef_sym=__cla_scratchpad_start
+#endif //CLA_C
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000,   length = 0x000002
+   RAMM0           	: origin = 0x000122,   length = 0x0002DE
+   RAMD0           	: origin = 0x00B000,   length = 0x000800
+   RAMD1            : origin = 0x00B800,   length = 0x000800
+   /* RAMLS4      	    : origin = 0x00A000, length = 0x000800 */
+   /* RAMLS5           : origin = 0x00A800, length = 0x000800 */
+   RAMLS4_5         : origin = 0x00A000,   length = 0x001000 
+   RESET           	: origin = 0x3FFFC0,   length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD        : origin = 0x000002,   length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1            : origin = 0x000400,   length = 0x000400     /* on-chip RAM block M1 */
+
+   RAMLS0          	: origin = 0x008000,   length = 0x000800
+   RAMLS1          	: origin = 0x008800,   length = 0x000800
+   RAMLS2      		: origin = 0x009000,   length = 0x000800
+   RAMLS3      		: origin = 0x009800,   length = 0x000800
+
+   RAMGS0           : origin = 0x00C000,   length = 0x001000
+   RAMGS1           : origin = 0x00D000,   length = 0x001000
+   RAMGS2           : origin = 0x00E000,   length = 0x001000
+   RAMGS3           : origin = 0x00F000,   length = 0x001000
+   RAMGS4           : origin = 0x010000,   length = 0x001000
+   RAMGS5           : origin = 0x011000,   length = 0x001000
+   RAMGS6           : origin = 0x012000,   length = 0x001000
+   RAMGS7           : origin = 0x013000,   length = 0x001000
+   RAMGS8           : origin = 0x014000,   length = 0x001000
+   RAMGS9           : origin = 0x015000,   length = 0x001000
+   RAMGS10          : origin = 0x016000,   length = 0x001000
+   RAMGS11          : origin = 0x017000,   length = 0x001000
+   RAMGS12          : origin = 0x018000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13          : origin = 0x019000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14          : origin = 0x01A000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000,   length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   EMIF1_CS0n       : origin = 0x80000000, length = 0x10000000
+   EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000
+   EMIF1_CS3n       : origin = 0x00300000, length = 0x00080000
+   EMIF1_CS4n       : origin = 0x00380000, length = 0x00060000
+   EMIF2_CS0n       : origin = 0x90000000, length = 0x10000000
+   EMIF2_CS2n       : origin = 0x00002000, length = 0x00001000
+
+   CANA_MSG_RAM     : origin = 0x049000,   length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000,   length = 0x000800
+
+   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
+   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
+}
+
+SECTIONS
+{
+   codestart        : > BEGIN,      PAGE = 0
+   .text            : >> RAMM0 | RAMD0 | RAMD1,    PAGE = 0
+   .cinit           : > RAMM0,      PAGE = 0
+   .pinit           : > RAMM0,      PAGE = 0
+   .switch          : > RAMM0,      PAGE = 0
+   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,      PAGE = 1
+   .ebss            : > RAMLS2,     PAGE = 1
+   .econst          : > RAMLS3,     PAGE = 1
+   .esysmem         : > RAMLS3,     PAGE = 1
+   Filter_RegsFile  : > RAMGS0,	    PAGE = 1
+
+   .em1_cs0         : > EMIF1_CS0n, PAGE = 1
+   .em1_cs2         : > EMIF1_CS2n, PAGE = 1
+   .em1_cs3         : > EMIF1_CS3n, PAGE = 1
+   .em1_cs4         : > EMIF1_CS4n, PAGE = 1
+   .em2_cs0         : > EMIF2_CS0n, PAGE = 1
+   .em2_cs2         : > EMIF2_CS2n, PAGE = 1
+
+    /* CLA specific sections */
+   Cla1Prog         : > RAMLS4_5, PAGE=0
+
+   CLADataLS0		: > RAMLS0, PAGE=1
+   CLADataLS1		: > RAMLS1, PAGE=1
+
+   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
+   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
+
+   /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+    ramfuncs    : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+#ifdef CLA_C
+   /* CLA C compiler sections */
+   //
+   // Must be allocated to memory the CLA has write access to
+   //
+   CLAscratch       :
+                     { *.obj(CLAscratch)
+                     . += CLA_SCRATCHPAD_SIZE;
+                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 1
+
+   .scratchpad      : > RAMLS1,       PAGE = 1
+   .bss_cla		    : > RAMLS1,       PAGE = 1
+   .const_cla	    : > RAMLS1,       PAGE = 1
+#endif //CLA_C
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,38 @@
+/* Linker map for Soprano Shared Memory. */
+
+MEMORY
+{
+PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */
+
+
+PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */
+
+    CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+    CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+
+    /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+}
+
+/*
+* ===========================================================================
+* End of file.
+* ===========================================================================
+*/
@@ -0,0 +1,37 @@
+/* Linker map for Soprano Shared Memory. */
+
+MEMORY
+{
+PAGE 0 : /* Program memory. This is a legacy description since the C28 has a unified memory model. */
+
+PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unified memory model. */
+
+	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+    CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+
+    /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+}
+
+/*
+* ===========================================================================
+* End of file.
+* ===========================================================================
+*/
@@ -0,0 +1,103 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1_LS2       : origin = 0x008800, length = 0x001000
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1_LS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAMLS5,    PAGE = 1
+   .econst          : > RAMLS5,    PAGE = 1
+   .esysmem         : > RAMLS5,    PAGE = 1
+   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+    ramfuncs    : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+    /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+
+   /* Allocate IQ math areas: */
+   IQmath			: > RAMLS0,     PAGE = 0            /* Math Code */
+   IQmathTables		: > RAMLS1_LS2, PAGE = 0
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,106 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAMLS5,    PAGE = 1
+   .econst          : > RAMLS5,    PAGE = 1
+   .esysmem         : > RAMLS5,    PAGE = 1
+   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
+
+   ramgs0           : > RAMGS0,    PAGE = 1
+   ramgs1           : > RAMGS1,    PAGE = 1
+   .cio				: > RAMGS2,	   PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+   /* Sine Table */
+   SINTBL			: > RAMGS2,	   PAGE = 1
+
+   /* Data Log */
+   DLOG				: > RAMGS3,    PAGE = 1
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+    /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,89 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+   RAMGS0_2         : origin = 0x00C000, length = 0x003000
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5          : origin = 0x00A800, length = 0x000800
+
+   RAMGS3          : origin = 0x00F000, length = 0x001000
+   RAMGS4          : origin = 0x010000, length = 0x001000
+   RAMGS5          : origin = 0x011000, length = 0x001000
+   RAMGS6          : origin = 0x012000, length = 0x001000
+   RAMGS7          : origin = 0x013000, length = 0x001000
+   RAMGS8          : origin = 0x014000, length = 0x001000
+   RAMGS9          : origin = 0x015000, length = 0x001000
+   RAMGS10         : origin = 0x016000, length = 0x001000
+   RAMGS11         : origin = 0x017000, length = 0x001000
+   RAMGS12         : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13         : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14         : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15         : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >>RAMGS0_2,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAMLS5,    PAGE = 1
+   .econst          : > RAMLS5,    PAGE = 1
+   .esysmem         : > RAMLS5,    PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,97 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMLS5           : origin = 0x00A800, length = 0x000800
+   RAMGS0           : origin = 0x00C000, length = 0x001000
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD        : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1            : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1            : origin = 0x00B800, length = 0x000800
+
+   RAMGS1           : origin = 0x00D000, length = 0x001000
+   RAMGS2_GS4       : origin = 0x00E000, length = 0x003000
+   /*
+   RAMGS2           : origin = 0x00E000, length = 0x001000
+   RAMGS3           : origin = 0x00F000, length = 0x001000
+   RAMGS4           : origin = 0x010000, length = 0x001000
+   */
+   RAMGS5           : origin = 0x011000, length = 0x001000
+   RAMGS6           : origin = 0x012000, length = 0x001000
+   RAMGS7           : origin = 0x013000, length = 0x001000
+   RAMGS8           : origin = 0x014000, length = 0x001000
+   RAMGS9           : origin = 0x015000, length = 0x001000
+   RAMGS10          : origin = 0x016000, length = 0x001000
+   RAMGS11          : origin = 0x017000, length = 0x001000
+   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13          : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+
+   CPU2TOCPU1RAM    : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM    : origin = 0x03FC00, length = 0x000400
+}
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            :>> RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMGS1,    PAGE = 1
+   .ebss            : > RAMGS2_GS4,PAGE = 1
+   .econst          : > RAMGS1,    PAGE = 1
+   .esysmem         : > RAMGS1,    PAGE = 1
+   Filter_RegsFile  : > RAMGS1,	   PAGE = 1
+
+   .sysmem          : > RAMGS1,    PAGE = 1
+   .cio             : > RAMGS1,    PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,99 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS234      		: origin = 0x009000, length = 0x001800
+ //  RAMLS3      		: origin = 0x009800, length = 0x000800
+ //  RAMLS4      		: origin = 0x00A000, length = 0x000800
+    RAMLS5      : origin = 0x00A800, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >> RAMD0 | RAMLS0 | RAMLS1,   PAGE = 0
+   .cinit           : >RAMM0 , PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : >> RAMGS0,    PAGE = 1
+   .econst          : >> RAMLS234,    PAGE = 0
+   .esysmem         : > RAMLS5,    PAGE = 0
+   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
+
+   ramgs0           : > RAMGS0,    PAGE = 1
+   ramgs1           : > RAMGS3,    PAGE = 1
+
+   SINETABLE        : > RAMLS234    PAGE = 0	/* Ram block for SINETABLE data */
+   fsk_corr_lib_data : > RAMGS5,	PAGE = 1	/* Ram block for lib data */
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+    ramfuncs    : > RAMM0      PAGE = 0
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,103 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAMLS5,    PAGE = 1
+   .econst          : > RAMLS5,    PAGE = 1
+   .esysmem         : > RAMLS5,    PAGE = 1
+   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
+
+   ramgs0           : > RAMGS0,    PAGE = 1
+   ramgs1           : > RAMGS1,    PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+    ramfuncs    : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+    /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,97 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x002000
+
+
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS01         : origin = 0x008000, length = 0x001000
+/*   RAMLS1          	: origin = 0x008800, length = 0x000800  */
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3_RAMLS4_RAMLS5      		: origin = 0x009800, length = 0x001800
+/*   RAMLS3      : origin = 0x009800, length = 0x000800  */
+/*   RAMLS4      : origin = 0x00A000, length = 0x000800  */
+/*   RAMLS5      : origin = 0x00A800, length = 0x000800  */
+   
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14     : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15     : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >> RAMGS0 | RAMGS1 | RAMGS2 | RAMGS3 | RAMGS4 | RAMGS5,   PAGE = 0
+   .cio             : > RAMLS3_RAMLS4_RAMLS5, PAGE = 1
+   .sysmem          : > RAMD1, PAGE = 1
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : >> RAMLS01 | RAMLS2 | RAMLS3_RAMLS4_RAMLS5,     PAGE = 1
+   .econst          : > RAMLS3_RAMLS4_RAMLS5,     PAGE = 1
+   .esysmem         : > RAMLS3_RAMLS4_RAMLS5,     PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,121 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5          : origin = 0x00A800, length = 0x000800
+
+   RAMGS0          : origin = 0x00C000, length = 0x001000
+   RAMGS1          : origin = 0x00D000, length = 0x001000
+   RAMGS2          : origin = 0x00E000, length = 0x001000
+   RAMGS3          : origin = 0x00F000, length = 0x001000
+   RAMGS4          : origin = 0x010000, length = 0x001000
+   RAMGS5          : origin = 0x011000, length = 0x001000
+   RAMGS6          : origin = 0x012000, length = 0x001000
+   RAMGS7          : origin = 0x013000, length = 0x001000
+   RAMGS8          : origin = 0x014000, length = 0x001000
+   RAMGS9          : origin = 0x015000, length = 0x001000
+   RAMGS10         : origin = 0x016000, length = 0x001000
+   RAMGS11         : origin = 0x017000, length = 0x001000
+   RAMGS12         : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13         : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS14         : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ 
+   RAMGS15         : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
+   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
+   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
+   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
+   EMIF2_CS0n      : origin = 0x90000000, length = 0x10000000
+   EMIF2_CS2n      : origin = 0x00002000, length = 0x00001000
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,           PAGE = 0
+   .text            : >>RAMM0 | RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,           PAGE = 0
+   .pinit           : > RAMM0,           PAGE = 0
+   .switch          : > RAMM0,           PAGE = 0
+   .reset           : > RESET,           PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,           PAGE = 1
+   .ebss            : > RAMLS5,          PAGE = 1
+   .econst          : > RAMLS5,          PAGE = 1
+   .esysmem         : > RAMLS5,          PAGE = 1
+
+   .farbss          : > EMIF1_CS0n,      PAGE = 1
+   .farconst        : > EMIF1_CS0n,      PAGE = 1
+
+   .em1_cs0         : > EMIF1_CS0n,      PAGE = 1
+   .em1_cs2         : > EMIF1_CS2n,      PAGE = 1
+   .em1_cs3         : > EMIF1_CS3n,      PAGE = 1
+   .em1_cs4         : > EMIF1_CS4n,      PAGE = 1
+   .em2_cs0         : > EMIF2_CS0n,      PAGE = 1
+   .em2_cs2         : > EMIF2_CS2n,      PAGE = 1
+
+   Filter_RegsFile  : > RAMGS0,	         PAGE = 1
+
+   ramgs0           : > RAMGS0,          PAGE = 1
+   ramgs1           : > RAMGS1,          PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,            PAGE = 0
+   #else
+   ramfuncs         : > RAMM0            PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+
+    /* The following section definition are for SDFM examples */
+   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
+   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
+   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
+   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
+   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,75 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000080, length = 0x000380
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          : origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET           : origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAMLS5,     PAGE = 1
+   .econst          : > RAMLS5,     PAGE = 1
+   .esysmem         : > RAMLS5,     PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,83 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000080, length = 0x000380
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0           : origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RESET            : origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   EMIF1_CS0n      : origin = 0x80000000, length = 0x10000000
+   EMIF1_CS2n      : origin = 0x00100000, length = 0x00200000
+   EMIF1_CS3n      : origin = 0x00300000, length = 0x00080000
+   EMIF1_CS4n      : origin = 0x00380000, length = 0x00060000
+
+   RAMLS5          : origin = 0x00A800, length = 0x000800
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+
+   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
+   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,      PAGE = 0
+   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,      PAGE = 0
+   .pinit           : > RAMM0,      PAGE = 0
+   .switch          : > RAMM0,      PAGE = 0
+   .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,      PAGE = 1
+   .ebss            : > RAMLS5,     PAGE = 1
+   .econst          : > RAMLS5,     PAGE = 1
+   .esysmem         : > RAMLS5,     PAGE = 1
+
+   .farbss          : > EMIF1_CS0n, PAGE = 1
+   .farconst        : > EMIF1_CS0n, PAGE = 1
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0       PAGE = 0   
+   #endif
+#endif
+
+   /* The following section definitions are required when using the IPC API Drivers */
+    GROUP : > CPU2TOCPU1RAM, PAGE = 1
+    {
+        PUTBUFFER
+        PUTWRITEIDX
+        GETREADIDX
+    }
+
+    GROUP : > CPU1TOCPU2RAM, PAGE = 1
+    {
+        GETBUFFER :    TYPE = DSECT
+        GETWRITEIDX :  TYPE = DSECT
+        PUTREADIDX :   TYPE = DSECT
+    }
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,92 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000122, length = 0x0002DE
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0          	: origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET           	: origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+}
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAMLS5,     PAGE = 1
+   .econst          : > RAMLS5,     PAGE = 1
+   .esysmem         : > RAMLS5,     PAGE = 1
+   Filter_RegsFile  : > RAMGS0,	   PAGE = 1
+
+   SHARERAMGS0		: > RAMGS0,		PAGE = 1
+   SHARERAMGS1		: > RAMGS1,		PAGE = 1
+   SHARERAMGS2		: > RAMGS2,		PAGE = 1
+   SHARERAMGS3		: > RAMGS3,		PAGE = 1
+   SHARERAMGS4		: > RAMGS4,		PAGE = 1
+   SHARERAMGS5		: > RAMGS5,		PAGE = 1
+   SHARERAMGS6		: > RAMGS6,		PAGE = 1
+   SHARERAMGS7		: > RAMGS7,		PAGE = 1
+   SHARERAMGS8		: > RAMGS8,		PAGE = 1
+   SHARERAMGS9		: > RAMGS9,		PAGE = 1
+   SHARERAMGS10		: > RAMGS10,	PAGE = 1
+   SHARERAMGS11		: > RAMGS11,	PAGE = 1
+   SHARERAMGS12		: > RAMGS12,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   SHARERAMGS13		: > RAMGS13,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   SHARERAMGS14		: > RAMGS14,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   SHARERAMGS15		: > RAMGS15,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,92 @@
+
+MEMORY
+{
+PAGE 0 :
+   /* BEGIN is used for the "boot to SARAM" bootloader mode   */
+
+   BEGIN           	: origin = 0x000000, length = 0x000002
+   RAMM0           	: origin = 0x000080, length = 0x000380
+   RAMD0           	: origin = 0x00B000, length = 0x000800
+   RAMLS0           : origin = 0x008000, length = 0x000800
+   RAMLS1          	: origin = 0x008800, length = 0x000800
+   RAMLS2      		: origin = 0x009000, length = 0x000800
+   RAMLS3      		: origin = 0x009800, length = 0x000800
+   RAMLS4      		: origin = 0x00A000, length = 0x000800
+   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS15          : origin = 0x01B000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RESET            : origin = 0x3FFFC0, length = 0x000002
+
+PAGE 1 :
+
+   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
+   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
+   RAMD1           : origin = 0x00B800, length = 0x000800
+
+   RAMLS5      : origin = 0x00A800, length = 0x000800
+
+   RAMGS0      : origin = 0x00C000, length = 0x001000
+   RAMGS1      : origin = 0x00D000, length = 0x001000
+   RAMGS2      : origin = 0x00E000, length = 0x001000
+   RAMGS3      : origin = 0x00F000, length = 0x001000
+   RAMGS4      : origin = 0x010000, length = 0x001000
+   RAMGS5      : origin = 0x011000, length = 0x001000
+   RAMGS6      : origin = 0x012000, length = 0x001000
+   RAMGS7      : origin = 0x013000, length = 0x001000
+   RAMGS8      : origin = 0x014000, length = 0x001000
+   RAMGS9      : origin = 0x015000, length = 0x001000
+   RAMGS10     : origin = 0x016000, length = 0x001000
+   RAMGS11     : origin = 0x017000, length = 0x001000
+   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
+   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
+}
+
+
+SECTIONS
+{
+   codestart        : > BEGIN,     PAGE = 0
+   .text            : >>RAMD0 |  RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4,   PAGE = 0
+   .cinit           : > RAMM0,     PAGE = 0
+   .pinit           : > RAMM0,     PAGE = 0
+   .switch          : > RAMM0,     PAGE = 0
+   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
+
+   .stack           : > RAMM1,     PAGE = 1
+   .ebss            : > RAMLS5,     PAGE = 1
+   .econst          : > RAMLS5,     PAGE = 1
+   .esysmem         : > RAMLS5,     PAGE = 1
+
+   SHARERAMGS0		: > RAMGS0,		PAGE = 1
+   SHARERAMGS1		: > RAMGS1,		PAGE = 1
+   SHARERAMGS2		: > RAMGS2,		PAGE = 1
+   SHARERAMGS3		: > RAMGS3,		PAGE = 1
+   SHARERAMGS4		: > RAMGS4,		PAGE = 1
+   SHARERAMGS5		: > RAMGS5,		PAGE = 1
+   SHARERAMGS6		: > RAMGS6,		PAGE = 1
+   SHARERAMGS7		: > RAMGS7,		PAGE = 1
+   SHARERAMGS8		: > RAMGS8,		PAGE = 1
+   SHARERAMGS9		: > RAMGS9,		PAGE = 1
+   SHARERAMGS10		: > RAMGS10,	PAGE = 1
+   SHARERAMGS11		: > RAMGS11,	PAGE = 1
+   SHARERAMGS12		: > RAMGS12,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   SHARERAMGS13		: > RAMGS13,	PAGE = 1     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   SHARERAMGS14		: > RAMGS14,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+   SHARERAMGS15		: > RAMGS15,	PAGE = 0     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
+
+#ifdef __TI_COMPILER_VERSION__
+   #if __TI_COMPILER_VERSION__ >= 15009000
+    .TI.ramfunc : {} > RAMM0,      PAGE = 0
+   #else
+   ramfuncs         : > RAMM0      PAGE = 0   
+   #endif
+#endif
+
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,68 @@
+
+/* this linker command file is to be included if user wants to use the DCSM feature on the device
+ * DCSM  means Dual Zone Code Security Module.
+ * This linker command file works as an addendum ot the already existing Flash/RAM linker command file
+ * that the project has.
+ * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file
+ * NOTE - please note fill=0xFFFF, this helps if users include this file in the project by mistake and
+ * doesn't provide the needed proper *_ZoneSelectBlock.asm sources .
+ * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this.
+ *
+ * Once users are confident that they want to program the passwords in OTP, the DSECT section type can be removed.
+ *
+*/
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+
+   /* Z1 OTP.  LinkPointers */
+   DCSM_OTP_Z1_LINKPOINTER   : origin = 0x78000, length = 0x00000C
+   /* Z1 OTP.  PSWDLOCK/RESERVED */
+   DCSM_OTP_Z1_PSWDLOCK	    : origin = 0x78010, length = 0x000004
+   /* Z1 OTP.  CRCLOCK/RESERVED */
+   DCSM_OTP_Z1_CRCLOCK	    : origin = 0x78014, length = 0x000004
+   /* Z1 OTP.  RESERVED/BOOTCTRL */
+   DCSM_OTP_Z1_BOOTCTRL	    : origin = 0x7801C, length = 0x000004
+
+   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
+   /* Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
+   DCSM_ZSEL_Z1_P0	        : origin = 0x78020, length = 0x000010
+
+   /* Z2 OTP.  LinkPointers */
+   DCSM_OTP_Z2_LINKPOINTER	: origin = 0x78200, length = 0x00000C
+   /* Z2 OTP.  GPREG1/GPREG2 */
+   DCSM_OTP_Z2_GPREG	        : origin = 0x7820C, length = 0x000004
+   /* Z2 OTP.  PSWDLOCK/RESERVED */
+   DCSM_OTP_Z2_PSWDLOCK	    : origin = 0x78210, length = 0x000004
+   /* Z2 OTP.  CRCLOCK/RESERVED */
+   DCSM_OTP_Z2_CRCLOCK	    : origin = 0x78214, length = 0x000004
+   /* Z2 OTP.  GPREG3/BOOTCTRL */
+   DCSM_OTP_Z2_BOOTCTRL	    : origin = 0x7821C, length = 0x000004
+
+   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
+   /* Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
+   DCSM_ZSEL_Z2_P0	        : origin = 0x78220, length = 0x000010
+
+}
+
+SECTIONS
+{
+   dcsm_otp_z1_linkpointer 	: > DCSM_OTP_Z1_LINKPOINTER		PAGE = 0, type = DSECT
+   dcsm_otp_z1_pswdlock		: > DCSM_OTP_Z1_PSWDLOCK		PAGE = 0, type = DSECT
+   dcsm_otp_z1_crclock		: > DCSM_OTP_Z1_CRCLOCK			PAGE = 0, type = DSECT
+   dcsm_otp_z1_bootctrl		: > DCSM_OTP_Z1_BOOTCTRL		PAGE = 0, type = DSECT
+   dcsm_zsel_z1				: > DCSM_ZSEL_Z1_P0				PAGE = 0, type = DSECT
+
+   dcsm_otp_z2_linkpointer	: > DCSM_OTP_Z2_LINKPOINTER		PAGE = 0, type = DSECT
+   dcsm_otp_z2_pswdlock		: > DCSM_OTP_Z2_PSWDLOCK		PAGE = 0, type = DSECT
+   dcsm_otp_z2_crclock		: > DCSM_OTP_Z2_CRCLOCK			PAGE = 0, type = DSECT
+   dcsm_otp_z2_bootctrl		: > DCSM_OTP_Z2_BOOTCTRL		PAGE = 0, type = DSECT
+   dcsm_zsel_z2				: > DCSM_ZSEL_Z2_P0				PAGE = 0, type = DSECT
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,44 @@
+
+/* this linker command file is to be included if user wants to use the DCSM feature on the device
+ * DCSM  means Dual Zone Code Security Module.
+ * This linker command file works as an addendum ot the already existing Flash/RAM linker command file
+ * that the project has.
+ * The sections in the *_ZoneSelectBlock.asm source file is linked as per the commands given in the file
+ * NOTEG - please note fill=0xFFFF, this helps if users include this file in the project by mistake and
+ * doesn't provide the needed *_ZoneSelectBlock.asm sources.
+ * Please refer to the Blinky DCSM example in the controlsuite examples for proper usage of this.
+*/
+
+MEMORY
+{
+PAGE 0 :  /* Program Memory */
+
+   /* Part of Z1 OTP.  LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */
+   DCSM_OTP_Z1_P0	: origin = 0x78000, length = 0x000020
+   /* Part of Z2 OTP.  LinkPointers/PSWD LOCK/CRC LOCK/JTAG lock/ Boot Ctrl */
+   DCSM_OTP_Z2_P0	: origin = 0x78200, length = 0x000020
+
+   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
+   /* Part of Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
+   DCSM_ZSEL_Z1_P0	: origin = 0x78020, length = 0x000010
+
+   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
+   /* Part of Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
+   DCSM_ZSEL_Z2_P0	: origin = 0x78220, length = 0x000010
+}
+
+
+SECTIONS
+{
+   dcsm_otp_z1		: > DCSM_OTP_Z1_P0,		PAGE = 0, type = DSECT
+   dcsm_otp_z2		: > DCSM_OTP_Z2_P0,		PAGE = 0, type = DSECT
+
+   dcsm_zsel_z1		: > DCSM_ZSEL_Z1_P0,	PAGE = 0, type = DSECT
+   dcsm_zsel_z2		: > DCSM_ZSEL_Z2_P0,	PAGE = 0, type = DSECT
+}
+
+/*
+//===========================================================================
+// End of file.
+//===========================================================================
+*/
@@ -0,0 +1,415 @@
+//###########################################################################
+//
+// FILE:   can.h
+//
+// TITLE:  Defines and Macros for the CAN controller.
+//
+//###########################################################################
+// $TI Release: F2837xD Support Library v3.05.00.00 $
+// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
+// $Copyright:
+// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+// 
+//   Redistributions of source code must retain the above copyright 
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the 
+//   documentation and/or other materials provided with the   
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef __CAN_H__
+#define __CAN_H__
+
+//*****************************************************************************
+//! \addtogroup can_api
+//! @{
+//*****************************************************************************
+
+//*****************************************************************************
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#define CAN_INDEX_TO_BASE(idx)             ((idx == 0) ? CAN_A_BASE : CAN_B_BASE)
+
+#define CAN_INDEX_TO_MSG_RAM_BASE(idx)     ((idx == 0) ? CAN_A_MSG_RAM : CAN_B_MSG_RAM)
+
+#define CAN_REG_WORD_MASK                  (0xFFFFU)
+
+//****************************************************************************
+//   These are the Defines to select CAN pin muxing when calling the functions
+//  ConfigCanPinMuxing(), ConfigGpioCanA() & ConfigGpioCanB() in F2837x_Can.c
+//****************************************************************************
+#define CAN_A_GPIO4_GPIO5       1   //switch case 1
+#define CAN_A_GPIO19_GPIO18     2   //switch case 2
+#define CAN_A_GPIO31_GPIO30     3   //switch case 3
+#define CAN_A_GPIO37_GPIO36     4   //switch case 4
+#define CAN_A_GPIO63_GPIO62     5   //switch case 5
+#define CAN_A_GPIO71_GPIO70     6   //switch case 6
+
+#define CAN_B_GPIO6_GPIO7       1   //switch case 1
+#define CAN_B_GPIO8_GPIO10      2   //switch case 2
+#define CAN_B_GPIO12_GPIO13     3   //switch case 3
+#define CAN_B_GPIO16_GPIO17     4   //switch case 4
+#define CAN_B_GPIO20_GPIO21     5   //switch case 5
+#define CAN_B_GPIO38_GPIO39     6   //switch case 6
+#define CAN_B_GPIO72_GPIO73     7   //switch case 7
+
+//*****************************************************************************
+// Miscellaneous defines for Message ID Types
+//*****************************************************************************
+
+//*****************************************************************************
+// These are the flags used by the tCANMsgObject.ui32Flags value when calling the
+// CANMessageSet() and CANMessageGet() functions.
+//*****************************************************************************
+
+//! This definition is used with the tCANMsgObject ui32Flags value and indicates
+//! that transmit interrupts should be enabled, or are enabled.
+#define MSG_OBJ_TX_INT_ENABLE           0x00000001
+
+//! This indicates that receive interrupts should be enabled, or are
+//! enabled.
+#define MSG_OBJ_RX_INT_ENABLE           0x00000002
+
+//! This indicates that a message object will use or is using an extended
+//! identifier.
+#define MSG_OBJ_EXTENDED_ID             0x00000004
+
+//! This indicates that a message object will use or is using filtering
+//! based on the object's message identifier.
+#define MSG_OBJ_USE_ID_FILTER           0x00000008
+
+//! This indicates that new data was available in the message object.
+#define MSG_OBJ_NEW_DATA                0x00000080
+
+//! This indicates that data was lost since this message object was last
+//! read.
+#define MSG_OBJ_DATA_LOST               0x00000100
+
+//! This indicates that a message object will use or is using filtering
+//! based on the direction of the transfer.  If the direction filtering is
+//! used, then ID filtering must also be enabled.
+#define MSG_OBJ_USE_DIR_FILTER          (0x00000010 | MSG_OBJ_USE_ID_FILTER)
+
+//! This indicates that a message object will use or is using message
+//! identifier filtering based on the extended identifier.  If the extended
+//! identifier filtering is used, then ID filtering must also be enabled.
+#define MSG_OBJ_USE_EXT_FILTER          (0x00000020 | MSG_OBJ_USE_ID_FILTER)
+
+//! This indicates that a message object is a remote frame.
+#define MSG_OBJ_REMOTE_FRAME            0x00000040
+
+//! This indicates that this message object is part of a FIFO structure and
+//! not the final message object in a FIFO.
+#define MSG_OBJ_FIFO                    0x00000200
+
+//! This indicates that a message object has no flags set.
+#define MSG_OBJ_NO_FLAGS                0x00000000
+
+//*****************************************************************************
+//! This define is used with the flag values to allow checking only status
+//! flags and not configuration flags.
+//*****************************************************************************
+#define MSG_OBJ_STATUS_MASK             (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
+
+//*****************************************************************************
+//! The structure used for encapsulating all the items associated with a CAN
+//! message object in the CAN controller.
+//*****************************************************************************
+typedef struct
+{
+        //! The CAN message identifier used for 11 or 29 bit identifiers.
+        uint32_t ui32MsgID;
+
+        //! The message identifier mask used when identifier filtering is enabled.
+        uint32_t ui32MsgIDMask;
+
+        //! This value holds various status flags and settings specified by
+        //! tCANObjFlags.
+        uint32_t ui32Flags;
+
+        //! This value is the number of bytes of data in the message object.
+        uint32_t ui32MsgLen;
+
+        //! This is a pointer to the message object's data.
+        unsigned char *pucMsgData;
+}
+tCANMsgObject;
+
+//*****************************************************************************
+//! This structure is used for encapsulating the values associated with setting
+//! up the bit timing for a CAN controller.  The structure is used when calling
+//! the CANGetBitTiming and CANSetBitTiming functions.
+//*****************************************************************************
+typedef struct
+{
+        //! This value holds the sum of the Synchronization, Propagation, and Phase
+        //! Buffer 1 segments, measured in time quanta.  The valid values for this
+        //! setting range from 2 to 16.
+        uint16_t  uSyncPropPhase1Seg;
+
+        //! This value holds the Phase Buffer 2 segment in time quanta.  The valid
+        //! values for this setting range from 1 to 8.
+        uint16_t  uPhase2Seg;
+
+        //! This value holds the Resynchronization Jump Width in time quanta.  The
+        //! valid values for this setting range from 1 to 4.
+        uint16_t  uSJW;
+
+        //! This value holds the CAN_CLK divider used to determine time quanta.
+        //! The valid values for this setting range from 1 to 1023.
+        uint16_t  uQuantumPrescaler;
+}
+tCANBitClkParms;
+
+//*****************************************************************************
+//! This data type is used to identify the interrupt status register.  This is
+//! used when calling the CANIntStatus() function.
+//*****************************************************************************
+typedef enum
+{
+        //! Read the CAN interrupt status information.
+        CAN_INT_STS_CAUSE,
+
+        //! Read a message object's interrupt status.
+        CAN_INT_STS_OBJECT
+}
+tCANIntStsReg;
+
+//*****************************************************************************
+//! This data type is used to identify which of several status registers to
+//! read when calling the CANStatusGet() function.
+//*****************************************************************************
+typedef enum
+{
+        //! Read the full CAN controller status.
+        CAN_STS_CONTROL,
+
+        //! Read the full 32-bit mask of message objects with a transmit request
+        //! set.
+        CAN_STS_TXREQUEST,
+
+        //! Read the full 32-bit mask of message objects with new data available.
+        CAN_STS_NEWDAT,
+
+        //! Read the full 32-bit mask of message objects that are enabled.
+        CAN_STS_MSGVAL
+}
+tCANStsReg;
+
+//*****************************************************************************
+// These definitions are used to specify interrupt sources to CANIntEnable()
+// and CANIntDisable().
+//*****************************************************************************
+//! This flag is used to allow a CAN controller to generate error
+//! interrupts.
+#define CAN_INT_ERROR           0x00000008
+
+//! This flag is used to allow a CAN controller to generate status
+//! interrupts.
+#define CAN_INT_STATUS          0x00000004
+
+//! This flag is used to allow a CAN controller to generate interrupts
+//! on interrupt line 0
+#define CAN_INT_IE0             0x00000002
+
+//! This flag is used to allow a CAN controller to generate interrupts
+//! on interrupt line 1
+#define CAN_INT_IE1             0x00020000
+
+// Defined to maintain compatibility with Stellaris Examples
+#define CAN_INT_MASTER          CAN_INT_IE0
+
+//*****************************************************************************
+// These definitions are used to specify the clock source to
+// CANClkSourceSelect()
+//*****************************************************************************
+//! This flag is used to clock the CAN controller Selected CPU SYSCLKOUT
+//! (CPU1.Sysclk or CPU2.Sysclk).
+#define CAN_CLK_CPU_SYSCLKOUT       0 // PERx.SYSCLK (default on reset)
+
+//! This flag is used to clock the CAN controller with the X1/X2 oscillator
+//! clock.
+#define CAN_CLK_EXT_OSC             1 // External Oscillator (XTAL)
+
+//! This flag is used to clock the CAN controller with the clock from
+//! AUXCLKIN (from GPIO)
+#define CAN_CLK_AUXCLKIN            2 // AUXCLKIN (from GPIO)
+
+
+//*****************************************************************************
+//! This definition is used to determine the type of message object that will
+//! be set up via a call to the CANMessageSet() API.
+//*****************************************************************************
+typedef enum
+{
+        //! Transmit message object.
+        MSG_OBJ_TYPE_TX,
+
+        //! Transmit remote request message object
+        MSG_OBJ_TYPE_TX_REMOTE,
+
+        //! Receive message object.
+        MSG_OBJ_TYPE_RX,
+
+        //! Receive remote request message object.
+        MSG_OBJ_TYPE_RX_REMOTE,
+
+        //! Remote frame receive remote, with auto-transmit message object.
+        MSG_OBJ_TYPE_RXTX_REMOTE
+}
+tMsgObjType;
+
+//*****************************************************************************
+// The following enumeration contains all error or status indicators that can
+// be returned when calling the CANStatusGet() function.
+//*****************************************************************************
+//! CAN controller is in local power down mode.
+#define CAN_STATUS_PDA                0x00000400
+
+//! CAN controller has initiated a system wakeup.
+#define CAN_STATUS_WAKE_UP            0x00000200
+
+//! CAN controller has detected a parity error.
+#define CAN_STATUS_PERR               0x00000100
+
+//! CAN controller has entered a Bus Off state.
+#define CAN_STATUS_BUS_OFF            0x00000080
+
+//! CAN controller error level has reached warning level.
+#define CAN_STATUS_EWARN              0x00000040
+
+//! CAN controller error level has reached error passive level.
+#define CAN_STATUS_EPASS              0x00000020
+
+//! A message was received successfully since the last read of this status.
+#define CAN_STATUS_RXOK               0x00000010
+
+//! A message was transmitted successfully since the last read of this
+//! status.
+#define CAN_STATUS_TXOK               0x00000008
+
+//! This is the mask for the last error code field.
+#define CAN_STATUS_LEC_MSK            0x00000007
+
+//! There was no error.
+#define CAN_STATUS_LEC_NONE           0x00000000
+
+//! A bit stuffing error has occurred.
+#define CAN_STATUS_LEC_STUFF          0x00000001
+
+//! A formatting error has occurred.
+#define CAN_STATUS_LEC_FORM           0x00000002
+
+//! An acknowledge error has occurred.
+#define CAN_STATUS_LEC_ACK            0x00000003
+
+//! The bus remained a bit level of 1 for longer than is allowed.
+#define CAN_STATUS_LEC_BIT1           0x00000004
+
+//! The bus remained a bit level of 0 for longer than is allowed.
+#define CAN_STATUS_LEC_BIT0           0x00000005
+
+//! A CRC error has occurred.
+#define CAN_STATUS_LEC_CRC            0x00000006
+
+//*****************************************************************************
+// The following macros are added for the new Global Interrupt EN/FLG/CLR
+// register
+//*****************************************************************************
+//CANINT0 global interrupt bit
+#define CAN_GLOBAL_INT_CANINT0       0x00000001
+
+//CANINT1 global interrupt bit
+#define CAN_GLOBAL_INT_CANINT1       0x00000002
+
+//*****************************************************************************
+// The following macros are missing in hw_can.h because of scripting
+// but driverlib can.c needs them
+//*****************************************************************************
+
+#define CAN_INT_INT0ID_STATUS       0x8000
+
+#define CAN_IF1ARB_STD_ID_S         18
+#define CAN_IF1ARB_STD_ID_M         0x1FFC0000 // Standard Message Identifier
+
+#define CAN_IF2ARB_STD_ID_S         18
+#define CAN_IF2ARB_STD_ID_M         0x1FFC0000 // Standard Message Identifier
+
+//*****************************************************************************
+// API Function prototypes
+//*****************************************************************************
+extern void CANClkSourceSelect(uint32_t ui32Base, uint16_t  ucSource);
+extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *pClkParms);
+extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *pClkParms);
+extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
+                              uint32_t ui32BitRate);
+extern void CANDisable(uint32_t ui32Base);
+extern void CANEnable(uint32_t ui32Base);
+extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
+                          uint32_t *pui32TxCount);
+extern void CANInit(uint32_t ui32Base);
+extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
+extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void CANIntRegister(uint32_t ui32Base, unsigned char ucIntNumber,
+                           void (*pfnHandler)(void));
+extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
+extern void CANIntUnregister(uint32_t ui32Base, unsigned char ucIntNumber);
+extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
+extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
+                          tCANMsgObject *pMsgObject, bool bClrPendingInt);
+extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
+                          tCANMsgObject *pMsgObject, tMsgObjType eMsgType);
+extern bool CANRetryGet(uint32_t ui32Base);
+extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
+extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
+extern void CANGlobalIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void CANGlobalIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void CANGlobalIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern bool CANGlobalIntstatusGet(uint32_t ui32Base, uint32_t ui32IntFlags);
+
+//*****************************************************************************
+// Mark the end of the C bindings section for C++ compilers.
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+//*****************************************************************************
+// Close the Doxygen group.
+//! @}
+//*****************************************************************************
+
+#endif //  __CAN_H__
+
+
@@ -0,0 +1,75 @@
+//###########################################################################
+//
+// FILE:   debug.h
+//
+// TITLE:  Stellaris style debug header. Included for compatability.
+//
+//###########################################################################
+// $TI Release: F2837xD Support Library v3.05.00.00 $
+// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
+// $Copyright:
+// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+// 
+//   Redistributions of source code must retain the above copyright 
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the 
+//   documentation and/or other materials provided with the   
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API.  This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+extern void __error__(char *pcFilename, unsigned long ulLine);
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking.  Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+
+
+#ifdef DEBUG
+#define ASSERT(expr) {                                      \
+                         if(!(expr))                        \
+                         {                                  \
+                             __error__(__FILE__, __LINE__); \
+                         }                                  \
+                     }
+#else
+#define ASSERT(expr)
+#endif
+
+#endif // __DEBUG_H__
+
+
@@ -0,0 +1,411 @@
+//###########################################################################
+//
+// FILE:   interrupt.c
+//
+// TITLE:  Stellaris style wrapper driver for C28x PIE Interrupt Controller.
+//
+//###########################################################################
+// $TI Release: F2837xD Support Library v3.05.00.00 $
+// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
+// $Copyright:
+// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+// 
+//   Redistributions of source code must retain the above copyright 
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the 
+//   documentation and/or other materials provided with the   
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+#include "F28x_Project.h"
+
+#include "inc/hw_types.h"
+#include "driverlib/interrupt.h"
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler.  Whenever an interrupt is
+//! unregisterd this handler takes it place.
+//!
+//! \return None.
+//
+//*****************************************************************************
+__interrupt void IntDefaultHandler(void)
+{
+    asm(" ESTOP0");
+    return;
+}
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! Allows the processor to respond to interrupts.  This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value.  As such, it was
+//! possible to include <tt>interrupt.h</tt> and call this function without
+//! having included <tt>hw_types.h</tt>.  Now that the return is a
+//! <tt>bool</tt>, a compiler error will occur in this case.  The solution
+//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+bool
+IntMasterEnable(void)
+{
+    //
+    // Enable processor interrupts.
+    //
+    return __enable_interrupts() & 0x1;
+}
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! Prevents the processor from receiving interrupts.  This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value.  As such, it was
+//! possible to include <tt>interrupt.h</tt> and call this function without
+//! having included <tt>hw_types.h</tt>.  Now that the return is a
+//! <tt>bool</tt>, a compiler error will occur in this case.  The solution
+//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+bool
+IntMasterDisable(void)
+{
+    //
+    // Disable processor interrupts.
+    //
+    return __disable_interrupts() & 0x1;
+}
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//
+//! Assumes PIE is enabled
+//!
+//! \param ui32Interrupt specifies the interrupt in question.
+//! \param pfnHandler is a pointer to the function to be called.
+//!
+//! This function is used to specify the handler function to be called when the
+//! given interrupt is asserted to the processor.  When the interrupt occurs,
+//! if it is enabled (via IntEnable()), the handler function will be called in
+//! interrupt context.  Since the handler function can pre-empt other code, care
+//! must be taken to protect memory or peripherals that are accessed by the
+//! handler and other non-handler code.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void))
+{
+    EALLOW;
+    //Copy ISR address into PIE table
+    memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &pfnHandler, sizeof(pfnHandler));
+    EDIS;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param ui32Interrupt specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler should be called when the
+//! given interrupt is asserted to the processor.  The interrupt source will be
+//! automatically disabled (via IntDisable()) if necessary.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntUnregister(uint32_t ui32Interrupt)
+{
+    uint32_t temp;
+
+    temp = (uint32_t) IntDefaultHandler;
+
+    EALLOW;
+    //Copy default ISR address into PIE table
+    memcpy((uint16_t *) &PieVectTable + ((ui32Interrupt & 0xFFFF0000) >> 16)*2, (uint16_t *) &temp, sizeof(temp));
+    EDIS;
+}
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller.  Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntEnable(uint32_t ui32Interrupt)
+{
+    uint16_t ui16IntsEnabled;
+
+    ui32Interrupt = ui32Interrupt >> 16;
+    EALLOW;
+    //Ensure that PIE is enabled
+    PieCtrlRegs.PIECTRL.bit.ENPIE=1;
+
+    ui16IntsEnabled = IntMasterDisable();
+
+    if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table
+    {
+        //Enable Individual PIE interrupt
+        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) |= 1 << ((ui32Interrupt-0x20)%8);
+
+        // Wait for any pending interrupts to get to the CPU
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+
+        //Clear the CPU flag
+        IntIFRClear(1 << ((ui32Interrupt - 0x20)/8));
+
+        //Acknowlege any interrupts
+        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8);
+
+        //Enable PIE Group Interrupt
+        IER |= 1 << ((ui32Interrupt - 0x20)/8);
+    }
+    else if (ui32Interrupt >= 0x80) //Upper PIE table
+    {
+        //Enable Individual PIE interrupt
+        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) |= 1 << (((ui32Interrupt-0x80)%8)+8);
+
+        // Wait for any pending interrupts to get to the CPU
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+
+        //Clear the CPU flag
+        IntIFRClear(1 << ((ui32Interrupt - 0x80)/8));
+
+        //Acknowlege any interrupts
+        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8);
+
+        //Enable PIE Group Interrupt
+        IER |= 1 << ((ui32Interrupt - 0x80)/8);
+    }
+    else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT
+    {
+        //Enable PIE Group Interrupt
+        IER |= 1 << (ui32Interrupt - 1);
+    }
+    else
+    {
+        //Other interrupts
+    }
+
+    EDIS;
+
+    //Re-enable interrupts if they were enabled
+    if(!ui16IntsEnabled){
+        IntMasterEnable();
+    }
+}
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param ui32Interrupt specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller.  Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntDisable(uint32_t ui32Interrupt)
+{
+    uint16_t ui16IntsEnabled;
+
+    ui32Interrupt = ui32Interrupt >> 16;
+    EALLOW;
+
+    ui16IntsEnabled = IntMasterDisable();
+
+    if (ui32Interrupt >= 0x20 && ui32Interrupt <= 0x7F) //Lower PIE table
+    {
+        //Disable Individual PIE interrupt
+        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x20)/8))*2) &= ~(1 << ((ui32Interrupt-0x20)%8));
+
+        // Wait for any pending interrupts to get to the CPU
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+
+        //Clear the CPU flag
+        IntIFRClear(1 << ((ui32Interrupt - 0x20)/8));
+
+        //Acknowlege any interrupts
+        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x20)/8);
+    }
+    else if (ui32Interrupt >= 0x80) //Upper PIE table
+    {
+        //Disable Individual PIE interrupt
+        *(uint16_t *)((&PieCtrlRegs.PIEIER1.all) + (((ui32Interrupt-0x80)/8))*2) &= ~(1 << (((ui32Interrupt-0x80)%8)+8));
+
+        // Wait for any pending interrupts to get to the CPU
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+        asm(" nop");
+
+        //Clear the CPU flag
+        IntIFRClear(1 << ((ui32Interrupt - 0x80)/8));
+
+        //Acknowlege any interrupts
+        PieCtrlRegs.PIEACK.all = 1 << ((ui32Interrupt - 0x80)/8);
+    }
+    else if (ui32Interrupt >= 0x0D && ui32Interrupt <= 0x10) //INT13, INT14, DLOGINT, & RTOSINT //Work-around Case
+    {
+        //Disable PIE Group Interrupt
+        IER &= ~(1 << (ui32Interrupt - 1));
+    }
+    else
+    {
+        //Other Interrupts
+    }
+    EDIS;
+
+    //Re-enable interrupts if they were enabled
+    if(!ui16IntsEnabled){
+        IntMasterEnable();
+    }
+}
+
+void IntIFRClear(uint16_t ui16Interrupts)
+{
+    switch(ui16Interrupts){
+    case 0x0001:
+        IFR &= ~0x0001;
+        break;
+    case 0x0002:
+        IFR &= ~0x0002;
+        break;
+    case 0x0004:
+        IFR &= ~0x0004;
+        break;
+    case 0x0008:
+        IFR &= ~0x0008;
+        break;
+    case 0x0010:
+        IFR &= ~0x0010;
+        break;
+    case 0x0020:
+        IFR &= ~0x0020;
+        break;
+    case 0x0040:
+        IFR &= ~0x0040;
+        break;
+    case 0x0080:
+        IFR &= ~0x0080;
+        break;
+    case 0x0100:
+        IFR &= ~0x0100;
+        break;
+    case 0x0200:
+        IFR &= ~0x0200;
+        break;
+    case 0x0400:
+        IFR &= ~0x0400;
+        break;
+    case 0x0800:
+        IFR &= ~0x0800;
+        break;
+    case 0x1000:
+        IFR &= ~0x1000;
+        break;
+    case 0x2000:
+        IFR &= ~0x2000;
+        break;
+    case 0x4000:
+        IFR &= ~0x4000;
+        break;
+    case 0x8000:
+        IFR &= ~0x8000;
+        break;
+    default:
+        break;
+    }
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
@@ -0,0 +1,81 @@
+//###########################################################################
+//
+// FILE:   interrupt.h
+//
+// TITLE:  Stellaris style wrapper driver for C28x PIE Interrupt Controller.
+//
+//###########################################################################
+// $TI Release: F2837xD Support Library v3.05.00.00 $
+// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
+// $Copyright:
+// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+// 
+//   Redistributions of source code must retain the above copyright 
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the 
+//   documentation and/or other materials provided with the   
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+    extern bool IntMasterEnable(void);
+    extern bool IntMasterDisable(void);
+    extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
+    extern void IntUnregister(uint32_t ui32Interrupt);
+    extern void IntEnable(uint32_t ui32Interrupt);
+    extern void IntDisable(uint32_t ui32Interrupt);
+    extern void IntIFRClear(uint16_t ui16Interrupts);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
+
+
@@ -0,0 +1,44 @@
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+// Copyright (c) 2007-2012 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+
+#endif //__ROM_H__
@@ -0,0 +1,107 @@
+//*****************************************************************************
+//
+// rtos_bindings.h - Macros ulIntIDended to aid porting of StellarisWare modules
+//                   for use with an RTOS.
+//
+// Copyright (c) 2012 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
+//
+//*****************************************************************************
+#ifndef RTOS_BINDINGS_H_
+#define RTOS_BINDINGS_H_
+
+#ifdef USE_RTOS
+//*****************************************************************************
+//
+// If an RTOS is in use, implement a header file called "stellaris_rtos.h"
+// which contains RTOS-specific versions of each of the macros defined below
+// and make sure it appears on the include path set when you build your
+// project.
+//
+// Note that there is no default implementation of this header file included
+// in StellarisWare - it is your responsibility to create it specifically for
+// your RTOS.
+//
+//*****************************************************************************
+#include "stellaris_rtos.h"
+
+#else
+//*****************************************************************************
+//
+// When no RTOS is in use, the follow macros compile to either nothing or a
+// minimal implementation that works in a bare-metal environment.
+//
+// Each of these macros must be redefined in stellaris_rtos.h if you are using
+// StellarisWare under an RTOS.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// A simple macro used to yield within polling loops.  In the default, non-RTOS
+// implementation, this compiles to nothing.
+//
+//*****************************************************************************
+#define OS_YIELD()
+
+//*****************************************************************************
+//
+// A simple macro around the SysCtlDelay function.  The parameter is the number
+// of 3 cycle loops to wait before returning (as for SysCtlDelay).  In an RTOS
+// implementation, this could be replaced with an OS delay call with
+// appropriate parameter scaling.
+//
+//*****************************************************************************
+#define OS_DELAY(ul3Cycles) MAP_SysCtlDelay(ul3Cycles)
+
+//*****************************************************************************
+//
+// Wrappers around low level interrupt control functions.  For information
+// on each of these functions, please see the appropriate API documentation
+// for the DriverLib Interrupt driver.
+//
+// The macros defined here represent interrupt-control functions that may be
+// called from within StellarisWare code.  It is expected that application
+// code will use RTOS-specific functions to control interrupt priority, to
+// pend interrupts and to perform runtime vector manipulation.  As a result,
+// no macros are defined to wrap any of these functions from interrupt.c.
+//
+//*****************************************************************************
+#define OS_INT_MASTER_ENABLE() MAP_IntMasterEnable()
+#define OS_INT_MASTER_DISABLE() MAP_IntMasterDisable()
+#define OS_INT_DISABLE(ulIntID) MAP_IntDisable(ulIntID)
+#define OS_INT_ENABLE(ulIntID) MAP_IntEnable(ulIntID)
+
+#endif // USE_RTOS
+
+#endif // RTOS_BINDINGS_H_
@@ -0,0 +1,283 @@
+//###########################################################################
+//
+// FILE:   sysctl.h
+//
+// TITLE:  Stellaris style wrapper driver for F2837x system control.
+//
+//###########################################################################
+// $TI Release: F2837xD Support Library v3.05.00.00 $
+// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
+// $Copyright:
+// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+// 
+//   Redistributions of source code must retain the above copyright 
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the 
+//   documentation and/or other materials provided with the   
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef __SYSCTL_H__
+#define __SYSCTL_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+//*****************************************************************************
+//
+//! \addtogroup sysctl_api
+//! @{
+//
+//*****************************************************************************
+#include "inc/hw_types.h"
+//*****************************************************************************
+//
+//! Defined system clock oscillator source speed.  Adjust this to reflect your
+//! actual clock speed.
+//
+//*****************************************************************************
+#if defined(_LAUNCHXL_F28379D) || defined(_LAUNCHXL_F28377S)
+#define SYSTEM_CLOCK_SPEED      10000000
+#else
+#define SYSTEM_CLOCK_SPEED      20000000
+#endif
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the SysCtlClockSet() API as
+// the ui32Config parameter.
+//
+//*****************************************************************************
+#define SYSCTL_SYSDIV_M         0x00001F80
+#define SYSCTL_SYSDIV_S         0x00000007
+// Only 1 or even values up to 126 are allowed
+#define SYSCTL_SYSDIV(x)        ((((x == 1) ? 0 : (x / 2)) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M)
+
+#define SYSCTL_IMULT_M          0x0000007F
+#define SYSCTL_IMULT_S          0x00000000
+#define SYSCTL_IMULT(x)         (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M)
+
+#define SYSCTL_FMULT_M          0x00006000
+#define SYSCTL_FMULT_S          0x0000000D
+#define SYSCTL_FMULT_0          0x00000000
+#define SYSCTL_FMULT_1_4        0x00002000
+#define SYSCTL_FMULT_1_2        0x00004000
+#define SYSCTL_FMULT_3_4        0x00006000
+
+#define SYSCTL_OSCSRC_M         0x00030000
+#define SYSCTL_OSCSRC_S         0x00000010
+#define SYSCTL_OSCSRC_OSC2      0x00000000
+#define SYSCTL_OSCSRC_XTAL      0x00010000
+#define SYSCTL_OSCSRC_OSC1      0x00020000
+
+#define SYSCTL_LSDIV_M          0x00700000
+#define SYSCTL_LSDIV_S          0x00000014
+// Only 1 or even values up to 14 are allowed
+#define SYSCTL_LSDIV(x)         (((x == 1) ? 0 : (x / 2)) << SYSCTL_LSDIV_S) & SYSCTL_LSDIV_M)
+
+#define SYSCTL_PLL_ENABLE       0x80000000
+#define SYSCTL_PLL_DISABLE      0x00000000
+
+//*****************************************************************************
+//
+// The following are values that can be passed to the
+// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(),
+// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the
+// ui32Peripheral parameter.  The peripherals in the fourth group (upper nibble
+// is 3) can only be used with the SysCtlPeripheralPresent() API.
+//
+//*****************************************************************************
+#define SYSCTL_PERIPH_REG_M             0x0000001F
+#define SYSCTL_PERIPH_REG_S             0x00000000
+
+#define SYSCTL_PERIPH_BIT_M             0x003F0000
+#define SYSCTL_PERIPH_BIT_S             0x00000010
+
+//PCLKCR0
+#define SYSCTL_PERIPH_CLA1              0x00000000
+#define SYSCTL_PERIPH_DMA               0x00020000
+#define SYSCTL_PERIPH_TIMER0            0x00030000
+#define SYSCTL_PERIPH_TIMER1            0x00040000
+#define SYSCTL_PERIPH_TIMER2            0x00050000
+#define SYSCTL_PERIPH_HRPWM             0x00100000
+#define SYSCTL_PERIPH_TBCLKSYNC         0x00120000
+#define SYSCTL_PERIPH_GTBCLKSYNC        0x00130000
+
+//PCLKCR1
+#define SYSCTL_PERIPH_EMIF1             0x00000001
+#define SYSCTL_PERIPH_EMIF2             0x00010001
+
+//PCLKCR2
+#define SYSCTL_PERIPH_EPWM1             0x00000002
+#define SYSCTL_PERIPH_EPWM2             0x00010002
+#define SYSCTL_PERIPH_EPWM3             0x00020002
+#define SYSCTL_PERIPH_EPWM4             0x00030002
+#define SYSCTL_PERIPH_EPWM5             0x00040002
+#define SYSCTL_PERIPH_EPWM6             0x00050002
+#define SYSCTL_PERIPH_EPWM7             0x00060002
+#define SYSCTL_PERIPH_EPWM8             0x00070002
+#define SYSCTL_PERIPH_EPWM9             0x00080002
+#define SYSCTL_PERIPH_EPWM10            0x00090002
+#define SYSCTL_PERIPH_EPWM11            0x000A0002
+#define SYSCTL_PERIPH_EPWM12            0x000B0002
+
+//PCLKCR3
+#define SYSCTL_PERIPH_ECAP1             0x00000003
+#define SYSCTL_PERIPH_ECAP2             0x00010003
+#define SYSCTL_PERIPH_ECAP3             0x00020003
+#define SYSCTL_PERIPH_ECAP4             0x00030003
+#define SYSCTL_PERIPH_ECAP5             0x00040003
+#define SYSCTL_PERIPH_ECAP6             0x00050003
+
+//PCLKCR4
+#define SYSCTL_PERIPH_EQEP1             0x00000004
+#define SYSCTL_PERIPH_EQEP2             0x00010004
+#define SYSCTL_PERIPH_EQEP3             0x00020004
+
+//PCLKCR5
+//Reserved
+
+//PCLKCR6
+#define SYSCTL_PERIPH_SD1               0x00000006
+#define SYSCTL_PERIPH_SD2               0x00010006
+
+//PCLKCR7
+#define SYSCTL_PERIPH_SCI1              0x00000007
+#define SYSCTL_PERIPH_SCI2              0x00010007
+#define SYSCTL_PERIPH_SCI3              0x00020007
+#define SYSCTL_PERIPH_SCI4              0x00030007
+
+//PCLKCR8
+#define SYSCTL_PERIPH_SPI1              0x00000008
+#define SYSCTL_PERIPH_SPI2              0x00010008
+#define SYSCTL_PERIPH_SPI3              0x00020008
+
+//PCLKCR9
+#define SYSCTL_PERIPH_I2C1              0x00000009
+#define SYSCTL_PERIPH_I2C2              0x00010009
+
+//PCLKCR10
+#define SYSCTL_PERIPH_CAN1              0x0000000A
+#define SYSCTL_PERIPH_CAN2              0x0001000A
+
+//PCLKCR11
+#define SYSCTL_PERIPH_MCBSP1            0x0000000B
+#define SYSCTL_PERIPH_MCBSP2            0x0001000B
+#define SYSCTL_PERIPH_USB0              0x0010000B
+
+//PCLKCR12
+#define SYSCTL_PERIPH_UPP1              0x0000000C
+
+//PCLKCR13
+#define SYSCTL_PERIPH_ADC1              0x0000000D
+#define SYSCTL_PERIPH_ADC2              0x0001000D
+#define SYSCTL_PERIPH_ADC3              0x0002000D
+#define SYSCTL_PERIPH_ADC4              0x0003000D
+
+//PCLKCR14
+#define SYSCTL_PERIPH_CMPSS1            0x0000000E
+#define SYSCTL_PERIPH_CMPSS2            0x0001000E
+#define SYSCTL_PERIPH_CMPSS3            0x0002000E
+#define SYSCTL_PERIPH_CMPSS4            0x0003000E
+#define SYSCTL_PERIPH_CMPSS5            0x0004000E
+#define SYSCTL_PERIPH_CMPSS6            0x0005000E
+#define SYSCTL_PERIPH_CMPSS7            0x0006000E
+#define SYSCTL_PERIPH_CMPSS8            0x0007000E
+
+//PCLKCR15
+//Reserved
+
+//PCLKCR16
+#define SYSCTL_PERIPH_BUFFDAC1          0x00000010
+#define SYSCTL_PERIPH_BUFFDAC2          0x00010010
+#define SYSCTL_PERIPH_BUFFDAC3          0x00020010
+
+
+//old
+//#define SYSCTL_PERIPH_UART_A     0x1  // SCI A
+//#define SYSCTL_PERIPH_UART_B     0x2  // SCI B
+//#define SYSCTL_PERIPH_UART_C     0x3  // SCI C
+//#define SYSCTL_PERIPH_UART_D     0x4  // SCI D
+//
+//#define SYSCTL_PERIPH_SPI_A      0x5  // SPI A
+//#define SYSCTL_PERIPH_SPI_B      0x6  // SPI B
+//#define SYSCTL_PERIPH_SPI_C      0x7  // SPI C
+//
+//#define SYSCTL_PERIPH_MCBSP_A    0x8  // McBSP A
+//#define SYSCTL_PERIPH_MCBSP_B    0x9  // McBSP B
+//
+//#define SYSCTL_PERIPH_DMA        0xA  // DMA
+//
+//#define SYSCTL_PERIPH_USB0       0xB  // USBA
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+
+extern uint32_t SysCtlSRAMSizeGet(void);
+extern uint32_t SysCtlFlashSizeGet(void);
+extern void SysCtlPeripheralReset(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral);
+extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral);
+extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral);
+extern void SysCtlDelay(uint32_t ulCount);
+extern uint32_t SysCtlClockGet(uint32_t u32ClockIn);
+extern void SysCtlClockSet(uint32_t ui32Config);
+extern void SysCtlAuxClockSet(uint32_t ui32Config);
+extern uint32_t SysCtlLowSpeedClockGet(uint32_t u32ClockIn);
+extern void SysCtlUSBPLLEnable(void);
+extern void SysCtlUSBPLLDisable(void);
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//****************************************************************************
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSCTL_H__
+
+
@@ -0,0 +1,305 @@
+//###########################################################################
+//
+// FILE:   systick.c
+//
+// TITLE:  Stellaris style wrapper driver for C28x CPU Timer 0.
+//
+//###########################################################################
+// $TI Release: F2837xD Support Library v3.05.00.00 $
+// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
+// $Copyright:
+// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+// 
+//   Redistributions of source code must retain the above copyright 
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the 
+//   documentation and/or other materials provided with the   
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#include "F28x_Project.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_types.h"
+#include "driverlib/debug.h"
+#include "driverlib/interrupt.h"
+#include "driverlib/systick.h"
+
+
+//*****************************************************************************
+//
+//! Initializes the Timer0 Module to act as a system tick
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickInit(void)
+{
+    // CPU Timer 0
+    // Initialize timer period to maximum:
+    CpuTimer0Regs.PRD.all  = 0xFFFFFFFF;
+    // Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
+    CpuTimer0Regs.TPR.all  = 0;
+    CpuTimer0Regs.TPRH.all = 0;
+    // Make sure timer is stopped:
+    CpuTimer0Regs.TCR.bit.TSS = 1;
+    // Reload all counter register with period value:
+    CpuTimer0Regs.TCR.bit.TRB = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This will start the SysTick counter.  If an interrupt handler has been
+//! registered, it will be called when the SysTick counter rolls over.
+//!
+//! \note Calling this function will cause the SysTick counter to (re)commence
+//! counting from its current value.  The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTickPeriodSet().  If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force this.  Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickEnable(void)
+{
+    //
+    // Enable SysTick.
+    //
+    CpuTimer0Regs.TCR.bit.TRB = 1;
+    CpuTimer0Regs.TCR.bit.TSS = 0;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This will stop the SysTick counter.  If an interrupt handler has been
+//! registered, it will no longer be called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickDisable(void)
+{
+    //
+    // Disable SysTick.
+    //
+    StopCpuTimer0();
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This sets the handler to be called when a SysTick interrupt occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+    //
+    // Register the interrupt handler, returning an error if an error occurs.
+    //
+    IntRegister(INT_TINT0, pfnHandler);
+
+    //
+    // Enable the SysTick interrupt.
+    //
+    IntEnable(INT_TINT0);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function will clear the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntUnregister(void)
+{
+    //
+    // Disable the SysTick interrupt.
+    //
+    IntDisable(INT_TINT0);
+
+    //
+    // Unregister the interrupt handler.
+    //
+    IntUnregister(INT_TINT0);
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function will enable the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler does not need to clear the SysTick
+//! interrupt source as this is done automatically by NVIC when the interrupt
+//! handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntEnable(void)
+{
+    //
+    // Enable the SysTick interrupt.
+    //
+    CpuTimer0Regs.TCR.bit.TIE = 1;
+    IntEnable(INT_TINT0);
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function will disable the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntDisable(void)
+{
+    //
+    // Disable the SysTick interrupt.
+    //
+    CpuTimer0Regs.TCR.bit.TIE = 0;
+    IntDisable(INT_TINT0);
+}
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param ui32Period is the number of clock ticks in each period of the SysTick
+//! counter; must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately.  If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written.  Any write to this register clears the SysTick
+//! counter to 0 and will cause a reload with the \e ui32Period supplied here on
+//! the next clock after the SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickPeriodSet(uint32_t ui32Period)
+{
+    //
+    // Check the arguments.
+    //
+    ASSERT((ui32Period > 0) && (ui32Period <= 16777216));
+
+    //
+    // Set the period of the SysTick counter.
+    //
+    CpuTimer0Regs.PRD.all = ui32Period;
+}
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps; this
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+uint32_t
+SysTickPeriodGet(void)
+{
+    //
+    // Return the period of the SysTick counter.
+    //
+    return(CpuTimer0Regs.PRD.all);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter; this will
+//! be a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+uint32_t
+SysTickValueGet(void)
+{
+    //
+    // Return the current value of the SysTick counter.
+    //
+    return(CpuTimer0Regs.TIM.all);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
+
+
@@ -0,0 +1,84 @@
+//###########################################################################
+//
+// FILE:   systick.h
+//
+// TITLE:  Stellaris style wrapper driver for C28x CPU Timer 0.
+//
+//###########################################################################
+// $TI Release: F2837xD Support Library v3.05.00.00 $
+// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
+// $Copyright:
+// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
+//
+// Redistribution and use in source and binary forms, with or without 
+// modification, are permitted provided that the following conditions 
+// are met:
+// 
+//   Redistributions of source code must retain the above copyright 
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the 
+//   documentation and/or other materials provided with the   
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// $
+//###########################################################################
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+    extern void SysTickInit(void);
+    extern void SysTickEnable(void);
+    extern void SysTickDisable(void);
+    extern void SysTickIntRegister(void (*pfnHandler)(void));
+    extern void SysTickIntUnregister(void);
+    extern void SysTickIntEnable(void);
+    extern void SysTickIntDisable(void);
+    extern void SysTickPeriodSet(uint32_t ui32Period);
+    extern uint32_t SysTickPeriodGet(void);
+    extern uint32_t SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSTICK_H__
+
+
--- a/Show More
+++ b/Show More