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Merge pull request #2110 from SummerGGift/add_stm32_new_framework
[bsp][stm32] sync stm32 series bsp and drivers
This commit is contained in:
Bernard Xiong
GitHub
+7
-1
@@ -80,12 +80,18 @@ env:
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- RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f091-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f767-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32f767-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
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# - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
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# - RTT_BSP='upd70f3454' # iar
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# - RTT_BSP='x86' # x86
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+18
-8
@@ -2,21 +2,31 @@
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STM32 系列 BSP 目前支持情况如下表所示：
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| 文件夹名称 | 开发板名称 |
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| BSP 文件夹名称 | 开发板名称 |
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|:------------------------- |:-------------------------- |
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| **F0 系列** | |
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| [stm32f091-nucleo](stm32f091-nucleo/) | ST 官方 stm32f091-nucleo 开发板 |
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| **F1 系列** | |
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| [stm32f103-atk-nano](stm32f103-atk-nano/) | 正点原子 F103 NANO 开发板 |
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| [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/) | 野火 F103 霸道开发板 |
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| **F4 系列** | |
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| [stm32f407-st-discovery](stm32f407-st-discovery/) | ST 官方 stm32f407-discovery 开发板 |
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| [stm32f407-atk-explorer](stm32f407-atk-explorer/) | 正点原子 F407 探索者开发板 |
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| [stm32f429-atk-apollo](stm32f429-atk-apollo/) | 正点原子 F429 阿波罗开发板 |
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| [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板 |
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| [stm32f429-armfly-v6](stm32f429-armfly-v6) | 安富莱 f429-v6 开发板 |
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| **F7 系列** | |
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| [stm32f767-atk-apollo](stm32f767-atk-apollo) | 正点原子 F767 阿波罗开发板 |
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| [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板 |
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| **L4 系列** | |
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| [stm32l475-atk-pandora](stm32l475-atk-pandora/) | 正点原子 L475 潘多拉 IoT 开发板 |
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| [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板 |
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了解每个 BSP 的详细情况可以阅读该 BSP 下的 readme 文件，如需使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档：
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可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：
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| 文档名称 | 简介 |
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| **BSP 使用教程** | **简介** |
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|:-------------------- |:------------------------------------------------- |
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| [BSP 进阶使用指南](docs/BSP进阶使用指南.md) | 介绍如何使用 BSP 提供的高级功能以及添加更多新功能 |
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| [STM32系列BSP添加教程](docs/STM32系列BSP添加教程.md) | 介绍如何添加一个新的 STM32 系列的 BSP |
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| [STM32系列BSP制作规范](docs/STM32系列BSP制作规范.md) | 介绍一个新 STM32 系列 BSP 的制作规范 |
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| [外设驱动使用教程](docs/STM32系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 |
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| [外设驱动介绍与应用](docs/STM32系列驱动介绍.md) | 讲解 STM32 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 |
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| **BSP 制作与提交** | **简介** |
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| [BSP 制作教程](docs/STM32系列BSP制作教程.md) | 讲解 STM32 系列 BSP 的制作方法，以及在制作 BSP 和提交 BSP 时应当遵守的规范 |
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| [外设驱动添加指南](docs/STM32系列外设驱动添加指南.md) | 讲解 BSP 添加更多设备驱动的方法 |
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@@ -0,0 +1,280 @@
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# STM32 系列 BSP 制作教程
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为了让广大开发者更好、更方便地使用 BSP 进行开发，RT-Thread 开发团队重新整理了现有的 STM32 系列的 BSP，推出了新的 BSP 框架。新的 BSP 框架在易用性、移植便利性、驱动完整性、代码规范性等方面都有较大提升，在新的 BSP 框架下进行开发，可以大大提高应用的开发效率。
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和 RT-Thread 以往提供的 BSP 不同，在新的 BSP 文件夹中将不会包含固件库、外设驱动等可以被多个 BSP 引用的代码文件。而是将这些通用的文件统一存放在 Library 文件夹中，通过在特定 BSP 中引用这些文件的方式，来包含 BSP 中所需的库文件或者驱动文件。这种方式不仅大大提高了代码复用率，降低了 BSP 的维护成本，而且可以更方便地给开发者提供更丰富的驱动文件，让开发者可以更容易地找到自己需要的资源。
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新的 BSP 框架还引入了 CubeMX 工具，可以使用该工具来对 BSP 中使用的外设引脚进行配置。CubeMX 工具提供了图形化的配置界面，这种图形化的配置方式对开发者来说更加直观，不仅可以让开发者灵活地配置 BSP 中使用的资源，并且可以让开发者对资源的使用情况一目了然。
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新 BSP 框架的主要特性如下：
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- 提供多系列 BSP 模板，大大降低新 BSP 的添加难度；
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- 每个 BSP 都配有齐全的驱动文件，开发者可以方便地使用所有驱动；
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- 开发者可以使用 CubeMX 工具对 BSP 进行图形化配置；
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## 1. BSP 框架介绍
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BSP 框架结构如下图所示：
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每一个 STM32 系列的 BSP 由三部分组成，分别是通用库、BSP 模板和特定开发板 BSP，下面的表格以 F1 系列 BSP 为例介绍这三个部分：
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|项目|文件夹|说明|
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| - | - | :-- |
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| 通用库 | stm32/libraries | 用于存放 HAL 库以及基于 HAL 库的多系列通用外设驱动文件 |
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| F1 系列 BSP 工程模板 | stm32/libraries/templates/stm32f10x | F1系列 BSP 模板，可以通过修改该模板制作更多 F1系列 BSP |
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| 特定开发板 BSP | stm32/stm32f103-atk-nano | 在 BSP 模板的基础上修改而成 |
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## 2. 知识准备
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制作一个 BSP 的过程就是构建一个新系统的过程，因此想要制作出好用的 BSP，要对 RT-Thread 系统的构建过程有一定了解，需要的知识准备如下所示：
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- 掌握 stm32 系列 BSP 的使用方法
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BSP 的使用方法可以参考《BSP 进阶使用指南》， 外设驱动的添加方法可以参考《stm32 系列外设驱动添加指南》。
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- 了解 scons 工程构建方法
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RT-Thread 使用 scons 作为系统的构建工具，因此了解 scons 的常用命令对制作新 BSP 是基本要求。
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- 了解设备驱动框架
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在 RT-Thread 系统中，应用程序通过设备驱动框架来操作硬件，因此了解设备驱动框架，对添加 BSP 驱动是很重要的。
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- 了解 kconfig 语法
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RT-Thread 系统通过 menuconfig 的方式进行配置，而 menuconfig 中的选项是由 kconfig 文件决定的，因此想要对 RT-Thread 系统进行配置，需要对 kconfig 语法有一定了解。
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- 熟悉 CubeMX 工具的使用
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在新的 stm32 系列 BSP 中利用了 CubeMX 工具对底层硬件进行配置，因此需要了解 CubeMX 工具的使用方法。
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## 3. BSP 制作方法
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本节以制作正点原子 `stm32f103-atk-nano` 开发板的 BSP 为例，讲解如何为一个新的开发板添加 BSP。
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BSP 的制作过程分为如下五个步骤：
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1. 复制通用模板
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2. 使用 CubeMX 工具配置工程
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3. 修改 BSP 中的 Kconfig 文件
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4. 修改构建工程相关文件
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5. 重新生成工程
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在接下来的章节中将会详细介绍这五个步骤，帮助开发者快速创建所需要的 BSP。
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### 3.1 复制通用模板
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制作新 BSP 的第一步是复制一份同系列的 BSP 模板作为基础，通过对 BSP 模板的修改来获得新 BSP。目前提供的 BSP 模板系列如下表所示：
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| 工程模板 | 说明 |
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| ------- | ---- |
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| libraries/templates/stm32f0xx | F0 系列 BSP 模板 |
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| libraries/templates/stm32f10x | F1 系列 BSP 模板 |
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| libraries/templates/stm32f4xx | F4 系列 BSP 模板 |
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| libraries/templates/stm32f7xx | F7 系列 BSP 模板 |
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| libraries/templates/stm32l4xx | L4 系列 BSP 模板 |
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本次示例所用的 F1 系列 BSP 模板文件夹结构如下所示：
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本次制作的 BSP 为 F1 系列，因此拷贝模板文件夹下的 `stm32f10x` 文件夹，并将该文件夹的名称改为 `stm32f103-atk-nano` ，如下图所示：
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在接下来的 BSP 的制作过程中，将会修改 board 文件夹内的配置文件，将 F1 系列的 BSP 模板变成一个适用于正点原子 `stm32f103-atk-nano` 开发板的 BSP ，下表总结了 board 文件夹中需要修改的内容：
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| 项目 | 需要修改的内容说明 |
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|-------------|-------------------------------------------------------|
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| CubeMX_Config （文件夹）| CubeMX 工程 |
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| linker_scripts （文件夹）| BSP 特定的链接脚本 |
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|board.c/h | 系统时钟、GPIO 初始化函数、芯片存储器大小 |
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| Kconfig | 芯片型号、系列、外设资源 |
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| SConscript | 芯片启动文件、目标芯片型号 |
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### 3.2 使用 CubeMX 配置工程
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在制作 BSP 的第二步，需要创建一个基于目标芯片的 CubeMX 工程。默认的 CubeMX 工程在 **CubeMX_Config** 文件夹中，双击打开 `CubeMX_Config.ioc` 工程，如下图所示：
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在 CubeMX 工程中将芯片型号为修改芯片型号为 STM32F103RBTx 。
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#### 3.2.1 生成 CubeMX 工程
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配置系统时钟、外设引脚等，步骤如下图所示：
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1. 打开外部时钟、设置下载方式、打开串口外设：
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2. 配置系统时钟：
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3. 设置项目名称，并在指定地址重新生成 CubeMX 工程：
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最终 CubeMX 生成的工程目录结构如下图所示：
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#### 3.2.2 拷贝初始化函数
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在 **board.c** 文件中存放了函数 `SystemClock_Config()` ，该函数负责初始化系统时钟。当使用 CubeMX 工具对系统时钟重新配置的时候，需要更新这个函数。
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该函数由 CubeMX 工具生成，默认存放在`board/CubeMX_Config/Src/main.c` 文件中。但是该文件并没有被包含到我们的工程中，因此需要将这个函数从 main.c 中拷贝到 board.c 文件中。在整个 BSP 的制作过程中，这个函数是唯一要要拷贝的函数，该函数内容如下所示：
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在 **board.h** 文件中配置了 FLASH 和 RAM 的相关参数，这个文件中需要修改的是 `STM32_FLASH_SIZE` 和 `STM32_SRAM_SIZE` 这两个宏控制的参数。本次制作的 BSP 所用的 STM32F103RBTx 芯片的 flash 大小为 128k，ram 的大小为 20k，因此对该文件作出如下的修改：
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### 3.3 修改 Kconfig 选项
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在本小节中修改 `board/Kconfig` 文件的内容有如下两点：
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- 芯片型号和系列
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- BSP 上的外设支持选项
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芯片型号和系列的修改如下表所示：
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| 宏定义 | 意义 | 格式 |
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| ------------------ | -------- | ------------------ |
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| SOC_STM32F103RB | 芯片型号 | SOC_STM32xxx |
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| SOC_SERIES_STM32F1 | 芯片系列 | SOC_SERIES_STM32xx |
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关于 BSP 上的外设支持选项，一个初次提交的 BSP 仅仅需要支持 GPIO 驱动和串口驱动即可，因此在配置选项中只需保留这两个驱动配置项，如下图所示：
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### 3.4 修改工程构建相关文件
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接下来需要修改用于构建工程相关的文件。
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#### 3.4.1 修改链接脚本
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**linker_scripts** 链接文件如下图所示：
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下面以 MDK 使用的链接脚本 link.sct 为例，演示如何修改链接脚本：
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本次制作 BSP 使用的芯片为 STM32F103RB，FLASH 为 128k，因此修改 LR_IROM1 和 ER_IROM1 的参数为 0x00020000。RAM 的大小为20k， 因此修改 RW_IRAM1 的参数为 0x00005000。这样的修改方式在一般的应用下就够用了，后续如果有特殊要求，则需要按照链接脚本的语法来根据需求修改。
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其他两个链接脚本的文件分别为 iar 使用的 link.icf 和 gcc 编译器使用的 link.lds，修改的方式也是类似的，如下图所示：
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- link.icf 修改内容
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- link.lds 修改内容
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#### 3.4.2 修改构建脚本
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**SConscript** 脚本决定 MDK/IAR 工程的生成以及编译过程中要添加文件。
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在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：
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注意：如果在文件夹中找不到相应系列的 .s 文件，可能是多个系列的芯片重用了相同的启动文件，此时可以在 CubeMX 中生成目标芯片的工程，查看使用了哪个启动文件，然后再修改启动文件名。
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#### 3.4.3 修改工程模板
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**template** 文件是生成 MDK/IAR 工程的模板文件，通过修改该文件可以设置工程中使用的芯片型号以及下载方式。MDK4/MDK5/IAR 的工程模板文件，如下图所示：
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下面以 MDK5 模板的修改为例，介绍如何修改模板配置：
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修改程序下载方式：
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### 3.5 重新生成工程
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重新生成工程需要使用 env 工具。
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#### 3.5.1 重新生成 rt_config.h 文件
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在 env 界面输入命令 menuconfig 对工程进行配置，并生成新的 rt_config.h 文件。如下图所示：
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#### 3.5.2 重新 MDK/IAR 工程
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下面以重新生成 MDK 工程为例，介绍如何重新生成 BSP 工程。
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使用 env 工具输入命令 `scons --target=mdk5` 重新生成工程，如下图所示：
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重新生成工程成功：
|
||||
|
||||
|
||||
|
||||
到这一步为止，新的 BSP 就可以使用了。
|
||||
|
||||
接下来我们可以分别使用命令 `scons --target=mdk4` 和 `scons --target=iar`，来更新 mdk4 和 iar 的工程，使得该 BSP 变成一个完整的，可以提交到 GitHub 的 BSP。
|
||||
|
||||
感谢每一位贡献代码的开发者，RT-Thread 将与你一同成长。
|
||||
|
||||
## 4. 规范
|
||||
|
||||
本章节介绍 RT-Thread STM32 系列 BSP 制作与提交时应当遵守的规范 。开发人员在 BSP 制作完成后，可以根据本规范提出的检查点对制作的 BSP 进行检查，确保 BSP 在提交前有较高的质量 。
|
||||
|
||||
### 1. BSP 制作规范
|
||||
|
||||
STM32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和 IDE 配置。在已有的 STM32 系列 BSP 的模板中，已经根据下列规范对模板进行配置。在制作新 BSP 的过程中，拷贝模板进行修改时，需要注意的是不要修改这些默认的配置。BSP 制作完成后，需要对新制作的 BSP 进行功能测试，功能正常后再进行代码提交。
|
||||
|
||||
下面将详细介绍 BSP 的制作规范。
|
||||
|
||||
#### 工程配置
|
||||
|
||||
- 遵从RT-Thread 编码规范，代码注释风格统一
|
||||
- main 函数功能保持一致
|
||||
- 如果有 LED 的话，main 函数里只放一个 LED 1HZ 闪烁的程序
|
||||
- LED_PIN 定义在 board.h，初始化在 board.c 完成
|
||||
- 在 `rt_hw_board_init` 中需要完成堆的初始化：调用 `rt_system_heap_init`
|
||||
- 默认只初始化 GPIO 驱动和 FinSH 对应的串口驱动，不使用 DMA
|
||||
- 当使能板载外设驱动时，应做到不需要修改代码就能编译下载使用
|
||||
- 提交前应检查 gcc/mdk/iar 三种编译器直接编译或者重新生成后编译是否成功
|
||||
- 使用 dist 功能对 BSP 进行发布，检查使用 dist 命令生成的工程是否可以正常使用
|
||||
|
||||
#### ENV 配置
|
||||
|
||||
- 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND）
|
||||
- BSP 中需要打开调试选项中的断言（宏：RT_DEBUG）
|
||||
- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE）
|
||||
- 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT）
|
||||
- 需要开启 user main 选项（宏：RT_USING_USER_MAIN）
|
||||
- 默认关闭 libc（宏：RT_USING_LIBC）
|
||||
- FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY）
|
||||
|
||||
#### IDE 配置
|
||||
|
||||
- 使能下载代码后自动运行
|
||||
- 使能 C99 支持
|
||||
- 使能 One ELF Setion per Function（MDK）
|
||||
- keil/iar 生成的临时文件分别放到build下的 keil/iar 文件夹下
|
||||
- mdk/gcc/iar 生成 bin 文件名字统一成 rtthread.bin
|
||||
|
||||
### 2. BSP 提交规范
|
||||
|
||||
- 基础 BSP 和驱动应该分开提交
|
||||
- 基础 BSP 包括串口驱动和 GPIO 驱动，能运行 FinSH 控制台
|
||||
- 不同的驱动也要分开提交，方便 review 和合并
|
||||
- 只提交 BSP 必要的文件，删除无关的中间文件
|
||||
- 提交 stm32 不同系列的 Library 库时，请参考 f1/f4 系列的 HAL 库，删除多余库文件
|
||||
- 提交前要对 BSP 进行编译测试，确保在不同编译器下编译正常
|
||||
- 提交前要对 BSP 进行功能测试，确保 BSP 的在提交前符合工程配置章节中的要求
|
||||
@@ -1,35 +0,0 @@
|
||||
# STM32 系列 BSP 制作规范
|
||||
|
||||
本文档为 RT-Thread STM32 系列 BSP 制作规范 ，规定了 STM32 BSP 制作需要遵守的准则和需要实现的基本功能。方便开发者快速完成 BSP 的制作。同时，开发人员在 BSP 制作完成后，也可以使用本规范进行检查。
|
||||
|
||||
## BSP 制作规范
|
||||
|
||||
STM32 BSP 的制作规范分为 3 个方面：工程配置，ENV 配置和 IDE 配置。下面将分别详细介绍这 3 个方面需要准守的准则。
|
||||
|
||||
### 工程配置
|
||||
|
||||
- Main 函数执行的功能要统一
|
||||
- 如果有 LED 的话，main函数里只放一个 LED 1HZ 闪烁的程序
|
||||
- LED_PIN 定义在board.h，初始化在 board.c 完成
|
||||
- 在 `rt_hw_board_init` 中需要完成堆的初始化：调用 `rt_system_heap_init`
|
||||
- 默认只初始化 GPIO 驱动和 FinSH 对应的串口驱动，不使用 DMA
|
||||
- 当使能板载外设驱动时，应做到不需要修改代码就能编译下载使用
|
||||
- 代码注释风格要统一
|
||||
|
||||
### ENV 配置
|
||||
|
||||
- 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND）
|
||||
- BSP 中需要打开调试选项中的断言（宏：RT_DEBUG）
|
||||
- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE）
|
||||
- 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT）
|
||||
- 需要开启 user main 选项（宏：RT_USING_USER_MAIN）
|
||||
- 默认关闭 libc（宏：RT_USING_LIBC）
|
||||
- FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY）
|
||||
|
||||
### IDE 配置
|
||||
|
||||
- 使能下载代码后自动运行
|
||||
- 使能 C99 支持
|
||||
- 使能 One ELF Setion per Function（MDK）
|
||||
- keil/iar 生成的临时文件分别放到build下的 keil/iar 文件夹下
|
||||
- mdk/gcc/iar 生成 bin 文件名字统一成 rtthread.bin
|
||||
@@ -16,7 +16,7 @@
|
||||
|
||||
## 如何使用更多的板载资源
|
||||
|
||||
开发板上一般有很多的板载资源，如 Flash、SD卡、以太网等，但是 BSP 工程默认没有添加对这些外设的支持。如何在工程里添加这些外设的支持呢？这就需要使用 ENV 工具了。下面以在正点原子阿波罗 F429 开发板上开启 SPI Flash 支持为例，一步步的展示如何使用 ENV 工具对 BSP 进行配置。
|
||||
开发板上一般有很多板载资源，如 Flash、SD卡、以太网等，但是 BSP 工程默认没有开启这些外设驱动。RT-Thread 提供了 ENV 工具来开启或关闭 BSP 的外设驱动。下面以在正点原子阿波罗 F429 开发板上开启 SPI Flash 驱动为例，一步步的展示如何使用 ENV 工具对 BSP 进行配置。
|
||||
|
||||
### 1）打开配置工具
|
||||
|
||||
@@ -78,38 +78,10 @@
|
||||
|
||||
|
||||
|
||||
## 如何添加更多的片上资源选项
|
||||
配置完成后重新生成工程，编译下载，在 FinSH 控制台输入 `list_device` 命令，可以看到 I2C1 总线已经启用。
|
||||
|
||||
如果想使用的片上外设是 `片上外设配置菜单` 里没有的，就需要自己添加了。下面以添加 SPI3 的驱动支持为例讲解如何添加更多片上外设支持。
|
||||
|
||||
|
||||
> 没有安装 stm32cubemx 软件的移步 STM32cube中文网：<http://www.stm32cube.com/> ，在 `资源下载` 里下载 stm32cubemx 软件。
|
||||
## 总结
|
||||
|
||||
添加 SPI3 的外设支持需要以下几步：
|
||||
|
||||
### 1）打开 Cube 的工程
|
||||
|
||||
|
||||
|
||||
### 2）配置好 SPI3 的引脚，并生成代码
|
||||
|
||||
按照图中所示步骤操作：
|
||||
|
||||
|
||||
|
||||
### 3）修改 Konfig 文件
|
||||
|
||||
打开board文件夹下的 Konfig 文件，拷贝 SPI2 的配置项，并重命名 SPI2 为 SPI3。
|
||||
|
||||
|
||||
|
||||
### 4）重新配置工程
|
||||
|
||||
经过上一步的修改，此时重新打开 ENV 工具，在 menuconfig 中就会出现添加的 SPI3 的配置项。
|
||||
|
||||
|
||||
|
||||
### 5）生成工程，编译下载
|
||||
|
||||
重新生成工程之后，编译下载到开发板，程序会自动开始运行。输入 `list_device` 命令可以看到 spi3 总线设备已经挂载成功了。
|
||||
|
||||
|
||||
当开发者需要使用未开启的外设时，只要在 ENV 工具中使能相关的外设即可，重新生成的工程中就会添加对应的驱动文件。开发者就可以利用 RT-Thread 提供的驱动开快速开发应用了。
|
||||
@@ -1,167 +0,0 @@
|
||||
# STM32 系列 BSP 添加教程
|
||||
|
||||
为了让广大开发者更好、更方便地使用 BSP 进行开发，RT-Thread 开发团队重新整理了现有的 STM32 系列的 BSP，推出了新的 BSP 框架。新的 BSP 框架在易用性、移植便利性、驱动完整性、代码规范性等方面都有较大提升，在新的 BSP 框架下进行开发，可以大大提高应用的开发效率。
|
||||
|
||||
和 RT-Thread 以往提供的 BSP 不同，在新的 BSP 文件夹中将不会包含固件库、外设驱动等可以被多个 BSP 引用的代码文件。而是将这些通用的文件统一存放在 Library 文件夹中，通过在特定 BSP 中引用这些文件的方式，来包含 BSP 中所需的库文件或者驱动文件。这种方式不仅大大提高了代码复用率，降低了 BSP 的维护成本，而且可以更方便地给开发者提供更丰富的驱动文件，让开发者可以更容易地找到自己需要的资源。
|
||||
|
||||
新的 BSP 框架还引入了 CubeMX 工具，使用该工具来对 BSP 中使用的外设引脚进行配置。CubeMX 工具 提供了图形化的配置界面，这种图形化的配置方式对开发者来说更加直观，不仅可以让开发者灵活地配置 BSP 中使用的资源，并且可以让开发者对资源的使用情况一目了然。
|
||||
|
||||
新 BSP 框架的主要特性如下：
|
||||
|
||||
- 提供多系列 BSP 模板，大大降低新 BSP 的添加难度；
|
||||
- 每个 BSP 都配有齐全的驱动文件，开发者可以方便地使用所有驱动；
|
||||
- 开发者可以使用 CubeMX 工具对 BSP 进行图形化配置；
|
||||
|
||||
## BSP 框架介绍
|
||||
|
||||
BSP 框架结构如下图所示：
|
||||
|
||||
|
||||
|
||||
STM32 BSP 由三部分组成，分别是 (1) 通用库、(2) BSP 模板和 (3) 特定芯片 BSP，下面的表格以 F1 系列 BSP 为例介绍这三个部分：
|
||||
|
||||
|项目|文件夹|说明|
|
||||
| - | - | :-- |
|
||||
| 通用库 | stm32/libraries | 用于存放 HAL 库以及基于 HAL 库的通用驱动文件 |
|
||||
| F1 系列 BSP 工程模板 | stm32/libraries/templates/stm32f10x | F1系列 BSP 模板，通过修改该模板制作更多 F1系列 BSP |
|
||||
| 特定开发板 BSP | stm32/stm32f103-atk-nano | 在 BSP 模板的基础上修改而成 |
|
||||
|
||||
## 新 BSP 添加方法
|
||||
|
||||
本节以添加一个新的名为 `stm32f103-atk-nano` 的 BSP 为例，讲解如何添加一个新的 STM32 系列 BSP。
|
||||
|
||||
新的 BSP 可以通过修改相应系列的 BSP 模板而快速得到，开发者需要修改的文件主要是在 board 文件夹下，下表总结了需要修改的文件内容：
|
||||
|
||||
| 项目 | 需要修改的内容说明 |
|
||||
|-------------|-------------------------------------------------------|
|
||||
| CubeMX_Config （文件夹）| CubeMX 工程 |
|
||||
|board.c/h | 系统时钟、GPIO 初始化函数、芯片 SRAM 大小 |
|
||||
| Kconfig | 芯片型号、系列、外设资源 |
|
||||
| SConscript | 芯片启动文件、目标芯片型号 |
|
||||
| linker_scripts （文件夹）| BSP 特定的链接脚本 |
|
||||
| template.uvprojx ; template.uvproj ; template.ewp | MDK/IAR 工程模板：修改芯片型号、仿真器选项 |
|
||||
|
||||
添加新 BSP 的过程分为如下五个步骤：
|
||||
|
||||
1. 复制通用模板
|
||||
2. 使用 CubeMX 配置工程
|
||||
3. 修改 Kconfig 文件中 BSP 的特定选项
|
||||
4. 修改构建工程相关文件
|
||||
5. 重新生成工程
|
||||
|
||||
在接下来的章节中将会详细介绍这五个步骤，帮助开发者快速创建所需要的 BSP。
|
||||
|
||||
### 复制通用模板
|
||||
|
||||
制作新 BSP 的第一步是复制一份同系列的 BSP 模板作为新 BSP 的基础，目前提供的通用 BSP 模板如下：
|
||||
|
||||
| 工程模板 | 说明 |
|
||||
| ------- | ---- |
|
||||
| libraries/templates/stm32f10x | F1系列芯片模板 |
|
||||
| libraries/templates/stm32f4xx | F4系列芯片模板 |
|
||||
| libraries/templates/stm32f7xx | F7系列芯片模板 |
|
||||
| libraries/templates/stm32l4xx | L4系列芯片模板 |
|
||||
|
||||
拷贝 `stm32/libraries/templates/stm32f10x` 文件夹并改名为 `stm32/stm32f103-atk-nano` 。如下图所示：
|
||||
|
||||
|
||||
|
||||
### 使用 CubeMX 配置工程
|
||||
|
||||
这一步中需要在 **CubeMX_Config** 文件夹下创建一个基于目标芯片的 CubeMX 工程，本次创建示例 BSP 选择的芯片型号为 STM32F103RBTx 。
|
||||
|
||||
#### 重新生成 CubeMX 工程
|
||||
|
||||
配置系统时钟、外设引脚等，步骤如下图所示：
|
||||
|
||||
1. 打开外部时钟、设置下载方式、打开串口外设：
|
||||
|
||||
|
||||
|
||||
2. 配置系统时钟：
|
||||
|
||||
|
||||
|
||||
3. 设置项目名称，并在指定地址重新生成 CubeMX 工程：
|
||||
|
||||
|
||||
|
||||
最终 CubeMX 生成的工程目录结构如下图所示：
|
||||
|
||||
|
||||
|
||||
#### 拷贝初始化函数
|
||||
|
||||
**board.c** 文件中只包含 SystemClock_Config() 和 MX_GPIO_Init() 这两个函数。这两个函数由 CubeMX 工具生成，需要从目录 `board/CubeMX_Config/Src/main.c` 文件中拷贝到 board.c 文件中，如下图所示：
|
||||
|
||||
|
||||
|
||||
**board.h** 文件内 STM32_SRAM_SIZE 大小修改如下图所示：
|
||||
|
||||
|
||||
|
||||
### 修改 Kconfig 选项
|
||||
|
||||
修改 `board/Kconfig` 文件内容，如下图所示：
|
||||
|
||||
|
||||
|
||||
上图中使用的宏定义说明如下所示：
|
||||
|
||||
| 宏定义 | 意义 | 格式 |
|
||||
|-|-|-|
|
||||
| SOC_STM32F103RB | 芯片型号 | SOC_STM32xxx |
|
||||
| SOC_SERIES_STM32F1 | 芯片系列| SOC_SERIES_STM32xx |
|
||||
|
||||
用户可参考这个链接学习 Kconfig语法：(https://blog.csdn.net/jianwen_hi/article/details/53398141)
|
||||
|
||||
### 修改工程构建相关文件
|
||||
接下来需要修改用于构建工程相关的文件。
|
||||
|
||||
#### 修改链接脚本
|
||||
**linker_scripts** 链接文件如下图所示：
|
||||
|
||||
|
||||
|
||||
修改这些文件需要用户掌握链接脚本语法，根据相应的芯片进行修改。
|
||||
|
||||
#### 修改 SConscript 构建脚本
|
||||
**SConscript** 脚本决定 MDK/IAR 工程的生成过程中要添加那些文件。在这一步中需要修改芯片型号以及芯片启动文件的地址，修改内容如下图所示：
|
||||
|
||||
|
||||
|
||||
注意：如果在文件夹中找不到相应系列的 .s 文件，可能是多个系列的芯片重用了相同的启动文件，此时可以在 CubeMX 中生成目标芯片的工程，查看使用了哪个启动文件，然后再修改启动文件名。
|
||||
|
||||
#### 修改工程模板
|
||||
|
||||
**template** 文件是生成 MDK/IAR 工程的模板文件，通过修改该文件可以设置工程中使用的芯片型号以及下载方式。MDK4/MDK5/IAR 的工程模板文件，如下图所示：
|
||||
|
||||
|
||||
|
||||
下面以 MDK5 模板的修改为例，介绍如何修改模板配置：
|
||||
|
||||
|
||||
|
||||
修改程序下载方式：
|
||||
|
||||
|
||||
|
||||
### 重新生成工程
|
||||
|
||||
重新生成工程需要使用 env 工具，在 env 界面输入命令 menuconfig 对工程进行配置，并生成新的 rt_config.h 文件。如下图所示：
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
下面以重新生成 MDK 工程为例，介绍如何重新生成 BSP 工程。
|
||||
|
||||
使用 env 工具输入命令 `scons --target=mdk5` 重新生成工程，如下图所示：
|
||||
|
||||
|
||||
|
||||
重新生成工程成功：
|
||||
|
||||
|
||||
|
||||
到这一步为止，新的 BSP 就制作完毕，可以使用了。
|
||||
@@ -0,0 +1,98 @@
|
||||
# STM32 系列外设驱动添加指南
|
||||
|
||||
## 1. 简介
|
||||
|
||||
本文档是为需要给现有的 STM32 BSP 添加更多外设驱动的开发者准备的。通过阅读本文，开发者可以按照自己的实际情况给现有 BSP 添加自己需要的驱动。
|
||||
|
||||
## 2. 前提要求
|
||||
|
||||
- 熟练使用 ENV 工具，参考：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/rtthread-development-guide/rtthread-tool-manual/env/env-user-manual/)
|
||||
- 熟悉 Kconfig 语法
|
||||
- 熟悉 STM32CubeMX 工具
|
||||
- 对 RT-Thread 设备驱动框架有一定了解
|
||||
|
||||
## 3. 如何添加更多的外设驱动选项
|
||||
|
||||
本章节以添加片上外设驱动为例，讲解如何为 BSP 添加更多可用驱动。如果想使用的片上外设是 `片上外设配置菜单` 里没有的，就需要开发者自己添加了。下面我们将演示如何为 stm32f429-atk-apollo BSP 添加 SPI3 驱动。
|
||||
|
||||
> 没有安装 stm32cubemx 软件的可以访问 STM32cube中文网：<http://www.stm32cube.com/> ，在 `资源下载` 里下载 stm32cubemx 软件。
|
||||
|
||||
阿波罗 BSP 默认只支持 SPI1、SPI2 和 SPI5，是不支持 SPI3 的。开发者如果需要使用 SPI3，则需要自己添加。
|
||||
|
||||
|
||||
|
||||
添加 SPI3 的外设支持需要以下几步：
|
||||
|
||||
### 1）打开 STM32CubeMX 工程
|
||||
|
||||
打开 BSP 的 STM32CubeMX 配置文件。
|
||||
|
||||
|
||||
|
||||
### 2）按原理图配置 SPI3 的引脚，并生成代码
|
||||
|
||||
按图示顺序配置 SPI3，并生成代码。
|
||||
|
||||
|
||||
|
||||
> 为 BSP 添加驱动时，STM32CubeMX 工具可以快速的完成**使能外设**和**配置管脚**的工作。而外设初始化，中断配置，DMA配置等等则由 RT-Thread 提供的驱动文件来完成。也就是说，虽然 STM32CubeMX 生成了多个文件用来初始化外设，但 RT-Thread 只使用了 STM32CubeMX 生成的 `stm32fxx_hal_msp.c` 文件和 `stm32fxx_hal_conf.h` 文件。
|
||||
>
|
||||
> 对于不同的外设驱动，通过 STM32CubeMX 工具配置的内容也不一样。开发者可以参考本文档的附录 [CubeMX配置说明]() 章节来了解不同外设的配置方法。
|
||||
|
||||
### 3）修改 Kconfig 文件
|
||||
|
||||
打开 board 文件夹下的 Konfig 文件，拷贝 SPI2 的配置项，并重命名 SPI2 为 SPI3。
|
||||
|
||||
|
||||
|
||||
### 4）重新配置工程
|
||||
|
||||
经过上一步的修改，此时重新打开 ENV 工具，在 menuconfig 中就会出现添加的 SPI3 的配置项。
|
||||
|
||||
|
||||
|
||||
### 5）生成工程，检查驱动文件
|
||||
|
||||
使用 ENV 重新生成工程并打开，检查原有驱动文件是否支持新添加的驱动（查看是否有新驱动的配置文件，中断函数，DMA配置和中断函数等等），如不支持，需参考现有驱动添加相关的代码。
|
||||
|
||||
|
||||
|
||||
### 6）编译下载
|
||||
|
||||
检查完工程后，编译下载到开发板，程序会自动开始运行。输入 `list_device` 命令，可以看到 spi3 总线已经注册到内核，说明驱动已经添加成功。
|
||||
|
||||
|
||||
|
||||
|
||||
## 4. 注意事项
|
||||
|
||||
- 部分驱动如果没有适配 BSP 所属的 STM32 系列，请等待 RT-Thread 团队更新。
|
||||
- 驱动文件对 STM32 系列的支持情况可以查看 [STM32系列驱动介绍文档](STM32系列驱动介绍文档.md)。
|
||||
- 对于驱动文件或文档说明，有任何建议或者意见，欢迎反馈到 [RT_Thread GitHub](https://github.com/RT-Thread/rt-thread) 网站或 [RT-Thread 官方论坛](https://www.rt-thread.org/qa/forum.php)。
|
||||
|
||||
## 5. 附录
|
||||
|
||||
### 5.1 CubeMX配置说明
|
||||
|
||||
本小节介绍 stm32 系列的 BSP 是如何利用 CubeMX 工具对 BSP 进行配置的。
|
||||
|
||||
就像文档中提到的那样，stm32 系列的 BSP 只利用了 CubeMX 工具生成的 `stm32XXxx_hal_conf.h` 和 `stm32XXxx_hal_msp.c` 文件。在 HAL 库中， `stm32XXxx_hal_conf.h` 文件里提供的宏开关会决定 HAL 库将哪些外设驱动添加到工程中。 而`stm32XXxx_hal_msp.c` 文件中则存放了在 CubeMX 工具中开启的外设驱动的配置代码。
|
||||
|
||||
### 5.2 外设配置总结
|
||||
|
||||
当开发者想要在 BSP 中添加更多驱动时，需要使用 CubeMX 工具来配置这些外设。对于绝大多数驱动的配置，只需要在工具中使能相应的外设即可。但是对于一些复杂的外设，则需要更多的配置内容。下表展示了不同驱动在 CubeMX 工具配置步骤的总结：
|
||||
|
||||
| 序号 | 驱动 | CubeMx 工程中的配置情况（**加粗部分为必做步骤**） |
|
||||
| :--: | :------- | :----------------------------------------------------------- |
|
||||
| 1 | GPIO | 无需任何操作 |
|
||||
| 2 | UART | **开启该外设** ，然后配置所需要的引脚（或者使用默认引脚） |
|
||||
| 3 | SPI | **开启该外设** ，然后配置所需要的引脚（或者使用默认引脚） |
|
||||
| 4 | I2C | 依赖于PIN 驱动，无需任何操作 |
|
||||
| 5 | TIMER | **使能 internal Clock 时钟** |
|
||||
| 7 | PWM | **首先使能 internal Clock 时钟，然后为 channelx 选项选择PWM Generation CHx，** 最后配置所需要的引脚（或者使用默认引脚） |
|
||||
| 8 | ADC | **开启该外设，然后选择使用的通道** |
|
||||
| 9 | RTC | **开启该外设，然后在时钟树状图里将 RTC 选择为 LSE 时钟** |
|
||||
| 10 | Watchdog | **开启该外设** |
|
||||
| 11 | EMAC | **配置 ETH 外设的工作模式（一般为 RMII 模式）** |
|
||||
| 12 | SDRAM | **需要根据板载的 SDRAM 型号配置片选脚，地址线，数据线等** |
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
# 外设驱动介绍与应用
|
||||
|
||||
在 RT-Thread 实时操作系统中，各种各样的设备驱动是通过一套 I/O 设备管理框架来管理的。设备管理框架给上层应用提供了一套标准的设备操作 API，开发者通过调用这些标准设备操作 API，可以高效地完成和底层硬件外设的交互。设备管理框架的结构如下图所示：
|
||||
|
||||
|
||||
|
||||
使用 I/O 设备管理框架开发应用程序，有如下优点：
|
||||
|
||||
- 使用同一套标准的 API 开发应用程序，使应用程序具有更好的移植性
|
||||
- 底层驱动的升级和修改不会影响到上层代码
|
||||
- 驱动和应用程序相互独立，方便多个开发者协同开发
|
||||
|
||||
## 1. 驱动分类介绍
|
||||
|
||||
本小节介绍 BSP 提供的不同类别驱动的概念，对一个 BSP 而言，有如下三类驱动：
|
||||
|
||||
- **板载外设驱动**：指 MCU 之外，开发板上外设，例如 TF 卡、以太网和 LCD 等
|
||||
- **片上外设驱动**：指 MCU 芯片上的外设，例如硬件定时器、ADC 和看门狗等
|
||||
- **扩展模块驱动**：指可以通过扩展接口或者杜邦线连接的开发板的模块，例如 ESP8266 模块
|
||||
|
||||
这三种外设的示意图如下所示：
|
||||
|
||||
|
||||
|
||||
## 2. 外设驱动的使用方法
|
||||
|
||||
当前 RT-Thread 提供的驱动库已经支持 STM32 多个系列的 BSP。点击下表中的驱动名称，即可跳转到对应驱动框架的介绍文档。开发者可以通过阅读相关资料，了解如何在应用开发中通过设备驱动框架来使用这些外设驱动。
|
||||
|
||||
### 2.1 片上外设
|
||||
|
||||
| 序号 | 驱动 | 简介 |
|
||||
| ---- | ------------------------------------------------------------ | ------------------------------------------------ |
|
||||
| 1 | [GPIO](https://www.rt-thread.org/document/site/rtthread-application-note/driver/gpio/an0002-rtthread-driver-gpio/) | 操作 GPIO 管脚 |
|
||||
| 2 | UART | 通过串口收发数据 |
|
||||
| 3 | soft I2C | 通过软件 I2C 收发数据 |
|
||||
| 4 | SPI | 通过 SPI 收发数据 |
|
||||
| 5 | ADC | 测量管脚上的模拟量 |
|
||||
| 6 | SDIO | 通过 SDIO 读写数据 |
|
||||
| 7 | TIMER | 使用硬件定时器实现测量时间和定时执行回调函数功能 |
|
||||
| 8 | PWM | 在特定的管脚输出 PWM 波形 |
|
||||
| 9 | RTC | 设置和读取时间 |
|
||||
| 10 | WDT | 看门狗驱动 |
|
||||
| 11 | QSPI | 通过 SPI（1、2、4线） 收发数据 |
|
||||
|
||||
### 2.2 板载外设
|
||||
|
||||
| 序号 | 驱动 | 简介 |
|
||||
| ---- | ------- | --------------------------------------- |
|
||||
| 1 | SD | 适用于 SPI 接口或 SDIO 接口的 SD(TF) 卡 |
|
||||
| 2 | ETH PHY | 以太网 |
|
||||
| 3 | USB PHY | USB |
|
||||
| 4 | LCD | 显示屏 |
|
||||
|
||||
### 2.3 扩展模块
|
||||
|
||||
| 序号 | 驱动 | 简介 |
|
||||
| ---- | -------- | ---------------------- |
|
||||
| 1 | ESP8266 | 串口转 WIFI 模块 |
|
||||
| 2 | ENC28J60 | SPI 接口的以太网控制器 |
|
||||
|
||||
### 2.4 驱动示例代码
|
||||
|
||||
在 RT-Thread 的 `examples\test` 目录下，有 RT-Thread 提供的基于不同外设驱动的示例代码。在 env 工具中开启 BSP 中要测试的驱动，并将 `examples\test` 中对应的驱动框架测试文件加入工程，即可快速测试 BSP 中提供的驱动。
|
||||
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@@ -33,7 +33,7 @@ if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
|
||||
src += ['drv_soft_i2c.c']
|
||||
|
||||
if GetDepend('RT_USING_LWIP'):
|
||||
src += ['drv_emac.c']
|
||||
src += ['drv_eth.c']
|
||||
|
||||
if GetDepend(['RT_USING_ADC']):
|
||||
src += Glob('drv_adc.c')
|
||||
@@ -43,13 +43,16 @@ if GetDepend('BSP_USING_SDRAM'):
|
||||
|
||||
if GetDepend('BSP_USING_ONCHIP_RTC'):
|
||||
src += ['drv_rtc.c']
|
||||
|
||||
|
||||
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
|
||||
src += ['drv_flash/drv_flash_f0.c']
|
||||
|
||||
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
|
||||
src += ['drv_flash/drv_flash_f1.c']
|
||||
|
||||
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
|
||||
src += ['drv_flash/drv_flash_f4.c']
|
||||
|
||||
|
||||
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
|
||||
src += ['drv_flash/drv_flash_f7.c']
|
||||
|
||||
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-24 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_CONFIG
|
||||
#define ADC1_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1, \
|
||||
.Init.Resolution = ADC_RESOLUTION_12B, \
|
||||
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
|
||||
.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD, \
|
||||
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
|
||||
.Init.LowPowerAutoWait = DISABLE, \
|
||||
.Init.LowPowerAutoPowerOff = DISABLE, \
|
||||
.Init.ContinuousConvMode = DISABLE, \
|
||||
.Init.DiscontinuousConvMode = ENABLE, \
|
||||
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
|
||||
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
|
||||
.Init.DMAContinuousRequests = ENABLE, \
|
||||
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
|
||||
}
|
||||
#endif /* ADC1_CONFIG */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-24 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __PWM_CONFIG_H__
|
||||
#define __PWM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef BSP_USING_PWM2
|
||||
#ifndef PWM2_CONFIG
|
||||
#define PWM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.name = "pwm2", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM2_CONFIG */
|
||||
#endif /* BSP_USING_PWM2 */
|
||||
|
||||
#ifdef BSP_USING_PWM3
|
||||
#ifndef PWM3_CONFIG
|
||||
#define PWM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.name = "pwm3", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM3_CONFIG */
|
||||
#endif /* BSP_USING_PWM3 */
|
||||
|
||||
#ifdef BSP_USING_PWM4
|
||||
#ifndef PWM4_CONFIG
|
||||
#define PWM4_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM4, \
|
||||
.name = "pwm4", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM4_CONFIG */
|
||||
#endif /* BSP_USING_PWM4 */
|
||||
|
||||
#ifdef BSP_USING_PWM5
|
||||
#ifndef PWM5_CONFIG
|
||||
#define PWM5_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM5, \
|
||||
.name = "pwm5", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM5_CONFIG */
|
||||
#endif /* BSP_USING_PWM5 */
|
||||
|
||||
#endif /* __PWM_CONFIG_H__ */
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 SummerGift change to new framework
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
.dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \
|
||||
.dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \
|
||||
.dma_rx.Instance = DMA1_Channel2, \
|
||||
.dma_rx.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
|
||||
.dma_tx.Instance = DMA1_Channel3, \
|
||||
.dma_tx.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
|
||||
}
|
||||
|
||||
#define SPI1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
|
||||
#define SPI1_DMA_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-24 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __TIM_CONFIG_H__
|
||||
#define __TIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifndef TIM_DEV_INFO_CONFIG
|
||||
#define TIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 2000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = HWTIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_TIM14
|
||||
#ifndef TIM14_CONFIG
|
||||
#define TIM14_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM14, \
|
||||
.tim_irqn = TIM14_IRQn, \
|
||||
.name = "timer14", \
|
||||
}
|
||||
#endif /* TIM14_CONFIG */
|
||||
#endif /* BSP_USING_TIM14 */
|
||||
|
||||
#ifdef BSP_USING_TIM16
|
||||
#ifndef TIM16_CONFIG
|
||||
#define TIM16_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM16, \
|
||||
.tim_irqn = TIM16_IRQn, \
|
||||
.name = "timer16", \
|
||||
}
|
||||
#endif /* TIM16_CONFIG */
|
||||
#endif /* BSP_USING_TIM16 */
|
||||
|
||||
#ifdef BSP_USING_TIM17
|
||||
#ifndef TIM17_CONFIG
|
||||
#define TIM17_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM17, \
|
||||
.tim_irqn = TIM17_IRQn, \
|
||||
.name = "timer17", \
|
||||
}
|
||||
#endif /* TIM17_CONFIG */
|
||||
#endif /* BSP_USING_TIM17 */
|
||||
|
||||
#endif /* __TIM_CONFIG_H__ */
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = USART1, \
|
||||
.irq_type = USART1_IRQn, \
|
||||
.dma.Instance = DMA1_Channel3, \
|
||||
.dma_rcc = RCC_AHBENR_DMA1EN, \
|
||||
.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
|
||||
}
|
||||
|
||||
#define USART1_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = USART2, \
|
||||
.irq_type = USART2_IRQn, \
|
||||
.dma.Instance = DMA1_Channel3, \
|
||||
.dma_rcc = RCC_AHBENR_DMA1EN, \
|
||||
.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
|
||||
}
|
||||
|
||||
#define USART2_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
|
||||
#endif /* UART2_CONFIG */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#endif /* __UART_CONFIG_H__ */
|
||||
@@ -26,8 +26,6 @@
|
||||
.dma_tx.dma_irq = DMA2_Channel4_IRQn, \
|
||||
}
|
||||
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Channel4_IRQHandler
|
||||
#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
|
||||
#endif
|
||||
|
||||
#endif /*__SDIO_CONFIG_H__ */
|
||||
|
||||
@@ -28,8 +28,6 @@
|
||||
.dma_tx.dma_irq = DMA2_Stream6_IRQn, \
|
||||
}
|
||||
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
|
||||
#define SPI1_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
|
||||
#endif
|
||||
|
||||
#endif /*__SDIO_CONFIG_H__ */
|
||||
|
||||
@@ -61,13 +61,13 @@
|
||||
.dma_rx.Instance = DMA1_Stream0, \
|
||||
.dma_rx.channel = DMA_CHANNEL_0, \
|
||||
.dma_rx.dma_irq = DMA1_Stream0_IRQn, \
|
||||
.dma_tx.Instance = DMA1_Stream2, \
|
||||
.dma_tx.Instance = DMA1_Stream5, \
|
||||
.dma_tx.channel = DMA_CHANNEL_0, \
|
||||
.dma_tx.dma_irq = DMA1_Stream2_IRQn, \
|
||||
.dma_tx.dma_irq = DMA1_Stream5_IRQn, \
|
||||
}
|
||||
|
||||
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
|
||||
#define SPI3_DMA_TX_IRQHandler DMA1_Stream2_IRQHandler
|
||||
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI4
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-22 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = QUADSPI, \
|
||||
.Init.FifoThreshold = 4, \
|
||||
.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
|
||||
.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = DMA2_Stream7, \
|
||||
.Init.Channel = DMA_CHANNEL_3, \
|
||||
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
|
||||
.Init.PeriphInc = DMA_PINC_DISABLE, \
|
||||
.Init.MemInc = DMA_MINC_ENABLE, \
|
||||
.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
|
||||
.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \
|
||||
.Init.Mode = DMA_NORMAL, \
|
||||
.Init.Priority = DMA_PRIORITY_LOW \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
|
||||
#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE()
|
||||
#define QSPI_IRQn QUADSPI_IRQn
|
||||
#define QSPI_DMA_IRQn DMA2_Stream7_IRQn
|
||||
#define QSPI_IRQHandler QUADSPI_IRQHandler
|
||||
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
|
||||
|
||||
#endif /* __QSPI_CONFIG_H__ */
|
||||
@@ -28,8 +28,6 @@
|
||||
.dma_tx.dma_irq = DMA2_Stream6_IRQn, \
|
||||
}
|
||||
|
||||
#define SPI1_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
|
||||
#define SPI1_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
|
||||
#endif
|
||||
|
||||
#endif /*__SDIO_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-22 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = QUADSPI, \
|
||||
.Init.FifoThreshold = 4, \
|
||||
.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
|
||||
.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = DMA1_Channel5, \
|
||||
.Init.Request = DMA_REQUEST_5, \
|
||||
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
|
||||
.Init.PeriphInc = DMA_PINC_DISABLE, \
|
||||
.Init.MemInc = DMA_MINC_ENABLE, \
|
||||
.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
|
||||
.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \
|
||||
.Init.Mode = DMA_NORMAL, \
|
||||
.Init.Priority = DMA_PRIORITY_LOW \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
|
||||
#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE()
|
||||
#define QSPI_IRQn QUADSPI_IRQn
|
||||
#define QSPI_DMA_IRQn DMA1_Channel5_IRQn
|
||||
#define QSPI_IRQHandler QUADSPI_IRQHandler
|
||||
#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
|
||||
|
||||
#endif /* __QSPI_CONFIG_H__ */
|
||||
@@ -127,7 +127,7 @@ static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
|
||||
case 17:
|
||||
stm32_channel = ADC_CHANNEL_17;
|
||||
break;
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
case 18:
|
||||
stm32_channel = ADC_CHANNEL_18;
|
||||
break;
|
||||
@@ -149,7 +149,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
|
||||
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
if (channel <= 17)
|
||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
if (channel <= 18)
|
||||
#endif
|
||||
{
|
||||
@@ -160,13 +160,15 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
LOG_E("ADC channel must be between 0 and 17.");
|
||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
LOG_E("ADC channel must be between 0 and 18.");
|
||||
#endif
|
||||
return -RT_ERROR;
|
||||
}
|
||||
ADC_ChanConf.Rank = 1;
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
#if defined(SOC_SERIES_STM32F0)
|
||||
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
|
||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
|
||||
@@ -186,7 +188,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
|
||||
HAL_ADC_Start(stm32_adc_handler);
|
||||
|
||||
/* Wait for the ADC to convert */
|
||||
HAL_ADC_PollForConversion(stm32_adc_handler, 10);
|
||||
HAL_ADC_PollForConversion(stm32_adc_handler, 100);
|
||||
|
||||
/* get ADC value */
|
||||
*value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
|
||||
|
||||
@@ -95,6 +95,16 @@ void _Error_Handler(char *s, int num)
|
||||
*/
|
||||
RT_WEAK void rt_hw_board_init()
|
||||
{
|
||||
#ifdef SCB_EnableICache
|
||||
/* Enable I-Cache---------------------------------------------------------*/
|
||||
SCB_EnableICache();
|
||||
#endif
|
||||
|
||||
#ifdef SCB_EnableDCache
|
||||
/* Enable D-Cache---------------------------------------------------------*/
|
||||
SCB_EnableDCache();
|
||||
#endif
|
||||
|
||||
/* HAL_Init() function is called at the beginning of the program */
|
||||
HAL_Init();
|
||||
|
||||
@@ -102,9 +112,6 @@ RT_WEAK void rt_hw_board_init()
|
||||
SystemClock_Config();
|
||||
rt_hw_systick_init();
|
||||
|
||||
/* Hardware GPIO initialization */
|
||||
MX_GPIO_Init();
|
||||
|
||||
/* Heap initialization */
|
||||
#if defined(RT_USING_HEAP)
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 SummerGift change to new framework
|
||||
* 2018-10-30 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
@@ -14,7 +14,13 @@
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
#if defined(SOC_SERIES_STM32F0)
|
||||
#include "f0/uart_config.h"
|
||||
#include "f0/spi_config.h"
|
||||
#include "f0/tim_config.h"
|
||||
#include "f0/pwm_config.h"
|
||||
#include "f0/adc_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
#include "f1/uart_config.h"
|
||||
#include "f1/spi_config.h"
|
||||
#include "f1/adc_config.h"
|
||||
@@ -31,6 +37,7 @@
|
||||
#elif defined(SOC_SERIES_STM32F7)
|
||||
#include "f7/uart_config.h"
|
||||
#include "f7/spi_config.h"
|
||||
#include "f7/qspi_config.h"
|
||||
#include "f7/adc_config.h"
|
||||
#include "f7/tim_config.h"
|
||||
#include "f7/sdio_config.h"
|
||||
@@ -38,6 +45,7 @@
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
#include "l4/uart_config.h"
|
||||
#include "l4/spi_config.h"
|
||||
#include "l4/qspi_config.h"
|
||||
#include "l4/adc_config.h"
|
||||
#include "l4/tim_config.h"
|
||||
#include "l4/pwm_config.h"
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
|
||||
#if defined(SOC_SERIES_STM32F0) || (SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
|
||||
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
||||
|
||||
+130
-89
@@ -6,12 +6,14 @@
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-19 SummerGift first version
|
||||
* 2018-12-25 zylx fix some bugs
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_config.h"
|
||||
#include <netif/ethernetif.h>
|
||||
#include "lwipopts.h"
|
||||
#include "drv_eth.h"
|
||||
|
||||
/*
|
||||
* Emac driver uses CubeMX tool to generate emac and phy's configuration,
|
||||
@@ -32,11 +34,12 @@ struct rt_stm32_eth
|
||||
/* inherit from ethernet device */
|
||||
struct eth_device parent;
|
||||
|
||||
/* interface address info. */
|
||||
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
|
||||
|
||||
uint32_t ETH_Speed; /*!< @ref ETH_Speed */
|
||||
uint32_t ETH_Mode; /*!< @ref ETH_Duplex_Mode */
|
||||
/* interface address info, hw address */
|
||||
rt_uint8_t dev_addr[MAX_ADDR_LEN];
|
||||
/* ETH_Speed */
|
||||
uint32_t ETH_Speed;
|
||||
/* ETH_Duplex_Mode */
|
||||
uint32_t ETH_Mode;
|
||||
};
|
||||
|
||||
static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
|
||||
@@ -50,7 +53,7 @@ static struct rt_semaphore tx_wait;
|
||||
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
|
||||
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
|
||||
{
|
||||
unsigned char *buf = (unsigned char*)ptr;
|
||||
unsigned char *buf = (unsigned char *)ptr;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < buflen; i += 16)
|
||||
@@ -73,35 +76,34 @@ static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
|
||||
#endif
|
||||
|
||||
extern void phy_reset(void);
|
||||
/* EMAC initialization function */
|
||||
/* EMAC initialization function */
|
||||
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
|
||||
{
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
|
||||
phy_reset();
|
||||
|
||||
/* ETHERNET Configuration --------------------------------------------------*/
|
||||
/* ETHERNET Configuration */
|
||||
EthHandle.Instance = ETH;
|
||||
EthHandle.Init.MACAddr = (rt_uint8_t*)&stm32_eth_device.dev_addr[0];
|
||||
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
|
||||
EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
|
||||
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;
|
||||
EthHandle.Init.Speed = ETH_SPEED_100M;
|
||||
EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
||||
EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
||||
EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
||||
EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
|
||||
//EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
|
||||
EthHandle.Init.PhyAddress = EXTERNAL_PHY_ADDRESS;
|
||||
|
||||
HAL_ETH_DeInit(&EthHandle);
|
||||
|
||||
/* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
|
||||
if (HAL_ETH_Init(&EthHandle) == HAL_OK)
|
||||
if (HAL_ETH_Init(&EthHandle) != HAL_OK)
|
||||
{
|
||||
LOG_D("emac hardware init sucess");
|
||||
LOG_E("eth hardware init failed");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("emac hardware init faild");
|
||||
LOG_D("eth hardware init success");
|
||||
}
|
||||
|
||||
/* Initialize Tx Descriptors list: Chain Mode */
|
||||
@@ -110,6 +112,10 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
|
||||
/* Initialize Rx Descriptors list: Chain Mode */
|
||||
HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, Rx_Buff, ETH_RXBUFNB);
|
||||
|
||||
/* ETH interrupt Init */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x07, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable MAC and DMA transmission and reception */
|
||||
if (HAL_ETH_Start(&EthHandle) == HAL_OK)
|
||||
{
|
||||
@@ -117,13 +123,10 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("emac hardware start faild");
|
||||
LOG_E("emac hardware start faild");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
/* ETH interrupt Init */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x07, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
@@ -139,14 +142,14 @@ static rt_err_t rt_stm32_eth_close(rt_device_t dev)
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
|
||||
{
|
||||
LOG_D("emac read");
|
||||
rt_set_errno(-RT_ENOSYS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
|
||||
{
|
||||
LOG_D("emac write");
|
||||
rt_set_errno(-RT_ENOSYS);
|
||||
@@ -155,11 +158,11 @@ static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void*
|
||||
|
||||
static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
switch(cmd)
|
||||
switch (cmd)
|
||||
{
|
||||
case NIOCTL_GADDR:
|
||||
/* get mac address */
|
||||
if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
|
||||
if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
|
||||
else return -RT_ERROR;
|
||||
break;
|
||||
|
||||
@@ -172,7 +175,7 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
|
||||
|
||||
/* ethernet device interface */
|
||||
/* transmit data*/
|
||||
rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||
rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
|
||||
{
|
||||
rt_err_t ret = RT_ERROR;
|
||||
HAL_StatusTypeDef state;
|
||||
@@ -204,12 +207,12 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||
}
|
||||
|
||||
/* copy frame from pbufs to driver buffers */
|
||||
for(q = p; q != NULL; q = q->next)
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
/* Is this buffer available? If not, goto error */
|
||||
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||
if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||
{
|
||||
LOG_D("buffer not valid");
|
||||
LOG_E("buffer not valid");
|
||||
ret = ERR_USE;
|
||||
goto error;
|
||||
}
|
||||
@@ -219,18 +222,18 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||
payloadoffset = 0;
|
||||
|
||||
/* Check if the length of data to copy is bigger than Tx buffer size*/
|
||||
while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
|
||||
while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
|
||||
{
|
||||
/* Copy data to Tx buffer*/
|
||||
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
|
||||
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
|
||||
|
||||
/* Point to next descriptor */
|
||||
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
|
||||
|
||||
/* Check if the buffer is available */
|
||||
if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||
if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||
{
|
||||
LOG_D("dma tx desc buffer is not valid");
|
||||
LOG_E("dma tx desc buffer is not valid");
|
||||
ret = ERR_USE;
|
||||
goto error;
|
||||
}
|
||||
@@ -244,7 +247,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||
}
|
||||
|
||||
/* Copy the remaining bytes */
|
||||
memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
|
||||
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
|
||||
bufferoffset = bufferoffset + byteslefttocopy;
|
||||
framelength = framelength + byteslefttocopy;
|
||||
}
|
||||
@@ -256,12 +259,11 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||
/* Prepare transmit descriptors to give to DMA */
|
||||
/* TODO Optimize data send speed*/
|
||||
LOG_D("transmit frame lenth :%d", framelength);
|
||||
rt_thread_mdelay(1);
|
||||
|
||||
state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
|
||||
if (state != HAL_OK)
|
||||
{
|
||||
LOG_D("eth transmit frame faild: %d", state);
|
||||
LOG_E("eth transmit frame faild: %d", state);
|
||||
}
|
||||
|
||||
ret = ERR_OK;
|
||||
@@ -324,16 +326,16 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
|
||||
{
|
||||
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||
bufferoffset = 0;
|
||||
for(q = p; q != NULL; q = q->next)
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
byteslefttocopy = q->len;
|
||||
payloadoffset = 0;
|
||||
|
||||
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
|
||||
while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
|
||||
while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
|
||||
{
|
||||
/* Copy data to pbuf */
|
||||
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
|
||||
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
|
||||
|
||||
/* Point to next descriptor */
|
||||
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
||||
@@ -344,7 +346,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
|
||||
bufferoffset = 0;
|
||||
}
|
||||
/* Copy remaining data in pbuf */
|
||||
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
|
||||
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
|
||||
bufferoffset = bufferoffset + byteslefttocopy;
|
||||
}
|
||||
}
|
||||
@@ -399,41 +401,41 @@ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
rt_err_t result;
|
||||
result = eth_device_ready(&(stm32_eth_device.parent));
|
||||
if( result != RT_EOK )
|
||||
LOG_D("RX err = %d", result );
|
||||
if (result != RT_EOK)
|
||||
LOG_E("RX err = %d", result);
|
||||
}
|
||||
|
||||
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
LOG_D("eth err");
|
||||
LOG_E("eth err");
|
||||
}
|
||||
|
||||
/* PHY: LAN8720 */
|
||||
static uint8_t phy_speed = 0;
|
||||
#define PHY_LINK_MASK (1<<0)
|
||||
#define PHY_100M_MASK (1<<1)
|
||||
#define PHY_DUPLEX_MASK (1<<2)
|
||||
static void phy_monitor_thread_entry(void *parameter)
|
||||
{
|
||||
uint8_t phy_addr = 0xFF;
|
||||
uint8_t phy_speed_new = 0;
|
||||
rt_uint32_t status = 0;
|
||||
|
||||
/* phy search */
|
||||
rt_uint32_t i, temp;
|
||||
for(i=0; i<=0x1F; i++)
|
||||
for (i = 0; i <= 0x1F; i++)
|
||||
{
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, 0x02, (uint32_t *)&temp);
|
||||
EthHandle.Init.PhyAddress = i;
|
||||
|
||||
if( temp != 0xFFFF )
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ID1_REG, (uint32_t *)&temp);
|
||||
|
||||
if (temp != 0xFFFF && temp != 0x00)
|
||||
{
|
||||
phy_addr = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(phy_addr == 0xFF)
|
||||
if (phy_addr == 0xFF)
|
||||
{
|
||||
LOG_D("phy not probe!\r\n");
|
||||
LOG_E("phy not probe!\r\n");
|
||||
return;
|
||||
}
|
||||
else
|
||||
@@ -443,47 +445,49 @@ static void phy_monitor_thread_entry(void *parameter)
|
||||
|
||||
/* RESET PHY */
|
||||
LOG_D("RESET PHY!");
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BCR, PHY_RESET);
|
||||
rt_thread_delay(RT_TICK_PER_SECOND * 2);
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BCR, PHY_AUTONEGOTIATION);
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
|
||||
rt_thread_mdelay(2000);
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
|
||||
|
||||
while(1)
|
||||
while (1)
|
||||
{
|
||||
rt_uint32_t status;
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BSR, (uint32_t *)&status);
|
||||
LOG_D("LAN8720 status:0x%04X\r\n", status);
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
|
||||
LOG_D("PHY BASIC STATUS REG:0x%04X\r\n", status);
|
||||
|
||||
phy_speed_new = 0;
|
||||
|
||||
if(status & (PHY_AUTONEGO_COMPLETE | PHY_LINKED_STATUS))
|
||||
if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
|
||||
{
|
||||
rt_uint32_t SR;
|
||||
|
||||
SR = HAL_ETH_ReadPHYRegister(&EthHandle, 31, (uint32_t *)&SR);
|
||||
LOG_D("LAN8720 REG 31:0x%04X ", SR);
|
||||
|
||||
SR = (SR >> 2) & 0x07; /* LAN8720, REG31[4:2], Speed Indication. */
|
||||
phy_speed_new = PHY_LINK_MASK;
|
||||
|
||||
if((SR & 0x03) == 2)
|
||||
SR = HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
|
||||
LOG_D("PHY Control/Status REG:0x%04X ", SR);
|
||||
|
||||
if (SR & PHY_100M_MASK)
|
||||
{
|
||||
phy_speed_new |= PHY_100M_MASK;
|
||||
}
|
||||
|
||||
if(SR & 0x04)
|
||||
else if (SR & PHY_10M_MASK)
|
||||
{
|
||||
phy_speed_new |= PHY_DUPLEX_MASK;
|
||||
phy_speed_new |= PHY_10M_MASK;
|
||||
}
|
||||
|
||||
if (SR & PHY_FULL_DUPLEX_MASK)
|
||||
{
|
||||
phy_speed_new |= PHY_FULL_DUPLEX_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/* linkchange */
|
||||
if(phy_speed_new != phy_speed)
|
||||
if (phy_speed_new != phy_speed)
|
||||
{
|
||||
if(phy_speed_new & PHY_LINK_MASK)
|
||||
if (phy_speed_new & PHY_LINK_MASK)
|
||||
{
|
||||
LOG_D("link up ");
|
||||
|
||||
if(phy_speed_new & PHY_100M_MASK)
|
||||
if (phy_speed_new & PHY_100M_MASK)
|
||||
{
|
||||
LOG_D("100Mbps");
|
||||
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||||
@@ -494,7 +498,7 @@ static void phy_monitor_thread_entry(void *parameter)
|
||||
LOG_D("10Mbps");
|
||||
}
|
||||
|
||||
if(phy_speed_new & PHY_DUPLEX_MASK)
|
||||
if (phy_speed_new & PHY_FULL_DUPLEX_MASK)
|
||||
{
|
||||
LOG_D("full-duplex");
|
||||
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
||||
@@ -504,54 +508,62 @@ static void phy_monitor_thread_entry(void *parameter)
|
||||
LOG_D("half-duplex");
|
||||
stm32_eth_device.ETH_Mode = ETH_MODE_HALFDUPLEX;
|
||||
}
|
||||
rt_stm32_eth_init((rt_device_t)&stm32_eth_device);
|
||||
|
||||
/* send link up. */
|
||||
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
|
||||
|
||||
} /* link up. */
|
||||
else
|
||||
{
|
||||
LOG_D("link down\r\n");
|
||||
LOG_I("link down\r\n");
|
||||
/* send link down. */
|
||||
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
|
||||
}
|
||||
}
|
||||
phy_speed = phy_speed_new;
|
||||
}
|
||||
}
|
||||
|
||||
rt_thread_delay(RT_TICK_PER_SECOND);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Register the EMAC device */
|
||||
static int rt_hw_stm32_eth_init(void)
|
||||
{
|
||||
rt_err_t state = RT_EOK;
|
||||
|
||||
/* Prepare receive and send buffers */
|
||||
Rx_Buff = (rt_uint8_t *)rt_calloc(ETH_RXBUFNB, ETH_MAX_PACKET_SIZE);
|
||||
if (Rx_Buff == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
|
||||
Tx_Buff = (rt_uint8_t *)rt_calloc(ETH_TXBUFNB, ETH_MAX_PACKET_SIZE);
|
||||
if (Rx_Buff == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
DMARxDscrTab = (ETH_DMADescTypeDef * )rt_calloc(ETH_RXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||
|
||||
DMARxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_RXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||
if (DMARxDscrTab == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
DMATxDscrTab = (ETH_DMADescTypeDef * )rt_calloc(ETH_TXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||
|
||||
DMATxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_TXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||
if (DMATxDscrTab == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
rt_err_t state;
|
||||
|
||||
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||||
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
||||
|
||||
@@ -560,9 +572,9 @@ static int rt_hw_stm32_eth_init(void)
|
||||
stm32_eth_device.dev_addr[1] = 0x80;
|
||||
stm32_eth_device.dev_addr[2] = 0xE1;
|
||||
/* generate MAC addr from 96bit unique ID (only for test). */
|
||||
stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(UID_BASE + 4);
|
||||
stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(UID_BASE + 2);
|
||||
stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(UID_BASE + 0);
|
||||
stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
|
||||
stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
|
||||
stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
|
||||
|
||||
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
||||
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
|
||||
@@ -587,9 +599,11 @@ static int rt_hw_stm32_eth_init(void)
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("emac device init faild: %d", state);
|
||||
LOG_E("emac device init faild: %d", state);
|
||||
state = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
|
||||
/* start phy monitor */
|
||||
rt_thread_t tid;
|
||||
tid = rt_thread_create("phy",
|
||||
@@ -600,9 +614,36 @@ static int rt_hw_stm32_eth_init(void)
|
||||
2);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
state = -RT_ERROR;
|
||||
}
|
||||
__exit:
|
||||
if (state != RT_EOK)
|
||||
{
|
||||
if (Rx_Buff)
|
||||
{
|
||||
rt_free(Rx_Buff);
|
||||
}
|
||||
|
||||
if (Tx_Buff)
|
||||
{
|
||||
rt_free(Tx_Buff);
|
||||
}
|
||||
|
||||
if (DMARxDscrTab)
|
||||
{
|
||||
rt_free(DMARxDscrTab);
|
||||
}
|
||||
|
||||
if (DMATxDscrTab)
|
||||
{
|
||||
rt_free(DMATxDscrTab);
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
INIT_APP_EXPORT(rt_hw_stm32_eth_init);
|
||||
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-25 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_ETH_H__
|
||||
#define __DRV_ETH_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* The PHY basic control register */
|
||||
#define PHY_BASIC_CONTROL_REG 0x00U
|
||||
#define PHY_RESET_MASK (1<<15)
|
||||
#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
|
||||
|
||||
/* The PHY basic status register */
|
||||
#define PHY_BASIC_STATUS_REG 0x01U
|
||||
#define PHY_LINKED_STATUS_MASK (1<<2)
|
||||
#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
|
||||
|
||||
/* The PHY ID one register */
|
||||
#define PHY_ID1_REG 0x02U
|
||||
|
||||
/* The PHY ID two register */
|
||||
#define PHY_ID2_REG 0x03U
|
||||
|
||||
/* The PHY auto-negotiate advertise register */
|
||||
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
|
||||
|
||||
#ifdef PHY_USING_LAN8720A
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x1DU
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MSAK_REG 0x1EU
|
||||
#define PHY_LINK_DOWN_MASK (1<<4)
|
||||
#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
|
||||
|
||||
/* The PHY status register. */
|
||||
#define PHY_Status_REG 0x1FU
|
||||
#define PHY_10M_MASK (1<<2)
|
||||
#define PHY_100M_MASK (1<<3)
|
||||
#define PHY_FULL_DUPLEX_MASK (1<<4)
|
||||
#endif /* PHY_USING_LAN8720A */
|
||||
|
||||
#ifdef PHY_USING_DM9161CEP
|
||||
#define PHY_Status_REG 0x11U
|
||||
#define PHY_10M_MASK ((1<<12) || (1<<13))
|
||||
#define PHY_100M_MASK ((1<<14) || (1<<15))
|
||||
#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
|
||||
|
||||
#endif /* PHY_USING_DM9161CEP */
|
||||
|
||||
#endif /* __DRV_ETH_H__ */
|
||||
@@ -16,8 +16,8 @@
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
int stm32_flash_erase(long offset, size_t size);
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
|
||||
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size);
|
||||
|
||||
#endif /* __DRV_FLASH_H__ */
|
||||
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-22 zylx first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#ifdef BSP_USING_ON_CHIP_FLASH
|
||||
#include "drv_config.h"
|
||||
#include "drv_flash.h"
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
#include "fal.h"
|
||||
#endif
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.flash"
|
||||
#include <drv_log.h>
|
||||
|
||||
/**
|
||||
* @brief Gets the page of a given address
|
||||
* @param Addr: Address of the FLASH Memory
|
||||
* @retval The page of a given address
|
||||
*/
|
||||
static uint32_t GetPage(uint32_t addr)
|
||||
{
|
||||
uint32_t page = 0;
|
||||
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
|
||||
return page;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read data from flash.
|
||||
* @note This operation's units is word.
|
||||
*
|
||||
* @param addr flash address
|
||||
* @param buf buffer to store read data
|
||||
* @param size read bytes size
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i++, buf++, addr++)
|
||||
{
|
||||
*buf = *(rt_uint8_t *) addr;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write data to flash.
|
||||
* @note This operation's units is word.
|
||||
* @note This operation must after erase. @see flash_erase.
|
||||
*
|
||||
* @param addr flash address
|
||||
* @param buf the write data buffer
|
||||
* @param size write bytes size
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t end_addr = addr + size;
|
||||
|
||||
if (addr % 4 != 0)
|
||||
{
|
||||
LOG_E("write addr must be 4-byte alignment");
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
if (size % 4 != 0)
|
||||
{
|
||||
LOG_E("write size must be 4-byte alignment");
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
if ((end_addr) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
HAL_FLASH_Unlock();
|
||||
|
||||
while (addr < end_addr)
|
||||
{
|
||||
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
|
||||
{
|
||||
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
addr += 4;
|
||||
buf += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
HAL_FLASH_Lock();
|
||||
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase data on flash.
|
||||
* @note This operation is irreversible.
|
||||
* @note This operation's units is different which on many chips.
|
||||
*
|
||||
* @param addr flash address
|
||||
* @param size erase bytes size
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
uint32_t PAGEError = 0;
|
||||
|
||||
/*Variable used for Erase procedure*/
|
||||
FLASH_EraseInitTypeDef EraseInitStruct;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
HAL_FLASH_Unlock();
|
||||
|
||||
/* Fill EraseInit structure*/
|
||||
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
|
||||
EraseInitStruct.PageAddress = GetPage(addr);
|
||||
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
|
||||
|
||||
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
__exit:
|
||||
HAL_FLASH_Lock();
|
||||
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
|
||||
return result;
|
||||
}
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_erase(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* BSP_USING_ON_CHIP_FLASH */
|
||||
@@ -44,10 +44,9 @@ static uint32_t GetPage(uint32_t addr)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
size_t i;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
@@ -74,10 +73,9 @@ int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
rt_uint32_t end_addr = addr + size;
|
||||
|
||||
if (addr % 4 != 0)
|
||||
@@ -139,10 +137,9 @@ int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_erase(long offset, size_t size)
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
uint32_t PAGEError = 0;
|
||||
|
||||
/*Variable used for Erase procedure*/
|
||||
@@ -180,6 +177,27 @@ __exit:
|
||||
}
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_erase(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* BSP_USING_ON_CHIP_FLASH */
|
||||
|
||||
@@ -178,10 +178,9 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
size_t i;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
@@ -208,10 +207,9 @@ int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
rt_uint32_t end_addr = addr + size;
|
||||
|
||||
if ((end_addr) > STM32_FLASH_END_ADDRESS)
|
||||
@@ -267,10 +265,9 @@ int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_erase(long offset, size_t size)
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
rt_uint32_t FirstSector = 0, NbOfSectors = 0;
|
||||
rt_uint32_t SECTORError = 0;
|
||||
|
||||
@@ -317,6 +314,61 @@ __exit:
|
||||
}
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, (128 * 1024), {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
|
||||
|
||||
static int fal_flash_read_16k(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_read_64k(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);
|
||||
|
||||
static int fal_flash_write_16k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write_64k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
|
||||
static int fal_flash_erase_16k(long offset, size_t size);
|
||||
static int fal_flash_erase_64k(long offset, size_t size);
|
||||
static int fal_flash_erase_128k(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev stm32_onchip_flash_16k = { "onchip_flash_16k", STM32_FLASH_START_ADRESS, FLASH_SIZE_GRANULARITY_16K, (16 * 1024), {NULL, fal_flash_read_16k, fal_flash_write_16k, fal_flash_erase_16k} };
|
||||
const struct fal_flash_dev stm32_onchip_flash_64k = { "onchip_flash_64k", STM32_FLASH_START_ADRESS, FLASH_SIZE_GRANULARITY_64K, (64 * 1024), {NULL, fal_flash_read_64k, fal_flash_write_64k, fal_flash_erase_64k} };
|
||||
const struct fal_flash_dev stm32_onchip_flash_128k = { "onchip_flash_128k", STM32_FLASH_START_ADRESS, FLASH_SIZE_GRANULARITY_128K, (128 * 1024), {NULL, fal_flash_read_128k, fal_flash_write_128k, fal_flash_erase_128k} };
|
||||
|
||||
static int fal_flash_read_16k(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash_16k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_read_64k(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash_64k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash_128k.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write_16k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash_16k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_write_64k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash_64k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash_128k.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase_16k(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash_16k.addr + offset, size);
|
||||
}
|
||||
static int fal_flash_erase_64k(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash_64k.addr + offset, size);
|
||||
}
|
||||
static int fal_flash_erase_128k(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash_128k.addr + offset, size);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* BSP_USING_ON_CHIP_FLASH */
|
||||
|
||||
@@ -22,33 +22,18 @@
|
||||
#define LOG_TAG "drv.flash"
|
||||
#include <drv_log.h>
|
||||
|
||||
/* Base address of the Flash sectors Bank 1 */
|
||||
#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
|
||||
|
||||
/* Base address of the Flash sectors Bank 2 */
|
||||
#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_16 ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_17 ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_18 ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_19 ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_20 ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_21 ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_22 ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_23 ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_0 ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_1 ((rt_uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_2 ((rt_uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_3 ((rt_uint32_t)0x08018000) /* Base address of Sector 3, 32 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_4 ((rt_uint32_t)0x08020000) /* Base address of Sector 4, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_5 ((rt_uint32_t)0x08040000) /* Base address of Sector 5, 256 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_6 ((rt_uint32_t)0x08080000) /* Base address of Sector 6, 256 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_7 ((rt_uint32_t)0x080C0000) /* Base address of Sector 7, 256 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_8 ((rt_uint32_t)0x08100000) /* Base address of Sector 8, 256 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_9 ((rt_uint32_t)0x08140000) /* Base address of Sector 9, 256 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_10 ((rt_uint32_t)0x08180000) /* Base address of Sector 10, 256 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_11 ((rt_uint32_t)0x081C0000) /* Base address of Sector 11, 256 Kbytes */
|
||||
|
||||
/**
|
||||
* @brief Gets the sector of a given address
|
||||
@@ -59,104 +44,54 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
|
||||
{
|
||||
rt_uint32_t sector = 0;
|
||||
|
||||
if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
|
||||
if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
|
||||
{
|
||||
sector = FLASH_SECTOR_0;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
|
||||
{
|
||||
sector = FLASH_SECTOR_1;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
|
||||
{
|
||||
sector = FLASH_SECTOR_2;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
|
||||
{
|
||||
sector = FLASH_SECTOR_3;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
|
||||
{
|
||||
sector = FLASH_SECTOR_4;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
|
||||
{
|
||||
sector = FLASH_SECTOR_5;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
|
||||
{
|
||||
sector = FLASH_SECTOR_6;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
|
||||
{
|
||||
sector = FLASH_SECTOR_7;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
|
||||
{
|
||||
sector = FLASH_SECTOR_8;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
|
||||
{
|
||||
sector = FLASH_SECTOR_9;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
|
||||
else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
|
||||
{
|
||||
sector = FLASH_SECTOR_10;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11))
|
||||
else /* (Address < FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_11) */
|
||||
{
|
||||
sector = FLASH_SECTOR_11;
|
||||
}
|
||||
#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx)|| defined(STM32F777xx) || defined(STM32F779xx)
|
||||
else if((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12))
|
||||
{
|
||||
sector = FLASH_SECTOR_12;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_14) && (Address >= ADDR_FLASH_SECTOR_13))
|
||||
{
|
||||
sector = FLASH_SECTOR_13;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_15) && (Address >= ADDR_FLASH_SECTOR_14))
|
||||
{
|
||||
sector = FLASH_SECTOR_14;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_16) && (Address >= ADDR_FLASH_SECTOR_15))
|
||||
{
|
||||
sector = FLASH_SECTOR_15;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_17) && (Address >= ADDR_FLASH_SECTOR_16))
|
||||
{
|
||||
sector = FLASH_SECTOR_16;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_18) && (Address >= ADDR_FLASH_SECTOR_17))
|
||||
{
|
||||
sector = FLASH_SECTOR_17;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_19) && (Address >= ADDR_FLASH_SECTOR_18))
|
||||
{
|
||||
sector = FLASH_SECTOR_18;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_20) && (Address >= ADDR_FLASH_SECTOR_19))
|
||||
{
|
||||
sector = FLASH_SECTOR_19;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_21) && (Address >= ADDR_FLASH_SECTOR_20))
|
||||
{
|
||||
sector = FLASH_SECTOR_20;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_22) && (Address >= ADDR_FLASH_SECTOR_21))
|
||||
{
|
||||
sector = FLASH_SECTOR_21;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_23) && (Address >= ADDR_FLASH_SECTOR_22))
|
||||
{
|
||||
sector = FLASH_SECTOR_22;
|
||||
}
|
||||
else /* (Address < FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_23) */
|
||||
{
|
||||
sector = FLASH_SECTOR_23;
|
||||
}
|
||||
#endif
|
||||
return sector;
|
||||
}
|
||||
|
||||
@@ -170,14 +105,13 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
size_t i;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("read outrange flash size! addr is (0x%p)", (void*)(addr + size));
|
||||
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
|
||||
return -1;
|
||||
}
|
||||
|
||||
@@ -200,15 +134,14 @@ int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
rt_uint32_t end_addr = addr + size;
|
||||
|
||||
if ((end_addr) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("write outrange flash size! addr is (0x%p)", (void*)(addr + size));
|
||||
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
@@ -217,8 +150,8 @@ int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
/* Unlock the Flash to enable the flash control register access */
|
||||
HAL_FLASH_Unlock();
|
||||
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR);
|
||||
|
||||
for (size_t i = 0; i < size; i++, addr++, buf++)
|
||||
@@ -259,16 +192,15 @@ int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_erase(long offset, size_t size)
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
rt_uint32_t FirstSector = 0, NbOfSectors = 0;
|
||||
rt_uint32_t SECTORError = 0;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void*)(addr + size));
|
||||
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
@@ -295,6 +227,7 @@ int stm32_flash_erase(long offset, size_t size)
|
||||
}
|
||||
|
||||
__exit:
|
||||
|
||||
HAL_FLASH_Lock();
|
||||
|
||||
if (result != RT_EOK)
|
||||
@@ -302,11 +235,66 @@ __exit:
|
||||
return result;
|
||||
}
|
||||
|
||||
LOG_D("erase done: addr (0x%p), size %d", (void*)addr, size);
|
||||
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
|
||||
return result;
|
||||
}
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, (128 * 1024), {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
|
||||
|
||||
static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_read_256k(long offset, rt_uint8_t *buf, size_t size);
|
||||
|
||||
static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write_256k(long offset, const rt_uint8_t *buf, size_t size);
|
||||
|
||||
static int fal_flash_erase_32k(long offset, size_t size);
|
||||
static int fal_flash_erase_128k(long offset, size_t size);
|
||||
static int fal_flash_erase_256k(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev stm32_onchip_flash_32k = { "onchip_flash_32k", STM32_FLASH_START_ADRESS, FLASH_SIZE_GRANULARITY_32K, (32 * 1024), {NULL, fal_flash_read_32k, fal_flash_write_32k, fal_flash_erase_32k} };
|
||||
const struct fal_flash_dev stm32_onchip_flash_128k = { "onchip_flash_128k", STM32_FLASH_START_ADRESS, FLASH_SIZE_GRANULARITY_128K, (128 * 1024), {NULL, fal_flash_read_128k, fal_flash_write_128k, fal_flash_erase_128k} };
|
||||
const struct fal_flash_dev stm32_onchip_flash_256k = { "onchip_flash_256k", STM32_FLASH_START_ADRESS, FLASH_SIZE_GRANULARITY_256K, (256 * 1024), {NULL, fal_flash_read_256k, fal_flash_write_256k, fal_flash_erase_256k} };
|
||||
|
||||
static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash_32k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash_128k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_read_256k(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash_256k.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash_32k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash_128k.addr + offset, buf, size);
|
||||
}
|
||||
static int fal_flash_write_256k(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash_256k.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase_32k(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash_32k.addr + offset, size);
|
||||
}
|
||||
static int fal_flash_erase_128k(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash_128k.addr + offset, size);
|
||||
}
|
||||
static int fal_flash_erase_256k(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash_256k.addr + offset, size);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* BSP_USING_ON_CHIP_FLASH */
|
||||
|
||||
@@ -92,10 +92,9 @@ static uint32_t GetBank(uint32_t Addr)
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
size_t i;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
@@ -123,12 +122,11 @@ int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
* @return result
|
||||
*/
|
||||
|
||||
int stm32_flash_write(long offset, const uint8_t *buf, size_t size)
|
||||
int stm32_flash_write(rt_uint32_t addr, const uint8_t *buf, size_t size)
|
||||
{
|
||||
size_t i, j;
|
||||
rt_err_t result = 0;
|
||||
rt_uint64_t write_data = 0, temp_data = 0;
|
||||
rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
@@ -221,10 +219,9 @@ __exit:
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_erase(long offset, size_t size)
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
uint32_t addr = STM32_FLASH_START_ADRESS + offset;
|
||||
uint32_t FirstPage = 0, NbOfPages = 0, BankNumber = 0;
|
||||
uint32_t PAGEError = 0;
|
||||
|
||||
@@ -272,6 +269,27 @@ __exit:
|
||||
}
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, 2048, {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_erase(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, 2048, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* BSP_USING_ON_CHIP_FLASH */
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 balanceTWK change to new framework
|
||||
* 2018-11-06 balanceTWK first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
@@ -217,6 +217,24 @@ static const struct pin_index pins[] =
|
||||
|
||||
static const struct pin_irq_map pin_irq_map[] =
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F0)
|
||||
{GPIO_PIN_0, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_1, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_3, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_5, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_6, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_7, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_8, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_9, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_10, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_11, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_12, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_13, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_14, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_15, EXTI4_15_IRQn},
|
||||
#else
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_IRQn},
|
||||
@@ -233,6 +251,7 @@ static const struct pin_irq_map pin_irq_map[] =
|
||||
{GPIO_PIN_13, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_14, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_10_IRQn},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
|
||||
@@ -608,6 +627,41 @@ void EXTI15_10_IRQHandler(void)
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI0_1_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI2_3_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
void EXTI4_15_IRQHandler(void)
|
||||
{
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
|
||||
}
|
||||
|
||||
int rt_hw_pin_init(void)
|
||||
{
|
||||
#if defined(__HAL_RCC_GPIOA_CLK_ENABLE)
|
||||
|
||||
@@ -164,15 +164,17 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
|
||||
tim_device = (struct stm32_hwtimer *)timer;
|
||||
|
||||
/* time init */
|
||||
#if defined(SOC_SERIES_STM32F4)
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#ifndef SOC_SERIES_STM32F0
|
||||
prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * 2 / 10000) - 1;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -190,7 +192,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
|
||||
tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
|
||||
}
|
||||
tim->Init.RepetitionCounter = 0;
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)
|
||||
tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
#endif
|
||||
if (HAL_TIM_Base_Init(tim) != HAL_OK)
|
||||
@@ -276,23 +278,27 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
|
||||
/* set timer frequence */
|
||||
freq = *((rt_uint32_t *)arg);
|
||||
|
||||
#if defined(SOC_SERIES_STM32F4)
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
val = HAL_RCC_GetPCLK2Freq() / freq;
|
||||
#else
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4)
|
||||
val = HAL_RCC_GetPCLK2Freq() * 2 / freq;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4)
|
||||
val = HAL_RCC_GetPCLK1Freq() * 2 / freq;
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
val = HAL_RCC_GetPCLK1Freq() / freq;
|
||||
#endif
|
||||
}
|
||||
__HAL_TIM_SET_PRESCALER(tim, val - 1);
|
||||
|
||||
@@ -393,7 +399,11 @@ void TIM8_UP_TIM13_IRQHandler(void)
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM14
|
||||
void TIM8_TRG_COM_TIM14_IRQHandler(void)
|
||||
#if defined(SOC_SERIES_STM32F4)
|
||||
void TIM8_TRG_COM_TIM14_IRQHandler(void)
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
void TIM14_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
@@ -413,7 +423,11 @@ void TIM1_BRK_TIM15_IRQHandler(void)
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM16
|
||||
void TIM1_UP_TIM16_IRQHandler(void)
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
void TIM1_UP_TIM16_IRQHandler(void)
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
void TIM16_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
@@ -423,7 +437,11 @@ void TIM1_UP_TIM16_IRQHandler(void)
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM17
|
||||
void TIM1_TRG_COM_TIM17_IRQHandler(void)
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
void TIM1_TRG_COM_TIM17_IRQHandler(void)
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
void TIM17_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
@@ -185,19 +185,21 @@ static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
|
||||
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
|
||||
rt_uint64_t tim_clock;
|
||||
|
||||
#if defined(SOC_SERIES_STM32F4)
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#ifndef SOC_SERIES_STM32F0
|
||||
tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq();
|
||||
#else
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
|
||||
@@ -228,19 +230,21 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
|
||||
/* Converts the channel number to the channel number of Hal library */
|
||||
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
|
||||
|
||||
#if defined(SOC_SERIES_STM32F4)
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#ifndef SOC_SERIES_STM32F0
|
||||
tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq();
|
||||
#else
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
|
||||
@@ -407,6 +411,9 @@ __exit:
|
||||
|
||||
static void pwm_get_channel(void)
|
||||
{
|
||||
#ifdef BSP_USING_PWM2_CH1
|
||||
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM2_CH4
|
||||
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
|
||||
@@ -5,8 +5,7 @@
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-27 zylx change to new framework
|
||||
* 2018-12-12 greedyhao Porting for stm32f7xx
|
||||
* 2018-11-27 zylx first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
@@ -21,14 +20,6 @@
|
||||
|
||||
#if defined(BSP_USING_QSPI)
|
||||
|
||||
#if defined (SOC_SERIES_STM32L4)
|
||||
#define QUADSPI_DMA_IRQ DMA1_Channel5_IRQn
|
||||
#define QUADSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
|
||||
#elif defined (SOC_SERIES_STM32F7)
|
||||
#define QUADSPI_DMA_IRQ DMA2_Stream2_IRQn
|
||||
#define QUADSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
|
||||
#endif /* SOC_SERIES_STM32L4 */
|
||||
|
||||
struct stm32_hw_spi_cs
|
||||
{
|
||||
uint16_t Pin;
|
||||
@@ -58,6 +49,9 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
|
||||
struct stm32_qspi_bus *qspi_bus = device->parent.bus->parent.user_data;
|
||||
rt_memset(&qspi_bus->QSPI_Handler, 0, sizeof(qspi_bus->QSPI_Handler));
|
||||
|
||||
QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG;
|
||||
qspi_bus->QSPI_Handler = QSPI_Handler_config;
|
||||
|
||||
while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
|
||||
{
|
||||
i++;
|
||||
@@ -84,14 +78,6 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
|
||||
/* flash size */
|
||||
qspi_bus->QSPI_Handler.Init.FlashSize = POSITION_VAL(qspi_cfg->medium_size) - 1;
|
||||
|
||||
qspi_bus->QSPI_Handler.Instance = QUADSPI;
|
||||
/* fifo threshold is 4 byte */
|
||||
qspi_bus->QSPI_Handler.Init.FifoThreshold = 4;
|
||||
/* Sampling shift half a cycle */
|
||||
qspi_bus->QSPI_Handler.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
|
||||
/* cs high time */
|
||||
qspi_bus->QSPI_Handler.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE;
|
||||
|
||||
result = HAL_QSPI_Init(&qspi_bus->QSPI_Handler);
|
||||
if (result == HAL_OK)
|
||||
{
|
||||
@@ -104,34 +90,23 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
/* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
|
||||
HAL_NVIC_SetPriority(QUADSPI_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
|
||||
HAL_NVIC_SetPriority(QUADSPI_DMA_IRQ, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(QUADSPI_DMA_IRQ);
|
||||
HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(QSPI_IRQn);
|
||||
HAL_NVIC_SetPriority(QSPI_DMA_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(QSPI_DMA_IRQn);
|
||||
|
||||
/* init QSPI DMA */
|
||||
__HAL_RCC_DMA1_CLK_ENABLE();
|
||||
/* init QSPI DMA */
|
||||
QSPI_DMA_CLK_ENABLE;
|
||||
HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
|
||||
#if defined(SOC_SERIES_STM32F4)
|
||||
qspi_bus->hdma_quadspi.Instance = DMA1_Channel5;
|
||||
qspi_bus->hdma_quadspi.Init.Request = DMA_REQUEST_5;
|
||||
#elif defined(SOC_SERIES_STM32F7)
|
||||
qspi_bus->hdma_quadspi.Instance = DMA2_Stream2;
|
||||
qspi_bus->hdma_quadspi.Init.channel = DMA_CHANNEL_11;
|
||||
#endif
|
||||
qspi_bus->hdma_quadspi.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
qspi_bus->hdma_quadspi.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
qspi_bus->hdma_quadspi.Init.MemInc = DMA_MINC_ENABLE;
|
||||
qspi_bus->hdma_quadspi.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
qspi_bus->hdma_quadspi.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
qspi_bus->hdma_quadspi.Init.Mode = DMA_NORMAL;
|
||||
qspi_bus->hdma_quadspi.Init.Priority = DMA_PRIORITY_LOW;
|
||||
DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
|
||||
qspi_bus->hdma_quadspi = hdma_quadspi_config;
|
||||
|
||||
if (HAL_DMA_Init(&qspi_bus->hdma_quadspi) != HAL_OK)
|
||||
{
|
||||
LOG_E("qspi dma init failed (%d)!", result);
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(&qspi_bus->QSPI_Handler,hdma,qspi_bus->hdma_quadspi);
|
||||
|
||||
__HAL_LINKDMA(&qspi_bus->QSPI_Handler, hdma, qspi_bus->hdma_quadspi);
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
|
||||
return result;
|
||||
@@ -269,8 +244,8 @@ static rt_uint32_t qspixfer(struct rt_spi_device *device, struct rt_spi_message
|
||||
#endif
|
||||
{
|
||||
len = length;
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
while(qspi_bus->QSPI_Handler.RxXferCount != 0);
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
while (qspi_bus->QSPI_Handler.RxXferCount != 0);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
@@ -380,7 +355,7 @@ __exit:
|
||||
}
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
void QUADSPI_IRQHandler(void)
|
||||
void QSPI_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
@@ -391,7 +366,7 @@ void QUADSPI_IRQHandler(void)
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void QUADSPI_DMA_IRQHandler(void)
|
||||
void QSPI_DMA_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
@@ -24,8 +24,8 @@ static RTC_HandleTypeDef RTC_Handler;
|
||||
|
||||
static time_t get_rtc_timestamp(void)
|
||||
{
|
||||
RTC_TimeTypeDef RTC_TimeStruct;
|
||||
RTC_DateTypeDef RTC_DateStruct;
|
||||
RTC_TimeTypeDef RTC_TimeStruct = {0};
|
||||
RTC_DateTypeDef RTC_DateStruct = {0};
|
||||
struct tm tm_new;
|
||||
|
||||
HAL_RTC_GetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN);
|
||||
@@ -44,9 +44,9 @@ static time_t get_rtc_timestamp(void)
|
||||
|
||||
static rt_err_t set_rtc_time_stamp(time_t time_stamp)
|
||||
{
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
RTC_TimeTypeDef RTC_TimeStruct;
|
||||
RTC_DateTypeDef RTC_DateStruct;
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
RTC_TimeTypeDef RTC_TimeStruct = {0};
|
||||
RTC_DateTypeDef RTC_DateStruct = {0};
|
||||
struct tm *p_tm;
|
||||
|
||||
HAL_PWR_EnableBkUpAccess();
|
||||
@@ -86,7 +86,7 @@ static void rt_rtc_init(void)
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||
@@ -95,7 +95,7 @@ static void rt_rtc_init(void)
|
||||
|
||||
static rt_err_t rt_rtc_config(struct rt_device *dev)
|
||||
{
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
HAL_PWR_EnableBkUpAccess();
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||
@@ -110,9 +110,13 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
RTC_Handler.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
|
||||
RTC_Handler.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
|
||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
|
||||
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
RTC_Handler.Init.AsynchPrediv = 0X7F;
|
||||
#ifndef SOC_SERIES_STM32F0
|
||||
RTC_Handler.Init.SynchPrediv = 0XFF;
|
||||
#else
|
||||
RTC_Handler.Init.SynchPrediv = 0x0130;
|
||||
#endif
|
||||
RTC_Handler.Init.HourFormat = RTC_HOURFORMAT_24;
|
||||
RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
|
||||
RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user