[bsp][rockchip] support RK3528

1. CLK for RK3528
2. Pinctrl for RK3528
3. hwrng for RK-RNG
4. OTP for RK3528
5. TSADC for RK3528

Signed-off-by: GuEe-GUI <2991707448@qq.com>

bsp/rockchip/dm/adc/adc-rockchip_saradc.c

@@ -223,6 +223,23 @@ static const struct rockchip_saradc_soc_data rk3399_saradc_data =
     .power_down = rockchip_saradc_power_down_v1,
 };
 
+static const struct saradc_channel rockchip_rk3528_channels[] =
+{
+    SARADC_CHANNEL(0, "adc0", 10),
+    SARADC_CHANNEL(1, "adc1", 10),
+    SARADC_CHANNEL(2, "adc2", 10),
+    SARADC_CHANNEL(3, "adc3", 10),
+};
+
+static const struct rockchip_saradc_soc_data rk3528_saradc_data =
+{
+    .channels = rockchip_rk3528_channels,
+    .num_channels = RT_ARRAY_SIZE(rockchip_rk3528_channels),
+    .clk_rate = 1000000,
+    .start = rockchip_saradc_start_v2,
+    .read = rockchip_saradc_read_v2,
+};
+
 static const struct saradc_channel rk3568_saradc_channels[] =
 {
     SARADC_CHANNEL(0, "adc0", 10),
@@ -503,6 +520,7 @@ static const struct rt_ofw_node_id rockchip_saradc_ofw_ids[] =
     { .compatible = "rockchip,saradc", .data = &saradc_data },
     { .compatible = "rockchip,rk3066-tsadc", .data = &rk3066_tsadc_data },
     { .compatible = "rockchip,rk3399-saradc", .data = &rk3399_saradc_data },
+    { .compatible = "rockchip,rk3528-saradc", .data = &rk3528_saradc_data, },
     { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_data },
     { .compatible = "rockchip,rk3588-saradc", .data = &rk3588_saradc_data, },
     { /* sentinel */ }

bsp/rockchip/dm/clk/Kconfig

@@ -20,6 +20,11 @@ config RT_CLK_ROCKCHIP_RK3308
     depends on RT_CLK_ROCKCHIP
     default n
 
+config RT_CLK_ROCKCHIP_RK3528
+    bool "Rockchip RK3528 clock controller support"
+    depends on RT_CLK_ROCKCHIP
+    default n
+
 config RT_CLK_ROCKCHIP_RK3568
     bool "Rockchip RK3568 clock controller support"
     depends on RT_CLK_ROCKCHIP

bsp/rockchip/dm/clk/SConscript

@@ -19,6 +19,9 @@ if GetDepend(['RT_CLK_ROCKCHIP']):
 if GetDepend(['RT_CLK_ROCKCHIP_RK3308']):
     src += ['clk-rk3308.c']
 
+if GetDepend(['RT_CLK_ROCKCHIP_RK3528']):
+    src += ['clk-rk3528.c']
+
 if GetDepend(['RT_CLK_ROCKCHIP_RK3568']):
     src += ['clk-rk3568.c']
 

bsp/rockchip/dm/hwcrypto/hw-rng-rockchip.c

@@ -86,6 +86,25 @@
 #define TRNG_v1_VERSION_CODE            0x46bc
 /* end of TRNG_V1 register define */
 
+/* start of RKRNG register define */
+#define RKRNG_CTRL                      0x0010
+#define RKRNG_CTRL_INST_REQ             RT_BIT(0)
+#define RKRNG_CTRL_RESEED_REQ           RT_BIT(1)
+#define RKRNG_CTRL_TEST_REQ             RT_BIT(2)
+#define RKRNG_CTRL_SW_DRNG_REQ          RT_BIT(3)
+#define RKRNG_CTRL_SW_TRNG_REQ          RT_BIT(4)
+
+#define RKRNG_STATE                     0x0014
+#define RKRNG_STATE_INST_ACK            RT_BIT(0)
+#define RKRNG_STATE_RESEED_ACK          RT_BIT(1)
+#define RKRNG_STATE_TEST_ACK            RT_BIT(2)
+#define RKRNG_STATE_SW_DRNG_ACK         RT_BIT(3)
+#define RKRNG_STATE_SW_TRNG_ACK         RT_BIT(4)
+
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
+#define RKRNG_DRNG_DATA_0               0x0070
+#define RKRNG_DRNG_DATA_7               0x008C
+
 struct rockchip_rng;
 
 struct rockchip_rng_soc_data
@@ -319,6 +338,49 @@ _time_out:
     return res;
 }
 
+static rt_err_t rkrng_init(struct rockchip_rng *rk_rng)
+{
+    rt_uint32_t reg;
+
+    rockchip_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
+    reg = rockchip_rng_readl(rk_rng, RKRNG_STATE);
+    rockchip_rng_writel(rk_rng, reg, RKRNG_STATE);
+
+    return 0;
+}
+
+static rt_uint32_t rkrng_read(struct rockchip_rng *rk_rng, void *buf,
+        rt_size_t max, rt_bool_t wait)
+{
+    rt_err_t err;
+    rt_uint32_t reg_ctrl = RKRNG_CTRL_SW_DRNG_REQ;
+
+    rockchip_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0), RKRNG_CTRL);
+
+    err = readl_poll_timeout(rk_rng->regs + RKRNG_STATE, reg_ctrl,
+            (reg_ctrl & RKRNG_STATE_SW_DRNG_ACK),
+            ROCKCHIP_POLL_PERIOD_US,
+            ROCKCHIP_POLL_TIMEOUT_US);
+
+    if (err)
+    {
+        goto _exit;
+    }
+
+
+    rockchip_rng_writel(rk_rng, reg_ctrl, RKRNG_STATE);
+
+    err = rt_min_t(rt_size_t, max, RK_MAX_RNG_BYTE);
+
+    rockchip_rng_read_regs(rk_rng, RKRNG_DRNG_DATA_0, buf, err);
+
+_exit:
+    /* Close TRNG */
+    rockchip_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), RKRNG_CTRL);
+
+    return err;
+}
+
 static rt_uint32_t rockchip_rng_read(struct rockchip_rng *rk_rng, void *buf,
         rt_size_t max, rt_bool_t wait)
 {
@@ -546,11 +608,19 @@ static const struct rockchip_rng_soc_data rk_trng_v1_soc_data =
     .read = rockchip_trng_v1_read,
 };
 
+static const struct rockchip_rng_soc_data rkrng_soc_data =
+{
+    .default_offset = 0,
+    .init = rkrng_init,
+    .read = rkrng_read,
+};
+
 static const struct rt_ofw_node_id rockchip_rng_ofw_ids[] =
 {
     { .compatible = "rockchip,cryptov1-rng", .data = &rk_crypto_v1_soc_data, },
     { .compatible = "rockchip,cryptov2-rng", .data = &rk_crypto_v2_soc_data, },
     { .compatible = "rockchip,trngv1", .data = &rk_trng_v1_soc_data, },
+    { .compatible = "rockchip,rkrng", .data = &rkrng_soc_data, },
     { /* sentinel */ }
 };
 

bsp/rockchip/dm/include/pinctrl-rockchip.h

@@ -46,7 +46,9 @@ enum rockchip_pin_pull_type
 enum rockchip_pinctrl_type
 {
     RK3308,
+    RK3528,
     RK3568,
+    RK3576,
     RK3588,
 };
 

bsp/rockchip/dm/nvmem/nvmem-rockchip-otp.c

@@ -880,6 +880,12 @@ static const struct rockchip_otp_data px30s_data =
     .read = px30s_otp_read,
 };
 
+static const struct rockchip_otp_data rk3528_data =
+{
+    .size = 0x80,
+    .read = rk3568_otp_read,
+};
+
 static const struct rockchip_otp_data rk3568_data =
 {
     .size = 0x80,
@@ -1018,6 +1024,7 @@ static const struct rt_ofw_node_id rockchip_otp_ofw_ids[] =
     { .compatible = "rockchip,px30s-otp", .data = &px30s_data, },
     { .compatible = "rockchip,rk3308-otp", .data = &px30_data, },
     { .compatible = "rockchip,rk3308bs-otp", .data = &px30s_data, },
+    { .compatible = "rockchip,rk3528-otp", .data = &rk3528_data, },
     { .compatible = "rockchip,rk3568-otp", .data = &rk3568_data, },
     { .compatible = "rockchip,rk3576-otp", .data = &rk3576_data, },
     { .compatible = "rockchip,rk3588-otp", .data = &rk3588_data, },

bsp/rockchip/dm/thermal/thermal-rockchip_tsadc.c

@@ -46,6 +46,7 @@
 #define TSADCV2_AUTO_PERIOD_HT              0x6c
 #define TSADCV3_AUTO_PERIOD                 0x154
 #define TSADCV3_AUTO_PERIOD_HT              0x158
+#define TSADCV9_Q_MAX                       0x210
 
 #define TSADCV2_AUTO_EN                     RT_BIT(0)
 #define TSADCV2_AUTO_EN_MASK                RT_BIT(16)
@@ -56,6 +57,7 @@
 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK    RT_BIT(24)
 
 #define TSADCV3_AUTO_Q_SEL_EN               RT_BIT(1)
+#define TSADCV3_AUTO_Q_SEL_EN_MASK          RT_BIT(17)
 
 #define TSADCV2_INT_SRC_EN(chn)             RT_BIT(chn)
 #define TSADCV2_INT_SRC_EN_MASK(chn)        RT_BIT(16 + (chn))
@@ -69,6 +71,7 @@
 #define TSADCV2_DATA_MASK                   0xfff
 #define TSADCV3_DATA_MASK                   0x3ff
 #define TSADCV4_DATA_MASK                   0x1ff
+#define TSADCV5_DATA_MASK                   0x7ff
 
 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT    4
 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT  4
@@ -81,6 +84,10 @@
 #define TSADCV5_AUTO_PERIOD_HT_TIME         1622 /* 2.5ms */
 #define TSADCV6_AUTO_PERIOD_TIME            5000 /* 2.5ms */
 #define TSADCV6_AUTO_PERIOD_HT_TIME         5000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_TIME            3000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_HT_TIME         3000 /* 2.5ms */
+
+#define TSADCV3_Q_MAX_VAL                   0x7ff /* 11bit 2047 */
 
 #define TSADCV2_USER_INTER_PD_SOC           0x340 /* 13 clocks */
 #define TSADCV5_USER_INTER_PD_SOC           0xfc0 /* 97us, at least 90us */
@@ -91,6 +98,8 @@
 
 #define PX30_GRF_SOC_CON2                   0x0408
 
+#define RK3528_GRF_TSADC_CON                0x40030
+
 #define RK3568_GRF_TSADC_CON                0x0600
 #define RK3568_GRF_TSADC_ANA_REG0           (0x10001 << 0)
 #define RK3568_GRF_TSADC_ANA_REG1           (0x10001 << 1)
@@ -502,6 +511,38 @@ static void rk_tsadcv8_initialize(struct rt_syscon *grf, void *regs,
     }
 }
 
+static void rk_tsadcv11_initialize(struct rt_syscon *grf, void *regs,
+        enum tshut_polarity tshut_polarity)
+{
+    HWREG32(regs + TSADCV3_AUTO_PERIOD) = TSADCV7_AUTO_PERIOD_TIME;
+    HWREG32(regs + TSADCV3_AUTO_PERIOD_HT) = TSADCV7_AUTO_PERIOD_HT_TIME;
+    HWREG32(regs + TSADCV3_HIGHT_INT_DEBOUNCE) = TSADCV2_HIGHT_INT_DEBOUNCE_COUNT;
+    HWREG32(regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE) = TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT;
+    HWREG32(regs + TSADCV9_Q_MAX) = TSADCV3_Q_MAX_VAL;
+    HWREG32(regs + TSADCV2_AUTO_CON) = TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK;
+
+    if (tshut_polarity == TSHUT_HIGH_ACTIVE)
+    {
+        HWREG32(regs + TSADCV2_AUTO_CON) = TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+                TSADCV2_AUTO_TSHUT_POLARITY_MASK;
+    }
+    else
+    {
+        HWREG32(regs + TSADCV2_AUTO_CON) = TSADCV2_AUTO_TSHUT_POLARITY_MASK;
+    }
+
+    if (grf)
+    {
+        rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
+        rt_hw_us_delay(15);
+
+        rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
+        rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
+        rt_syscon_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
+        rt_hw_us_delay(150);
+    }
+}
+
 static void rk_tsadcv2_irq_ack(void *regs)
 {
     rt_uint32_t val;
@@ -1250,6 +1291,75 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data =
     },
 };
 
+static const struct tsadc_table rk3528_code_table[] =
+{
+    { 0, -60000 },
+    { 1386, -60000 },
+    { 1410, -40000 },
+    { 1419, -35000 },
+    { 1428, -30000 },
+    { 1436, -25000 },
+    { 1445, -20000 },
+    { 1454, -15000 },
+    { 1463, -10000 },
+    { 1471, -5000 },
+    { 1480, 0 },
+    { 1489, 5000 },
+    { 1498, 10000 },
+    { 1506, 15000 },
+    { 1515, 20000 },
+    { 1524, 25000 },
+    { 1533, 30000 },
+    { 1541, 35000 },
+    { 1550, 40000 },
+    { 1558, 45000 },
+    { 1567, 50000 },
+    { 1575, 55000 },
+    { 1584, 60000 },
+    { 1593, 65000 },
+    { 1602, 70000 },
+    { 1610, 75000 },
+    { 1619, 80000 },
+    { 1628, 85000 },
+    { 1637, 90000 },
+    { 1646, 95000 },
+    { 1654, 100000 },
+    { 1663, 105000 },
+    { 1672, 110000 },
+    { 1680, 115000 },
+    { 1689, 120000 },
+    { 1697, 125000 },
+    { 1790, 180000 },
+    { TSADCV5_DATA_MASK, 180000 },
+};
+
+static const struct rockchip_tsadc_chip rk3528_tsadc_data =
+{
+    .chn_offset = 0,
+    .chn_num = 1, /* one channels for tsadc */
+    .chn_name = chn_name_common,
+
+    .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
+    .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+    .tshut_temp = 95000,
+
+    .initialize = rk_tsadcv11_initialize,
+    .irq_ack = rk_tsadcv4_irq_ack,
+    .control = rk_tsadcv4_control,
+    .get_temp = rk_tsadcv4_get_temp,
+    .set_alarm_temp = rk_tsadcv3_alarm_temp,
+    .set_tshut_temp = rk_tsadcv3_tshut_temp,
+    .set_tshut_mode = rk_tsadcv4_tshut_mode,
+
+    .table =
+    {
+        .id = rk3528_code_table,
+        .length = RT_ARRAY_SIZE(rk3528_code_table),
+        .data_mask = TSADCV2_DATA_MASK,
+        .mode = ADC_INCREMENT,
+    },
+};
+
 static const struct tsadc_table rk3568_code_table[] =
 {
     {    0, -40000 },
@@ -1678,6 +1788,7 @@ static const struct rt_ofw_node_id rockchip_tsadc_ofw_ids[] =
     { .compatible = "rockchip,rk3366-tsadc", .data = &rk3366_tsadc_data, },
     { .compatible = "rockchip,rk3368-tsadc", .data = &rk3368_tsadc_data, },
     { .compatible = "rockchip,rk3399-tsadc", .data = &rk3399_tsadc_data, },
+    { .compatible = "rockchip,rk3528-tsadc", .data = &rk3528_tsadc_data, },
     { .compatible = "rockchip,rk3568-tsadc", .data = &rk3568_tsadc_data, },
     { .compatible = "rockchip,rk3576-tsadc", .data = &rk3576_tsadc_data, },
     { .compatible = "rockchip,rk3588-tsadc", .data = &rk3588_tsadc_data, },

bsp/rockchip/rk3500/.config

@@ -11,18 +11,8 @@
 # rt_vsnprintf options
 #
 # CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set
-CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y
-CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y
-CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y
-CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y
-CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y
-CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y
-# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set
-CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32
-CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32
-CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6
-CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9
-CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set
+# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set
 # end of rt_vsnprintf options
 
 #
@@ -192,11 +182,12 @@ CONFIG_RT_USING_HEAP=y
 
 CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_DEVICE_OPS=y
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_INTERRUPT_INFO=y
 CONFIG_RT_USING_THREADSAFE_PRINTF=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=1024
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
+CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y
 CONFIG_RT_VER_NUM=0x50300
 CONFIG_RT_USING_STDC_ATOMIC=y
 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
@@ -513,11 +504,14 @@ CONFIG_RT_PCI_DW_HOST=y
 CONFIG_RT_PCI_DW_EP=y
 CONFIG_RT_PCI_DW_ROCKCHIP=y
 CONFIG_RT_USING_PIC=y
+# CONFIG_RT_USING_PIC_STATISTICS is not set
 CONFIG_MAX_HANDLERS=2048
-# CONFIG_RT_PIC_ARM_GIC is not set
+CONFIG_RT_PIC_ARM_GIC=y
+# CONFIG_RT_PIC_ARM_GIC_V2M is not set
 CONFIG_RT_PIC_ARM_GIC_V3=y
 CONFIG_RT_PIC_ARM_GIC_V3_ITS=y
 CONFIG_RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX=256
+CONFIG_RT_PIC_ARM_GIC_MAX_NR=1
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_PIN_PL061 is not set
 CONFIG_RT_PIN_ROCKCHIP=y
@@ -532,6 +526,7 @@ CONFIG_RT_CLK_ROCKCHIP_RK8XX_CLKOUT=y
 CONFIG_RT_CLK_ROCKCHIP_LINK=y
 CONFIG_RT_CLK_ROCKCHIP=y
 # CONFIG_RT_CLK_ROCKCHIP_RK3308 is not set
+CONFIG_RT_CLK_ROCKCHIP_RK3528=y
 CONFIG_RT_CLK_ROCKCHIP_RK3568=y
 CONFIG_RT_CLK_ROCKCHIP_RK3576=y
 CONFIG_RT_CLK_ROCKCHIP_RK3588=y

bsp/rockchip/rk3500/README.md

@@ -11,14 +11,15 @@ https://www.rock-chips.com/a/cn/product/RK35xilie/index.html
 ### Condition
 
 | SoC | Condition | Earlycon |
-| ------ | ----  | ----  |
+| ------ | ---- | ---- |
 | RK3576 | Support | earlycon=uart8250,mmio32,0x2ad40000 |
 | RK3588 | Support | earlycon=uart8250,mmio32,0xfeb50000 |
 | RK3562 | - | - |
 | RK3568J | Support | earlycon=uart8250,mmio32,0xfe660000 |
 | RK3568 | Support | earlycon=uart8250,mmio32,0xfe660000 |
 | RK3566 | Support | earlycon=uart8250,mmio32,0xfe660000 |
-| RK3506 | - |
+| RK3528 | Support | earlycon=uart8250,mmio32,0xff9f0000 |
+| RK3506 | - | - |
 
 ## 2. Compiling
 

bsp/rockchip/rk3500/README_ZH.md

@@ -11,13 +11,14 @@ https://www.rock-chips.com/a/cn/product/RK35xilie/index.html
 ### 支持列表
 
 | 驱动 | 支持情况  | Earlycon |
-| ------ | ----  | ----  |
+| ------ | ---- | ---- |
 | RK3576 | 支持 | earlycon=uart8250,mmio32,0x2ad40000 |
 | RK3588 | 支持 | earlycon=uart8250,mmio32,0xfeb50000 |
 | RK3562 | - | - |
 | RK3568J | 支持 | earlycon=uart8250,mmio32,0xfe660000 |
 | RK3568 | 支持 | earlycon=uart8250,mmio32,0xfe660000 |
 | RK3566 | 支持 | earlycon=uart8250,mmio32,0xfe660000 |
+| RK3528 | 支持 | earlycon=uart8250,mmio32,0xff9f0000 |
 | RK3506 | - | - |
 
 ## 2. 编译

bsp/rockchip/rk3500/rtconfig.h

@@ -7,17 +7,6 @@
 
 /* rt_vsnprintf options */
 
-#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
-#define RT_KLIBC_USING_VSNPRINTF_STANDARD
-#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS
-#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS
-#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER
-#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER
-#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32
-#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32
-#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6
-#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9
-#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4
 /* end of rt_vsnprintf options */
 
 /* rt_vsscanf options */
@@ -120,10 +109,12 @@
 /* end of Memory Management */
 #define RT_USING_DEVICE
 #define RT_USING_DEVICE_OPS
+#define RT_USING_INTERRUPT_INFO
 #define RT_USING_THREADSAFE_PRINTF
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 1024
 #define RT_CONSOLE_DEVICE_NAME "uart2"
+#define RT_USING_CONSOLE_OUTPUT_CTL
 #define RT_VER_NUM 0x50300
 #define RT_USING_STDC_ATOMIC
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
@@ -346,9 +337,11 @@
 #define RT_PCI_DW_ROCKCHIP
 #define RT_USING_PIC
 #define MAX_HANDLERS 2048
+#define RT_PIC_ARM_GIC
 #define RT_PIC_ARM_GIC_V3
 #define RT_PIC_ARM_GIC_V3_ITS
 #define RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX 256
+#define RT_PIC_ARM_GIC_MAX_NR 1
 #define RT_USING_PIN
 #define RT_PIN_ROCKCHIP
 #define RT_USING_PINCTRL
@@ -359,6 +352,7 @@
 #define RT_CLK_ROCKCHIP_RK8XX_CLKOUT
 #define RT_CLK_ROCKCHIP_LINK
 #define RT_CLK_ROCKCHIP
+#define RT_CLK_ROCKCHIP_RK3528
 #define RT_CLK_ROCKCHIP_RK3568
 #define RT_CLK_ROCKCHIP_RK3576
 #define RT_CLK_ROCKCHIP_RK3588

bsp/rockchip/rk3500/rtconfig.py

@@ -34,7 +34,10 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
 
-    DEVICE = ' -g -march=armv8.2-a -mtune=cortex-a55 -fdiagnostics-color=always'
+    # For Cortex-A55/A76
+    # DEVICE = ' -g -march=armv8.2-a -mtune=cortex-a55 -fdiagnostics-color=always'
+    # For Cortex-A53/A72
+    DEVICE = ' -g -mcpu=cortex-a53 -fdiagnostics-color=always'
     CPPFLAGS= ' -nostdinc -undef -E -P -x assembler-with-cpp'
     CFLAGS = DEVICE + ' -Wall -Wno-cpp'
     AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'