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fix: remove extra space at the end of files

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wirano
2024-07-24 23:18:40 +08:00
committed by Rbb666
parent 229b2bffec
commit d56452e662
170 changed files with 6742 additions and 4645 deletions
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2
bsp/gd32/arm/gd32h759i-start/applications/main.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

2
bsp/gd32/arm/gd32h759i-start/board/board.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*

8
bsp/gd32/arm/gd32h759i-start/board/board.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -19,10 +19,10 @@
#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */
#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
// <o> Internal SRAM memory size[Kbytes] <8-512>
// <i>Default: 512
/* <o> Internal SRAM memory size[Kbytes] <8-512>*/
/* <i>Default: 512*/
#ifdef __ICCARM__
// Use *.icf ram symbal, to avoid hardcode.
/* Use *.icf ram symbal, to avoid hardcode.*/
extern char __ICFEDIT_region_RAM_end__;
#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__
#else

32
bsp/gd32/arm/gd32h759i-start/board/gd32h7xx_libopt.h
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_libopt.h
\brief library optional for gd32h7xx
\version 2024-01-05, V1.2.0, demo for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

119
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/GD/GD32H7xx/Source/system_gd32h7xx.c
View File

@@ -38,16 +38,16 @@
/* select a system clock by uncommenting the following line */
/* use IRC64M */
//#define __SYSTEM_CLOCK_IRC64M (__IRC64M)
//#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000)
/*#define __SYSTEM_CLOCK_IRC64M (__IRC64M)*/
/*#define __SYSTEM_CLOCK_600M_PLL0_IRC64M (uint32_t)(600000000)*/
/* use LPIRC4M */
//#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M)
/*#define __SYSTEM_CLOCK_LPIRC4M (__LPIRC4M)*/
/* use HXTAL(CK_HXTAL = 25M) */
//#define __SYSTEM_CLOCK_HXTAL (__HXTAL)
//#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000)
//#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000)
/*#define __SYSTEM_CLOCK_HXTAL (__HXTAL)*/
/*#define __SYSTEM_CLOCK_200M_PLL0_HXTAL (uint32_t)(200000000)*/
/*#define __SYSTEM_CLOCK_400M_PLL0_HXTAL (uint32_t)(400000000)*/
#define __SYSTEM_CLOCK_600M_PLL0_HXTAL (uint32_t)(600000000)
/*
@@ -63,18 +63,18 @@ Note: the power mode need to match the mcu selection and external power supply c
the following macro SEL_PMU_SMPS_MODE.
*/
#if defined(GD32H7XXI)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO
//#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT
//#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT
/*#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY*/
/*#define SEL_PMU_SMPS_MODE PMU_DIRECT_SMPS_SUPPLY*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT_AND_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT_AND_LDO*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_1V8_SUPPLIES_EXT*/
/*#define SEL_PMU_SMPS_MODE PMU_SMPS_2V5_SUPPLIES_EXT*/
#define SEL_PMU_SMPS_MODE PMU_BYPASS
#elif defined(GD32H7XXZ) | defined(GD32H7XXV)
//#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY
//#define SEL_PMU_SMPS_MODE PMU_BYPASS
/*#define SEL_PMU_SMPS_MODE PMU_LDO_SUPPLY*/
/*#define SEL_PMU_SMPS_MODE PMU_BYPASS*/
#endif
#define SEL_IRC64MDIV 0x00U
@@ -153,7 +153,8 @@ void SystemInit(void)
/* enable IRC64M */
RCU_CTL |= RCU_CTL_IRC64MEN;
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
}
/* no TCM wait state */
@@ -256,8 +257,10 @@ static void system_clock_64m_irc64m(void)
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
while(1)
{
}
}
@@ -281,7 +284,8 @@ static void system_clock_64m_irc64m(void)
RCU_CFG0 |= RCU_CKSYSSRC_IRC64MDIV;
/* wait until IRC64M is selected as system clock */
while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_IRC64MDIV != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@@ -307,8 +311,10 @@ static void system_clock_600m_irc64m(void)
} while((0U == stab_flag) && (IRC64M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_IRC64MSTB))
{
while(1)
{
}
}
@@ -347,7 +353,8 @@ static void system_clock_600m_irc64m(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@@ -355,7 +362,8 @@ static void system_clock_600m_irc64m(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@@ -380,8 +388,10 @@ static void system_clock_4m_lpirc4m(void)
stab_flag = (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB);
} while((0U == stab_flag) && (LPIRC4M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB)) {
while(1) {
if(0U == (RCU_ADDCTL1 & RCU_ADDCTL1_LPIRC4MSTB))
{
while(1)
{
}
}
@@ -402,7 +412,8 @@ static void system_clock_4m_lpirc4m(void)
RCU_CFG0 |= RCU_CKSYSSRC_LPIRC4M;
/* wait until LPIRC4M is selected as system clock */
while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_LPIRC4M != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@@ -427,8 +438,10 @@ static void system_clock_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@@ -449,7 +462,8 @@ static void system_clock_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
/* wait until HXTAL is selected as system clock */
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@@ -474,8 +488,10 @@ static void system_clock_200m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@@ -508,7 +524,8 @@ static void system_clock_200m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@@ -516,7 +533,8 @@ static void system_clock_200m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@@ -541,8 +559,10 @@ static void system_clock_400m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@@ -579,7 +599,8 @@ static void system_clock_400m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@@ -587,7 +608,8 @@ static void system_clock_400m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@@ -612,8 +634,10 @@ static void system_clock_600m_hxtal(void)
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while(1) {
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB))
{
while(1)
{
}
}
@@ -650,7 +674,8 @@ static void system_clock_600m_hxtal(void)
RCU_CTL |= RCU_CTL_PLL0EN;
/* wait until PLL0 is stable */
while(0U == (RCU_CTL & RCU_CTL_PLL0STB)) {
while(0U == (RCU_CTL & RCU_CTL_PLL0STB))
{
}
/* select PLL0 as system clock */
@@ -658,7 +683,8 @@ static void system_clock_600m_hxtal(void)
RCU_CFG0 |= RCU_CKSYSSRC_PLL0P;
/* wait until PLL0 is selected as system clock */
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS)) {
while(RCU_SCSS_PLL0P != (RCU_CFG0 & RCU_CFG0_SCSS))
{
}
}
@@ -677,7 +703,8 @@ void SystemCoreClockUpdate(void)
uint32_t pllpsc = 0U, plln = 0U, pllp = 0U, pllsel = 0U;
sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws) {
switch(sws)
{
/* IRC64M is selected as CK_SYS */
case SEL_IRC64MDIV:
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
@@ -700,10 +727,12 @@ void SystemCoreClockUpdate(void)
/* PLL clock source selection, HXTAL or IRC64M_VALUE or LPIRC4M_VALUE */
pllsel = GET_BITS(RCU_PLLALL, 16, 17);
if(0U == pllsel) {
if(0U == pllsel)
{
irc64div = (1U << GET_BITS(RCU_ADDCTL1, 16, 17));
SystemCoreClock = (IRC64M_VALUE / irc64div / pllpsc) * plln / pllp;
} else if(1U == pllsel) {
} else if(1U == pllsel)
{
SystemCoreClock = (LPIRC4M_VALUE / pllpsc) * plln / pllp;
} else {
SystemCoreClock = (HXTAL_VALUE / pllpsc) * plln / pllp;

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cachel1_armv7.h
View File

@@ -115,7 +115,8 @@ __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
if ( isize > 0 )
{
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
@@ -358,7 +359,8 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
@@ -388,7 +390,8 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
@@ -418,7 +421,8 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
if ( dsize > 0 )
{
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;

22
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang.h
View File

@@ -64,7 +64,8 @@
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
@@ -153,7 +154,8 @@
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
@@ -1217,7 +1219,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1240,7 +1242,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1265,7 +1267,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@@ -1287,7 +1289,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@@ -1309,7 +1311,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1332,7 +1334,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1356,7 +1358,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@@ -1377,7 +1379,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) )
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

22
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_armclang_ltm.h
View File

@@ -64,7 +64,8 @@
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
@@ -152,7 +153,8 @@
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
@@ -1201,7 +1203,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1223,7 +1225,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1247,7 +1249,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@@ -1268,7 +1270,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@@ -1289,7 +1291,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1311,7 +1313,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1334,7 +1336,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@@ -1354,7 +1356,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));

5
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_compiler.h
View File

@@ -103,7 +103,8 @@
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
@@ -236,7 +237,7 @@
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
/* NO RETURN is automatically detected hence no warning here*/
#define __NO_RETURN
#endif
#ifndef __USED

48
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/cmsis_gcc.h
View File

@@ -71,7 +71,8 @@
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
#pragma GCC diagnostic ignored "-Wattributes"
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
struct __attribute__((packed))T_UINT32
{ uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
@@ -154,14 +155,18 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
extern const __zero_table_t __zero_table_start__;
extern const __zero_table_t __zero_table_end__;
for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
for(uint32_t i=0u; i<pTable->wlen; ++i) {
for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable)
{
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = pTable->src[i];
}
}
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
for(uint32_t i=0u; i<pTable->wlen; ++i) {
for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable)
{
for(uint32_t i=0u; i<pTable->wlen; ++i)
{
pTable->dest[i] = 0u;
}
}
@@ -202,7 +207,8 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop)
{
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
@@ -1421,7 +1427,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1442,7 +1448,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1466,7 +1472,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
@@ -1486,7 +1492,7 @@ __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
/* without main extensions, the non-secure PSPLIM is RAZ/WI*/
(void)ProcStackPtrLimit;
#else
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
@@ -1508,7 +1514,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1530,7 +1536,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
return 0U;
#else
uint32_t result;
@@ -1554,7 +1560,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
@@ -1574,7 +1580,7 @@ __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
/* without main extensions, the non-secure MSPLIM is RAZ/WI*/
(void)MainStackPtrLimit;
#else
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
@@ -1596,8 +1602,8 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* Re-enable using built-in when GCC has been fixed*/
/* || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)*/
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
@@ -1622,8 +1628,8 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* Re-enable using built-in when GCC has been fixed*/
/* || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)*/
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
@@ -1995,7 +2001,8 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
} else {
result = __SXTB16(__ROR(op1, rotate)) ;
@@ -2014,7 +2021,8 @@ __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
{
uint32_t result;
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) {
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
{
__ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate));
} else {
result = __SXTAB16(op1, __ROR(op2, rotate));

105
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/CMSIS/mpu_armv7.h
View File

@@ -21,51 +21,51 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) /*/!< MPU Region Size 32 Bytes*/
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) /*/!< MPU Region Size 64 Bytes*/
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) /*/!< MPU Region Size 128 Bytes*/
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) /*/!< MPU Region Size 256 Bytes*/
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) /*/!< MPU Region Size 512 Bytes*/
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) /*/!< MPU Region Size 1 KByte*/
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) /*/!< MPU Region Size 2 KBytes*/
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) /*/!< MPU Region Size 4 KBytes*/
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) /*/!< MPU Region Size 8 KBytes*/
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) /*/!< MPU Region Size 16 KBytes*/
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) /*/!< MPU Region Size 32 KBytes*/
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) /*/!< MPU Region Size 64 KBytes*/
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /*/!< MPU Region Size 128 KBytes*/
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) /*/!< MPU Region Size 256 KBytes*/
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) /*/!< MPU Region Size 512 KBytes*/
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) /*/!< MPU Region Size 1 MByte*/
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) /*/!< MPU Region Size 2 MBytes*/
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) /*/!< MPU Region Size 4 MBytes*/
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) /*/!< MPU Region Size 8 MBytes*/
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) /*/!< MPU Region Size 16 MBytes*/
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) /*/!< MPU Region Size 32 MBytes*/
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) /*/!< MPU Region Size 64 MBytes*/
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) /*/!< MPU Region Size 128 MBytes*/
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) /*/!< MPU Region Size 256 MBytes*/
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) /*/!< MPU Region Size 512 MBytes*/
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) /*/!< MPU Region Size 1 GByte*/
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) /*/!< MPU Region Size 2 GBytes*/
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /*/!< MPU Region Size 4 GBytes*/
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
#define ARM_MPU_AP_NONE 0U /*/!< MPU Access Permission no access*/
#define ARM_MPU_AP_PRIV 1U /*/!< MPU Access Permission privileged access only*/
#define ARM_MPU_AP_URO 2U /*/!< MPU Access Permission unprivileged access read-only*/
#define ARM_MPU_AP_FULL 3U /*/!< MPU Access Permission full access*/
#define ARM_MPU_AP_PRO 5U /*/!< MPU Access Permission privileged access read-only*/
#define ARM_MPU_AP_RO 6U /*/!< MPU Access Permission read-only access*/
/** MPU Region Base Address Register Value
*
@@ -79,12 +79,12 @@
/**
* MPU Memory Access Attributes
*
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
@@ -93,7 +93,7 @@
/**
* MPU Region Attribute and Size Register Value
*
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
@@ -110,7 +110,7 @@
/**
* MPU Region Attribute and Size Register Value
*
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
@@ -119,7 +119,7 @@
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
@@ -129,7 +129,7 @@
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
@@ -140,7 +140,7 @@
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
@@ -153,7 +153,7 @@
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
@@ -181,10 +181,10 @@
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
uint32_t RBAR; /*!< The region base address register value (RBAR)*/
uint32_t RASR; /*!< The region attribute and size register value (RASR) \ref MPU_RASR*/
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
@@ -224,7 +224,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
@@ -235,7 +235,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
@@ -251,7 +251,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
@@ -261,10 +261,11 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
while (cnt > MPU_TYPE_RALIASES)
{
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;

46
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_axiim.h
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_axiim.h
\brief definitions for AXIIM(AXI interconnect matrix)
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -51,7 +51,7 @@ OF SUCH DAMAGE.
#define AXI_COMP_ID0 REG32(AXIIM + 0x00001FF0U) /*!< AXI componet ID0 register */
#define AXI_COMP_ID1 REG32(AXIIM + 0x00001FF4U) /*!< AXI componet ID1 register */
#define AXI_COMP_ID2 REG32(AXIIM + 0x00001FF8U) /*!< AXI componet ID2 register */
#define AXI_COMP_ID3 REG32(AXIIM + 0x00001FFCU) /*!< AXI componet ID3 register */
#define AXI_COMP_ID3 REG32(AXIIM + 0x00001FFCU) /*!< AXI componet ID3 register */
#define AXI_MPXBM_ISS_CTL(mportx) REG32(AXIIM + 0x00002008U + 0x00001000U * (mportx)) /*!< AXI master port x bus matrix issuing functionality control register */
#define AXI_MP0BM_ISS_CTL REG32(AXIIM + 0x00002008U) /*!< AXI master port 0 bus matrix issuing functionality control register */
@@ -89,7 +89,7 @@ OF SUCH DAMAGE.
/* AXI slave port x = 0 to 5 */
#define AXI_SPX_RDQOS_CTL(sportx) REG32(AXIIM + 0x00042100U + 0x00001000U * (sportx)) /*!< AXI slave port x read QOS control register */
#define AXI_SPX_WRQOS_CTL(sportx) REG32(AXIIM + 0x00042104U + 0x00001000U * (sportx)) /*!< AXI slave port x write QOS control register */
#define AXI_SPX_WRQOS_CTL(sportx) REG32(AXIIM + 0x00042104U + 0x00001000U * (sportx)) /*!< AXI slave port x write QOS control register */
#define AXI_SPX_ISS_CTL(sportx) REG32(AXIIM + 0x00042108U + 0x00001000U * (sportx)) /*!< AXI slave port x issuing functionality control register */
#define AXI_PERIPH_ID4_JEP106CCODE BITS(0,3) /*!< JEP106 continuation code */
@@ -106,7 +106,7 @@ OF SUCH DAMAGE.
#define AXI_PERIPH_ID3_CUSTMOD BITS(0,3) /*!< customer modification[3:0] */
#define AXI_PERIPH_ID3_CUSTREV BITS(4,7) /*!< customer version */
#define AXI_COMP_ID0_PREAMB BITS(0,7) /*!< preamble bits[7:0] */
#define AXI_COMP_ID1_PREAMB BITS(0,3) /*!< preamble bits[11:8] */
@@ -131,15 +131,15 @@ OF SUCH DAMAGE.
#define AXI_SPX_AHBISS_CTL_WR_AHB_ISSOV BIT(0) /*!< converts AHB-Lite write transaction to single beat AXI transaction */
#define AXI_SPX_AHBISS_CTL_RD_AHB_ISSOV BIT(1) /*!< converts AHB-Lite read transaction to single beat AXI transaction */
#define AXI_SPX_RDQOS_CTL_RDQOS BITS(0,3) /*!< slave port read channel QoS configure bits */
#define AXI_SPX_RDQOS_CTL_RDQOS BITS(0,3) /*!< slave port read channel QoS configure bits */
#define AXI_SPX_WRQOS_CTL_WRQOS BITS(0,3) /*!< slave port write channel QoS configure bits */
#define AXI_SPX_WRQOS_CTL_WRQOS BITS(0,3) /*!< slave port write channel QoS configure bits */
#define AXI_SPX_ISS_CTL_RD_ISSOV BIT(0) /*!< slave port override ASIB read issuing control bit */
#define AXI_SPX_ISS_CTL_WR_ISSOV BIT(1) /*!< slave port override ASIB write issuing control bit */
/* AXI master port select */
typedef enum
typedef enum
{
MASTER_PORT0 = 0U, /*!< AXI master port 0 */
MASTER_PORT1, /*!< AXI master port 1 */
@@ -152,7 +152,7 @@ typedef enum
} master_port_enum;
/* AXI slave port select */
typedef enum
typedef enum
{
SLAVE_PORT0 = 0U, /*!< AXI slave port 0 */
SLAVE_PORT1, /*!< AXI slave port 1 */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_cau.h
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_cau.h
\brief definitions for the CAU
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_cpdm.h
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_cpdm.h
\brief definitions for the CPDM
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

34
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ctc.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -48,7 +48,7 @@ OF SUCH DAMAGE.
/* bits definitions */
/* CTC_CTL0 */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
@@ -176,7 +176,7 @@ void ctc_interrupt_enable(uint32_t interrupt);
/* disable the CTC interrupt */
void ctc_interrupt_disable(uint32_t interrupt);
/* get CTC interrupt flag */
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
/* clear CTC interrupt flag */
void ctc_interrupt_flag_clear(uint32_t int_flag);

34
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dac.h
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_dac.h
\brief definitions for the DAC
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -72,7 +72,7 @@ OF SUCH DAMAGE.
#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */
#define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DACx_OUT0 DMA underrun interrupt enable */
#define DAC_CTL0_CALEN0 BIT(14) /*!< DACx_OUT0 calibration enable */
#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable bit */
#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable bit */
#define DAC_CTL0_DTEN1 BIT(17) /*!< DACx_OUT1 trigger enable */
#define DAC_CTL0_DTSEL1 BITS(18,19) /*!< DACx_OUT1 trigger selection */
#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */

34
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_dbg.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -110,7 +110,7 @@ OF SUCH DAMAGE.
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
/* register index */
typedef enum
typedef enum
{
DBG_IDX_CTL1 = 0x34U, /*!< DBG control register 1 offset */
DBG_IDX_CTL2 = 0x3CU, /*!< DBG control register 2 offset */
@@ -147,7 +147,7 @@ typedef enum
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 17U), /*!< debug TIMER15 kept when core is halted */
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 16U), /*!< debug TIMER14 kept when core is halted */
DBG_CAN2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 4U), /*!< debug CAN2 kept when core is halted */
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 3U), /*!< debug CAN1 kept when core is halted */
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 2U), /*!< debug CAN0 kept when core is halted */
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 1U), /*!< debug TIMER7 kept when core is halted */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL3, 0U), /*!< debug TIMER0 kept when core is halted */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_enet.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -470,7 +470,7 @@ OF SUCH DAMAGE.
/* ENET DMA Tx descriptor TDES3 */
#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */
//#define SELECT_DESCRIPTORS_ENHANCED_MODE
/*#define SELECT_DESCRIPTORS_ENHANCED_MODE*/
#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE
/* ENET DMA Tx descriptor TDES6 */

56
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_fac.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -42,7 +42,7 @@ OF SUCH DAMAGE.
#define REG16_INT(addr) (*(volatile int16_t *)(uint32_t)(addr))
#define REG32_FLOAT(addr) (*(volatile float *)(uint32_t)(addr))
/* registers definitions */
#define FAC_X0BCFG REG32((FAC) + 0x00000000U) /*!< FAC X0 buffer configure register */
#define FAC_X1BCFG REG32((FAC) + 0x00000004U) /*!< FAC X1 buffer configure register */
@@ -75,14 +75,14 @@ OF SUCH DAMAGE.
#define FAC_YBCFG_Y_WBEF BITS(24,25) /*!< watermark for buffer empty flag */
/* FAC_PARACFG */
#define FAC_PARACFG_IPP BITS(0,7) /*!< input parameter IPP */
#define FAC_PARACFG_IPQ BITS(8,15) /*!< input parameter IPQ */
#define FAC_PARACFG_IPR BITS(16,23) /*!< input parameter IPR */
#define FAC_PARACFG_FUN BITS(24,30) /*!< function */
#define FAC_PARACFG_EXE BIT(31) /*!< execution */
#define FAC_PARACFG_IPP BITS(0,7) /*!< input parameter IPP */
#define FAC_PARACFG_IPQ BITS(8,15) /*!< input parameter IPQ */
#define FAC_PARACFG_IPR BITS(16,23) /*!< input parameter IPR */
#define FAC_PARACFG_FUN BITS(24,30) /*!< function */
#define FAC_PARACFG_EXE BIT(31) /*!< execution */
/* FAC_CTL */
#define FAC_CTL_RIE BIT(0) /*!< read interrupt enable */
#define FAC_CTL_RIE BIT(0) /*!< read interrupt enable */
#define FAC_CTL_WIE BIT(1) /*!< write interrupt enable */
#define FAC_CTL_OFEIE BIT(2) /*!< overflow error interrupt enable */
#define FAC_CTL_UFEIE BIT(3) /*!< underflow error interrupt enable */
@@ -95,7 +95,7 @@ OF SUCH DAMAGE.
#define FAC_CTL_RST BIT(16) /*!< reset FAC unit */
/* FAC_STAT */
#define FAC_STAT_YBEF BIT(0) /*!< Y buffer empty flag */
#define FAC_STAT_YBEF BIT(0) /*!< Y buffer empty flag */
#define FAC_STAT_X0BFF BIT(1) /*!< X0 buffer full flag */
#define FAC_STAT_OFEF BIT(8) /*!< overflow error flag */
#define FAC_STAT_UFEF BIT(9) /*!< underflow error flag */
@@ -167,14 +167,14 @@ typedef struct
#define FAC_THRESHOLD_2 X0BCFG_X0_WBFF(1) /*!< full/empty flag when buffer less than 2 */
#define FAC_THRESHOLD_4 X0BCFG_X0_WBFF(2) /*!< full/empty flag when buffer less than 4 */
#define FAC_THRESHOLD_8 X0BCFG_X0_WBFF(3) /*!< full/empty flag when buffer less than 8 */
/* FAC clip function definitions */
/* FAC clip function definitions */
#define FAC_CP_DISABLE ((uint8_t)0x00U) /*!< clipping disabled */
#define FAC_CP_ENABLE ((uint8_t)0x01U) /*!< clipping enabled */
/* FAC function execution definitions */
#define PARACFG_EXE(regval) (FAC_PARACFG_EXE & ((uint32_t)(regval) << 31))
#define FAC_FUNC_START PARACFG_EXE(0) /*!< start execution function */
#define FAC_FUNC_START PARACFG_EXE(0) /*!< start execution function */
#define FAC_FUNC_STOP PARACFG_EXE(1) /*!< stop execution function */
/* FAC DMA mdoe definitions */
@@ -189,7 +189,7 @@ typedef struct
#define FAC_INT_FLAG_STEF ((uint8_t)0x04U) /*!< saturation error interrupt flag */
#define FAC_INT_FLAG_GSTEF ((uint8_t)0x05U) /*!< gain saturation error interrupt flag */
/* FAC flag definitions */
/* FAC flag definitions */
#define FAC_FLAG_YBEF FAC_STAT_YBEF /*!< Y buffer empty flag */
#define FAC_FLAG_X0BFF FAC_STAT_X0BFF /*!< X0 buffer full flag */
#define FAC_FLAG_OFEF FAC_STAT_OFEF /*!< overflow error flag */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_fwdgt.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

40
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_gpio.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -67,7 +67,7 @@ OF SUCH DAMAGE.
/* bits definitions */
/* GPIO_CTL */
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
@@ -236,8 +236,8 @@ OF SUCH DAMAGE.
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
/* GPIO_AFSEL1 */
/* GPIO_AFSEL1 */
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
@@ -381,9 +381,9 @@ typedef FlagStatus bit_status;
/* GPIO alternate function values */
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
/* GPIO alternate function */
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */

36
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_hau.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -90,7 +90,7 @@ OF SUCH DAMAGE.
#define HAU_STAT_BUSY BIT(3) /*!< busy bit */
/* constants definitions */
/* structure for initialization of the hau */
/* structure for initialization of the hau */
typedef struct
{
uint32_t algo; /*!< algorithm selection */
@@ -114,7 +114,7 @@ typedef struct
uint32_t hau_ctxs_bak[54]; /*!< backup of HAU_CTXSx registers */
}hau_context_parameter_struct;
/* hau_ctl register value */
/* hau_ctl register value */
#define HAU_ALGO_SHA1 ((uint32_t)0x00000000U) /*!< HAU function is SHA1 */
#define HAU_ALGO_SHA224 HAU_CTL_ALGM_1 /*!< HAU function is SHA224 */
#define HAU_ALGO_SHA256 (HAU_CTL_ALGM_1 | HAU_CTL_ALGM_0) /*!< HAU function is SHA256 */
@@ -148,7 +148,7 @@ typedef struct
#define HAU_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */
#define HAU_FLAG_DMA HAU_STAT_DMAS /*!< DMA is enabled (DMAE =1) or a transfer is processing */
#define HAU_FLAG_BUSY HAU_STAT_BUSY /*!< data block is in process */
#define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */
#define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */
#define HAU_INT_FLAG_DATA_INPUT HAU_STAT_DIF /*!< there is enough space (16 bytes) in the input FIFO */
#define HAU_INT_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_mdio.h
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_mdio.h
\brief definitions for the MDIO
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

28
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_mdma.h
View File

@@ -42,13 +42,13 @@ OF SUCH DAMAGE.
/* registers definitions */
#define MDMA_GINTF REG32(MDMA + 0x00000000U) /*!< MDMA global interrupt flag register */
#define MDMA_CHXSTAT0(mdma_chx) REG32(MDMA + 0x00000040U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 0 */
#define MDMA_CHXSTATC(mdma_chx) REG32(MDMA + 0x00000044U + (0x40U * (mdma_chx))) /*!< MDMA channel x status clear register */
#define MDMA_CHXSTAT1(mdma_chx) REG32(MDMA + 0x00000048U + (0x40U * (mdma_chx))) /*!< MDMA channel x status register 1*/
#define MDMA_CHXCTL0(mdma_chx) REG32(MDMA + 0x0000004CU + (0x40U * (mdma_chx))) /*!< MDMA channel x control register 0 */
#define MDMA_CHXCFG(mdma_chx) REG32(MDMA + 0x00000050U + (0x40U * (mdma_chx))) /*!< MDMA channel x configure register */
#define MDMA_CHXBTCFG(mdma_chx) REG32(MDMA + 0x00000054U + (0x40U * (mdma_chx))) /*!< MDMA channel x block transfer configure register */
#define MDMA_CHXBTCFG(mdma_chx) REG32(MDMA + 0x00000054U + (0x40U * (mdma_chx))) /*!< MDMA channel x block transfer configure register */
#define MDMA_CHXSADDR(mdma_chx) REG32(MDMA + 0x00000058U + (0x40U * (mdma_chx))) /*!< MDMA channel x source address register */
#define MDMA_CHXDADDR(mdma_chx) REG32(MDMA + 0x0000005CU + (0x40U * (mdma_chx))) /*!< MDMA channel x destination address register */
#define MDMA_CHXMBADDRU(mdma_chx) REG32(MDMA + 0x00000060U + (0x40U * (mdma_chx))) /*!< MDMA channel x multi-block address update register */
@@ -145,23 +145,23 @@ OF SUCH DAMAGE.
#define MDMA_CHXMBADDRU_SADDRUV BITS(0,15) /*!< source address update value */
#define MDMA_CHXMBADDRU_DADDRUV BITS(16,31) /*!< destination address update value */
/* MDMA_CHxLADDR,x=0..15 */
/* MDMA_CHxLADDR,x=0..15 */
#define MDMA_CHXLADDR_LADDR BITS(0,31) /*!< link address */
/* MDMA_CHxCTL1,x=0..15 */
/* MDMA_CHxCTL1,x=0..15 */
#define MDMA_CHXCTL1_TRIGSEL BITS(0,5) /*!< trigger select */
#define MDMA_CHXCTL1_SBSEL BIT(16) /*!< source bus select */
#define MDMA_CHXCTL1_DBSEL BIT(17) /*!< destination bus select */
/* MDMA_CHxMADDR,x=0..15 */
/* MDMA_CHxMADDR,x=0..15 */
#define MDMA_CHXMADDR_MADDR BITS(0,31) /*!< mask address */
/* MDMA_CHxMDATA,x=0..15 */
/* MDMA_CHxMDATA,x=0..15 */
#define MDMA_CHXMDATA_MDATA BITS(0,31) /*!< mask data */
/* constants definitions */
/* MDMA configuration structure definition */
typedef struct {
typedef struct {
uint32_t request; /*!< specifies the MDMA request */
uint32_t trans_trig_mode; /*!< specifies the trigger transfer mode */
uint32_t priority; /*!< specifies the software priority for the MDMA channelx */
@@ -357,15 +357,15 @@ typedef enum {
#define MDMA_SOURCE_AXI ((uint32_t)0x00000000U) /*!< source bus of channel x is the system bus or AXI bus */
#define MDMA_SOURCE_AHB_TCM MDMA_CHXCTL1_SBSEL /*!< source bus of channel x is AHB bus or TCM */
/* destination bus select */
/* destination bus select */
#define MDMA_DESTINATION_AXI ((uint32_t)0x00000000U) /*!< destination bus of channel x is the system bus or AXI bus */
#define MDMA_DESTINATION_AHB_TCM MDMA_CHXCTL1_DBSEL /*!< destination bus of channel x is AHB bus or TCM */
/* MDMA access error direction */
/* MDMA access error direction */
#define MDMA_READ_ERROR ((uint32_t)0x00000000U) /*!< read access error */
#define MDMA_WRITE_ERROR MDMA_CHXSTAT1_TERRD /*!< write access error */
/* MDMA bufferable write mode */
/* MDMA bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_DISABLE ((uint32_t)0x00000000U) /*!< diable bufferable write mode */
#define MDMA_BUFFERABLE_WRITE_ENABLE MDMA_CHXCFG_BWMOD /*!< enable bufferable write mode */
@@ -382,14 +382,14 @@ typedef enum {
#define MDMA_FLAG_ASERR (MDMA_CHXSTAT1_ASERR | STAT1_FLAG) /*!< address and size error flag */
#define MDMA_FLAG_BZERR (MDMA_CHXSTAT1_BZERR | STAT1_FLAG) /*!< block size error flag */
/* MDMA interrupt */
/* MDMA interrupt */
#define MDMA_INT_ERR MDMA_CHXCTL0_ERRIE /*!< transfer error interrupt */
#define MDMA_INT_CHTC MDMA_CHXCTL0_CHTCIE /*!< channel transfer complete interrupt */
#define MDMA_INT_MBTC MDMA_CHXCTL0_MBTCIE /*!< multi-block transfer complete interrupt */
#define MDMA_INT_BTC MDMA_CHXCTL0_BTCIE /*!< block transfer complete interrupt */
#define MDMA_INT_TC MDMA_CHXCTL0_TCIE /*!< buffer transfer complete interrupt */
/* MDMA interrupt flags */
/* MDMA interrupt flags */
#define MDMA_INT_FLAG_ERR MDMA_CHXSTAT0_ERR /*!< transfer error interrupt flag */
#define MDMA_INT_FLAG_CHTCF MDMA_CHXSTAT0_CHTCF /*!< channel transfer complete interrupt flag */
#define MDMA_INT_FLAG_MBTCF MDMA_CHXSTAT0_MBTCF /*!< multi-block transfer complete interrupt flag */

64
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ospi.h
View File

@@ -285,69 +285,69 @@ typedef struct {
/* OSPI FIFO threshold level set */
#define OSPI_FTL(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U))
#define OSPI_FIFO_THRESHOLD_1 OSPI_FTL(0) /*!< in indirect write mode, there are 1 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_1 OSPI_FTL(0) /*!< in indirect write mode, there are 1 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 1 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_2 OSPI_FTL(1) /*!< in indirect write mode, there are 2 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_2 OSPI_FTL(1) /*!< in indirect write mode, there are 2 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 2 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_3 OSPI_FTL(2) /*!< in indirect write mode, there are 3 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_3 OSPI_FTL(2) /*!< in indirect write mode, there are 3 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 3 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_4 OSPI_FTL(3) /*!< in indirect write mode, there are 4 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_4 OSPI_FTL(3) /*!< in indirect write mode, there are 4 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 4 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_5 OSPI_FTL(4) /*!< in indirect write mode, there are 5 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_5 OSPI_FTL(4) /*!< in indirect write mode, there are 5 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 5 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_6 OSPI_FTL(5) /*!< in indirect write mode, there are 6 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_6 OSPI_FTL(5) /*!< in indirect write mode, there are 6 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 6 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_7 OSPI_FTL(6) /*!< in indirect write mode, there are 7 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_7 OSPI_FTL(6) /*!< in indirect write mode, there are 7 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 7 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_8 OSPI_FTL(7) /*!< in indirect write mode, there are 8 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_8 OSPI_FTL(7) /*!< in indirect write mode, there are 8 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 8 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_9 OSPI_FTL(8) /*!< in indirect write mode, there are 9 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_9 OSPI_FTL(8) /*!< in indirect write mode, there are 9 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 9 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_10 OSPI_FTL(9) /*!< in indirect write mode, there are 10 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_10 OSPI_FTL(9) /*!< in indirect write mode, there are 10 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 10 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_11 OSPI_FTL(10) /*!< in indirect write mode, there are 11 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_11 OSPI_FTL(10) /*!< in indirect write mode, there are 11 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 11 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_12 OSPI_FTL(11) /*!< in indirect write mode, there are 12 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_12 OSPI_FTL(11) /*!< in indirect write mode, there are 12 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 12 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_13 OSPI_FTL(12) /*!< in indirect write mode, there are 13 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_13 OSPI_FTL(12) /*!< in indirect write mode, there are 13 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 13 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_14 OSPI_FTL(13) /*!< in indirect write mode, there are 14 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_14 OSPI_FTL(13) /*!< in indirect write mode, there are 14 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 14 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_15 OSPI_FTL(14) /*!< in indirect write mode, there are 15 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_15 OSPI_FTL(14) /*!< in indirect write mode, there are 15 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 15 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_16 OSPI_FTL(15) /*!< in indirect write mode, there are 16 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_16 OSPI_FTL(15) /*!< in indirect write mode, there are 16 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 16 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_17 OSPI_FTL(16) /*!< in indirect write mode, there are 17 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_17 OSPI_FTL(16) /*!< in indirect write mode, there are 17 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 17 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_18 OSPI_FTL(17) /*!< in indirect write mode, there are 18 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_18 OSPI_FTL(17) /*!< in indirect write mode, there are 18 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 18 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_19 OSPI_FTL(18) /*!< in indirect write mode, there are 19 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_19 OSPI_FTL(18) /*!< in indirect write mode, there are 19 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 19 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_20 OSPI_FTL(19) /*!< in indirect write mode, there are 20 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_20 OSPI_FTL(19) /*!< in indirect write mode, there are 20 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 20 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_21 OSPI_FTL(20) /*!< in indirect write mode, there are 21 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_21 OSPI_FTL(20) /*!< in indirect write mode, there are 21 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 21 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_22 OSPI_FTL(21) /*!< in indirect write mode, there are 22 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_22 OSPI_FTL(21) /*!< in indirect write mode, there are 22 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 22 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_23 OSPI_FTL(22) /*!< in indirect write mode, there are 23 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_23 OSPI_FTL(22) /*!< in indirect write mode, there are 23 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 23 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_24 OSPI_FTL(23) /*!< in indirect write mode, there are 24 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_24 OSPI_FTL(23) /*!< in indirect write mode, there are 24 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 24 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_25 OSPI_FTL(24) /*!< in indirect write mode, there are 25 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_25 OSPI_FTL(24) /*!< in indirect write mode, there are 25 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 25 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_26 OSPI_FTL(25) /*!< in indirect write mode, there are 26 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_26 OSPI_FTL(25) /*!< in indirect write mode, there are 26 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 26 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_27 OSPI_FTL(26) /*!< in indirect write mode, there are 27 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_27 OSPI_FTL(26) /*!< in indirect write mode, there are 27 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 27 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_28 OSPI_FTL(27) /*!< in indirect write mode, there are 28 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_28 OSPI_FTL(27) /*!< in indirect write mode, there are 28 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 28 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_29 OSPI_FTL(28) /*!< in indirect write mode, there are 29 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_29 OSPI_FTL(28) /*!< in indirect write mode, there are 29 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 29 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_30 OSPI_FTL(29) /*!< in indirect write mode, there are 30 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_30 OSPI_FTL(29) /*!< in indirect write mode, there are 30 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 30 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_31 OSPI_FTL(30) /*!< in indirect write mode, there are 31 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_31 OSPI_FTL(30) /*!< in indirect write mode, there are 31 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 31 or more free bytes available to be read from the FIFO */
#define OSPI_FIFO_THRESHOLD_32 OSPI_FTL(31) /*!< in indirect write mode, there are 32 or more free bytes available to be written to the FIFO,
#define OSPI_FIFO_THRESHOLD_32 OSPI_FTL(31) /*!< in indirect write mode, there are 32 or more free bytes available to be written to the FIFO,
in indirect read mode, there are 32 or more free bytes available to be read from the FIFO */
/* OSPI chip select high cycle */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_ospim.h
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@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_pmu.h
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@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

42
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_rameccmu.h
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@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -84,9 +84,9 @@ OF SUCH DAMAGE.
#define RAMECCMU_INT_GEIE BIT(0) /*!< global ECC interrupt enable */
#define RAMECCMU_INT_GESERRIE BIT(1) /*!< global ECC single error interrupt enable */
#define RAMECCMU_INT_GEDERRIE BIT(2) /*!< global ECC double error interrupt enable */
#define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */
#define RAMECCMU_INT_GEDERRBWIE BIT(3) /*!< global ECC double error on byte write interrupt enable */
/* RAMECCMU_MxCTL */
/* RAMECCMU_MxCTL */
#define RAMECCMU_MXCTL_ECCSERRIE BIT(2) /*!< ECC single error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRIE BIT(3) /*!< ECC double error interrupt enable */
#define RAMECCMU_MXCTL_ECCDERRBWIE BIT(4) /*!< ECC double error on byte write interrupt enable */
@@ -101,17 +101,17 @@ OF SUCH DAMAGE.
#define RAMECCMU_MXFADDR_ECCFADDR BITS(0,31) /*!< ECC error failing address */
/* RAMECCMU_MxFDL */
#define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */
#define RAMECCMU_MXFDL_ECCFDL BITS(0,31) /*!< ECC failing data low bits */
/* RAMECCMU_MxFDH */
#define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */
#define RAMECCMU_MXFDH_ECCFDH BITS(0,31) /*!< ECC failing data high bits */
/* RAMECCMU_MxFECODE */
#define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */
#define RAMECCMU_MXFECODE_ECCFECODE BITS(0,31) /*!< ECC failing error code */
/* constants definitions */
/* RAMECCMU monitor select */
typedef enum
typedef enum
{
RAMECCMU0_MONITOR0 = 0x00U, /*!< RAMECCMU0 monitor 0 */
RAMECCMU0_MONITOR1 = 0x01U, /*!< RAMECCMU0 monitor 1 */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_rtc.h
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@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -234,7 +234,7 @@ OF SUCH DAMAGE.
/* RTC_CFG */
#define RTC_CFG_OUT2EN BIT(1) /*!< RTC_OUT is output on PB2 or PC13 */
#define RTC_CFG_ALRMOUTTYPE BIT(0) /*!< RTC_ALARM output is Push-pull output type */
#define RTC_CFG_ALRMOUTTYPE BIT(0) /*!< RTC_ALARM output is Push-pull output type */
/* RTC_BKP0 */
#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */

36
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_spi.h
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@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -194,7 +194,7 @@ OF SUCH DAMAGE.
/* constants definitions */
/* SPI and I2S parameter struct definitions */
typedef struct
{
{
uint32_t device_mode; /*!< SPI master or slave */
uint32_t trans_mode; /*!< SPI transtype */
uint32_t data_size; /*!< SPI data frame size */
@@ -460,7 +460,7 @@ typedef struct
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
/* SPI DMA constants definitions */
/* SPI DMA constants definitions */
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
@@ -496,7 +496,7 @@ typedef struct
#define SPI_I2S_INT_FLAG_SPD ((uint8_t)0x0BU) /*!< suspend interrupt flag */
#define SPI_I2S_INT_FLAG_TC ((uint8_t)0x0CU) /*!< TXFIFO clear interrupt flag */
/* SPI/I2S flag definitions */
/* SPI/I2S flag definitions */
#define SPI_FLAG_RP SPI_STAT_RP /*!< RP flag */
#define SPI_FLAG_TP SPI_STAT_TP /*!< TP flag */
#define SPI_FLAG_DP SPI_STAT_DP /*!< DP flag */

46
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_tli.h
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@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -191,7 +191,7 @@ OF SUCH DAMAGE.
/* constants definitions */
/* TLI parameter struct definitions */
typedef struct
{
{
uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */
uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */
uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */
@@ -207,7 +207,7 @@ typedef struct
uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */
uint32_t signalpolarity_de; /*!< data enable polarity selection */
uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */
}tli_parameter_struct;
}tli_parameter_struct;
/* TLI layer parameter struct definitions */
typedef struct
@@ -228,7 +228,7 @@ typedef struct
uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */
uint16_t layer_frame_line_length; /*!< frame line length */
uint16_t layer_frame_total_line_number; /*!< frame total line number */
}tli_layer_parameter_struct;
}tli_layer_parameter_struct;
/* TLI layer LUT parameter struct definitions */
typedef struct
@@ -237,10 +237,10 @@ typedef struct
uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */
uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */
uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */
}tli_layer_lut_parameter_struct;
}tli_layer_lut_parameter_struct;
/* packeted pixel format */
typedef enum
typedef enum
{
LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */
LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */
@@ -312,7 +312,7 @@ typedef enum
/* initialization functions, TLI enable or disable, TLI reload mode configuration */
/* deinitialize TLI registers */
void tli_deinit(void);
/* initialize the parameters of TLI parameter structure with the default values, it is suggested
/* initialize the parameters of TLI parameter structure with the default values, it is suggested
that call this function after a tli_parameter_struct structure is defined */
void tli_struct_para_init(tli_parameter_struct *tli_struct);
/* initialize TLI */
@@ -327,14 +327,14 @@ void tli_disable(void);
void tli_reload_config(uint8_t reload_mod);
/* TLI layer configuration functions */
/* initialize the parameters of TLI layer structure with the default values, it is suggested
/* initialize the parameters of TLI layer structure with the default values, it is suggested
that call this function after a tli_layer_parameter_struct structure is defined */
void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct);
/* initialize TLI layer */
void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct);
/* reconfigure window position */
void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y);
/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested
/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested
that call this function after a tli_layer_lut_parameter_struct structure is defined */
void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct);
/* initialize TLI layer LUT */

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_tmu.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_trigsel.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_trng.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -136,7 +136,7 @@ typedef enum
/* trng status flag */
typedef enum
{
{
TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */
TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */
TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */

32
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_vref.h
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_vref.h
\brief definitions for the VREF
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

30
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Include/gd32h7xx_wwdgt.h
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

174
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_adc.c
View File

@@ -74,7 +74,8 @@ OF SUCH DAMAGE.
*/
void adc_deinit(uint32_t adc_periph)
{
switch(adc_periph) {
switch(adc_periph)
{
case ADC0:
rcu_periph_reset_enable(RCU_ADC0RST);
rcu_periph_reset_disable(RCU_ADC0RST);
@@ -121,7 +122,8 @@ void adc_deinit(uint32_t adc_periph)
*/
void adc_clock_config(uint32_t adc_periph, uint32_t prescaler)
{
if(ADC2 == adc_periph) {
if(ADC2 == adc_periph)
{
ADC_SYNCCTL(ADC2) &= ~((uint32_t)(ADC_SYNCCTL_ADCCK | ADC_SYNCCTL_ADCSCK));
ADC_SYNCCTL(ADC2) |= (uint32_t)prescaler;
} else {
@@ -144,29 +146,36 @@ void adc_clock_config(uint32_t adc_periph, uint32_t prescaler)
*/
void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(RESET != (function & ADC_SCAN_MODE)) {
if(ENABLE == newvalue)
{
if(RESET != (function & ADC_SCAN_MODE))
{
/* enable scan mode */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_SCAN_MODE;
}
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) {
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO))
{
/* enable inserted channel group convert automatically */
ADC_CTL0(adc_periph) |= (uint32_t)ADC_INSERTED_CHANNEL_AUTO;
}
if(RESET != (function & ADC_CONTINUOUS_MODE)) {
if(RESET != (function & ADC_CONTINUOUS_MODE))
{
/* enable continuous mode */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CONTINUOUS_MODE;
}
} else {
if(RESET != (function & ADC_SCAN_MODE)) {
if(RESET != (function & ADC_SCAN_MODE))
{
/* disable scan mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_SCAN_MODE);
}
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) {
if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO))
{
/* disable inserted channel group convert automatically */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_INSERTED_CHANNEL_AUTO);
}
if(RESET != (function & ADC_CONTINUOUS_MODE)) {
if(RESET != (function & ADC_CONTINUOUS_MODE))
{
/* disable continuous mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CONTINUOUS_MODE);
}
@@ -185,10 +194,12 @@ void adc_special_function_config(uint32_t adc_periph, uint32_t function, Control
*/
void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
{
if(ADC_DATAALIGN_RIGHT == data_alignment) {
if(ADC_DATAALIGN_RIGHT == data_alignment)
{
/* LSB alignment */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
} else if(ADC_DATAALIGN_LEFT == data_alignment) {
} else if(ADC_DATAALIGN_LEFT == data_alignment)
{
/* MSB alignment */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_DAL;
} else {
@@ -204,7 +215,8 @@ void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment)
*/
void adc_enable(uint32_t adc_periph)
{
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)) {
if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON))
{
/* enable ADC */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
}
@@ -234,10 +246,12 @@ void adc_disable(uint32_t adc_periph)
*/
void adc_calibration_mode_config(uint32_t adc_periph, uint32_t clb_mode)
{
if(ADC_CALIBRATION_OFFSET_MISMATCH == clb_mode) {
if(ADC_CALIBRATION_OFFSET_MISMATCH == clb_mode)
{
/* offset and mismatch mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_CALMOD);
} else if(ADC_CALIBRATION_OFFSET == clb_mode) {
} else if(ADC_CALIBRATION_OFFSET == clb_mode)
{
/* offset mode */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CALMOD;
} else {
@@ -276,12 +290,14 @@ void adc_calibration_enable(uint32_t adc_periph)
/* reset the selected ADC calibration registers */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_RSTCLB;
/* check the RSTCLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)) {
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB))
{
}
/* enable ADC calibration process */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_CLB;
/* check the CLB bit state */
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)) {
while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB))
{
}
}
@@ -302,14 +318,17 @@ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
{
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES);
if(ADC2 == adc_periph) {
if(ADC_RESOLUTION_14B == resolution) {
if(ADC2 == adc_periph)
{
if(ADC_RESOLUTION_14B == resolution)
{
/* illegal parameters */
} else {
ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution - 1U);
}
} else {
if(ADC_RESOLUTION_6B == resolution) {
if(ADC_RESOLUTION_6B == resolution)
{
/* illegal parameters */
} else {
ADC_CTL0(adc_periph) |= (uint32_t)CTL0_DRES(resolution);
@@ -331,7 +350,8 @@ void adc_resolution_config(uint32_t adc_periph, uint32_t resolution)
*/
void adc_internal_channel_config(uint32_t internal_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_CTL1(ADC2) |= (uint32_t)internal_channel;
} else {
ADC_CTL1(ADC2) &= ~((uint32_t)internal_channel);
@@ -425,11 +445,13 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou
{
/* disable discontinuous mode of regular & inserted channel */
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
/* config the number of conversions in discontinuous mode */
ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
if((length <= 8U) && (length >= 1U)) {
if((length <= 8U) && (length >= 1U))
{
ADC_CTL0(adc_periph) |= CTL0_DISNUM((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
}
/* enable regular channel group discontinuous mode */
@@ -461,15 +483,18 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou
*/
void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
{
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
if((length >= 1U) && (length <= 16U)) {
if((length >= 1U) && (length <= 16U))
{
ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
}
break;
case ADC_INSERTED_CHANNEL:
if((length >= 1U) && (length <= 4U)) {
if((length >= 1U) && (length <= 4U))
{
ADC_ISQ0(adc_periph) &= ~((uint32_t)ADC_ISQ0_IL);
ADC_ISQ0(adc_periph) |= ISQ0_IL((uint32_t)(length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
}
@@ -495,14 +520,16 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
uint32_t rsq;
/* configure ADC regular sequence */
if(rank < ADC_REGULAR_CHANNEL_RANK_ONE) {
if(rank < ADC_REGULAR_CHANNEL_RANK_ONE)
{
/* the regular group sequence rank is smaller than one */
rsq = ADC_RSQ8(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH * rank)));
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
rank));
ADC_RSQ8(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THREE) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THREE)
{
/* the regular group sequence rank is smaller than three */
rsq = ADC_RSQ7(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -510,7 +537,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_ONE)));
ADC_RSQ7(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIVE) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIVE)
{
/* the regular group sequence rank is smaller than five */
rsq = ADC_RSQ6(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -518,7 +546,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_THREE)));
ADC_RSQ6(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SEVEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SEVEN)
{
/* the regular group sequence rank is smaller than seven */
rsq = ADC_RSQ5(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -526,7 +555,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_FIVE)));
ADC_RSQ5(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_NINE) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_NINE)
{
/* the regular group sequence rank is smaller than nine */
rsq = ADC_RSQ4(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -534,7 +564,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_SEVEN)));
ADC_RSQ4(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_ELEVEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_ELEVEN)
{
/* the regular group sequence rank is smaller than eleven */
rsq = ADC_RSQ3(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -542,7 +573,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_NINE)));
ADC_RSQ3(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THIRTEEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_THIRTEEN)
{
/* the regular group sequence rank is smaller than thirteen */
rsq = ADC_RSQ2(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -550,7 +582,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_ELEVEN)));
ADC_RSQ2(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIFTEEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_FIFTEEN)
{
/* the regular group sequence rank is smaller than fifteen */
rsq = ADC_RSQ1(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -558,7 +591,8 @@ void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_c
rsq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
(rank - ADC_REGULAR_CHANNEL_RANK_THIRTEEN)));
ADC_RSQ1(adc_periph) = rsq;
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN) {
} else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN)
{
/* the regular group sequence rank is smaller than sixteen */
rsq = ADC_RSQ0(adc_periph);
rsq &= ~((uint32_t)((ADC_RSQX_RSMPN | ADC_RSQX_RSQN) << (ADC_REGULAR_CHANNEL_SHIFT_LENGTH *
@@ -592,13 +626,15 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_
rankx = ADC_OFFSET_LENGTH - inserted_length + rank;
/* configure ADC inserted sequence */
if(rankx < ADC_INSERTED_CHANNEL_RANK_ONE) {
if(rankx < ADC_INSERTED_CHANNEL_RANK_ONE)
{
/* the inserted group sequence rank is smaller than one */
isq = ADC_ISQ2(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx)));
isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH * rankx));
ADC_ISQ2(adc_periph) = isq;
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_THREE) {
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_THREE)
{
/* the inserted group sequence rank is smaller than three */
isq = ADC_ISQ1(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
@@ -606,7 +642,8 @@ void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_
isq |= ((uint32_t)(SQX_SMP(sample_time) | adc_channel) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
(rankx - ADC_INSERTED_CHANNEL_RANK_ONE)));
ADC_ISQ1(adc_periph) = isq;
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_FOUR) {
} else if(rankx < ADC_INSERTED_CHANNEL_RANK_FOUR)
{
/* the inserted group sequence rank is smaller than four */
isq = ADC_ISQ0(adc_periph);
isq &= ~((uint32_t)((ADC_ISQX_ISMPN | ADC_ISQX_ISQN) << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH *
@@ -640,7 +677,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch
inserted_length = (uint8_t)GET_BITS(ADC_ISQ0(adc_periph), 20U, 21U);
num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
if(num <= ADC_OFFSET_LENGTH) {
if(num <= ADC_OFFSET_LENGTH)
{
/* calculate the offset of the register */
num = num * ADC_OFFSET_SHIFT_LENGTH;
/* config the offset of the selected channels */
@@ -660,7 +698,8 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_ch
*/
void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_DIFCTL(adc_periph) |= (uint32_t)adc_channel;
} else {
ADC_DIFCTL(adc_periph) &= ~((uint32_t)adc_channel);
@@ -685,7 +724,8 @@ void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_chan
*/
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t trigger_mode)
{
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
/* configure ADC regular channel group external trigger mode */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC);
@@ -714,11 +754,13 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group,
void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
{
/* enable regular group channel software trigger */
if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL)) {
if(RESET != (adc_channel_group & ADC_REGULAR_CHANNEL))
{
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST;
}
/* enable inserted channel group software trigger */
if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL)) {
if(RESET != (adc_channel_group & ADC_INSERTED_CHANNEL))
{
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST;
}
}
@@ -735,10 +777,12 @@ void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group)
*/
void adc_end_of_conversion_config(uint32_t adc_periph, uint32_t end_selection)
{
if(ADC_EOC_SET_SEQUENCE == end_selection) {
if(ADC_EOC_SET_SEQUENCE == end_selection)
{
/* only at the end of a sequence of regular conversions, the EOC bit is set */
ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM);
} else if(ADC_EOC_SET_CONVERSION == end_selection) {
} else if(ADC_EOC_SET_CONVERSION == end_selection)
{
/* at the end of each regular conversion, the EOC bit is set. Overflow is detected automatically */
ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_EOCM;
} else {
@@ -774,7 +818,8 @@ uint32_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel)
{
uint32_t idata;
/* read the data of the selected channel */
switch(inserted_channel) {
switch(inserted_channel)
{
case ADC_INSERTED_CHANNEL_0:
/* read the data of channel 0 */
idata = ADC_IDATA0(adc_periph);
@@ -831,7 +876,8 @@ void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel
{
ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWD0EN | ADC_CTL0_IWD0EN | ADC_CTL0_WD0SC));
/* select the group */
switch(adc_channel_group) {
switch(adc_channel_group)
{
case ADC_REGULAR_CHANNEL:
ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_RWD0EN;
break;
@@ -870,7 +916,8 @@ void adc_watchdog0_disable(uint32_t adc_periph)
*/
void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_WD1SR(adc_periph) |= (uint32_t)selection_channel;
} else {
ADC_WD1SR(adc_periph) &= ~((uint32_t)selection_channel);
@@ -889,7 +936,8 @@ void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t selection_channe
*/
void adc_watchdog2_channel_config(uint32_t adc_periph, uint32_t selection_channel, ControlStatus newvalue)
{
if(ENABLE == newvalue) {
if(ENABLE == newvalue)
{
ADC_WD2SR(adc_periph) |= (uint32_t)selection_channel;
} else {
ADC_WD2SR(adc_periph) &= ~((uint32_t)selection_channel);
@@ -987,10 +1035,12 @@ void adc_watchdog2_threshold_config(uint32_t adc_periph, uint32_t low_threshold,
*/
void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint16_t ratio)
{
if(ADC_OVERSAMPLING_ALL_CONVERT == mode) {
if(ADC_OVERSAMPLING_ALL_CONVERT == mode)
{
/* all oversampled conversions for a channel are done consecutively after a trigger */
ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
} else if(ADC_OVERSAMPLING_ONE_CONVERT == mode) {
} else if(ADC_OVERSAMPLING_ONE_CONVERT == mode)
{
/* each oversampled conversion for a channel needs a trigger */
ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS;
} else {
@@ -1042,7 +1092,8 @@ void adc_oversample_mode_disable(uint32_t adc_periph)
FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t flag)
{
FlagStatus reval = RESET;
if(ADC_STAT(adc_periph) & flag) {
if(ADC_STAT(adc_periph) & flag)
{
reval = SET;
}
return reval;
@@ -1126,46 +1177,53 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t int_flag)
FlagStatus reval = RESET;
uint32_t state;
/* check the interrupt bits */
switch(int_flag) {
switch(int_flag)
{
case ADC_INT_FLAG_WDE0:
/* get the ADC analog watchdog 0 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE0;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE0IE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_EOC:
/* get the ADC end of group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_EOIC:
/* get the ADC end of inserted group conversion interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_ROVF:
/* get the ADC regular data register overflow interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_ROVF;
if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_WDE1:
/* get the ADC analog watchdog 1 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE1;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE1IE) && state)
{
reval = SET;
}
break;
case ADC_INT_FLAG_WDE2:
/* get the ADC analog watchdog 2 interrupt bits */
state = ADC_STAT(adc_periph) & ADC_STAT_WDE2;
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE2IE) && state) {
if((ADC_CTL0(adc_periph) & ADC_CTL0_WDE2IE) && state)
{
reval = SET;
}
break;

324
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_can.c
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File diff suppressed because it is too large Load Diff

74
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau.c
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_cau.c
\brief CAU driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -408,7 +408,8 @@ void cau_fifo_flush(void)
ControlStatus cau_enable_state_get(void)
{
ControlStatus ret = DISABLE;
if(RESET != (CAU_CTL & CAU_CTL_CAUEN)) {
if(RESET != (CAU_CTL & CAU_CTL_CAUEN))
{
ret = ENABLE;
}
return ret;
@@ -476,7 +477,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
algm_reg = CAU_CTL & CAU_CTL_ALGM;
/* AES or DES */
if((uint32_t)0 != (algm_reg & (~CAU_MODE_TDES_CBC))) {
if((uint32_t)0 != (algm_reg & (~CAU_MODE_TDES_CBC)))
{
/* wait until both the IN and OUT FIFOs are empty (IEM=1 and ONE=0 in the CAU_STAT0 register) and BUSY=0 */
checkbits = CAU_STAT0_IEM;
checkmask = STAT0_AESDES_MASK;
@@ -487,7 +489,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
checkmask = STAT0_TDES_MASK;
}
while((CAU_STAT0 & checkmask) != checkbits) {
while((CAU_STAT0 & checkmask) != checkbits)
{
}
/* stop DMA transfers on the OUT FIFO by clear CAU_DMAEN_DMAOEN=0 */
@@ -513,7 +516,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
cau_context->key_3_high = key_initpara->key_3_high;
cau_context->key_3_low = key_initpara->key_3_low;
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg)) {
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg))
{
/* if not in ECB mode, save the initialization vectors */
cau_context->iv_0_high = CAU_IV0H;
cau_context->iv_0_low = CAU_IV0L;
@@ -522,7 +526,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
}
/* if in GCM/CCM mode, save the context switch registers */
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg)) {
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg))
{
cau_context->gcmccmctxs[0U] = CAU_GCMCCMCTXSx(0U);
cau_context->gcmccmctxs[1U] = CAU_GCMCCMCTXSx(1U);
cau_context->gcmccmctxs[2U] = CAU_GCMCCMCTXSx(2U);
@@ -534,7 +539,8 @@ void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_paramet
}
/* if in GCM mode, save the context switch registers */
if(CAU_MODE_AES_GCM == algm_reg) {
if(CAU_MODE_AES_GCM == algm_reg)
{
cau_context->gcmctxs[0U] = CAU_GCMCTXSx(0U);
cau_context->gcmctxs[1U] = CAU_GCMCTXSx(1U);
cau_context->gcmctxs[2U] = CAU_GCMCTXSx(2U);
@@ -586,7 +592,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
CAU_KEY3H = cau_context->key_3_high;
CAU_KEY3L = cau_context->key_3_low;
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg)) {
if((CAU_MODE_TDES_ECB != algm_reg) && (CAU_MODE_DES_ECB != algm_reg) && (CAU_MODE_AES_ECB != algm_reg))
{
/* restore the initialization vectors */
CAU_IV0H = cau_context->iv_0_high;
CAU_IV0L = cau_context->iv_0_low;
@@ -595,7 +602,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
}
/* if in GCM/CCM mode, restore the context switch registers */
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg)) {
if((CAU_MODE_AES_GCM == algm_reg) || (CAU_MODE_AES_CCM == algm_reg))
{
CAU_GCMCCMCTXSx(0U) = cau_context->gcmccmctxs[0U];
CAU_GCMCCMCTXSx(1U) = cau_context->gcmccmctxs[1U];
CAU_GCMCCMCTXSx(2U) = cau_context->gcmccmctxs[2U];
@@ -607,7 +615,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
}
/* if in GCM mode, restore the context switch registers */
if(CAU_MODE_AES_GCM == algm_reg) {
if(CAU_MODE_AES_GCM == algm_reg)
{
CAU_GCMCTXSx(0U) = cau_context->gcmctxs[0U];
CAU_GCMCTXSx(1U) = cau_context->gcmctxs[1U];
CAU_GCMCTXSx(2U) = cau_context->gcmctxs[2U];
@@ -620,7 +629,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
/* if it is AES ECB/CBC decryption, then first prepare key */
aes_decrypt = CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR);
if(((CAU_MODE_AES_ECB | CAU_DECRYPT) == aes_decrypt) || ((CAU_MODE_AES_CBC | CAU_DECRYPT) == aes_decrypt)) {
if(((CAU_MODE_AES_ECB | CAU_DECRYPT) == aes_decrypt) || ((CAU_MODE_AES_CBC | CAU_DECRYPT) == aes_decrypt))
{
uint32_t alg_dir, algo_mode, swapping;
/* flush IN/OUT FIFOs */
@@ -635,7 +645,8 @@ void cau_context_restore(cau_context_parameter_struct *cau_context)
cau_enable();
/* wait until BUSY=0 */
while((uint32_t)0U != cau_flag_get(CAU_FLAG_BUSY)) {
while((uint32_t)0U != cau_flag_get(CAU_FLAG_BUSY))
{
}
/* parameters for decryption */
@@ -666,7 +677,8 @@ FlagStatus cau_flag_get(uint32_t flag)
FlagStatus ret_flag = RESET;
/* check if the flag is in CAU_STAT1 register */
if(RESET != (flag & FLAG_MASK)) {
if(RESET != (flag & FLAG_MASK))
{
reg = CAU_STAT1;
} else {
/* the flag is in CAU_STAT0 register */
@@ -674,7 +686,8 @@ FlagStatus cau_flag_get(uint32_t flag)
}
/* check the status of the specified CAU flag */
if(RESET != (reg & flag)) {
if(RESET != (reg & flag))
{
ret_flag = SET;
}
@@ -725,7 +738,8 @@ FlagStatus cau_interrupt_flag_get(uint32_t int_flag)
FlagStatus flag = RESET;
/* check the status of the specified CAU interrupt */
if(RESET != (CAU_INTF & int_flag)) {
if(RESET != (CAU_INTF & int_flag))
{
flag = SET;
}

173
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_aes.c
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_cau_aes.c
\brief CAU AES driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -74,7 +74,8 @@ ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
cau_key_init(&key_initpara);
/* AES decryption */
if(CAU_DECRYPT == cau_parameter->alg_dir) {
if(CAU_DECRYPT == cau_parameter->alg_dir)
{
/* flush the IN and OUT FIFOs */
cau_fifo_flush();
/* initialize the CAU peripheral */
@@ -89,7 +90,8 @@ ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output)
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
}
}
@@ -141,7 +143,8 @@ ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
cau_key_init(&key_initpara);
/* AES decryption */
if(CAU_DECRYPT == cau_parameter->alg_dir) {
if(CAU_DECRYPT == cau_parameter->alg_dir)
{
/* flush the IN and OUT FIFOs */
cau_fifo_flush();
/* initialize the CAU peripheral */
@@ -156,7 +159,8 @@ ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output)
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
}
}
@@ -396,11 +400,13 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */
cau_enable();
/* wait for CAUEN bit to be 0 */
while(ENABLE == cau_enable_state_get()) {
while(ENABLE == cau_enable_state_get())
{
}
/* aad phase */
if((uint32_t)0U != cau_parameter->aad_size) {
if((uint32_t)0U != cau_parameter->aad_size)
{
/* select aad phase */
cau_phase_config(CAU_AAD_PHASE);
/* flush the IN and OUT FIFOs */
@@ -410,13 +416,15 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
ret = cau_fill_data(cau_parameter->aad, cau_parameter->aad_size);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
/* encrypt or decrypt phase */
if((uint32_t)0U != cau_parameter->in_length) {
if((uint32_t)0U != cau_parameter->in_length)
{
/* select encrypt or decrypt phase */
cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE);
/* flush the IN and OUT FIFOs */
@@ -427,7 +435,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* AES calculate process */
ret = cau_aes_calculate(cau_parameter->input, cau_parameter->in_length, output);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
@@ -440,7 +449,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */
cau_enable();
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
@@ -450,7 +460,8 @@ ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(__REV((uint32_t)inputlength));
/* wait until the ONE flag is set */
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY))
{
}
/* read the tag in the OUT FIFO */
@@ -510,9 +521,11 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
uint32_t temp_tag[4U];
/* formatting the aad block */
if((uint32_t)0U != aadsize) {
if((uint32_t)0U != aadsize)
{
/* check that the aad length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(aadsize < 65280U) {
if(aadsize < 65280U)
{
aad_buf[head_index++] = (uint8_t)((aadsize >> 8U) & 0xFFU);
aad_buf[head_index++] = (uint8_t)((aadsize) & 0xFFU);
aad_block_size = aadsize + 2U;
@@ -527,13 +540,16 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
aad_block_size = aadsize + 6U;
}
/* copy the aad buffer in internal buffer "HBuffer" */
for(i = 0U; i < aadsize; i++) {
for(i = 0U; i < aadsize; i++)
{
aad_buf[head_index++] = *(uint8_t *)((uint32_t)(aadaddr + i));
}
/* check if the aad block size is modulo 16 */
if(0U != (aad_block_size % 16U)) {
if(0U != (aad_block_size % 16U))
{
/* Pad the aad buffer with 0s till the HBuffer length is modulo 16 */
for(i = aad_block_size; i <= ((aad_block_size / 16U) + 1U) * 16U; i++) {
for(i = aad_block_size; i <= ((aad_block_size / 16U) + 1U) * 16U; i++)
{
aad_buf[i] = 0U;
}
/* set the aad size to modulo 16 */
@@ -544,26 +560,31 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
}
/* formatting the block B0 */
if(0U != aadsize) {
if(0U != aadsize)
{
blockb0[0] = 0x40U;
}
/* flags byte */
blockb0[0] |= (0U | (((((uint8_t) tag_size - 2U) / 2U) & 0x07U) << 3U) | (((uint8_t)(15U - ivsize) - 1U) & 0x07U));
if(ivsize > MAX_CCM_IV_SIZE) {
if(ivsize > MAX_CCM_IV_SIZE)
{
return ERROR;
}
for(i = 0U; i < ivsize; i++) {
for(i = 0U; i < ivsize; i++)
{
blockb0[i + 1U] = *(uint8_t *)((uint32_t)(ivaddr + i));
}
/* the byte length for payload length expressing, which plus the ivsize must equal to 15 bytes */
plen = 15U - ivsize;
/* if the byte length for payload length expressing is more than 4 bytes */
if(plen > 4U) {
if(plen > 4U)
{
/* pad the blockb0 after vectors, and before the last 4 bytes */
for(; i < 11U; i++) {
for(; i < 11U; i++)
{
blockb0[i + 1U] = 0U;
}
blockb0[12U] = (uint8_t)((inputsize >> 24U) & 0xFFU);
@@ -572,7 +593,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
blockb0[15U] = (uint8_t)(inputsize & 0xFFU);
} else {
/* the payload length is expressed in plen bytes */
for(; i < 15U; i++) {
for(; i < 15U; i++)
{
blockb0[i + 1U] = (uint8_t)((inputsize >> ((plen - 1U) * 8U)) & 0xFFU);
plen--;
}
@@ -581,7 +603,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* formatting the initial counter */
/* byte 0: bits 0-2 contain the same encoding of q as in B0 */
counter[0] = blockb0[0] & BLOCK_B0_MASK;
for(i = 1U; i < ivsize + 1U; i++) {
for(i = 1U; i < ivsize + 1U; i++)
{
counter[i] = blockb0[i];
}
/* set the LSB to 1 */
@@ -628,11 +651,13 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(*(uint32_t *)(b0addr));
/* wait for CAUEN bit to be 0 */
while(ENABLE == cau_enable_state_get()) {
while(ENABLE == cau_enable_state_get())
{
}
/* aad phase */
if((uint32_t)0U != aadsize) {
if((uint32_t)0U != aadsize)
{
/* select aad phase */
cau_phase_config(CAU_AAD_PHASE);
/* enable the CAU peripheral */
@@ -640,7 +665,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
ret = cau_fill_data((uint8_t *)aadaddr, aad_block_size);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
@@ -648,7 +674,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* encrypt or decrypt phase */
inputsize = cau_parameter->in_length;
if((uint32_t)0U != inputsize) {
if((uint32_t)0U != inputsize)
{
/* select encrypt or decrypt phase */
cau_phase_config(CAU_ENCRYPT_DECRYPT_PHASE);
/* enable the CAU peripheral */
@@ -657,7 +684,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* AES calculate process */
ret = cau_aes_calculate((uint8_t *)inputaddr, inputsize, (uint8_t *)outputaddr);
if(ERROR == ret) {
if(ERROR == ret)
{
return ret;
}
}
@@ -668,7 +696,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
/* enable the CAU peripheral */
cau_enable();
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
@@ -684,7 +713,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_data_write(*(uint32_t *)(ctraddr) & 0xFEFFFFFFU);
/* wait until the ONE flag is set */
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_OUTFIFO_NO_EMPTY))
{
}
/* read the tag in the OUT FIFO */
@@ -697,7 +727,8 @@ ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint
cau_disable();
/* Copy temporary authentication TAG in user TAG buffer */
for(i = 0U; i < tag_size; i++) {
for(i = 0U; i < tag_size; i++)
{
tag[i] = (uint8_t)(temp_tag[i / 4U] >> (8U * (i % 4U)));
}
@@ -722,7 +753,8 @@ static void cau_aes_key_config(uint8_t *key, uint32_t keysize, cau_key_parameter
{
uint32_t keyaddr = (uint32_t)key;
switch(keysize) {
switch(keysize)
{
/* 128-bit key initialization */
case 128:
cau_aes_keysize_config(CAU_KEYSIZE_128BIT);
@@ -786,16 +818,20 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
__IO uint32_t counter = 0U;
uint32_t busystatus = 0U;
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE) {
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE)
{
/* wait until the IEM flag is set */
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY))
{
}
if(i + BLOCK_DATA_SIZE > in_length) {
if(i + BLOCK_DATA_SIZE > in_length)
{
/* the last block data number is less than 128bit */
uint32_t block_data_temp[4] = {0U};
@@ -804,10 +840,13 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
inputaddr = (uint32_t)block_data_temp;
/* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */
if((CAU_CTL & CAU_CTL_GCM_CCMPH) == CAU_ENCRYPT_DECRYPT_PHASE) {
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT)) {
if((CAU_CTL & CAU_CTL_GCM_CCMPH) == CAU_ENCRYPT_DECRYPT_PHASE)
{
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT)) {
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else {
}
@@ -831,7 +870,8 @@ static ErrStatus cau_fill_data(uint8_t *input, uint32_t in_length)
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
}
@@ -854,17 +894,21 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE) {
for(i = 0U; i < in_length; i += BLOCK_DATA_SIZE)
{
/* wait until the IEM flag is set */
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY)) {
while(RESET == cau_flag_get(CAU_FLAG_INFIFO_EMPTY))
{
}
/* check if the last input data block */
if(i + BLOCK_DATA_SIZE > in_length) {
if(i + BLOCK_DATA_SIZE > in_length)
{
/* the last block data number is less than 128bit */
uint32_t block_data_temp[4] = {0};
@@ -873,9 +917,11 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
inputaddr = (uint32_t)block_data_temp;
/* if GCM encryption or CCM decryption, then configurate NBPILB bits in CTL register */
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT)) {
if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_GCM | CAU_ENCRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT)) {
} else if((CAU_CTL & (CAU_CTL_ALGM | CAU_CTL_CAUDIR)) == (CAU_MODE_AES_CCM | CAU_DECRYPT))
{
CAU_CTL |= CAU_PADDING_BYTES(i + BLOCK_DATA_SIZE - in_length);
} else {
}
@@ -898,7 +944,8 @@ static ErrStatus cau_aes_calculate(uint8_t *input, uint32_t in_length, uint8_t *
counter++;
} while((AESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
} else {
/* read the output block from the output FIFO */

41
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_des.c
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_cau_des.c
\brief CAU DES driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -150,11 +150,13 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *
uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += 8U) {
for(i = 0U; i < in_length; i += 8U)
{
/* write data to the IN FIFO */
cau_data_write(*(uint32_t *)(inputaddr));
inputaddr += 4U;
@@ -168,7 +170,8 @@ static ErrStatus cau_des_calculate(uint8_t *input, uint32_t in_length, uint8_t *
counter++;
} while((DESBUSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
} else {
/* read the output block from the output FIFO */

41
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cau_tdes.c
View File

@@ -1,34 +1,34 @@
/*!
\file gd32h7xx_cau_tdes.c
\brief CAU TDES driver
\version 2024-01-05, V1.2.0, firmware for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -165,11 +165,13 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t
uint32_t busystatus = 0U;
/* the clock is not enabled or there is no embedded CAU peripheral */
if(DISABLE == cau_enable_state_get()) {
if(DISABLE == cau_enable_state_get())
{
return ERROR;
}
for(i = 0U; i < in_length; i += 8U) {
for(i = 0U; i < in_length; i += 8U)
{
/* write data to the IN FIFO */
cau_data_write(*(uint32_t *)(inputaddr));
inputaddr += 4U;
@@ -183,7 +185,8 @@ static ErrStatus cau_tdes_calculate(uint8_t *input, uint32_t in_length, uint8_t
counter++;
} while((TDESBSY_TIMEOUT != counter) && (RESET != busystatus));
if(RESET != busystatus) {
if(RESET != busystatus)
{
return ERROR;
} else {
/* read the output block from the output FIFO */

168
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cmp.c
View File

@@ -44,12 +44,14 @@ OF SUCH DAMAGE.
*/
void cmp_deinit(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ((uint32_t)0x00000000U);
CMP_IFC &= ((uint32_t)0xFFFEFFFFU);
CMP_STAT &= ((uint32_t)0xFFFEFFFEU);
CMP_SR &= ((uint32_t)0x00000000U);
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ((uint32_t)0x00000000U);
CMP_IFC &= ((uint32_t)0xFFFDFFFFU);
CMP_STAT &= ((uint32_t)0xFFFDFFFDU);
@@ -88,13 +90,15 @@ void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t invert
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* initialize comparator 0 mode */
temp = CMP0_CS;
temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST);
temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis);
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* initialize comparator 1 mode */
temp = CMP1_CS;
temp &= ~(uint32_t)(CMP_CS_CMPXM | CMP_CS_CMPXMISEL | CMP_CS_CMPXHST);
@@ -119,12 +123,14 @@ void cmp_noninverting_input_select(cmp_enum cmp_periph, uint32_t noninverting_in
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
temp = CMP0_CS;
temp &= ~(uint32_t)CMP_CS_CMPXPSEL;
temp |= (uint32_t)noninverting_input;
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
temp = CMP1_CS;
temp &= ~(uint32_t)CMP_CS_CMPXPSEL;
temp |= (uint32_t)noninverting_input;
@@ -148,21 +154,25 @@ void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity)
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* initialize comparator 0 output */
temp = CMP0_CS;
/* output polarity */
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity)
{
temp |= (uint32_t)CMP_CS_CMPXPL;
}else{
temp &= ~(uint32_t)CMP_CS_CMPXPL;
}
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* initialize comparator 1 output */
temp = CMP1_CS;
/* output polarity */
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity)
{
temp |= (uint32_t)CMP_CS_CMPXPL;
}else{
temp &= ~(uint32_t)CMP_CS_CMPXPL;
@@ -194,9 +204,11 @@ void cmp_output_init(cmp_enum cmp_periph, uint32_t output_polarity)
*/
void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP_SR &= ~(uint32_t)cmp_output_sel;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP_SR |= cmp_output_sel;
}else{
}
@@ -207,7 +219,7 @@ void cmp_output_mux_config(cmp_enum cmp_periph, uint32_t cmp_output_sel)
\param[in] cmp_periph
\arg CMP0: comparator 0
\arg CMP1: comparator 1
\param[in] blanking_source_selection
\param[in] blanking_source_selection
\arg CMP_BLANKING_NONE: CMP no blanking source
\arg CMP_BLANKING_TIMER0_OC0: CMP TIMER0_CH0 output compare signal selected as blanking source
\arg CMP_BLANKING_TIMER1_OC2: CMP TIMER1_CH2 output compare signal selected as blanking source
@@ -222,12 +234,14 @@ void cmp_blanking_init(cmp_enum cmp_periph, uint32_t blanking_source_selection)
{
uint32_t temp = 0U;
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
temp = CMP0_CS;
temp &= ~(uint32_t)CMP_CS_CMPXBLK;
temp |= (uint32_t)blanking_source_selection;
CMP0_CS = temp;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
temp = CMP1_CS;
temp &= ~(uint32_t)CMP_CS_CMPXBLK;
temp |= (uint32_t)blanking_source_selection;
@@ -246,9 +260,11 @@ void cmp_blanking_init(cmp_enum cmp_periph, uint32_t blanking_source_selection)
*/
void cmp_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXEN;
}else{
}
@@ -264,9 +280,11 @@ void cmp_enable(cmp_enum cmp_periph)
*/
void cmp_disable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXEN;
}else{
}
@@ -304,10 +322,12 @@ void cmp_window_disable(void)
*/
void cmp_lock_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* lock CMP0 */
CMP0_CS |= (uint32_t)CMP_CS_CMPXLK;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* lock CMP1 */
CMP1_CS |= (uint32_t)CMP_CS_CMPXLK;
}else{
@@ -324,9 +344,11 @@ void cmp_lock_enable(cmp_enum cmp_periph)
*/
void cmp_voltage_scaler_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXSEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXSEN;
}else{
}
@@ -342,15 +364,17 @@ void cmp_voltage_scaler_enable(cmp_enum cmp_periph)
*/
void cmp_voltage_scaler_disable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXSEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXSEN;
}else{
}
}
/*!
/*!
\brief enable the scaler bridge
\param[in] cmp_periph
\arg CMP0: comparator 0
@@ -360,9 +384,11 @@ void cmp_voltage_scaler_disable(cmp_enum cmp_periph)
*/
void cmp_scaler_bridge_enable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS |= (uint32_t)CMP_CS_CMPXBEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS |= (uint32_t)CMP_CS_CMPXBEN;
}else{
}
@@ -378,9 +404,11 @@ void cmp_scaler_bridge_enable(cmp_enum cmp_periph)
*/
void cmp_scaler_bridge_disable(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
CMP0_CS &= ~(uint32_t)CMP_CS_CMPXBEN;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
CMP1_CS &= ~(uint32_t)CMP_CS_CMPXBEN;
}else{
}
@@ -396,16 +424,19 @@ void cmp_scaler_bridge_disable(cmp_enum cmp_periph)
*/
uint32_t cmp_output_level_get(cmp_enum cmp_periph)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* get output level of CMP0 */
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP0O)) {
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP0O))
{
return CMP_OUTPUTLEVEL_HIGH;
}else{
return CMP_OUTPUTLEVEL_LOW;
}
}else{
/* get output level of CMP1 */
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP1O)) {
if((uint32_t)RESET != (CMP_STAT & CMP_STAT_CMP1O))
{
return CMP_OUTPUTLEVEL_HIGH;
}else{
return CMP_OUTPUTLEVEL_LOW;
@@ -426,16 +457,22 @@ uint32_t cmp_output_level_get(cmp_enum cmp_periph)
FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag)
{
FlagStatus reval = RESET;
if(CMP0 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
if(0U != (CMP_STAT & CMP_STAT_CMP0IF)){
if(CMP0 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
if(0U != (CMP_STAT & CMP_STAT_CMP0IF))
{
reval = SET;
}
}
}else if(CMP1 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
if(0U != (CMP_STAT & CMP_STAT_CMP1IF)){
}else if(CMP1 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
if(0U != (CMP_STAT & CMP_STAT_CMP1IF))
{
reval = SET;
}
}
@@ -455,12 +492,16 @@ FlagStatus cmp_flag_get(cmp_enum cmp_periph, uint32_t flag)
*/
void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag)
{
if(CMP0 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
if(CMP0 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC;
}
}else if(CMP1 == cmp_periph){
if(CMP_FLAG_COMPARE == flag){
}else if(CMP1 == cmp_periph)
{
if(CMP_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC;
}
}else{
@@ -480,10 +521,12 @@ void cmp_flag_clear(cmp_enum cmp_periph, uint32_t flag)
*/
void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* enable CMP0 interrupt */
CMP0_CS |= (uint32_t)interrupt;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* enable CMP1 interrupt */
CMP1_CS |= (uint32_t)interrupt;
}else{
@@ -503,10 +546,12 @@ void cmp_interrupt_enable(cmp_enum cmp_periph, uint32_t interrupt)
*/
void cmp_interrupt_disable(cmp_enum cmp_periph, uint32_t interrupt)
{
if(CMP0 == cmp_periph){
if(CMP0 == cmp_periph)
{
/* disable CMP0 interrupt */
CMP0_CS &= ~(uint32_t)interrupt;
}else if(CMP1 == cmp_periph){
}else if(CMP1 == cmp_periph)
{
/* disable CMP1 interrupt */
CMP1_CS &= ~(uint32_t)interrupt;
}else{
@@ -527,15 +572,19 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
{
uint32_t intstatus = 0U, flagstatus = 0U;
if(CMP0 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
if(CMP0 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
/* get the corresponding flag bit status */
flagstatus = CMP_STAT & CMP_STAT_CMP0IF;
/* get the interrupt enable bit status */
intstatus = CMP0_CS & CMP_CS_CMPXINTEN;
}
}else if(CMP1 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
}else if(CMP1 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
/* get the corresponding flag bit status */
flagstatus = CMP_STAT & CMP_STAT_CMP1IF;
/* get the interrupt enable bit status */
@@ -544,7 +593,8 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
}else{
}
if((0U != flagstatus) && (0U != intstatus)){
if((0U != flagstatus) && (0U != intstatus))
{
return SET;
}else{
return RESET;
@@ -564,12 +614,16 @@ FlagStatus cmp_interrupt_flag_get(cmp_enum cmp_periph, uint32_t flag)
void cmp_interrupt_flag_clear(cmp_enum cmp_periph, uint32_t flag)
{
/* clear CMP interrupt flag */
if(CMP0 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
if(CMP0 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP0IC;
}
}else if(CMP1 == cmp_periph){
if(CMP_INT_FLAG_COMPARE == flag){
}else if(CMP1 == cmp_periph)
{
if(CMP_INT_FLAG_COMPARE == flag)
{
CMP_IFC |= (uint32_t)CMP_IFC_CMP1IC;
}
}else{

15
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_cpdm.c
View File

@@ -154,7 +154,8 @@ FlagStatus cpdm_delayline_length_valid_flag_get(uint32_t cpdm_periph)
uint32_t reg = 0U;
reg = CPDM_CFG(cpdm_periph);
if(reg & CPDM_DLLENF_MASK) {
if(reg & CPDM_DLLENF_MASK)
{
return SET;
} else {
return RESET;
@@ -214,21 +215,25 @@ void cpdm_clock_output(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock
reg |= CPDM_MAX_PHASE;
CPDM_CFG(cpdm_periph) = (uint32_t)reg;
for(delay_count = 0U; delay_count <= CPDM_MAX_DELAY_STEP_COUNT; delay_count++) {
for(delay_count = 0U; delay_count <= CPDM_MAX_DELAY_STEP_COUNT; delay_count++)
{
reg = CPDM_CFG(cpdm_periph);
reg &= CPDM_DLSTCNT_MASK;
/* configure delay line step count */
reg |= delay_count << CPDM_DLSTCNT_OFFSET;
CPDM_CFG(cpdm_periph) = (uint32_t)reg;
while(SET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF)) {
while(SET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF))
{
}
while(RESET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF)) {
while(RESET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF))
{
}
reg_cfg = CPDM_CFG(cpdm_periph);
if((((reg_cfg >> CPDM_DLLEN_OFFSET) & CPDM_DLLEN_10_0_MASK) > 0U) &&
((RESET == (reg_cfg & CPDM_DLLEN_11)) || (RESET == (reg_cfg & CPDM_DLLEN_10)))) {
((RESET == (reg_cfg & CPDM_DLLEN_11)) || (RESET == (reg_cfg & CPDM_DLLEN_10))))
{
break;
}
}

24
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_crc.c
View File

@@ -195,11 +195,14 @@ void crc_polynomial_set(uint32_t poly)
*/
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format)
{
if(INPUT_FORMAT_WORD == data_format) {
if(INPUT_FORMAT_WORD == data_format)
{
REG32(CRC) = sdata;
} else if(INPUT_FORMAT_HALFWORD == data_format) {
} else if(INPUT_FORMAT_HALFWORD == data_format)
{
REG16(CRC) = (uint16_t)sdata;
} else if(INPUT_FORMAT_BYTE == data_format) {
} else if(INPUT_FORMAT_BYTE == data_format)
{
REG8(CRC) = (uint8_t)sdata;
} else {
}
@@ -226,19 +229,24 @@ uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_forma
uint32_t *data32;
uint32_t index;
if(INPUT_FORMAT_WORD == data_format) {
if(INPUT_FORMAT_WORD == data_format)
{
data32 = (uint32_t *)array;
for(index = 0U; index < size; index++) {
for(index = 0U; index < size; index++)
{
REG32(CRC) = data32[index];
}
} else if(INPUT_FORMAT_HALFWORD == data_format) {
} else if(INPUT_FORMAT_HALFWORD == data_format)
{
data16 = (uint16_t *)array;
for(index = 0U; index < size; index++) {
for(index = 0U; index < size; index++)
{
REG16(CRC) = data16[index];
}
} else {
data8 = (uint8_t *)array;
for(index = 0U; index < size; index++) {
for(index = 0U; index < size; index++)
{
REG8(CRC) = data8[index];
}
}

92
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_ctc.c
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -118,7 +118,7 @@ void ctc_hardware_trim_mode_config(uint32_t hardmode)
CTC_CTL0 |= (uint32_t)hardmode;
}
/*!
/*!
\brief configure reference signal source polarity
\param[in] polarity: reference signal source edge
only one parameter can be selected which is shown as below:
@@ -218,7 +218,8 @@ uint16_t ctc_counter_capture_value_read(void)
*/
FlagStatus ctc_counter_direction_read(void)
{
if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
if(RESET != (CTC_STAT & CTC_STAT_REFDIR))
{
return SET;
}else{
return RESET;
@@ -254,10 +255,10 @@ uint8_t ctc_irc48m_trim_value_read(void)
/*!
\brief get CTC flag
\param[in] flag: the CTC flag
only one parameter can be selected which is shown as below:
only one parameter can be selected which is shown as below:
\arg CTC_FLAG_CKOK: clock trim OK flag
\arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_EREF: expect reference flag
\arg CTC_FLAG_CKERR: clock trim error flag
\arg CTC_FLAG_REFMISS: reference sync pulse miss flag
@@ -267,7 +268,8 @@ uint8_t ctc_irc48m_trim_value_read(void)
*/
FlagStatus ctc_flag_get(uint32_t flag)
{
if(RESET != (CTC_STAT & flag)){
if(RESET != (CTC_STAT & flag))
{
return SET;
}else{
return RESET;
@@ -279,8 +281,8 @@ FlagStatus ctc_flag_get(uint32_t flag)
\param[in] flag: the CTC flag
only one parameter can be selected which is shown as below:
\arg CTC_FLAG_CKOK: clock trim OK flag
\arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_CKWARN: clock trim warning flag
\arg CTC_FLAG_ERR: error flag
\arg CTC_FLAG_EREF: expect reference flag
\arg CTC_FLAG_CKERR: clock trim error flag
\arg CTC_FLAG_REFMISS: reference sync pulse miss flag
@@ -290,7 +292,8 @@ FlagStatus ctc_flag_get(uint32_t flag)
*/
void ctc_flag_clear(uint32_t flag)
{
if(RESET != (flag & CTC_FLAG_MASK)){
if(RESET != (flag & CTC_FLAG_MASK))
{
CTC_INTC |= CTC_INTC_ERRIC;
}else{
CTC_INTC |= flag;
@@ -301,16 +304,16 @@ void ctc_flag_clear(uint32_t flag)
\brief enable the CTC interrupt
\param[in] interrupt: CTC interrupt enable source
one or more parameters can be selected which are shown as below:
\arg CTC_INT_CKOK: clock trim OK interrupt
\arg CTC_INT_CKWARN: clock trim warning interrupt
\arg CTC_INT_ERR: error interrupt
\arg CTC_INT_EREF: expect reference interrupt
\arg CTC_INT_CKOK: clock trim OK interrupt
\arg CTC_INT_CKWARN: clock trim warning interrupt
\arg CTC_INT_ERR: error interrupt
\arg CTC_INT_EREF: expect reference interrupt
\param[out] none
\retval none
*/
void ctc_interrupt_enable(uint32_t interrupt)
{
CTC_CTL0 |= (uint32_t)interrupt;
CTC_CTL0 |= (uint32_t)interrupt;
}
/*!
@@ -318,15 +321,15 @@ void ctc_interrupt_enable(uint32_t interrupt)
\param[in] interrupt: CTC interrupt disable source
one or more parameters can be selected which are shown as below:
\arg CTC_INT_CKOK: clock trim OK interrupt
\arg CTC_INT_CKWARN: clock trim warning interrupt
\arg CTC_INT_CKWARN: clock trim warning interrupt
\arg CTC_INT_ERR: error interrupt
\arg CTC_INT_EREF: expect reference interrupt
\arg CTC_INT_EREF: expect reference interrupt
\param[out] none
\retval none
*/
void ctc_interrupt_disable(uint32_t interrupt)
{
CTC_CTL0 &= (uint32_t)(~interrupt);
CTC_CTL0 &= (uint32_t)(~interrupt);
}
/*!
@@ -334,11 +337,11 @@ void ctc_interrupt_disable(uint32_t interrupt)
\param[in] int_flag: the CTC interrupt flag
only one parameter can be selected which is shown as below:
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt flag
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt flag
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt flag
\arg CTC_INT_FLAG_ERR: error interrupt flag
\arg CTC_INT_FLAG_EREF: expect reference interrupt flag
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt flag
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt flag
\param[out] none
\retval FlagStatus: SET or RESET
@@ -346,18 +349,20 @@ void ctc_interrupt_disable(uint32_t interrupt)
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
{
uint32_t interrupt_flag = 0U, intenable = 0U;
/* check whether the interrupt is enabled */
if(RESET != (int_flag & CTC_FLAG_MASK)){
if(RESET != (int_flag & CTC_FLAG_MASK))
{
intenable = CTC_CTL0 & CTC_CTL0_ERRIE;
}else{
intenable = CTC_CTL0 & int_flag;
}
/* get interrupt flag status */
interrupt_flag = CTC_STAT & int_flag;
if(interrupt_flag && intenable){
if(interrupt_flag && intenable)
{
return SET;
}else{
return RESET;
@@ -370,17 +375,18 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
only one parameter can be selected which is shown as below:
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt flag
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt flag
\arg CTC_INT_FLAG_ERR: error interrupt flag
\arg CTC_INT_FLAG_EREF: expect reference interrupt flag
\arg CTC_INT_FLAG_ERR: error interrupt flag
\arg CTC_INT_FLAG_EREF: expect reference interrupt flag
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt flag
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt flag
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt flag
\param[out] none
\retval none
*/
*/
void ctc_interrupt_flag_clear(uint32_t int_flag)
{
if(RESET != (int_flag & CTC_FLAG_MASK)){
if(RESET != (int_flag & CTC_FLAG_MASK))
{
CTC_INTC |= CTC_INTC_ERRIC;
}else{
CTC_INTC |= int_flag;

179
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dac.c
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -51,7 +51,8 @@ OF SUCH DAMAGE.
*/
void dac_deinit(uint32_t dac_periph)
{
switch(dac_periph){
switch(dac_periph)
{
case DAC0:
/* reset DAC0 */
rcu_periph_reset_enable(RCU_DACRST);
@@ -71,9 +72,11 @@ void dac_deinit(uint32_t dac_periph)
*/
void dac_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN1;
}else{
/* illegal parameters */
@@ -89,9 +92,11 @@ void dac_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_disable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN1);
}else{
/* illegal parameters */
@@ -107,9 +112,11 @@ void dac_disable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN1;
}else{
/* illegal parameters */
@@ -125,9 +132,11 @@ void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN1);
}else{
/* illegal parameters */
@@ -153,11 +162,13 @@ void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DAC0 mode */
DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE0;
DAC_MDCR(dac_periph) |= mode;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DAC1 mode */
DAC_MDCR(dac_periph) &= ~(uint32_t)DAC_MDCR_MODE1;
DAC_MDCR(dac_periph) |= (mode << OUT1_REG_OFFSET);
@@ -176,10 +187,12 @@ void dac_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t mode)
uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out)
{
uint32_t tmp = 0U;
if(DAC_OUT0 == dac_out) {
if(DAC_OUT0 == dac_out)
{
/* get the DAC_OUT_0 trimming value */
tmp = DAC_CALR(dac_periph) & DAC_CALR_OTV0;
} else if(DAC_OUT1 == dac_out) {
} else if(DAC_OUT1 == dac_out)
{
/* get the DAC_OUT_1 trimming value */
tmp = (DAC_CALR(dac_periph) & DAC_CALR_OTV1) >> OUT1_REG_OFFSET;
} else {
@@ -198,16 +211,18 @@ uint32_t dac_trimming_value_get(uint32_t dac_periph, uint32_t dac_out)
void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim_value)
{
uint32_t tmp = 0U;
/* get the trimming value */
tmp = DAC_CALR(dac_periph);
if(DAC_OUT0 == dac_out) {
if(DAC_OUT0 == dac_out)
{
/* set the DACx_OUT0 trimming value */
tmp &= ~(uint32_t)DAC_CALR_OTV0;
tmp |= (trim_value & DAC_CALR_OTV0);
DAC_CALR(dac_periph) = tmp;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* set the DACx_OUT1 trimming value */
tmp &= ~(uint32_t)DAC_CALR_OTV1;
tmp |= ((trim_value << OUT1_REG_OFFSET) & DAC_CALR_OTV1);
@@ -225,10 +240,12 @@ void dac_trimming_value_set(uint32_t dac_periph, uint32_t dac_out, uint32_t trim
*/
void dac_trimming_enable(uint32_t dac_periph, uint32_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* enable the DACx_OUT0 trimming */
DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* enable the DACx_OUT1 trimming */
DAC_CTL0(dac_periph) |= DAC_CTL0_CALEN1;
}else{
@@ -247,10 +264,12 @@ uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
{
uint16_t data = 0U;
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* store the DACx_OUT0 output value */
data = (uint16_t)DAC_OUT0_DO(dac_periph);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* store the DACx_OUT1 output value */
data = (uint16_t)DAC_OUT1_DO(dac_periph);
}else{
@@ -276,8 +295,10 @@ uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data)
{
/* DAC_OUT0 data alignment */
if(DAC_OUT0 == dac_out){
switch(dac_align){
if(DAC_OUT0 == dac_out)
{
switch(dac_align)
{
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
DAC_OUT0_R12DH(dac_periph) = data;
@@ -293,9 +314,11 @@ void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint
default:
break;
}
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* DAC_OUT1 data alignment */
switch(dac_align){
switch(dac_align)
{
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
DAC_OUT1_R12DH(dac_periph) = data;
@@ -325,9 +348,11 @@ void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint
*/
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN1;
}else{
/* illegal parameters */
@@ -343,9 +368,11 @@ void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN1);
}else{
/* illegal parameters */
@@ -365,11 +392,13 @@ void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 trigger source */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL0);
DAC_CTL0(dac_periph) |= triggersource;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 trigger source */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL1);
DAC_CTL0(dac_periph) |= (triggersource << OUT1_REG_OFFSET);
@@ -386,9 +415,11 @@ void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t tr
*/
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR0;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR1;
}else{
/* illegal parameters */
@@ -409,11 +440,13 @@ void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
*/
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 wave mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM0);
DAC_CTL0(dac_periph) |= wave_mode;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 wave mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM1);
DAC_CTL0(dac_periph) |= (wave_mode << OUT1_REG_OFFSET);
@@ -445,11 +478,13 @@ void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mo
*/
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 LFSR noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
DAC_CTL0(dac_periph) |= unmask_bits;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 LFSR noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
DAC_CTL0(dac_periph) |= (unmask_bits << OUT1_REG_OFFSET);
@@ -481,11 +516,13 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask
*/
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude)
{
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 triangle noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
DAC_CTL0(dac_periph) |= amplitude;
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 triangle noise mode */
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
DAC_CTL0(dac_periph) |= (amplitude << OUT1_REG_OFFSET);
@@ -533,7 +570,7 @@ void dac_concurrent_software_trigger_enable(uint32_t dac_periph)
uint32_t swt = 0U;
swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
DAC_SWT(dac_periph) |= (uint32_t)swt;
DAC_SWT(dac_periph) |= (uint32_t)swt;
}
/*!
@@ -553,7 +590,8 @@ void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t d
{
uint32_t data = 0U;
switch(dac_align){
switch(dac_align)
{
/* 12-bit right-aligned data */
case DAC_ALIGN_12B_R:
data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
@@ -588,7 +626,8 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
{
uint32_t tmp = 0U;
if(DAC_OUT0 == dac_out){
if(DAC_OUT0 == dac_out)
{
/* configure DACx_OUT0 Sample & Keep mode */
DAC_SKSTR0(dac_periph) |= (sample_time & DAC_SKSTR0_TSAMP0);
@@ -597,7 +636,8 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
tmp = (DAC_SKRTR(dac_periph) & ~(uint32_t)DAC_SKRTR_TREF0);
DAC_SKRTR(dac_periph) = tmp | (refresh_time & DAC_SKRTR_TREF0);
}else if(DAC_OUT1 == dac_out){
}else if(DAC_OUT1 == dac_out)
{
/* configure DACx_OUT1 Sample & Keep mode */
DAC_SKSTR1(dac_periph) |= (sample_time & DAC_SKSTR1_TSAMP1);
@@ -627,9 +667,11 @@ void dac_sample_keep_mode_config(uint32_t dac_periph, uint32_t dac_out, uint32_t
*/
FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag)
{
if(flag & DAC_STAT_FLAG_MASK0){
if(flag & DAC_STAT_FLAG_MASK0)
{
/* check DAC_STAT0 flag */
if(RESET != (DAC_STAT0(dac_periph) & flag)){
if(RESET != (DAC_STAT0(dac_periph) & flag))
{
return SET;
}else{
return RESET;
@@ -652,7 +694,8 @@ FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag)
*/
void dac_flag_clear(uint32_t dac_periph, uint32_t flag)
{
if(flag & DAC_STAT_FLAG_MASK0){
if(flag & DAC_STAT_FLAG_MASK0)
{
/* check DAC_STAT0 flag */
DAC_STAT0(dac_periph) = (uint32_t)(flag & DAC_STAT_FLAG_MASK0);
}else{
@@ -665,14 +708,15 @@ void dac_flag_clear(uint32_t dac_periph, uint32_t flag)
\param[in] dac_periph: DACx(x=0)
\param[in] interrupt: the DAC interrupt
only one parameter can be selected which is shown as below:
\arg DAC_INT_DDUDR0: DACx_OUT0 DMA underrun interrupt
\arg DAC_INT_DDUDR1: DACx_OUT1 DMA underrun interrupt
\arg DAC_INT_DDUDR0: DACx_OUT0 DMA underrun interrupt
\arg DAC_INT_DDUDR1: DACx_OUT1 DMA underrun interrupt
\param[out] none
\retval none
*/
void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt)
{
if(interrupt & DAC_INT_EN_MASK0){
if(interrupt & DAC_INT_EN_MASK0)
{
/* enable underrun interrupt */
DAC_CTL0(dac_periph) |= (uint32_t)(interrupt & DAC_INT_EN_MASK0);
}else{
@@ -692,7 +736,8 @@ void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt)
*/
void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt)
{
if(interrupt & DAC_INT_EN_MASK0){
if(interrupt & DAC_INT_EN_MASK0)
{
/* disable underrun interrupt */
DAC_CTL0(dac_periph) &= (uint32_t)(~(interrupt & DAC_INT_EN_MASK0));
}else{
@@ -714,7 +759,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag)
{
uint32_t reg1 = 0U, reg2 = 0U;
if(int_flag & DAC_INT_FLAG_MASK0){
if(int_flag & DAC_INT_FLAG_MASK0)
{
/* check underrun interrupt int_flag */
reg1 = DAC_STAT0(dac_periph) & int_flag;
reg2 = DAC_CTL0(dac_periph) & int_flag;
@@ -723,7 +769,8 @@ FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag)
}
/*get DAC interrupt flag status */
if((RESET != reg1) && (RESET != reg2)){
if((RESET != reg1) && (RESET != reg2))
{
return SET;
}else{
return RESET;

38
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dbg.c
View File

@@ -8,27 +8,27 @@
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
@@ -115,9 +115,9 @@ void dbg_trace_pin_disable(void)
}
/*!
\brief trace pin mode selection
\brief trace pin mode selection
\param[in] trace_mode:
\arg TRACE_MODE_ASYNC: trace pin used for async mode
\arg TRACE_MODE_ASYNC: trace pin used for async mode
\arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
\arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
\arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
@@ -133,7 +133,7 @@ void dbg_trace_pin_mode_set(uint32_t trace_mode)
/*!
\brief enable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum
\param[in] dbg_periph: refer to dbg_periph_enum
only one parameter can be selected which are shown as below:
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
@@ -151,7 +151,7 @@ void dbg_periph_enable(dbg_periph_enum dbg_periph)
/*!
\brief disable peripheral behavior when the mcu is in debug mode
\param[in] dbg_periph: refer to dbg_periph_enum
\param[in] dbg_periph: refer to dbg_periph_enum
only one parameter can be selected which are shown as below:
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted

12
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dci.c
View File

@@ -279,7 +279,8 @@ void dci_ccir_disable(void)
*/
void dci_ccir_mode_select(uint32_t ccir_mode)
{
if(CCIR_INTERLACE_MODE == ccir_mode) {
if(CCIR_INTERLACE_MODE == ccir_mode)
{
DCI_CTL |= DCI_CTL_CCMOD;
} else {
DCI_CTL &= ~DCI_CTL_CCMOD;
@@ -346,7 +347,8 @@ FlagStatus dci_flag_get(uint32_t flag)
{
uint32_t stat = 0U;
if(flag >> 31U) {
if(flag >> 31U)
{
/* get flag status from DCI_STAT1 register */
stat = DCI_STAT1;
} else {
@@ -354,7 +356,8 @@ FlagStatus dci_flag_get(uint32_t flag)
stat = DCI_STAT0;
}
if(flag & stat) {
if(flag & stat)
{
return SET;
} else {
return RESET;
@@ -421,7 +424,8 @@ void dci_interrupt_disable(uint32_t interrupt)
*/
FlagStatus dci_interrupt_flag_get(uint32_t int_flag)
{
if(RESET == (DCI_INTF & int_flag)) {
if(RESET == (DCI_INTF & int_flag))
{
return RESET;
} else {
return SET;

105
bsp/gd32/arm/libraries/GD32H7xx_Firmware_Library/GD32H7xx_standard_peripheral/Source/gd32h7xx_dma.c
View File

@@ -35,7 +35,8 @@ OF SUCH DAMAGE.
#include "gd32h7xx_dma.h"
#include <stdlib.h>
#define DMA_WRONG_HANDLE while(1){}
#define DMA_WRONG_HANDLE while(1)
{}
/* DMA register bit offset */
#define CHXFCTL_FCNT_OFFSET ((uint32_t)0x00000003U) /*!< bit offset of FCNT in DMA_CHxFCTL */
@@ -64,7 +65,8 @@ void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE;
if(channelx < DMA_CH4) {
if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
} else {
channelx -= (dma_channel_enum)4;
@@ -160,9 +162,11 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) {
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@@ -170,19 +174,22 @@ void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, d
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure DMA circular mode */
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) {
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
if(DMA0 == dma_periph) {
if(DMA0 == dma_periph)
{
DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
DMAMUX_RM_CHXCFG(channelx) |= init_struct->request;
} else {
@@ -239,9 +246,11 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm
DMA_CHCTL(dma_periph, channelx) = ctl;
/* configure peripheral increasing mode */
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) {
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@@ -249,20 +258,23 @@ void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dm
}
/* configure memory increasing mode */
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
}
/* configure DMA circular mode */
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) {
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
}
if(DMA0 == dma_periph) {
if(DMA0 == dma_periph)
{
DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
DMAMUX_RM_CHXCFG(channelx) |= init_struct->request;
} else {
@@ -301,7 +313,8 @@ void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, u
*/
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address)
{
if(memory_flag) {
if(memory_flag)
{
DMA_CHM1ADDR(dma_periph, channelx) = address;
} else {
DMA_CHM0ADDR(dma_periph, channelx) = address;
@@ -479,7 +492,8 @@ void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uin
*/
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
{
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) {
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
@@ -502,9 +516,11 @@ void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum
*/
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
{
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) {
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
} else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) {
} else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
@@ -612,7 +628,8 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel
/* configure memory1 base address */
DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr;
if(DMA_MEMORY_0 == memory_select) {
if(DMA_MEMORY_0 == memory_select)
{
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS;
} else {
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS;
@@ -630,7 +647,8 @@ void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channel
*/
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx)
{
if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) {
if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS)
{
return DMA_MEMORY_1;
} else {
return DMA_MEMORY_0;
@@ -705,15 +723,18 @@ uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx)
*/
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
if(channelx < DMA_CH4) {
if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) {
if(channelx < DMA_CH4)
{
if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx))
{
return SET;
} else {
return RESET;
}
} else {
channelx -= (dma_channel_enum)4;
if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) {
if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx))
{
return SET;
} else {
return RESET;
@@ -739,7 +760,8 @@ FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t
*/
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
{
if(channelx < DMA_CH4) {
if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
} else {
channelx -= (dma_channel_enum)4;
@@ -765,7 +787,8 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla
*/
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
{
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt)) {
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt))
{
DMA_CHCTL(dma_periph, channelx) |= interrupt;
} else {
DMA_CHFCTL(dma_periph, channelx) |= DMA_CHXFCTL_FEEIE;
@@ -791,7 +814,8 @@ void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32
*/
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
{
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt)) {
if(DMA_CHXFCTL_FEEIE != (DMA_CHXFCTL_FEEIE & interrupt))
{
DMA_CHCTL(dma_periph, channelx) &= ~interrupt;
} else {
DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_FEEIE;
@@ -821,8 +845,10 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
dma_channel_enum channel_flag_offset = channelx;
/* flags for channel0-3 */
if(channelx < DMA_CH4) {
switch(int_flag) {
if(channelx < DMA_CH4)
{
switch(int_flag)
{
case DMA_INTF_FEEIF:
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(int_flag, channelx);
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@@ -849,7 +875,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
/* flags for channel4-7 */
} else {
channel_flag_offset -= (dma_channel_enum)4U;
switch(int_flag) {
switch(int_flag)
{
case DMA_INTF_FEEIF:
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(int_flag, channel_flag_offset);
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
@@ -875,7 +902,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
}
}
if(interrupt_flag && interrupt_enable) {
if(interrupt_flag && interrupt_enable)
{
return SET;
} else {
return RESET;
@@ -900,7 +928,8 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx
*/
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag)
{
if(channelx < DMA_CH4) {
if(channelx < DMA_CH4)
{
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(int_flag, channelx);
} else {
channelx -= (dma_channel_enum)4U;
@@ -916,7 +945,8 @@ void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, ui
*/
void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct)
{
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@@ -949,7 +979,8 @@ void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamu
{
uint32_t cfg;
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@@ -1022,7 +1053,8 @@ void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx)
*/
void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct)
{
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@@ -1055,7 +1087,8 @@ void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamu
{
uint32_t cfg;
if(NULL == init_struct) {
if(NULL == init_struct)
{
DMA_WRONG_HANDLE
}
@@ -1506,7 +1539,8 @@ FlagStatus dmamux_flag_get(dmamux_flag_enum flag)
{
FlagStatus reval;
if(RESET != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag)))) {
if(RESET != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag))))
{
reval = SET;
} else {
reval = RESET;
@@ -1664,7 +1698,8 @@ FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag)
/* get the corresponding flag bit status */
flagstatus = (DMAMUX_REG_VAL(int_flag) & BIT(DMAMUX_BIT_POS(int_flag)));
if(flagstatus && intenable) {
if(flagstatus && intenable)
{
reval = SET;
} else {
reval = RESET;

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