[bsp][stm32] add more drivers for stm32 bsp

2026-09-21 02:06:14 +08:00 · 2018-12-10 09:48:10 +08:00
parent 506ccc573c
commit d509db834b
76 changed files with 8152 additions and 584 deletions
@@ -29,16 +29,35 @@ if GetDepend(['RT_USING_SDCARD']):
 if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
    src += ['drv_soft_i2c.c']

-if GetDepend(['RT_USING_WDT']):
-    src += ['drv_iwg.c']
-
 if GetDepend('RT_USING_LWIP'):
    src += ['drv_emac.c']

+if GetDepend(['RT_USING_ADC']):
+    src += Glob('drv_adc.c')
+
+if GetDepend('BSP_USING_SDRAM'):
+    src += ['drv_sdram.c']
+
+if GetDepend('BSP_USING_ONCHIP_RTC'):
+    src += ['drv_rtc.c']
+    
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
+    src += ['drv_flash/drv_flash_f1.c']
+    
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
+    src += ['drv_flash/drv_flash_f4.c']
+    
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
+    src += ['drv_flash/drv_flash_l4.c']
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
 src += ['drv_common.c']

-path = [cwd]
-path +=[cwd + '/config']
+path =  [cwd]
+path += [cwd + '/config']
+path += [cwd + '/drv_flash']

 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC1,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC2,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC3,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#endif /* __ADC_CONFIG_H__ */
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#endif /* __ADC_CONFIG_H__ */
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#endif /* __ADC_CONFIG_H__ */
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-05     zylx         first version
+ */
+
+#include <board.h>
+
+#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.adc"
+#include <drv_log.h>
+
+static ADC_HandleTypeDef adc_config[] =
+{
+#ifdef BSP_USING_ADC1
+    ADC1_CONFIG,
+#endif
+
+#ifdef BSP_USING_ADC2
+    ADC2_CONFIG,
+#endif
+
+#ifdef BSP_USING_ADC3
+    ADC3_CONFIG,
+#endif
+};
+
+struct stm32_adc
+{
+    ADC_HandleTypeDef ADC_Handler;
+    struct rt_adc_device stm32_adc_device;
+};
+
+static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
+
+static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
+
+    RT_ASSERT(device != RT_NULL);
+
+    if (enabled)
+    {
+#ifdef SOC_SERIES_STM32L4
+        ADC_Enable(stm32_adc_handler);
+#else
+        __HAL_ADC_ENABLE(stm32_adc_handler);
+#endif
+    }
+    else
+    {
+#ifdef SOC_SERIES_STM32L4
+        ADC_Disable(stm32_adc_handler);
+#else
+        __HAL_ADC_DISABLE(stm32_adc_handler);
+#endif
+    }
+
+    return RT_EOK;
+}
+
+static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
+{
+    rt_uint32_t stm32_channel = 0;
+
+    switch (channel)
+    {
+    case  0:
+        stm32_channel = ADC_CHANNEL_0;
+        break;
+    case  1:
+        stm32_channel = ADC_CHANNEL_1;
+        break;
+    case  2:
+        stm32_channel = ADC_CHANNEL_2;
+        break;
+    case  3:
+        stm32_channel = ADC_CHANNEL_3;
+        break;
+    case  4:
+        stm32_channel = ADC_CHANNEL_4;
+        break;
+    case  5:
+        stm32_channel = ADC_CHANNEL_5;
+        break;
+    case  6:
+        stm32_channel = ADC_CHANNEL_6;
+        break;
+    case  7:
+        stm32_channel = ADC_CHANNEL_7;
+        break;
+    case  8:
+        stm32_channel = ADC_CHANNEL_8;
+        break;
+    case  9:
+        stm32_channel = ADC_CHANNEL_9;
+        break;
+    case 10:
+        stm32_channel = ADC_CHANNEL_10;
+        break;
+    case 11:
+        stm32_channel = ADC_CHANNEL_11;
+        break;
+    case 12:
+        stm32_channel = ADC_CHANNEL_12;
+        break;
+    case 13:
+        stm32_channel = ADC_CHANNEL_13;
+        break;
+    case 14:
+        stm32_channel = ADC_CHANNEL_14;
+        break;
+    case 15:
+        stm32_channel = ADC_CHANNEL_15;
+        break;
+    case 16:
+        stm32_channel = ADC_CHANNEL_16;
+        break;
+    case 17:
+        stm32_channel = ADC_CHANNEL_17;
+        break;
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+    case 18:
+        stm32_channel = ADC_CHANNEL_18;
+        break;
+#endif
+    }
+
+    return stm32_channel;
+}
+
+static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    ADC_ChannelConfTypeDef ADC_ChanConf;
+    ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+
+    rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
+
+#if defined(SOC_SERIES_STM32F1)
+    if (channel <= 17)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+    if (channel <= 18)
+#endif
+    {
+        /* set stm32 ADC channel */
+        ADC_ChanConf.Channel =  stm32_adc_get_channel(channel);
+    }
+    else
+    {
+#if defined(SOC_SERIES_STM32F1)
+        LOG_E("ADC channel must be between 0 and 17.");
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+        LOG_E("ADC channel must be between 0 and 18.");
+#endif
+        return -RT_ERROR;
+    }
+    ADC_ChanConf.Rank = 1;
+#if defined(SOC_SERIES_STM32F1)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
+#elif defined(SOC_SERIES_STM32F4)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
+#elif defined(SOC_SERIES_STM32L4)
+    ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
+#endif
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+    ADC_ChanConf.Offset = 0;
+#endif
+#ifdef SOC_SERIES_STM32L4
+    ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
+    ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
+#endif
+    HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
+
+    /* start ADC */
+    HAL_ADC_Start(stm32_adc_handler);
+
+    /* Wait for the ADC to convert */
+    HAL_ADC_PollForConversion(stm32_adc_handler, 10);
+
+    /* get ADC value */
+    *value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops stm_adc_ops =
+{
+    .enabled = stm32_adc_enabled,
+    .convert = stm32_get_adc_value,
+};
+
+static int stm32_adc_init(void)
+{
+    int result = RT_EOK;
+    /* save adc name */
+    char name_buf[6] = {0};
+    int i = 0;
+
+    for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
+    {
+        /* ADC init */
+        stm32_adc_obj[i].ADC_Handler = adc_config[i];
+        if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
+        {
+            LOG_E("ADC%d init failed", i + 1);
+            result = -RT_ERROR;
+        }
+        else
+        {
+            rt_sprintf(name_buf, "adc%d", i + 1);
+            /* register ADC device */
+            if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
+            {
+                LOG_D("ADC%d init success", i + 1);
+            }
+            else
+            {
+                LOG_E("ADC%d register failed", i + 1);
+                result = -RT_ERROR;
+            }
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(stm32_adc_init);
+
+#endif /* BSP_USING_ADC */
@@ -17,12 +17,15 @@
 #if defined(SOC_SERIES_STM32F1)
 #include "f1/uart_config.h"
 #include "f1/spi_config.h"
+#include "f1/adc_config.h"
 #elif  defined(SOC_SERIES_STM32F4)
 #include "f4/uart_config.h"
 #include "f4/spi_config.h"
+#include "f4/adc_config.h"
 #elif  defined(SOC_SERIES_STM32L4)
 #include "l4/uart_config.h"
 #include "l4/spi_config.h"
+#include "l4/adc_config.h"
 #endif

 #endif
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size);
+int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size);
+int stm32_flash_erase(long offset, size_t size);
+
+#endif  /* __DRV_FLASH_H__ */
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_config.h"
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t addr)
+{
+    uint32_t page = 0;
+    page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
+    return page;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result        = RT_EOK;
+    rt_uint32_t addr       = STM32_FLASH_START_ADRESS + offset;
+    rt_uint32_t end_addr   = addr + size;
+
+    if (addr % 4 != 0)
+    {
+        LOG_E("write addr must be 4-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    if (size % 4 != 0)
+    {
+        LOG_E("write size must be 4-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    if ((end_addr) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    while (addr < end_addr)
+    {
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
+        {
+            if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
+            {
+                result = -RT_ERROR;
+                break;
+            }
+            addr += 4;
+            buf  += 4;
+        }
+        else
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(long offset, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+    uint32_t PAGEError = 0;
+
+    /*Variable used for Erase procedure*/
+    FLASH_EraseInitTypeDef EraseInitStruct;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.PageAddress = GetPage(addr);
+    EraseInitStruct.NbPages     = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
+    {
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return result;
+}
+
+#if defined(PKG_USING_FAL)
+const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */
@@ -0,0 +1,312 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_config.h"
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/* Base address of the Flash sectors Bank 1 */
+#define ADDR_FLASH_SECTOR_0     ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_1     ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_2     ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_3     ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_4     ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
+#define ADDR_FLASH_SECTOR_5     ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_6     ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_7     ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_8     ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_9     ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_10    ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_11    ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
+
+/* Base address of the Flash sectors Bank 2 */
+#define ADDR_FLASH_SECTOR_12     ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_13     ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_14     ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_15     ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_16     ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */
+#define ADDR_FLASH_SECTOR_17     ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_18     ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_19     ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_20     ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes  */
+#define ADDR_FLASH_SECTOR_21     ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes  */
+#define ADDR_FLASH_SECTOR_22     ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_23     ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */
+
+/**
+  * @brief  Gets the sector of a given address
+  * @param  None
+  * @retval The sector of a given address
+  */
+static rt_uint32_t GetSector(rt_uint32_t Address)
+{
+    rt_uint32_t sector = 0;
+
+    if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
+    {
+        sector = FLASH_SECTOR_0;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
+    {
+        sector = FLASH_SECTOR_1;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
+    {
+        sector = FLASH_SECTOR_2;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
+    {
+        sector = FLASH_SECTOR_3;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
+    {
+        sector = FLASH_SECTOR_4;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
+    {
+        sector = FLASH_SECTOR_5;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
+    {
+        sector = FLASH_SECTOR_6;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
+    {
+        sector = FLASH_SECTOR_7;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
+    {
+        sector = FLASH_SECTOR_8;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
+    {
+        sector = FLASH_SECTOR_9;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
+    {
+        sector = FLASH_SECTOR_10;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11))
+    {
+        sector = FLASH_SECTOR_11;
+    }
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+    else if((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12))
+    {
+        sector = FLASH_SECTOR_12;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_14) && (Address >= ADDR_FLASH_SECTOR_13))
+    {
+        sector = FLASH_SECTOR_13;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_15) && (Address >= ADDR_FLASH_SECTOR_14))
+    {
+        sector = FLASH_SECTOR_14;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_16) && (Address >= ADDR_FLASH_SECTOR_15))
+    {
+        sector = FLASH_SECTOR_15;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_17) && (Address >= ADDR_FLASH_SECTOR_16))
+    {
+        sector = FLASH_SECTOR_16;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_18) && (Address >= ADDR_FLASH_SECTOR_17))
+    {
+        sector = FLASH_SECTOR_17;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_19) && (Address >= ADDR_FLASH_SECTOR_18))
+    {
+        sector = FLASH_SECTOR_18;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_20) && (Address >= ADDR_FLASH_SECTOR_19))
+    {
+        sector = FLASH_SECTOR_19;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_21) && (Address >= ADDR_FLASH_SECTOR_20))
+    {
+        sector = FLASH_SECTOR_20;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_22) && (Address >= ADDR_FLASH_SECTOR_21))
+    {
+        sector = FLASH_SECTOR_21;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_23) && (Address >= ADDR_FLASH_SECTOR_22))
+    {
+        sector = FLASH_SECTOR_22;
+    }
+    else /* (Address < FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_23) */
+    {
+        sector = FLASH_SECTOR_23;
+    }
+#endif
+    return sector;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void*)(addr + size));
+        return -1;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result      = RT_EOK;
+    rt_uint32_t addr     = STM32_FLASH_START_ADRESS + offset;
+    rt_uint32_t end_addr = addr + size;
+
+    if ((end_addr) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR);
+
+    for (size_t i = 0; i < size; i++, addr++, buf++)
+    {
+        /* write data to flash */
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr, (rt_uint64_t)(*buf)) == HAL_OK)
+        {
+            if (*(rt_uint8_t *)addr != *buf)
+            {
+                result = -RT_ERROR;
+                break;
+            }
+        }
+        else
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(long offset, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+    rt_uint32_t FirstSector = 0, NbOfSectors = 0;
+    rt_uint32_t SECTORError = 0;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    /*Variable used for Erase procedure*/
+    FLASH_EraseInitTypeDef EraseInitStruct;
+
+    /* Unlock the Flash to enable the flash control register access */
+    HAL_FLASH_Unlock();
+
+    /* Get the 1st sector to erase */
+    FirstSector = GetSector(addr);
+    /* Get the number of sector to erase from 1st sector*/
+    NbOfSectors = GetSector(addr + size) - FirstSector + 1;
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase     = FLASH_TYPEERASE_SECTORS;
+    EraseInitStruct.VoltageRange  = FLASH_VOLTAGE_RANGE_3;
+    EraseInitStruct.Sector        = FirstSector;
+    EraseInitStruct.NbSectors     = NbOfSectors;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
+    {
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void*)addr, size);
+    return result;
+}
+
+#if defined(PKG_USING_FAL)
+const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, (128 * 1024), {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_config.h"
+#include "drv_flash.h"    
+ 
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The page of a given address
+  */
+static uint32_t GetPage(uint32_t Addr)
+{
+    uint32_t page = 0;
+
+    if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
+    {
+        /* Bank 1 */
+        page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;
+    }
+    else
+    {
+        /* Bank 2 */
+        page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE;
+    }
+
+    return page;
+}
+
+/**
+  * @brief  Gets the bank of a given address
+  * @param  Addr: Address of the FLASH Memory
+  * @retval The bank of a given address
+  */
+static uint32_t GetBank(uint32_t Addr)
+{
+    uint32_t bank = 0;
+
+    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
+    {
+        /* No Bank swap */
+        if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
+        {
+            bank = FLASH_BANK_1;
+        }
+        else
+        {
+            bank = FLASH_BANK_2;
+        }
+    }
+    else
+    {
+        /* Bank swap */
+        if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
+        {
+            bank = FLASH_BANK_2;
+        }
+        else
+        {
+            bank = FLASH_BANK_1;
+        }
+    }
+
+    return bank;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+
+int stm32_flash_write(long offset, const uint8_t *buf, size_t size)
+{
+    size_t i, j;
+    rt_err_t result = 0;
+    rt_uint64_t write_data = 0, temp_data = 0;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: write outrange flash size! addr is (0x%p)\n", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+    
+    if(addr % 8 != 0)
+    {
+        LOG_E("write addr must be 8-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    if(size % 8 != 0)
+    {
+        LOG_E("write size must be 8-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR);
+
+    if (size < 1)
+    {
+        return -RT_ERROR;
+    }
+
+    for (i = 0; i < size;)
+    {
+        if ((size - i) < 8)
+        {
+            for (j = 0; (size - i) > 0; i++, j++)
+            {
+                temp_data = *buf;
+                write_data = (write_data) | (temp_data << 8 * j);
+                buf ++;
+            }
+        }
+        else
+        {
+            for (j = 0; j < 8; j++, i++)
+            {
+                temp_data = *buf;
+                write_data = (write_data) | (temp_data << 8 * j);
+                buf ++;
+            }
+        }
+
+        /* write data */
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, addr, write_data) == HAL_OK)
+        {
+            /* Check the written value */
+            if (*(uint64_t*)addr != write_data)
+            {
+                LOG_E("ERROR: write data != read data\n");
+                result = -RT_ERROR;
+                goto __exit;
+            }
+        }
+        else
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        temp_data = 0;
+        write_data = 0;
+
+        addr += 8;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+    if (result != 0)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(long offset, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+    uint32_t FirstPage = 0, NbOfPages = 0, BankNumber = 0;
+    uint32_t PAGEError = 0;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    /*Variable used for Erase procedure*/
+    FLASH_EraseInitTypeDef EraseInitStruct;
+    /* Unlock the Flash to enable the flash control register access *************/
+    HAL_FLASH_Unlock();
+
+    /* Clear OPTVERR bit set on virgin samples */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+    /* Get the 1st page to erase */
+    FirstPage = GetPage(addr);
+    /* Get the number of pages to erase from 1st page */
+    NbOfPages = GetPage(addr + size) - FirstPage + 1;
+    /* Get the bank */
+    BankNumber = GetBank(addr);
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
+    EraseInitStruct.Banks       = BankNumber;
+    EraseInitStruct.Page        = FirstPage;
+    EraseInitStruct.NbPages     = NbOfPages;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
+    {
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void*)addr, size);
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, 2048, {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date         Author      Notes
+ * 2018-12-04   balanceTWK        change to new framework
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ONCHIP_RTC
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.rtc"
+#include <drv_log.h>
+
+#define BKUP_REG_DATA 0xA5A5
+
+static struct rt_device rtc;
+
+static RTC_HandleTypeDef RTC_Handler;
+
+static time_t get_rtc_timestamp(void)
+{
+    RTC_TimeTypeDef RTC_TimeStruct;
+    RTC_DateTypeDef RTC_DateStruct;
+    struct tm tm_new;
+
+    HAL_RTC_GetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN);
+    HAL_RTC_GetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN);
+
+    tm_new.tm_sec  = RTC_TimeStruct.Seconds;
+    tm_new.tm_min  = RTC_TimeStruct.Minutes;
+    tm_new.tm_hour = RTC_TimeStruct.Hours;
+    tm_new.tm_mday = RTC_DateStruct.Date;
+    tm_new.tm_mon  = RTC_DateStruct.Month - 1;
+    tm_new.tm_year = RTC_DateStruct.Year + 100;
+
+    LOG_D("get rtc time.");
+    return mktime(&tm_new);
+}
+
+static rt_err_t set_rtc_time_stamp(time_t time_stamp)
+{
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+    RTC_TimeTypeDef RTC_TimeStruct;
+    RTC_DateTypeDef RTC_DateStruct;
+    struct tm *p_tm;
+
+    HAL_PWR_EnableBkUpAccess();
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+    PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+    p_tm = localtime(&time_stamp);
+    if (p_tm->tm_year < 100)
+    {
+        return -RT_ERROR;
+    }
+
+    RTC_TimeStruct.Seconds = p_tm->tm_sec ;
+    RTC_TimeStruct.Minutes = p_tm->tm_min ;
+    RTC_TimeStruct.Hours   = p_tm->tm_hour;
+    RTC_DateStruct.Date    = p_tm->tm_mday;
+    RTC_DateStruct.Month   = p_tm->tm_mon + 1 ;
+    RTC_DateStruct.Year    = p_tm->tm_year - 100;
+    RTC_DateStruct.WeekDay = p_tm->tm_wday + 1;
+
+    if(HAL_RTC_SetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN) != HAL_OK)
+    {
+        return -RT_ERROR;
+    }
+    if(HAL_RTC_SetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN) != HAL_OK)
+    {
+        return -RT_ERROR;
+    }
+
+    LOG_D("set rtc time.");
+    HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR1, BKUP_REG_DATA);
+    return RT_EOK;
+}
+
+static void rt_rtc_init(void)
+{
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+    RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+}
+
+static rt_err_t rt_rtc_config(struct rt_device *dev)
+{
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+    HAL_PWR_EnableBkUpAccess();
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+    PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+    RTC_Handler.Instance = RTC;
+    if (HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR1) != BKUP_REG_DATA)
+    {
+        LOG_W("RTC hasn't been configured, please use <date> command to config.");
+
+#if defined(SOC_SERIES_STM32F1)
+        RTC_Handler.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
+        RTC_Handler.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+        RTC_Handler.Init.AsynchPrediv = 0X7F;
+        RTC_Handler.Init.SynchPrediv = 0XFF;
+        RTC_Handler.Init.HourFormat = RTC_HOURFORMAT_24;
+        RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
+        RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+        RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+#endif
+        if (HAL_RTC_Init(&RTC_Handler) != HAL_OK)
+        {
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+}
+
+static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(dev != RT_NULL);
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+        *(rt_uint32_t *)args = get_rtc_timestamp();
+        LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args());
+        break;
+
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+        if(set_rtc_time_stamp(*(rt_uint32_t *)args))
+        {
+            result = -RT_ERROR;
+        }
+        LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+        break;
+    }
+
+    return result;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops rtc_ops = 
+{
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    rt_rtc_control
+};
+#endif
+
+static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    rt_rtc_init();
+    if (rt_rtc_config(device) != RT_EOK)
+    {
+        return -RT_ERROR;
+    }
+#ifdef RT_USING_DEVICE_OPS
+    device->ops         = &rtc_ops;
+#else
+    device->init        = RT_NULL;
+    device->open        = RT_NULL;
+    device->close       = RT_NULL;
+    device->read        = RT_NULL;
+    device->write       = RT_NULL;
+    device->control     = rt_rtc_control;
+#endif
+    device->type        = RT_Device_Class_RTC;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->user_data   = RT_NULL;
+
+    /* register a character device */
+    return rt_device_register(device, name, flag);
+}
+
+int rt_hw_rtc_init(void)
+{
+    rt_err_t result;
+    result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
+    if (result != RT_EOK)
+    {
+        LOG_E("rtc register err code: %d", result);
+        return result;
+    }
+    LOG_D("rtc init success");
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+
+#endif /* BSP_USING_ONCHIP_RTC */
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-04     zylx         The first version for STM32F4xx
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef BSP_USING_SDRAM
+#include <sdram_port.h>
+
+#define DRV_DEBUG
+#define LOG_TAG             "drv.sdram"
+#include <drv_log.h>
+
+static SDRAM_HandleTypeDef hsdram1;
+static FMC_SDRAM_CommandTypeDef command;
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+static struct rt_memheap system_heap;
+#endif
+
+/**
+  * @brief  Perform the SDRAM exernal memory inialization sequence
+  * @param  hsdram: SDRAM handle
+  * @param  Command: Pointer to SDRAM command structure
+  * @retval None
+  */
+static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
+{
+    __IO uint32_t tmpmrd = 0;
+    uint32_t target_bank = 0;
+
+#if SDRAM_TARGET_BANK == 1
+    target_bank = FMC_SDRAM_CMD_TARGET_BANK1;
+#else
+    target_bank = FMC_SDRAM_CMD_TARGET_BANK2;
+#endif
+
+    /* Configure a clock configuration enable command */
+    Command->CommandMode           = FMC_SDRAM_CMD_CLK_ENABLE;
+    Command->CommandTarget         = target_bank;
+    Command->AutoRefreshNumber     = 1;
+    Command->ModeRegisterDefinition = 0;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+
+    /* Insert 100 ms delay */
+    /* interrupt is not enable, just to delay some time. */
+    for (tmpmrd = 0; tmpmrd < 0xffffff; tmpmrd ++)
+        ;
+
+    /* Configure a PALL (precharge all) command */
+    Command->CommandMode            = FMC_SDRAM_CMD_PALL;
+    Command->CommandTarget          = target_bank;
+    Command->AutoRefreshNumber      = 1;
+    Command->ModeRegisterDefinition = 0;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+
+    /* Configure a Auto-Refresh command */
+    Command->CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
+    Command->CommandTarget          = target_bank;
+    Command->AutoRefreshNumber      = 8;
+    Command->ModeRegisterDefinition = 0;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+
+    /* Program the external memory mode register */
+#if SDRAM_DATA_WIDTH == 8
+    tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1     |
+#elif SDRAM_DATA_WIDTH == 16
+    tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2     |
+#else
+    tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_4     |
+#endif
+             SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL        |
+#if SDRAM_CAS_LATENCY == 3
+             SDRAM_MODEREG_CAS_LATENCY_3                |
+#else
+             SDRAM_MODEREG_CAS_LATENCY_2                |
+#endif
+             SDRAM_MODEREG_OPERATING_MODE_STANDARD      |
+             SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
+
+    Command->CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
+    Command->CommandTarget          = target_bank;
+    Command->AutoRefreshNumber      = 1;
+    Command->ModeRegisterDefinition = tmpmrd;
+
+    /* Send the command */
+    HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
+
+    /* Set the device refresh counter */
+    HAL_SDRAM_ProgramRefreshRate(hsdram, SDRAM_REFRESH_COUNT);
+}
+
+static int SDRAM_Init(void)
+{
+    int result = RT_EOK;
+    FMC_SDRAM_TimingTypeDef SDRAM_Timing;
+
+    /* SDRAM device configuration */
+    hsdram1.Instance = FMC_SDRAM_DEVICE;
+    SDRAM_Timing.LoadToActiveDelay    = LOADTOACTIVEDELAY;
+    SDRAM_Timing.ExitSelfRefreshDelay = EXITSELFREFRESHDELAY;
+    SDRAM_Timing.SelfRefreshTime      = SELFREFRESHTIME;
+    SDRAM_Timing.RowCycleDelay        = ROWCYCLEDELAY;
+    SDRAM_Timing.WriteRecoveryTime    = WRITERECOVERYTIME;
+    SDRAM_Timing.RPDelay              = RPDELAY;
+    SDRAM_Timing.RCDDelay             = RCDDELAY;
+
+#if SDRAM_TARGET_BANK == 1
+    hsdram1.Init.SDBank             = FMC_SDRAM_BANK1;
+#else
+    hsdram1.Init.SDBank             = FMC_SDRAM_BANK2;
+#endif
+#if SDRAM_COLUMN_BITS == 8
+    hsdram1.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_8;
+#elif SDRAM_COLUMN_BITS == 9
+    hsdram1.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_9;
+#elif SDRAM_COLUMN_BITS == 10
+    hsdram1.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_10;
+#else
+    hsdram1.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_11;
+#endif
+#if SDRAM_ROW_BITS == 11
+    hsdram1.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_11;
+#elif SDRAM_ROW_BITS == 12
+    hsdram1.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12;
+#else
+    hsdram1.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_13;
+#endif
+
+#if SDRAM_DATA_WIDTH == 8
+    hsdram1.Init.MemoryDataWidth    = FMC_SDRAM_MEM_BUS_WIDTH_8;
+#elif SDRAM_DATA_WIDTH == 16
+    hsdram1.Init.MemoryDataWidth    = FMC_SDRAM_MEM_BUS_WIDTH_16;
+#else
+    hsdram1.Init.MemoryDataWidth    = FMC_SDRAM_MEM_BUS_WIDTH_32;
+#endif
+    hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
+#if SDRAM_CAS_LATENCY == 1
+    hsdram1.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_1;
+#elif SDRAM_CAS_LATENCY == 2
+    hsdram1.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_2;
+#else
+    hsdram1.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_3;
+#endif
+    hsdram1.Init.WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
+#if SDCLOCK_PERIOD == 2
+    hsdram1.Init.SDClockPeriod      = FMC_SDRAM_CLOCK_PERIOD_2;
+#else
+    hsdram1.Init.SDClockPeriod      = FMC_SDRAM_CLOCK_PERIOD_3;
+#endif
+    hsdram1.Init.ReadBurst          = FMC_SDRAM_RBURST_ENABLE;
+#if SDRAM_RPIPE_DELAY == 0
+    hsdram1.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0;
+#elif SDRAM_RPIPE_DELAY == 1
+    hsdram1.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_1;
+#else
+    hsdram1.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_2;
+#endif
+
+    /* Initialize the SDRAM controller */
+    if (HAL_SDRAM_Init(&hsdram1, &SDRAM_Timing) != HAL_OK)
+    {
+        LOG_E("SDRAM init failed!");
+        result = -RT_ERROR;
+    }
+    else
+    {
+        /* Program the SDRAM external device */
+        SDRAM_Initialization_Sequence(&hsdram1, &command);
+        LOG_D("sdram init success, mapped at 0x%X, size is %d bytes, data width is %d", SDRAM_BANK_ADDR, SDRAM_SIZE, SDRAM_DATA_WIDTH);
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+        /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap */
+        rt_memheap_init(&system_heap, "sdram", (void *)SDRAM_BANK_ADDR, SDRAM_SIZE);
+#endif
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(SDRAM_Init);
+
+#ifdef DRV_DEBUG
+#ifdef FINSH_USING_MSH
+int sdram_test(void)
+{
+    int i = 0;
+    uint32_t start_time = 0, time_cast = 0;
+#if SDRAM_DATA_WIDTH == 8
+    char data_width = 1;
+    uint8_t data = 0;
+#elif SDRAM_DATA_WIDTH == 16
+    char data_width = 2;
+    uint16_t data = 0;
+#else
+    char data_width = 4;
+    uint32_t data = 0;
+#endif
+
+    /* write data */
+    LOG_D("Writing the %ld bytes data, waiting....", SDRAM_SIZE);
+    start_time = rt_tick_get();
+    for (i = 0; i < SDRAM_SIZE / data_width; i++)
+    {
+#if SDRAM_DATA_WIDTH == 8
+        *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
+#elif SDRAM_DATA_WIDTH == 16
+        *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555;
+#else
+        *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
+#endif
+    }
+    time_cast = rt_tick_get() - start_time;
+    LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
+          time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
+
+    /* read data */
+    LOG_D("start Reading and verifying data, waiting....");
+    for (i = 0; i < SDRAM_SIZE / data_width; i++)
+    {
+#if SDRAM_DATA_WIDTH == 8
+        data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width);
+        if (data != 0x55)
+        {
+            LOG_E("SDRAM test failed!");
+            break;
+        }
+#elif SDRAM_DATA_WIDTH == 16
+        data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
+        if (data != 0x5555)
+        {
+            LOG_E("SDRAM test failed!");
+            break;
+        }
+#else
+        data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width);
+        if (data != 0x55555555)
+        {
+            LOG_E("SDRAM test failed!");
+            break;
+        }
+#endif
+    }
+
+    if (i >= SDRAM_SIZE / data_width)
+    {
+        LOG_D("SDRAM test success!");
+    }
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(sdram_test, sdram test)
+#endif /* FINSH_USING_MSH */
+#endif /* DRV_DEBUG */
+#endif /* BSP_USING_SDRAM */
@@ -124,7 +124,7 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
    {
        return -RT_ERROR;
    }
-    __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TC);
+
    return RT_EOK;
 }

@@ -174,6 +174,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
    RT_ASSERT(serial != RT_NULL);

    uart = (struct stm32_uart *)serial->parent.user_data;
+    __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TC);
 #if defined(SOC_SERIES_STM32L4)
    uart->handle.Instance->TDR = c;
 #else
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2018-12-07     balanceTWK        first version
+ */
+
+#include <board.h>
+
+#ifdef RT_USING_WDT
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.wdt"
+#include <drv_log.h>
+
+static IWDG_HandleTypeDef hiwdg;
+static struct rt_watchdog_ops ops;
+static rt_watchdog_t watchdog;
+
+static rt_err_t wdt_init(rt_watchdog_t *wdt)
+{
+    hiwdg.Instance = IWDG;
+    hiwdg.Init.Prescaler = IWDG_PRESCALER_32;
+
+    hiwdg.Init.Reload = 0x00000FFE;
+#if defined(SOC_SERIES_STM32L4)
+    hiwdg.Init.Window = 0x00000FFF;
+#endif
+
+    if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
+    {
+        LOG_E("wdt init failed.");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    switch (cmd)
+    {
+        /* feed the watchdog */
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        HAL_IWDG_Refresh(&hiwdg);
+        break;
+        /* set watchdog timeout */
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        hiwdg.Init.Reload = (rt_uint32_t)arg;
+        if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
+        {
+            LOG_E("wdg set timeout failed.");
+            return -RT_ERROR;
+        }
+        break;
+    default:
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+int rt_wdt_init(void)
+{
+    ops.init = &wdt_init;
+    ops.control = &wdt_control;
+    watchdog.ops = &ops;
+    /* register watchdog device */
+    if (rt_hw_watchdog_register(&watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+    {
+        LOG_E("wdt device register failed.");
+        return -RT_ERROR;
+    }
+    LOG_D("wdt device register success.");
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_wdt_init);
+
+#endif /* RT_USING_WDT */
@@ -40,11 +40,15 @@ ATK-NANO STM32F103 是正点原子推出的一款基于 ARM Cortex-M3 内核的
 | :----------------- | :----------: | :------------------------------------- |
 | USB 转串口        |     支持     |  使用 UART1                              |
 | SPI Flash         |     支持     |     使用 SPI1                            |
+| 电位器             |     支持     |     使用 ADC1                            |
 | **片上外设**      | **支持情况** | **备注**                              |
 | GPIO              |     支持     | PA0, PA1...PD2 ---> PIN: 0, 1...63 |
 | UART              |     支持     | UART1/2/3                             |
 | SPI               |     支持     | SPI1/2                              |
 | I2C               |     支持     | 软件 I2C                              |
+| RTC               |     支持     |                                       |
+| WDT               |     支持     |                                       |
+| ADC               |     支持     |                                       |
 | **扩展模块**      | **支持情况** | **备注**                              |
 | DS18B20/DHT11  |   暂不支持   |                               |

@@ -49,7 +49,7 @@
  */
  
 #define HAL_MODULE_ENABLED  
-/*#define HAL_ADC_MODULE_ENABLED   */
+#define HAL_ADC_MODULE_ENABLED
 /*#define HAL_CRYP_MODULE_ENABLED   */
 /*#define HAL_CAN_MODULE_ENABLED   */
 /*#define HAL_CEC_MODULE_ENABLED   */
@@ -63,7 +63,7 @@
 /*#define HAL_I2C_MODULE_ENABLED   */
 /*#define HAL_I2S_MODULE_ENABLED   */
 /*#define HAL_IRDA_MODULE_ENABLED   */
-/*#define HAL_IWDG_MODULE_ENABLED   */
+#define HAL_IWDG_MODULE_ENABLED
 /*#define HAL_NOR_MODULE_ENABLED   */
 /*#define HAL_NAND_MODULE_ENABLED   */
 /*#define HAL_PCCARD_MODULE_ENABLED   */
@@ -71,7 +71,7 @@
 /*#define HAL_HCD_MODULE_ENABLED   */
 /*#define HAL_PWR_MODULE_ENABLED   */
 /*#define HAL_RCC_MODULE_ENABLED   */
-/*#define HAL_RTC_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
 /*#define HAL_SD_MODULE_ENABLED   */
 /*#define HAL_MMC_MODULE_ENABLED   */
 /*#define HAL_SDRAM_MODULE_ENABLED   */
@@ -62,6 +62,12 @@
 /* USER CODE END PM */

 /* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+
+IWDG_HandleTypeDef hiwdg;
+
+RTC_HandleTypeDef hrtc;
+
 SPI_HandleTypeDef hspi2;

 UART_HandleTypeDef huart1;
@@ -76,6 +82,9 @@ void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
 static void MX_USART1_UART_Init(void);
 static void MX_SPI2_Init(void);
+static void MX_RTC_Init(void);
+static void MX_IWDG_Init(void);
+static void MX_ADC1_Init(void);
 /* USER CODE BEGIN PFP */
 /* Private function prototypes -----------------------------------------------*/

@@ -116,6 +125,9 @@ int main(void)
  MX_GPIO_Init();
  MX_USART1_UART_Init();
  MX_SPI2_Init();
+  MX_RTC_Init();
+  MX_IWDG_Init();
+  MX_ADC1_Init();
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */
@@ -141,13 +153,17 @@ void SystemClock_Config(void)
 {
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};

  /**Initializes the CPU, AHB and APB busses clocks 
  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
@@ -168,6 +184,116 @@ void SystemClock_Config(void)
  {
    Error_Handler();
  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
+  PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /**Common config 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 1;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /**Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_9;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief IWDG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_IWDG_Init(void)
+{
+
+  /* USER CODE BEGIN IWDG_Init 0 */
+
+  /* USER CODE END IWDG_Init 0 */
+
+  /* USER CODE BEGIN IWDG_Init 1 */
+
+  /* USER CODE END IWDG_Init 1 */
+  hiwdg.Instance = IWDG;
+  hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
+  hiwdg.Init.Reload = 4095;
+  if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN IWDG_Init 2 */
+
+  /* USER CODE END IWDG_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /**Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
+  hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
 }

 /**
@@ -250,6 +376,7 @@ static void MX_GPIO_Init(void)
 {

  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
  __HAL_RCC_GPIOD_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();
@@ -101,6 +101,119 @@ void HAL_MspInit(void)
  /* USER CODE END MspInit 1 */
 }

+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC1 GPIO Configuration    
+    PB1     ------> ADC1_IN9 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC1_CLK_DISABLE();
+  
+    /**ADC1 GPIO Configuration    
+    PB1     ------> ADC1_IN9 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1);
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+
+  /* USER CODE END RTC_MspInit 0 */
+    HAL_PWR_EnableBkUpAccess();
+    /* Enable BKP CLK enable for backup registers */
+    __HAL_RCC_BKP_CLK_ENABLE();
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief SPI MSP Initialization
 * This function configures the hardware resources used in this example
@@ -1,26 +1,40 @@
 #MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_9
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.NbrOfConversionFlag=1
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.master=1
 File.Version=6
 KeepUserPlacement=false
 Mcu.Family=STM32F1
-Mcu.IP0=NVIC
-Mcu.IP1=RCC
-Mcu.IP2=SPI2
-Mcu.IP3=SYS
-Mcu.IP4=USART1
-Mcu.IPNb=5
+Mcu.IP0=ADC1
+Mcu.IP1=IWDG
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=RTC
+Mcu.IP5=SPI2
+Mcu.IP6=SYS
+Mcu.IP7=USART1
+Mcu.IPNb=8
 Mcu.Name=STM32F103R(8-B)Tx
 Mcu.Package=LQFP64
-Mcu.Pin0=PD0-OSC_IN
-Mcu.Pin1=PD1-OSC_OUT
-Mcu.Pin2=PB13
-Mcu.Pin3=PB14
-Mcu.Pin4=PB15
-Mcu.Pin5=PA9
-Mcu.Pin6=PA10
-Mcu.Pin7=PA13
-Mcu.Pin8=PA14
-Mcu.Pin9=VP_SYS_VS_Systick
-Mcu.PinsNb=10
+Mcu.Pin0=PC14-OSC32_IN
+Mcu.Pin1=PC15-OSC32_OUT
+Mcu.Pin10=PA13
+Mcu.Pin11=PA14
+Mcu.Pin12=VP_IWDG_VS_IWDG
+Mcu.Pin13=VP_RTC_VS_RTC_Activate
+Mcu.Pin14=VP_SYS_VS_Systick
+Mcu.Pin2=PD0-OSC_IN
+Mcu.Pin3=PD1-OSC_OUT
+Mcu.Pin4=PB1
+Mcu.Pin5=PB13
+Mcu.Pin6=PB14
+Mcu.Pin7=PB15
+Mcu.Pin8=PA9
+Mcu.Pin9=PA10
+Mcu.PinsNb=15
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F103RBTx
@@ -45,12 +59,17 @@ PA14.Mode=Serial_Wire
 PA14.Signal=SYS_JTCK-SWCLK
 PA9.Mode=Asynchronous
 PA9.Signal=USART1_TX
+PB1.Signal=ADCx_IN9
 PB13.Mode=Full_Duplex_Master
 PB13.Signal=SPI2_SCK
 PB14.Mode=Full_Duplex_Master
 PB14.Signal=SPI2_MISO
 PB15.Mode=Full_Duplex_Master
 PB15.Signal=SPI2_MOSI
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
 PCC.Checker=false
 PCC.Line=STM32F103
 PCC.MCU=STM32F103R(8-B)Tx
@@ -90,7 +109,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true
 RCC.ADCFreqValue=36000000
 RCC.AHBFreq_Value=72000000
 RCC.APB1CLKDivider=RCC_HCLK_DIV2
@@ -101,17 +120,21 @@ RCC.APB2TimFreq_Value=72000000
 RCC.FCLKCortexFreq_Value=72000000
 RCC.FamilyName=M
 RCC.HCLKFreq_Value=72000000
-RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
+RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
 RCC.MCOFreq_Value=72000000
 RCC.PLLCLKFreq_Value=72000000
 RCC.PLLMCOFreq_Value=36000000
 RCC.PLLMUL=RCC_PLL_MUL9
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
+RCC.RTCFreq_Value=32768
 RCC.SYSCLKFreq_VALUE=72000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
 RCC.TimSysFreq_Value=72000000
 RCC.USBFreq_Value=72000000
 RCC.VCOOutput2Freq_Value=8000000
+SH.ADCx_IN9.0=ADC1_IN9,IN9
+SH.ADCx_IN9.ConfNb=1
 SPI2.CalculateBaudRate=18.0 MBits/s
 SPI2.Direction=SPI_DIRECTION_2LINES
 SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
@@ -119,6 +142,10 @@ SPI2.Mode=SPI_MODE_MASTER
 SPI2.VirtualType=VM_MASTER
 USART1.IPParameters=VirtualMode
 USART1.VirtualMode=VM_ASYNC
+VP_IWDG_VS_IWDG.Mode=IWDG_Activate
+VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
 board=custom
@@ -24,6 +24,12 @@ menu "Onboard Peripheral Drivers"
        select RT_SFUD_USING_SFDP
        default n

+    config BSP_USING_POT
+        bool "Enable potentiometer"
+        select BSP_USING_ADC
+        select BSP_USING_ADC1
+        default n 
+
 endmenu

 menu "On-chip Peripheral Drivers"
@@ -83,6 +89,36 @@ menu "On-chip Peripheral Drivers"
                default 23
        endif

+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+
+            config BSP_USING_ADC2
+                bool "Enable ADC2"
+                default n
+
+        endif
+
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n 
+
+    config BSP_USING_ONCHIP_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        select RT_USING_LIBC
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
 endmenu

 menu "Board extended module Drivers"
@@ -11,6 +11,7 @@ if GetDepend(['BSP_USING_SPI_FLASH']):

 path = [cwd]
 path += [cwd + '/CubeMX_Config/Inc']
+path += [cwd + '/ports']

 if rtconfig.CROSS_TOOL == 'gcc':
    src += [cwd + '/../../libraries/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xb.s']
@@ -22,6 +22,10 @@
 #define LED1_PIN                       GET_PIN(C,  1)
 #endif

+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE             (128 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
 /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
 #define STM32_SRAM_SIZE      20
 #define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-8      zylx         first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev stm32_onchip_flash;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &stm32_onchip_flash,                                             \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                      \
+{                                                                                           \
+    {FAL_PART_MAGIC_WROD,        "app",   "onchip_flash",       0,          112 * 1024, 0}, \
+    {FAL_PART_MAGIC_WROD,        "param", "onchip_flash",       112* 1024 , 16 * 1024, 0},  \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
@@ -43,6 +43,7 @@
 | RS232        |     支持     | 使用 UART2                            |
 | SPI Flash    |     支持     | W25Q64                                |
 | 以太网       |     支持     | W5500                                 |
+| 电位器       |     支持     | 使用 ADC1                              |
 | SD卡         |   即将支持   |                                       |
 | CAN          |   即将支持   |                                       |
 | SDRAM        |   即将支持   |                                       |
@@ -52,12 +53,13 @@
 | UART         |     支持     | UART1/2/3                             |
 | SPI          |     支持     | SPI1/2/3                              |
 | I2C          |     支持     | 软件 I2C                              |
+| ADC          |     支持     |                                      |
+| RTC          |     支持     |                                      |
+| WDT          |     支持     |                                       |
 | SDIO         |   暂不支持   | 即将支持                              |
-| RTC          |   暂不支持   | 即将支持                              |
 | PWM          |   暂不支持   | 即将支持                              |
 | USB Device   |   暂不支持   | 即将支持                              |
 | USB Host     |   暂不支持   | 即将支持                              |
-| IWG          |   暂不支持   | 即将支持                              |
 | **扩展模块** | **支持情况** | **备注**                              |
 | 暂无         |   暂不支持   | 暂不支持                              |

@@ -49,7 +49,7 @@
  */
  
 #define HAL_MODULE_ENABLED  
-/*#define HAL_ADC_MODULE_ENABLED   */
+#define HAL_ADC_MODULE_ENABLED
 /*#define HAL_CRYP_MODULE_ENABLED   */
 /*#define HAL_CAN_MODULE_ENABLED   */
 /*#define HAL_CEC_MODULE_ENABLED   */
@@ -63,7 +63,7 @@
 /*#define HAL_I2C_MODULE_ENABLED   */
 /*#define HAL_I2S_MODULE_ENABLED   */
 /*#define HAL_IRDA_MODULE_ENABLED   */
-/*#define HAL_IWDG_MODULE_ENABLED   */
+#define HAL_IWDG_MODULE_ENABLED
 /*#define HAL_NOR_MODULE_ENABLED   */
 /*#define HAL_NAND_MODULE_ENABLED   */
 /*#define HAL_PCCARD_MODULE_ENABLED   */
@@ -71,7 +71,7 @@
 /*#define HAL_HCD_MODULE_ENABLED   */
 /*#define HAL_PWR_MODULE_ENABLED   */
 /*#define HAL_RCC_MODULE_ENABLED   */
-/*#define HAL_RTC_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
 /*#define HAL_SD_MODULE_ENABLED   */
 /*#define HAL_MMC_MODULE_ENABLED   */
 /*#define HAL_SDRAM_MODULE_ENABLED   */
@@ -62,6 +62,12 @@
 /* USER CODE END PM */

 /* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+
+IWDG_HandleTypeDef hiwdg;
+
+RTC_HandleTypeDef hrtc;
+
 SPI_HandleTypeDef hspi1;
 SPI_HandleTypeDef hspi2;

@@ -82,6 +88,9 @@ static void MX_SPI2_Init(void);
 static void MX_USART2_UART_Init(void);
 static void MX_SPI1_Init(void);
 static void MX_USART3_UART_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_RTC_Init(void);
+static void MX_IWDG_Init(void);
 /* USER CODE BEGIN PFP */
 /* Private function prototypes -----------------------------------------------*/

@@ -125,6 +134,9 @@ int main(void)
  MX_USART2_UART_Init();
  MX_SPI1_Init();
  MX_USART3_UART_Init();
+  MX_ADC1_Init();
+  MX_RTC_Init();
+  MX_IWDG_Init();
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */
@@ -150,13 +162,17 @@ void SystemClock_Config(void)
 {
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};

  /**Initializes the CPU, AHB and APB busses clocks 
  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
@@ -177,6 +193,116 @@ void SystemClock_Config(void)
  {
    Error_Handler();
  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
+  PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /**Common config 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 1;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /**Configure Regular Channel 
+  */
+  sConfig.Channel = ADC_CHANNEL_11;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
+/**
+  * @brief IWDG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_IWDG_Init(void)
+{
+
+  /* USER CODE BEGIN IWDG_Init 0 */
+
+  /* USER CODE END IWDG_Init 0 */
+
+  /* USER CODE BEGIN IWDG_Init 1 */
+
+  /* USER CODE END IWDG_Init 1 */
+  hiwdg.Instance = IWDG;
+  hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
+  hiwdg.Init.Reload = 4095;
+  if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN IWDG_Init 2 */
+
+  /* USER CODE END IWDG_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /**Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
+  hrtc.Init.OutPut = RTC_OUTPUTSOURCE_ALARM;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
 }

 /**
@@ -101,6 +101,119 @@ void HAL_MspInit(void)
  /* USER CODE END MspInit 1 */
 }

+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    /**ADC1 GPIO Configuration    
+    PC1     ------> ADC1_IN11 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC1_CLK_DISABLE();
+  
+    /**ADC1 GPIO Configuration    
+    PC1     ------> ADC1_IN11 
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1);
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+
+  /* USER CODE END RTC_MspInit 0 */
+    HAL_PWR_EnableBkUpAccess();
+    /* Enable BKP CLK enable for backup registers */
+    __HAL_RCC_BKP_CLK_ENABLE();
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief SPI MSP Initialization
 * This function configures the hardware resources used in this example
@@ -1,38 +1,50 @@
 #MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_11
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.NbrOfConversionFlag=1
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.master=1
 File.Version=6
 KeepUserPlacement=false
 Mcu.Family=STM32F1
-Mcu.IP0=NVIC
-Mcu.IP1=RCC
-Mcu.IP2=SPI1
-Mcu.IP3=SPI2
-Mcu.IP4=SYS
-Mcu.IP5=USART1
-Mcu.IP6=USART2
-Mcu.IP7=USART3
-Mcu.IPNb=8
+Mcu.IP0=ADC1
+Mcu.IP1=IWDG
+Mcu.IP10=USART3
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=RTC
+Mcu.IP5=SPI1
+Mcu.IP6=SPI2
+Mcu.IP7=SYS
+Mcu.IP8=USART1
+Mcu.IP9=USART2
+Mcu.IPNb=11
 Mcu.Name=STM32F103Z(C-D-E)Tx
 Mcu.Package=LQFP144
 Mcu.Pin0=PC14-OSC32_IN
 Mcu.Pin1=PC15-OSC32_OUT
-Mcu.Pin10=PB11
-Mcu.Pin11=PB13
-Mcu.Pin12=PB14
-Mcu.Pin13=PB15
-Mcu.Pin14=PA9
-Mcu.Pin15=PA10
-Mcu.Pin16=PA13
-Mcu.Pin17=PA14
-Mcu.Pin18=VP_SYS_VS_Systick
+Mcu.Pin10=PB10
+Mcu.Pin11=PB11
+Mcu.Pin12=PB13
+Mcu.Pin13=PB14
+Mcu.Pin14=PB15
+Mcu.Pin15=PA9
+Mcu.Pin16=PA10
+Mcu.Pin17=PA13
+Mcu.Pin18=PA14
+Mcu.Pin19=VP_IWDG_VS_IWDG
 Mcu.Pin2=OSC_IN
+Mcu.Pin20=VP_RTC_VS_RTC_Activate
+Mcu.Pin21=VP_SYS_VS_Systick
 Mcu.Pin3=OSC_OUT
-Mcu.Pin4=PA2
-Mcu.Pin5=PA3
-Mcu.Pin6=PA5
-Mcu.Pin7=PA6
-Mcu.Pin8=PA7
-Mcu.Pin9=PB10
-Mcu.PinsNb=19
+Mcu.Pin4=PC1
+Mcu.Pin5=PA2
+Mcu.Pin6=PA3
+Mcu.Pin7=PA5
+Mcu.Pin8=PA6
+Mcu.Pin9=PA7
+Mcu.PinsNb=22
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F103ZETx
@@ -49,9 +61,9 @@ NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false
 NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false
-OSC_IN.Mode=HSE-External-Clock-Source
+OSC_IN.Mode=HSE-External-Oscillator
 OSC_IN.Signal=RCC_OSC_IN
-OSC_OUT.Mode=HSE-External-Clock-Source
+OSC_OUT.Mode=HSE-External-Oscillator
 OSC_OUT.Signal=RCC_OSC_OUT
 PA10.Mode=Asynchronous
 PA10.Signal=USART1_RX
@@ -81,9 +93,11 @@ PB14.Mode=Full_Duplex_Master
 PB14.Signal=SPI2_MISO
 PB15.Mode=Full_Duplex_Master
 PB15.Signal=SPI2_MOSI
-PC14-OSC32_IN.Mode=LSE-External-Clock-Source
+PC1.Locked=true
+PC1.Signal=ADCx_IN11
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
 PC14-OSC32_IN.Signal=RCC_OSC32_IN
-PC15-OSC32_OUT.Mode=LSE-External-Clock-Source
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
 PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
 PCC.Checker=false
 PCC.Line=STM32F103
@@ -120,8 +134,9 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true
-RCC.ADCFreqValue=36000000
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_SPI1_Init-SPI1-false-HAL-true,7-MX_USART3_UART_Init-USART3-false-HAL-true,8-MX_ADC1_Init-ADC1-false-HAL-true,9-MX_RTC_Init-RTC-false-HAL-true,10-MX_IWDG_Init-IWDG-false-HAL-true
+RCC.ADCFreqValue=12000000
+RCC.ADCPresc=RCC_ADCPCLK2_DIV6
 RCC.AHBFreq_Value=72000000
 RCC.APB1CLKDivider=RCC_HCLK_DIV2
 RCC.APB1Freq_Value=36000000
@@ -134,12 +149,14 @@ RCC.FamilyName=M
 RCC.HCLKFreq_Value=72000000
 RCC.I2S2Freq_Value=72000000
 RCC.I2S3Freq_Value=72000000
-RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
+RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
 RCC.MCOFreq_Value=72000000
 RCC.PLLCLKFreq_Value=72000000
 RCC.PLLMCOFreq_Value=36000000
 RCC.PLLMUL=RCC_PLL_MUL9
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
+RCC.RTCFreq_Value=32768
 RCC.SDIOFreq_Value=72000000
 RCC.SDIOHCLKDiv2FreqValue=36000000
 RCC.SYSCLKFreq_VALUE=72000000
@@ -147,6 +164,8 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
 RCC.TimSysFreq_Value=72000000
 RCC.USBFreq_Value=72000000
 RCC.VCOOutput2Freq_Value=8000000
+SH.ADCx_IN11.0=ADC1_IN11,IN11
+SH.ADCx_IN11.ConfNb=1
 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
 SPI1.CalculateBaudRate=18.0 MBits/s
 SPI1.Direction=SPI_DIRECTION_2LINES
@@ -164,6 +183,10 @@ USART2.IPParameters=VirtualMode
 USART2.VirtualMode=VM_ASYNC
 USART3.IPParameters=VirtualMode
 USART3.VirtualMode=VM_ASYNC
+VP_IWDG_VS_IWDG.Mode=IWDG_Activate
+VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
 board=custom
@@ -24,6 +24,12 @@ menu "Onboard Peripheral Drivers"
        select RT_SFUD_USING_SFDP
        default n

+    config BSP_USING_POT
+        bool "Enable potentiometer"
+        select BSP_USING_ADC
+        select BSP_USING_ADC1
+        default n  
+
    config BSP_USING_EEPROM
        bool "Enable I2C EEPROM (i2c1)"
        select BSP_USING_I2C1
@@ -85,6 +91,10 @@ menu "On-chip Peripheral Drivers"
        bool "Enable UART RX DMA support"
        default n
        
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+
    config BSP_USING_SPI1
        bool "Enable SPI1 BUS"
        select RT_USING_SPI
@@ -121,6 +131,35 @@ menu "On-chip Peripheral Drivers"
                default 23
        endif

+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+
+            config BSP_USING_ADC2
+                bool "Enable ADC2"
+                default n
+
+            config BSP_USING_ADC3
+                bool "Enable ADC3"
+                default n
+        endif
+
+    config BSP_USING_ONCHIP_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        select RT_USING_LIBC
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
 endmenu

 menu "Board extended module Drivers"
@@ -12,8 +12,9 @@ if GetDepend(['BSP_USING_ETH']):
 if GetDepend(['BSP_USING_SPI_FLASH']):
    src += Glob('ports/spi_flash_init.c')

-path = [cwd]
+path =  [cwd]
 path += [cwd + '/CubeMX_Config/Inc']
+path += [cwd + '/ports']

 if rtconfig.CROSS_TOOL == 'gcc':
    src += [cwd + '/../../libraries/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s']
@@ -26,6 +26,10 @@
 #define STM32_SRAM_SIZE      64
 #define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)

+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE             (512 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
 #ifdef __CC_ARM
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev stm32_onchip_flash;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &stm32_onchip_flash,                                             \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                      \
+{                                                                                           \
+    {FAL_PART_MAGIC_WROD,        "app",   "onchip_flash",       0,          496 * 1024, 0}, \
+    {FAL_PART_MAGIC_WROD,        "param", "onchip_flash",       496* 1024 , 16 * 1024, 0},  \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
@@ -123,7 +123,18 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+CONFIG_RT_USING_SFUD=y
+CONFIG_RT_SFUD_USING_SFDP=y
+CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
+# CONFIG_RT_SFUD_USING_QSPI is not set
+# CONFIG_RT_DEBUG_SFUD is not set
+# CONFIG_RT_USING_W25QXX is not set
+# CONFIG_RT_USING_GD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set

@@ -141,7 +152,7 @@ CONFIG_RT_USING_PIN=y
 #
 # POSIX layer and C standard library
 #
-# CONFIG_RT_USING_LIBC is not set
+CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_PTHREADS is not set

 #
@@ -272,7 +283,15 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
+CONFIG_PKG_USING_FAL=y
+CONFIG_PKG_FAL_PATH="/packages/system/fal"
+CONFIG_FAL_DEBUG_CONFIG=y
+CONFIG_FAL_DEBUG=1
+CONFIG_FAL_PART_HAS_TABLE_CFG=y
+CONFIG_PKG_USING_FAL_LATEST_VERSION=y
+# CONFIG_PKG_USING_FAL_V00200 is not set
+# CONFIG_PKG_USING_FAL_V00100 is not set
+CONFIG_PKG_FAL_VER="latest"
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -336,7 +355,7 @@ CONFIG_SOC_STM32F407ZG=y
 # Onboard Peripheral Drivers
 #
 CONFIG_BSP_USING_USB_TO_USART=y
-# CONFIG_BSP_USING_SPI_FLASH is not set
+CONFIG_BSP_USING_SPI_FLASH=y
 # CONFIG_BSP_USING_COM3 is not set
 # CONFIG_BSP_USING_EEPROM is not set
 # CONFIG_BSP_USING_ETH is not set
@@ -350,12 +369,14 @@ CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
 # CONFIG_BSP_USING_UART6 is not set
+CONFIG_BSP_USING_ON_CHIP_FLASH=y
 # CONFIG_BSP_UART_USING_DMA_RX is not set
-# CONFIG_BSP_USING_SPI1 is not set
+CONFIG_BSP_USING_SPI1=y
 # CONFIG_BSP_USING_SPI2 is not set
 # CONFIG_BSP_USING_SPI3 is not set
-# CONFIG_BSP_SPI_USING_DMA is not set
+CONFIG_BSP_SPI_USING_DMA=y
 # CONFIG_BSP_USING_I2C1 is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set

 #
 # Board extended module Drivers
@@ -49,11 +49,12 @@
 | UART         |     支持     |              UART1/2/3/6              |
 | SPI          |     支持     |               SPI1/2/3                |
 | I2C          |     支持     |               软件 I2C                |
-| RTC          |   暂不支持   |               即将支持                |
+| ADC          |     支持     |                                       |
+| RTC          |     支持     |                                       |
+| WDT          |     支持     |                                       |
 | PWM          |   暂不支持   |               即将支持                |
 | USB Device   |   暂不支持   |               即将支持                |
 | USB Host     |   暂不支持   |               即将支持                |
-| IWG          |   暂不支持   |               即将支持                |
 | **扩展模块** | **支持情况** |               **备注**                |
 | ATK-ESP8266 模块 | 暂不支持 | 即将支持 |

@@ -1,43 +1,55 @@
 #MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,master
+ADC1.NbrOfConversionFlag=1
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
+ADC1.master=1
 ETH.IPParameters=MediaInterface
 ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
 File.Version=6
 KeepUserPlacement=false
 Mcu.Family=STM32F4
-Mcu.IP0=ETH
-Mcu.IP1=NVIC
-Mcu.IP2=RCC
-Mcu.IP3=SPI1
-Mcu.IP4=SYS
-Mcu.IP5=USART1
-Mcu.IP6=USART3
-Mcu.IPNb=7
+Mcu.IP0=ADC1
+Mcu.IP1=ETH
+Mcu.IP2=IWDG
+Mcu.IP3=NVIC
+Mcu.IP4=RCC
+Mcu.IP5=RTC
+Mcu.IP6=SPI1
+Mcu.IP7=SYS
+Mcu.IP8=USART1
+Mcu.IP9=USART3
+Mcu.IPNb=10
 Mcu.Name=STM32F407Z(E-G)Tx
 Mcu.Package=LQFP144
 Mcu.Pin0=PC14-OSC32_IN
 Mcu.Pin1=PC15-OSC32_OUT
-Mcu.Pin10=PB10
-Mcu.Pin11=PB11
-Mcu.Pin12=PA9
-Mcu.Pin13=PA10
-Mcu.Pin14=PA13
-Mcu.Pin15=PA14
-Mcu.Pin16=PG11
-Mcu.Pin17=PG13
-Mcu.Pin18=PG14
-Mcu.Pin19=PB3
+Mcu.Pin10=PC5
+Mcu.Pin11=PB10
+Mcu.Pin12=PB11
+Mcu.Pin13=PA9
+Mcu.Pin14=PA10
+Mcu.Pin15=PA13
+Mcu.Pin16=PA14
+Mcu.Pin17=PG11
+Mcu.Pin18=PG13
+Mcu.Pin19=PG14
 Mcu.Pin2=PH0-OSC_IN
-Mcu.Pin20=PB4
-Mcu.Pin21=PB5
-Mcu.Pin22=VP_SYS_VS_Systick
+Mcu.Pin20=PB3
+Mcu.Pin21=PB4
+Mcu.Pin22=PB5
+Mcu.Pin23=VP_IWDG_VS_IWDG
+Mcu.Pin24=VP_RTC_VS_RTC_Activate
+Mcu.Pin25=VP_SYS_VS_Systick
 Mcu.Pin3=PH1-OSC_OUT
 Mcu.Pin4=PC1
 Mcu.Pin5=PA1
 Mcu.Pin6=PA2
-Mcu.Pin7=PA7
-Mcu.Pin8=PC4
-Mcu.Pin9=PC5
-Mcu.PinsNb=23
+Mcu.Pin7=PA5
+Mcu.Pin8=PA7
+Mcu.Pin9=PC4
+Mcu.PinsNb=26
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F407ZGTx
@@ -65,6 +77,8 @@ PA14.Mode=Serial_Wire
 PA14.Signal=SYS_JTCK-SWCLK
 PA2.Mode=RMII
 PA2.Signal=ETH_MDIO
+PA5.Locked=true
+PA5.Signal=ADCx_IN5
 PA7.Mode=RMII
 PA7.Signal=ETH_CRS_DV
 PA9.Mode=Asynchronous
@@ -128,7 +142,7 @@ ProjectManager.FreePins=false
 ProjectManager.HalAssertFull=false
 ProjectManager.HeapSize=0x200
 ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=true
+ProjectManager.LastFirmware=false
 ProjectManager.LibraryCopy=0
 ProjectManager.MainLocation=Src
 ProjectManager.NoMain=false
@@ -140,7 +154,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI1_Init-SPI1-false-HAL-true,5-MX_ETH_Init-ETH-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_RTC_Init-RTC-false-HAL-true,9-MX_IWDG_Init-IWDG-false-HAL-true
 RCC.48MHZClocksFreq_Value=84000000
 RCC.AHBFreq_Value=168000000
 RCC.APB1CLKDivider=RCC_HCLK_DIV4
@@ -157,7 +171,7 @@ RCC.HCLKFreq_Value=168000000
 RCC.HSE_VALUE=8000000
 RCC.HSI_VALUE=16000000
 RCC.I2SClocksFreq_Value=192000000
-RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
+RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RCC_RTC_Clock_SourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
 RCC.LSI_VALUE=32000
 RCC.MCO2PinFreq_Value=168000000
 RCC.PLLCLKFreq_Value=168000000
@@ -165,7 +179,9 @@ RCC.PLLM=4
 RCC.PLLN=168
 RCC.PLLQCLKFreq_Value=84000000
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-RCC.RTCFreq_Value=32000
+RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
+RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
+RCC.RTCFreq_Value=32768
 RCC.RTCHSEDivFreq_Value=4000000
 RCC.SYSCLKFreq_VALUE=168000000
 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
@@ -173,6 +189,8 @@ RCC.VCOI2SOutputFreq_Value=384000000
 RCC.VCOInputFreq_Value=2000000
 RCC.VCOOutputFreq_Value=336000000
 RCC.VcooutputI2S=192000000
+SH.ADCx_IN5.0=ADC1_IN5,IN5
+SH.ADCx_IN5.ConfNb=1
 SPI1.CalculateBaudRate=42.0 MBits/s
 SPI1.Direction=SPI_DIRECTION_2LINES
 SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
@@ -182,6 +200,10 @@ USART1.IPParameters=VirtualMode
 USART1.VirtualMode=VM_ASYNC
 USART3.IPParameters=VirtualMode
 USART3.VirtualMode=VM_ASYNC
+VP_IWDG_VS_IWDG.Mode=IWDG_Activate
+VP_IWDG_VS_IWDG.Signal=IWDG_VS_IWDG
+VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
+VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
 board=custom
@@ -49,7 +49,7 @@
  */
 #define HAL_MODULE_ENABLED  

-/* #define HAL_ADC_MODULE_ENABLED   */
+#define HAL_ADC_MODULE_ENABLED
 /* #define HAL_CRYP_MODULE_ENABLED   */
 /* #define HAL_CAN_MODULE_ENABLED   */
 /* #define HAL_CRC_MODULE_ENABLED   */
@@ -66,10 +66,10 @@
 /* #define HAL_HASH_MODULE_ENABLED   */
 /* #define HAL_I2C_MODULE_ENABLED   */
 /* #define HAL_I2S_MODULE_ENABLED   */
-/* #define HAL_IWDG_MODULE_ENABLED   */
+#define HAL_IWDG_MODULE_ENABLED
 /* #define HAL_LTDC_MODULE_ENABLED   */
 /* #define HAL_RNG_MODULE_ENABLED   */
-/* #define HAL_RTC_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
 /* #define HAL_SAI_MODULE_ENABLED   */
 /* #define HAL_SD_MODULE_ENABLED   */
 /* #define HAL_MMC_MODULE_ENABLED   */
@@ -62,8 +62,14 @@
 /* USER CODE END PM */

 /* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
+
 ETH_HandleTypeDef heth;

+IWDG_HandleTypeDef hiwdg;
+
+RTC_HandleTypeDef hrtc;
+
 SPI_HandleTypeDef hspi1;

 UART_HandleTypeDef huart1;
@@ -81,6 +87,9 @@ static void MX_USART1_UART_Init(void);
 static void MX_SPI1_Init(void);
 static void MX_ETH_Init(void);
 static void MX_USART3_UART_Init(void);
+static void MX_ADC1_Init(void);
+static void MX_RTC_Init(void);
+static void MX_IWDG_Init(void);
 /* USER CODE BEGIN PFP */
 /* Private function prototypes -----------------------------------------------*/

@@ -123,6 +132,9 @@ int main(void)
  MX_SPI1_Init();
  MX_ETH_Init();
  MX_USART3_UART_Init();
+  MX_ADC1_Init();
+  MX_RTC_Init();
+  MX_IWDG_Init();
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */
@@ -148,6 +160,7 @@ void SystemClock_Config(void)
 {
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};

  /**Configure the main internal regulator output voltage 
  */
@@ -155,8 +168,11 @@ void SystemClock_Config(void)
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
  /**Initializes the CPU, AHB and APB busses clocks 
  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = 4;
@@ -180,6 +196,62 @@ void SystemClock_Config(void)
  {
    Error_Handler();
  }
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+  PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+  /**Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) 
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc1.Init.ScanConvMode = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /**Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. 
+  */
+  sConfig.Channel = ADC_CHANNEL_5;
+  sConfig.Rank = 1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
 }

 /**
@@ -227,6 +299,68 @@ static void MX_ETH_Init(void)

 }

+/**
+  * @brief IWDG Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_IWDG_Init(void)
+{
+
+  /* USER CODE BEGIN IWDG_Init 0 */
+
+  /* USER CODE END IWDG_Init 0 */
+
+  /* USER CODE BEGIN IWDG_Init 1 */
+
+  /* USER CODE END IWDG_Init 1 */
+  hiwdg.Instance = IWDG;
+  hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
+  hiwdg.Init.Reload = 4095;
+  if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN IWDG_Init 2 */
+
+  /* USER CODE END IWDG_Init 2 */
+
+}
+
+/**
+  * @brief RTC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_RTC_Init(void)
+{
+
+  /* USER CODE BEGIN RTC_Init 0 */
+
+  /* USER CODE END RTC_Init 0 */
+
+  /* USER CODE BEGIN RTC_Init 1 */
+
+  /* USER CODE END RTC_Init 1 */
+  /**Initialize RTC Only 
+  */
+  hrtc.Instance = RTC;
+  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+  hrtc.Init.AsynchPrediv = 127;
+  hrtc.Init.SynchPrediv = 255;
+  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
+  if (HAL_RTC_Init(&hrtc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN RTC_Init 2 */
+
+  /* USER CODE END RTC_Init 2 */
+
+}
+
 /**
  * @brief SPI1 Initialization Function
  * @param None
@@ -97,6 +97,70 @@ void HAL_MspInit(void)
  /* USER CODE END MspInit 1 */
 }

+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**ADC1 GPIO Configuration    
+    PA5     ------> ADC1_IN5 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC1_CLK_DISABLE();
+  
+    /**ADC1 GPIO Configuration    
+    PA5     ------> ADC1_IN5 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief ETH MSP Initialization
 * This function configures the hardware resources used in this example
@@ -199,6 +263,53 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)

 }

+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspInit 0 */
+
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief SPI MSP Initialization
 * This function configures the hardware resources used in this example
@@ -73,6 +73,10 @@ menu "On-chip Peripheral Drivers"
        bool "Enable UART6"
        select RT_USING_SERIAL
        default n
+        
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n

    config BSP_UART_USING_DMA_RX
        bool "Enable UART RX DMA support"
@@ -97,6 +101,24 @@ menu "On-chip Peripheral Drivers"
        bool "Enable SPI DMA support"
        default n

+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+
+            config BSP_USING_ADC2
+                bool "Enable ADC2"
+                default n
+
+            config BSP_USING_ADC3
+                bool "Enable ADC3"
+                default n
+        endif
+
    menuconfig BSP_USING_I2C1
        bool "Enable I2C1 BUS (software simulation)"
        default y
@@ -114,6 +136,17 @@ menu "On-chip Peripheral Drivers"
                default 25
        endif

+    config BSP_USING_ONCHIP_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        select RT_USING_LIBC
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
 endmenu

 menu "Board extended module Drivers"
@@ -13,8 +13,9 @@ if GetDepend(['BSP_USING_ETH']):
 if GetDepend(['BSP_USING_SPI_FLASH']):
    src += Glob('ports/spi_flash_init.c')

-path = [cwd]
+path =  [cwd]
 path += [cwd + '/CubeMX_Config/Inc']
+path += [cwd + '/ports']

 if rtconfig.CROSS_TOOL == 'gcc':
    src += [cwd + '/../../libraries/STM32F4xx_HAL/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s']
@@ -22,8 +22,12 @@
 #define LED1_PIN                       GET_PIN(F, 10)
 #endif

-#define STM32_SRAM_SIZE      (128)
-#define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)
+#define STM32_SRAM_SIZE        (128)
+#define STM32_SRAM_END         (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE             (1024 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))

 #ifdef __CC_ARM
 extern int Image$$RW_IRAM1$$ZI$$Limit;
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev stm32_onchip_flash;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &stm32_onchip_flash,                                             \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                               \
+{                                                                                                    \
+    {FAL_PART_MAGIC_WROD,        "app",   "onchip_flash",       0,                   1008 * 1024, 0},\
+    {FAL_PART_MAGIC_WROD,        "param", "onchip_flash",       1008* 1024 ,         16 * 1024, 0},  \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */
@@ -77,6 +77,10 @@
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
 #define RT_USING_PIN
+#define RT_USING_SPI
+#define RT_USING_SFUD
+#define RT_SFUD_USING_SFDP
+#define RT_SFUD_USING_FLASH_INFO_TABLE

 /* Using WiFi */

@@ -86,6 +90,7 @@

 /* POSIX layer and C standard library */

+#define RT_USING_LIBC

 /* Network */

@@ -140,6 +145,11 @@

 /* system packages */

+#define PKG_USING_FAL
+#define FAL_DEBUG_CONFIG
+#define FAL_DEBUG 1
+#define FAL_PART_HAS_TABLE_CFG
+#define PKG_USING_FAL_LATEST_VERSION

 /* peripheral libraries and drivers */

@@ -154,9 +164,6 @@

 /* example package: hello */

-
-/* rtpkgs online packages */
-
 #define SOC_FAMILY_STM32
 #define SOC_SERIES_STM32F4

@@ -167,11 +174,15 @@
 /* Onboard Peripheral Drivers */

 #define BSP_USING_USB_TO_USART
+#define BSP_USING_SPI_FLASH

 /* On-chip Peripheral Drivers */

 #define BSP_USING_GPIO
 #define BSP_USING_UART1
+#define BSP_USING_ON_CHIP_FLASH
+#define BSP_USING_SPI1
+#define BSP_SPI_USING_DMA

 /* Board extended module Drivers */

@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=1024
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -46,10 +48,9 @@ CONFIG_RT_USING_MESSAGEQUEUE=y
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_MEMHEAP=y
 # CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SMALL_MEM is not set
 # CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
-# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
 CONFIG_RT_USING_HEAP=y

 #
@@ -64,6 +65,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M4=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set

 #
 # RT-Thread Components
@@ -113,10 +115,12 @@ CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -174,6 +178,7 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set

 #
 # ARM CMSIS
@@ -318,6 +323,25 @@ CONFIG_RT_USING_PIN=y
 # example package: hello
 #
 # CONFIG_PKG_USING_HELLO is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RDBD_SRC is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32F4=y

@@ -332,6 +356,7 @@ CONFIG_SOC_STM32F429IG=y
 CONFIG_BSP_USING_USB_TO_USART=y
 # CONFIG_BSP_USING_COM2 is not set
 # CONFIG_BSP_USING_COM3 is not set
+# CONFIG_BSP_USING_SDRAM is not set
 # CONFIG_BSP_USING_SPI_FLASH is not set
 # CONFIG_BSP_USING_MPU9250 is not set
 # CONFIG_BSP_USING_ETH is not set
@@ -351,5 +376,5 @@ CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_I2C1 is not set

 #
-# Offboard Peripheral Drivers
+# Board extended module Drivers
 #
@@ -45,20 +45,21 @@
 | SPI Flash         |     支持     |                                       |
 | 以太网            |     支持     |                                       |
 | MPU9250九轴传感器 |     支持     |                                       |
+| SDRAM             |     支持     |                                       |
 | SD卡              |   暂不支持   |                                       |
 | CAN               |   暂不支持   |                                       |
-| SDRAM             |   暂不支持   |                                       |
 | **片上外设**      | **支持情况** | **备注**                              |
 | GPIO              |     支持     | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
 | UART              |     支持     | UART1/2/3                             |
 | SPI               |     支持     | SPI1/2/5                              |
 | I2C               |     支持     | 软件 I2C                              |
+| ADC               |     支持     |                                     |
+| RTC               |     支持     |                                      |
+| WDT               |     支持     |                                       |
 | SDIO              |   暂不支持   | 即将支持                              |
-| RTC               |   暂不支持   | 即将支持                              |
 | PWM               |   暂不支持   | 即将支持                              |
 | USB Device        |   暂不支持   | 即将支持                              |
 | USB Host          |   暂不支持   | 即将支持                              |
-| IWG               |   暂不支持   | 即将支持                              |
 | **扩展模块**      | **支持情况** | **备注**                              |
 | ATK-ESP8266 模块  |   暂不支持   | 即将支持                              |

--- a/Show More
+++ b/Show More