mirror of
https://github.com/RT-Thread/rt-thread.git
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add ethernet driver for zynqmp-r5-axu4ev
This commit is contained in:
Wang-Huachen
+270
-27
@@ -1,11 +1,13 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
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* Copyright (c) 2021 WangHuachen. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Change Logs:
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* Date Author Notes
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* 2020-03-19 WangHuachen first version
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* 2021-05-10 WangHuachen add more functions
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*/
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#include <rthw.h>
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#include <rtdef.h>
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@@ -44,41 +46,85 @@ typedef rt_uint32_t u32;
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XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
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#endif
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void Xil_DCacheEnable(void);
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void Xil_DCacheDisable(void);
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void Xil_DCacheInvalidate(void);
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void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
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void Xil_DCacheFlush(void);
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void Xil_DCacheFlushRange(INTPTR adr, u32 len);
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void Xil_DCacheInvalidateLine(INTPTR adr);
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void Xil_DCacheFlushLine(INTPTR adr);
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void Xil_DCacheStoreLine(INTPTR adr);
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void Xil_ICacheEnable(void);
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void Xil_ICacheDisable(void);
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void Xil_ICacheInvalidate(void);
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void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
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void Xil_ICacheInvalidateLine(INTPTR adr);
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void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
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void Xil_DCacheEnable(void)
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{
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register u32 CtrlReg;
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/* enable caches only if they are disabled */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
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#endif
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if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
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/* invalidate the Data cache */
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Xil_DCacheInvalidate();
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/* enable the Data cache */
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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}
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void Xil_DCacheDisable(void)
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{
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register u32 CtrlReg;
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/* clean and invalidate the Data cache */
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Xil_DCacheFlush();
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/* disable the Data cache */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
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#endif
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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void Xil_DCacheInvalidate(void)
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{
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u32 LocalAddr = adr;
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const u32 cacheline = 32U;
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u32 end;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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if (len != 0x00000000U) {
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/* Back the starting address up to the start of a cache line
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* perform cache operations until adr+len
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*/
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end = LocalAddr + len;
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LocalAddr = LocalAddr & ~(cacheline - 1U);
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/* Select cache L0 I-cache in CSSR */
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
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#if 0
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stack_end = (u32 )&_stack_end;
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stack_start = (u32 )&__undef_stack;
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stack_size = stack_start-stack_end;
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while (LocalAddr < end) {
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/* Flush stack memory to save return address */
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Xil_DCacheFlushRange(stack_end, stack_size);
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#endif
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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/* Invalidate L1 I-cache line */
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asm_inval_ic_line_mva_pou(LocalAddr);
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/*invalidate all D cache*/
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mtcp(XREG_CP15_INVAL_DC_ALL, 0);
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LocalAddr += cacheline;
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}
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}
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_DCacheFlushLine(INTPTR adr)
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void Xil_DCacheInvalidateLine(INTPTR adr)
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{
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u32 currmask;
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@@ -86,11 +132,11 @@ void Xil_DCacheFlushLine(INTPTR adr)
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
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mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
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/* Wait for flush to complete */
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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@@ -135,6 +181,79 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
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mtcpsr(currmask);
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}
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void Xil_DCacheFlush(void)
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{
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register u32 CsidReg, C7Reg;
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u32 CacheSize, LineSize, NumWays;
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u32 Way, WayIndex, Set, SetIndex, NumSet;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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/* Select cache level 0 and D cache in CSSR */
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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#if defined (__GNUC__)
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CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_CACHE_SIZE_ID,CsidReg);
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#endif
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/* Determine Cache Size */
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CacheSize = (CsidReg >> 13U) & 0x000001FFU;
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CacheSize += 0x00000001U;
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CacheSize *= (u32)128; /* to get number of bytes */
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/* Number of Ways */
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NumWays = (CsidReg & 0x000003ffU) >> 3U;
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NumWays += 0x00000001U;
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/* Get the cacheline size, way size, index size from csidr */
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LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
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NumSet = CacheSize/NumWays;
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NumSet /= (0x00000001U << LineSize);
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Way = 0U;
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Set = 0U;
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/* Invalidate all the cachelines */
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for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
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for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
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C7Reg = Way | Set;
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/* Flush by Set/Way */
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asm_clean_inval_dc_line_sw(C7Reg);
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Set += (0x00000001U << LineSize);
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}
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Set = 0U;
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Way += 0x40000000U;
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}
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/* Wait for flush to complete */
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dsb();
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mtcpsr(currmask);
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mtcpsr(currmask);
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}
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void Xil_DCacheFlushLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
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/* Wait for flush to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_DCacheFlushRange(INTPTR adr, u32 len)
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{
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u32 LocalAddr = adr;
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@@ -163,6 +282,130 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len)
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mtcpsr(currmask);
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}
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void Xil_DCacheStoreLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
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mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
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/* Wait for store to complete */
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dsb();
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isb();
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mtcpsr(currmask);
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}
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void Xil_ICacheEnable(void)
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{
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register u32 CtrlReg;
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/* enable caches only if they are disabled */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
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/* invalidate the instruction cache */
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mtcp(XREG_CP15_INVAL_IC_POU, 0);
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/* enable the instruction cache */
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CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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}
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void Xil_ICacheDisable(void)
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{
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register u32 CtrlReg;
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dsb();
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/* invalidate the instruction cache */
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mtcp(XREG_CP15_INVAL_IC_POU, 0);
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/* disable the instruction cache */
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#if defined (__GNUC__)
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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#elif defined (__ICCARM__)
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mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
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#endif
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CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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}
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void Xil_ICacheInvalidate(void)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
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/* invalidate the instruction cache */
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mtcp(XREG_CP15_INVAL_IC_POU, 0);
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_ICacheInvalidateLine(INTPTR adr)
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{
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
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mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
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{
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u32 LocalAddr = adr;
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const u32 cacheline = 32U;
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u32 end;
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u32 currmask;
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currmask = mfcpsr();
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mtcpsr(currmask | IRQ_FIQ_MASK);
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if (len != 0x00000000U) {
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/* Back the starting address up to the start of a cache line
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* perform cache operations until adr+len
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*/
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end = LocalAddr + len;
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LocalAddr = LocalAddr & ~(cacheline - 1U);
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/* Select cache L0 I-cache in CSSR */
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mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
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while (LocalAddr < end) {
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/* Invalidate L1 I-cache line */
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asm_inval_ic_line_mva_pou(LocalAddr);
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LocalAddr += cacheline;
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}
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}
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/* Wait for invalidate to complete */
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dsb();
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mtcpsr(currmask);
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}
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void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
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{
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if (ops == RT_HW_CACHE_INVALIDATE)
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@@ -6,6 +6,9 @@
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* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-03-19 WangHuachen first version
|
||||
* 2021-05-11 WangHuachen Added call to Xil_InitializeExistingMPURegConfig to
|
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* initialize the MPU configuration table with the MPU
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* configurations already set in Init_Mpu function.
|
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*/
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.equ Mode_USR, 0x10
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@@ -234,6 +237,7 @@ ctor_loop:
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b ctor_loop
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ctor_end:
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|
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bl Xil_InitializeExistingMPURegConfig /* Initialize MPU config */
|
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/* start RT-Thread Kernel */
|
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ldr pc, _entry
|
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|
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|
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@@ -0,0 +1,54 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2015 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xil_mmu.h
|
||||
* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API
|
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* defined for MPU in R5. R5 does not have mmu and for usage of similar API
|
||||
* the file has been created.
|
||||
*
|
||||
*
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.0 pkp 2/12/15 Initial version
|
||||
* </pre>
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* None.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_MMU_H
|
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#define XIL_MMU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_mpu.h"
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XIL_MMU_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,129 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xil_mmu.h
|
||||
*
|
||||
* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs
|
||||
*
|
||||
* MPU functions provides access to MPU operations such as enable MPU, disable
|
||||
* MPU and set attribute for section of memory.
|
||||
* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU
|
||||
* regions are allocated with another 6 being free for users. Overview of the
|
||||
* memory attributes for different MPU regions is as given below,
|
||||
*
|
||||
*| | Memory Range | Attributes of MPURegion |
|
||||
*|-----------------------|-------------------------|-----------------------------|
|
||||
*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable |
|
||||
*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered |
|
||||
*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory |
|
||||
*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory |
|
||||
*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory |
|
||||
*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory |
|
||||
*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory |
|
||||
*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory |
|
||||
*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable |
|
||||
*
|
||||
*
|
||||
* @note
|
||||
* For a system where DDR is less than 2GB, region after DDR and before PL is
|
||||
* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is
|
||||
* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is
|
||||
* allocated for lower LPS slaves.
|
||||
*
|
||||
* @{
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 02/10/14 Initial version
|
||||
* 6.4 asa 08/16/17 Added many APIs for MPU access to make MPU usage
|
||||
* user-friendly. The APIs added are: Xil_UpdateMPUConfig,
|
||||
* Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
|
||||
* Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
|
||||
* Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
|
||||
* Xil_InitializeExistingMPURegConfig.
|
||||
* Added a new array of structure of type XMpuConfig to
|
||||
* represent the MPU configuration table.
|
||||
* </pre>
|
||||
*
|
||||
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_MPU_H
|
||||
#define XIL_MPU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
#include "xil_types.h"
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
#define MPU_REG_DISABLED 0U
|
||||
#define MPU_REG_ENABLED 1U
|
||||
#define MAX_POSSIBLE_MPU_REGS 16U
|
||||
/**************************** Type Definitions *******************************/
|
||||
struct XMpuConfig{
|
||||
u32 RegionStatus; /* Enabled or disabled */
|
||||
INTPTR BaseAddress;/* MPU region base address */
|
||||
u64 Size; /* MPU region size address */
|
||||
u32 Attribute; /* MPU region size attribute */
|
||||
};
|
||||
|
||||
typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS];
|
||||
|
||||
extern XMpu_Config Mpu_Config;
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
|
||||
void Xil_EnableMPU(void);
|
||||
void Xil_DisableMPU(void);
|
||||
u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
|
||||
u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib);
|
||||
void Xil_GetMPUConfig (XMpu_Config mpuconfig);
|
||||
u32 Xil_GetNumOfFreeRegions (void);
|
||||
u32 Xil_GetNextMPURegion(void);
|
||||
u32 Xil_DisableMPURegionByRegNum (u32 reg_num);
|
||||
u16 Xil_GetMPUFreeRegMask (void);
|
||||
u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib);
|
||||
void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XIL_MPU_H */
|
||||
/**
|
||||
* @} End of "addtogroup r5_mpu_apis".
|
||||
*/
|
||||
Reference in New Issue
Block a user