mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-06-20 21:33:07 +08:00
Merge pull request #272 from wzyy2/master
[bsp/stm32f40x] code style change
This commit is contained in:
Bernard Xiong
@@ -53,11 +53,11 @@ extern int __bss_end;
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*******************************************************************************/
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void assert_failed(u8* file, u32 line)
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{
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rt_kprintf("\n\r Wrong parameter value detected on\r\n");
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rt_kprintf(" file %s\r\n", file);
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rt_kprintf(" line %d\r\n", line);
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rt_kprintf("\n\r Wrong parameter value detected on\r\n");
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rt_kprintf(" file %s\r\n", file);
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rt_kprintf(" line %d\r\n", line);
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while (1) ;
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while (1) ;
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}
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/**
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@@ -65,60 +65,60 @@ void assert_failed(u8* file, u32 line)
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*/
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void rtthread_startup(void)
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{
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/* init board */
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rt_hw_board_init();
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/* init board */
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rt_hw_board_init();
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/* show version */
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rt_show_version();
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/* show version */
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rt_show_version();
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/* init tick */
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rt_system_tick_init();
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/* init tick */
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rt_system_tick_init();
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/* init kernel object */
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rt_system_object_init();
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/* init kernel object */
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rt_system_object_init();
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/* init timer system */
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rt_system_timer_init();
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/* init timer system */
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rt_system_timer_init();
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rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END);
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/* init scheduler system */
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rt_system_scheduler_init();
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/* init scheduler system */
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rt_system_scheduler_init();
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/* init all device */
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rt_device_init_all();
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/* init all device */
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rt_device_init_all();
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/* init application */
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rt_application_init();
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/* init application */
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rt_application_init();
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#ifdef RT_USING_FINSH
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/* init finsh */
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finsh_system_init();
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finsh_set_device( FINSH_DEVICE_NAME );
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/* init finsh */
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finsh_system_init();
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finsh_set_device( FINSH_DEVICE_NAME );
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#endif
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/* init timer thread */
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rt_system_timer_thread_init();
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/* init idle thread */
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rt_thread_idle_init();
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/* init idle thread */
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rt_thread_idle_init();
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/* start scheduler */
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rt_system_scheduler_start();
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/* start scheduler */
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rt_system_scheduler_start();
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/* never reach here */
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return ;
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/* never reach here */
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return ;
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}
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int main(void)
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{
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/* disable interrupt first */
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rt_hw_interrupt_disable();
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/* disable interrupt first */
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rt_hw_interrupt_disable();
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/* startup RT-Thread RTOS */
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rtthread_startup();
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/* startup RT-Thread RTOS */
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rtthread_startup();
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return 0;
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return 0;
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}
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/*@}*/
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@@ -34,11 +34,11 @@
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void NVIC_Configuration(void)
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{
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#ifdef VECT_TAB_RAM
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/* Set the Vector Table base location at 0x20000000 */
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NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
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/* Set the Vector Table base location at 0x20000000 */
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NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
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#else /* VECT_TAB_FLASH */
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/* Set the Vector Table base location at 0x08000000 */
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NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
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/* Set the Vector Table base location at 0x08000000 */
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NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
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#endif
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NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
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@@ -53,16 +53,16 @@ void NVIC_Configuration(void)
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*******************************************************************************/
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void SysTick_Configuration(void)
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{
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RCC_ClocksTypeDef rcc_clocks;
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rt_uint32_t cnts;
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RCC_ClocksTypeDef rcc_clocks;
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rt_uint32_t cnts;
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RCC_GetClocksFreq(&rcc_clocks);
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RCC_GetClocksFreq(&rcc_clocks);
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cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
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cnts = cnts / 8;
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cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
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cnts = cnts / 8;
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SysTick_Config(cnts);
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SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
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SysTick_Config(cnts);
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SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
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}
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/**
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@@ -71,13 +71,13 @@ void SysTick_Configuration(void)
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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@@ -85,15 +85,15 @@ void SysTick_Handler(void)
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*/
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void rt_hw_board_init()
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{
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/* NVIC Configuration */
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NVIC_Configuration();
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/* NVIC Configuration */
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NVIC_Configuration();
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/* Configure the SysTick */
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SysTick_Configuration();
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/* Configure the SysTick */
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SysTick_Configuration();
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rt_hw_usart_init();
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rt_hw_usart_init();
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(CONSOLE_DEVICE);
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rt_console_set_device(CONSOLE_DEVICE);
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#endif
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}
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+282
-282
File diff suppressed because it is too large
Load Diff
+143
-143
@@ -39,9 +39,9 @@
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struct stm32_serial_int_rx uart1_int_rx;
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struct stm32_serial_device uart1 =
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{
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USART1,
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&uart1_int_rx,
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RT_NULL
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USART1,
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&uart1_int_rx,
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RT_NULL
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};
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struct rt_device uart1_device;
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#endif
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@@ -50,9 +50,9 @@ struct rt_device uart1_device;
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struct stm32_serial_int_rx uart2_int_rx;
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struct stm32_serial_device uart2 =
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{
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USART2,
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&uart2_int_rx,
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RT_NULL
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USART2,
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&uart2_int_rx,
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RT_NULL
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};
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struct rt_device uart2_device;
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#endif
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@@ -62,9 +62,9 @@ struct stm32_serial_int_rx uart3_int_rx;
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struct stm32_serial_dma_tx uart3_dma_tx;
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struct stm32_serial_device uart3 =
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{
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USART3,
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&uart3_int_rx,
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&uart3_dma_tx
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USART3,
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&uart3_int_rx,
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&uart3_dma_tx
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};
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struct rt_device uart3_device;
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#endif
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@@ -74,75 +74,75 @@ struct rt_device uart3_device;
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//#define USART3_DR_Base 0x40004804
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/* USART1_REMAP = 0 */
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#define UART1_GPIO_TX GPIO_Pin_9
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#define UART1_GPIO_TX GPIO_Pin_9
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#define UART1_TX_PIN_SOURCE GPIO_PinSource9
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#define UART1_GPIO_RX GPIO_Pin_10
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#define UART1_GPIO_RX GPIO_Pin_10
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#define UART1_RX_PIN_SOURCE GPIO_PinSource10
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#define UART1_GPIO GPIOA
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#define UART1_GPIO GPIOA
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#define UART1_GPIO_RCC RCC_AHB1Periph_GPIOA
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#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
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#define UART1_TX_DMA DMA1_Channel4
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#define UART1_RX_DMA DMA1_Channel5
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#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
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#define UART1_TX_DMA DMA1_Channel4
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#define UART1_RX_DMA DMA1_Channel5
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#define UART2_GPIO_TX GPIO_Pin_2
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#define UART2_GPIO_TX GPIO_Pin_2
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#define UART2_TX_PIN_SOURCE GPIO_PinSource2
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#define UART2_GPIO_RX GPIO_Pin_3
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#define UART2_GPIO_RX GPIO_Pin_3
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#define UART2_RX_PIN_SOURCE GPIO_PinSource3
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#define UART2_GPIO GPIOA
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#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
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#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
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#define UART2_GPIO GPIOA
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#define UART2_GPIO_RCC RCC_AHB1Periph_GPIOA
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#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
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/* USART3_REMAP[1:0] = 00 */
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#define UART3_GPIO_TX GPIO_Pin_10
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#define UART3_GPIO_TX GPIO_Pin_10
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#define UART3_TX_PIN_SOURCE GPIO_PinSource10
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#define UART3_GPIO_RX GPIO_Pin_11
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#define UART3_GPIO_RX GPIO_Pin_11
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#define UART3_RX_PIN_SOURCE GPIO_PinSource11
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#define UART3_GPIO GPIOB
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#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOB
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#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
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#define UART3_TX_DMA DMA1_Stream1
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#define UART3_RX_DMA DMA1_Stream3
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#define UART3_GPIO GPIOB
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#define UART3_GPIO_RCC RCC_AHB1Periph_GPIOB
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#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
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#define UART3_TX_DMA DMA1_Stream1
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#define UART3_RX_DMA DMA1_Stream3
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static void RCC_Configuration(void)
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{
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#ifdef RT_USING_UART1
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/* Enable USART2 GPIO clocks */
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RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
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/* Enable USART2 clock */
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RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
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/* Enable USART2 GPIO clocks */
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RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
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/* Enable USART2 clock */
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RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
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#endif
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#ifdef RT_USING_UART2
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/* Enable USART2 GPIO clocks */
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RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
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/* Enable USART2 clock */
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RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
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/* Enable USART2 GPIO clocks */
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RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
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/* Enable USART2 clock */
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RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
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#endif
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#ifdef RT_USING_UART3
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/* Enable USART3 GPIO clocks */
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RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
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/* Enable USART3 clock */
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RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
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/* Enable USART3 GPIO clocks */
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RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
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/* Enable USART3 clock */
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RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
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/* DMA clock enable */
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RCC_APB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
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/* DMA clock enable */
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RCC_APB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
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#endif
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}
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static void GPIO_Configuration(void)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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#ifdef RT_USING_UART1
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/* Configure USART1 Rx/tx PIN */
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GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
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GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
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/* Configure USART1 Rx/tx PIN */
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GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
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GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
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/* Connect alternate function */
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GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
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@@ -150,9 +150,9 @@ static void GPIO_Configuration(void)
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#endif
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#ifdef RT_USING_UART2
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/* Configure USART2 Rx/tx PIN */
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GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX | UART2_GPIO_RX;
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GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
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/* Configure USART2 Rx/tx PIN */
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GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX | UART2_GPIO_RX;
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GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
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/* Connect alternate function */
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GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
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@@ -160,9 +160,9 @@ static void GPIO_Configuration(void)
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#endif
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#ifdef RT_USING_UART3
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/* Configure USART3 Rx/tx PIN */
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GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX | UART3_GPIO_RX;
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GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
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/* Configure USART3 Rx/tx PIN */
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GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX | UART3_GPIO_RX;
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GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
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/* Connect alternate function */
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GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
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@@ -172,44 +172,44 @@ static void GPIO_Configuration(void)
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static void NVIC_Configuration(void)
|
||||
{
|
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NVIC_InitTypeDef NVIC_InitStructure;
|
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NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
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#ifdef RT_USING_UART1
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/* Enable the USART1 Interrupt */
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NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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/* Enable the USART1 Interrupt */
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NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
|
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
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||||
#endif
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||||
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||||
#ifdef RT_USING_UART2
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/* Enable the USART2 Interrupt */
|
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NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
|
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
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/* Enable the USART2 Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
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NVIC_Init(&NVIC_InitStructure);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART3
|
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/* Enable the USART3 Interrupt */
|
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NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
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NVIC_Init(&NVIC_InitStructure);
|
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/* Enable the USART3 Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
/* Enable the DMA1 Channel2 Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream1_IRQn;
|
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
/* Enable the DMA1 Channel2 Interrupt */
|
||||
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream1_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void DMA_Configuration(void)
|
||||
{
|
||||
#if defined (RT_USING_UART3)
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
|
||||
// /* Configure DMA Stream */
|
||||
// DMA_InitStructure.DMA_Channel = DMA_CHANNEL;
|
||||
@@ -249,24 +249,24 @@ static void DMA_Configuration(void)
|
||||
DMA_DeInit(UART3_TX_DMA);
|
||||
DMA_Init(UART3_TX_DMA, &DMA_InitStructure);
|
||||
|
||||
// /* fill init structure */
|
||||
// DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
// DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
// DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
// DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
// DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
// DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
|
||||
// DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
|
||||
// /* fill init structure */
|
||||
// DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
// DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
// DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
// DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
// DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
// DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
|
||||
// DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
|
||||
//
|
||||
// /* DMA1 Channel5 (triggered by USART3 Tx event) Config */
|
||||
// DMA_DeInit(UART3_TX_DMA);
|
||||
// DMA_InitStructure.DMA_PeripheralBaseAddr = USART3_DR_Base;
|
||||
// DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
|
||||
// DMA_InitStructure.DMA_MemoryBaseAddr = (u32)0;
|
||||
// DMA_InitStructure.DMA_BufferSize = 0;
|
||||
// DMA_Init(UART3_TX_DMA, &DMA_InitStructure);
|
||||
DMA_ITConfig(UART3_TX_DMA, DMA_IT_TC | DMA_IT_TE, ENABLE);
|
||||
// DMA_ClearFlag(DMA1_FLAG_TC5);
|
||||
// /* DMA1 Channel5 (triggered by USART3 Tx event) Config */
|
||||
// DMA_DeInit(UART3_TX_DMA);
|
||||
// DMA_InitStructure.DMA_PeripheralBaseAddr = USART3_DR_Base;
|
||||
// DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
|
||||
// DMA_InitStructure.DMA_MemoryBaseAddr = (u32)0;
|
||||
// DMA_InitStructure.DMA_BufferSize = 0;
|
||||
// DMA_Init(UART3_TX_DMA, &DMA_InitStructure);
|
||||
DMA_ITConfig(UART3_TX_DMA, DMA_IT_TC | DMA_IT_TE, ENABLE);
|
||||
// DMA_ClearFlag(DMA1_FLAG_TC5);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -277,73 +277,73 @@ volatile USART_TypeDef * uart2_debug = USART2;
|
||||
*/
|
||||
void rt_hw_usart_init()
|
||||
{
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
RCC_Configuration();
|
||||
RCC_Configuration();
|
||||
|
||||
GPIO_Configuration();
|
||||
GPIO_Configuration();
|
||||
|
||||
NVIC_Configuration();
|
||||
NVIC_Configuration();
|
||||
|
||||
DMA_Configuration();
|
||||
DMA_Configuration();
|
||||
|
||||
/* uart init */
|
||||
/* uart init */
|
||||
#ifdef RT_USING_UART1
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART1, &USART_InitStructure);
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART1, &USART_InitStructure);
|
||||
|
||||
/* register uart1 */
|
||||
rt_hw_serial_register(&uart1_device, "uart1",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
&uart1);
|
||||
/* register uart1 */
|
||||
rt_hw_serial_register(&uart1_device, "uart1",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
&uart1);
|
||||
|
||||
/* enable interrupt */
|
||||
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
|
||||
/* enable interrupt */
|
||||
USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART2
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART2, &USART_InitStructure);
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART2, &USART_InitStructure);
|
||||
|
||||
/* register uart2 */
|
||||
rt_hw_serial_register(&uart2_device, "uart2",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
&uart2);
|
||||
/* register uart2 */
|
||||
rt_hw_serial_register(&uart2_device, "uart2",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
|
||||
&uart2);
|
||||
|
||||
/* Enable USART2 DMA Rx request */
|
||||
USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
|
||||
/* Enable USART2 DMA Rx request */
|
||||
USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART3
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART3, &USART_InitStructure);
|
||||
USART_InitStructure.USART_BaudRate = 115200;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_Init(USART3, &USART_InitStructure);
|
||||
|
||||
// uart3_dma_tx.dma_channel= UART3_TX_DMA;
|
||||
// uart3_dma_tx.dma_channel= UART3_TX_DMA;
|
||||
|
||||
/* register uart3 */
|
||||
rt_hw_serial_register(&uart3_device, "uart3",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_TX,
|
||||
&uart3);
|
||||
/* register uart3 */
|
||||
rt_hw_serial_register(&uart3_device, "uart3",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_TX,
|
||||
&uart3);
|
||||
|
||||
/* Enable USART3 DMA Tx request */
|
||||
USART_DMACmd(USART3, USART_DMAReq_Tx , ENABLE);
|
||||
/* Enable USART3 DMA Tx request */
|
||||
USART_DMACmd(USART3, USART_DMAReq_Tx , ENABLE);
|
||||
|
||||
/* enable interrupt */
|
||||
USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);
|
||||
/* enable interrupt */
|
||||
USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user