[IFX]Add capsense support

bsp/Infineon/psoc6-cy8ckit-062S2-43012/board/ports/slider_sample.c

@@ -38,6 +38,7 @@ typedef struct
 } led_data_t;
 
 static rt_sem_t trans_done_semphr = RT_NULL;
+static rt_thread_t sld_thread = RT_NULL;
 
 #ifndef RT_USING_PWM
     #error You need enable PWM to use this sample
@@ -222,15 +223,15 @@ int Slider_ctrl_sample(void)
 {
     rt_err_t ret = RT_EOK;
 
-    rt_thread_t thread = rt_thread_create("slider_th",
-                                          Slider_thread_entry,
-                                          RT_NULL,
-                                          1024,
-                                          25,
-                                          10);
-    if (thread != RT_NULL)
+    sld_thread = rt_thread_create("slider_th",
+                                  Slider_thread_entry,
+                                  RT_NULL,
+                                  1024,
+                                  25,
+                                  10);
+    if (sld_thread != RT_NULL)
     {
-        rt_thread_startup(thread);
+        rt_thread_startup(sld_thread);
     }
     else
     {

bsp/Infineon/psoc6-cy8cproto-062S3-4343W/board/ports/slider_sample.c

@@ -38,6 +38,7 @@ typedef struct
 } led_data_t;
 
 static rt_sem_t trans_done_semphr = RT_NULL;
+static rt_thread_t sld_thread = RT_NULL;
 
 #ifndef RT_USING_PWM
     #error You need enable PWM to use this sample
@@ -222,15 +223,15 @@ int Slider_ctrl_sample(void)
 {
     rt_err_t ret = RT_EOK;
 
-    rt_thread_t thread = rt_thread_create("slider_th",
-                                          Slider_thread_entry,
-                                          RT_NULL,
-                                          1024,
-                                          25,
-                                          10);
-    if (thread != RT_NULL)
+    sld_thread = rt_thread_create("slider_th",
+                                  Slider_thread_entry,
+                                  RT_NULL,
+                                  1024,
+                                  25,
+                                  10);
+    if (sld_thread != RT_NULL)
     {
-        rt_thread_startup(thread);
+        rt_thread_startup(sld_thread);
     }
     else
     {

bsp/Infineon/psoc6-evaluationkit-062S2/.config

@@ -740,3 +740,8 @@ CONFIG_BSP_USING_UART0=y
 # CONFIG_BSP_USING_WDT is not set
 # CONFIG_BSP_USING_DAC is not set
 # CONFIG_BSP_USING_TIM is not set
+
+#
+# Board extended module Drivers
+#
+# CONFIG_BSP_USING_SLIDER is not set

bsp/Infineon/psoc6-evaluationkit-062S2/.cproject

@@ -64,23 +64,23 @@
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//applications}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board/ports}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers/config}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/capsense}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/core-lib/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/cmsis/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb_shared/csdidac}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb_shared/serial-flash}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb_shared/usbdev}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/psoc6cm0p}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/retarget-io}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_CY8CKIT-062S2-43012}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_RTT-062S2}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/HAL_Drivers/config}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/HAL_Drivers}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/capsense}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/core-lib/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/cmsis/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb_shared/csdidac}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb_shared/serial-flash}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb_shared/usbdev}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/psoc6cm0p}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/retarget-io}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/drivers/include}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/finsh}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}&quot;" />
@@ -177,23 +177,23 @@
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//applications}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board/ports}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//board}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers/config}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/HAL_Drivers}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/capsense}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/core-lib/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/cmsis/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/include}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb_shared/csdidac}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb_shared/serial-flash}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/mtb_shared/usbdev}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/psoc6cm0p}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libraries/IFX_PSOC6_HAL/retarget-io}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource}&quot;" />
-                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_CY8CKIT-062S2-43012}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//libs/TARGET_RTT-062S2}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/HAL_Drivers/config}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/HAL_Drivers}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/capsense}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/core-lib/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include_pvt}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/cmsis/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/include}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb_shared/csdidac}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb_shared/serial-flash}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb_shared/usbdev}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/psoc6cm0p}&quot;" />
+                  <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/retarget-io}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/drivers/include}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/finsh}&quot;" />
                   <listOptionValue builtIn="false" value="&quot;${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}&quot;" />
@@ -215,7 +215,7 @@
             </toolChain>
           </folderInfo>
           <sourceEntries>
-            <entry excluding="//board/ports|//libraries/HAL_Drivers/drv_adc.c|//libraries/HAL_Drivers/drv_dac.c|//libraries/HAL_Drivers/drv_flash.c|//libraries/HAL_Drivers/drv_hwtimer.c|//libraries/HAL_Drivers/drv_i2c.c|//libraries/HAL_Drivers/drv_rtc.c|//libraries/HAL_Drivers/drv_soft_i2c.c|//libraries/HAL_Drivers/drv_spi.c|//libraries/HAL_Drivers/drv_wdt.c|//libraries/IFX_PSOC6_HAL/capsense|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_43_smt.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_128_tqfp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_68_qfn.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_100_tqfp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_68_qfn.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_64_tqfp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_68_qfn.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_80_tqfp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_01.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_03.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_04.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1B|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1D|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_adc_mic.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_adc_sar.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_analog_common.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_audio_common.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_comp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_comp_ctb.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_comp_lp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_crc.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_crypto_common.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_dac.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_dma.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_dma_dmac.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_dma_dw.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_ezi2c.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_flash.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_i2c.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_i2s.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_keyscan.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_opamp.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_pdmpcm.c|//libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_qspi.c|//libraries/IFX_PSOC6_HAL/mLine truncated
+            <entry excluding="//board/ports|//dist/project|//libs/TARGET_RTT-062S2/COMPONENT_CM0P|//libs/TARGET_RTT-062S2/COMPONENT_CM4/TOOLCHAIN_ARM|//libs/TARGET_RTT-062S2/COMPONENT_CM4/TOOLCHAIN_A_Clang|//libs/TARGET_RTT-062S2/COMPONENT_CM4/TOOLCHAIN_IAR|//rt-thread/bsp/CME_M7|//rt-thread/bsp/ESP32_C3|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_adc.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_dac.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_flash.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_hwtimer.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_i2c.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_pwm.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_rtc.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_soft_i2c.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_spi.c|//rt-thread/bsp/Infineon/libraries/HAL_Drivers/drv_wdt.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/capsense|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_43_smt.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_128_tqfp.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_100_tqfp.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_03_68_qfn.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_64_tqfp.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_68_qfn.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_04_80_tqfp.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_01.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_03.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_04.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1B|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1C|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/COMPONENT_CAT1D|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtb-hal-cat1/source/cyhal_adc_mic.c|//rt-thread/bsp/Infineon/libraries/IFX_PSOC6_HAL/mtLine truncated
           </sourceEntries>
         </configuration>
       </storageModule>

bsp/Infineon/psoc6-evaluationkit-062S2/.settings/language.settings.xml

@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1522148012290462689" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1210189509587013598" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>

bsp/Infineon/psoc6-evaluationkit-062S2/.settings/projcfg.ini

@@ -1,5 +1,5 @@
 #RT-Thread Studio Project Configuration
-#Thu Jan 12 11:11:44 CST 2023
+#Wed Jan 18 15:54:34 CST 2023
 project_type=rt-thread
 chip_name=CY8C624ABZI
 os_branch=full
@@ -9,12 +9,12 @@ selected_rtt_version=latest
 cfg_version=v3.0
 board_base_nano_proj=False
 is_use_scons_build=True
-output_project_path=E\:/software/RT-ThreadStudio/workspace
+output_project_path=E\:\\workspace_work\\rt-thread-5.0\\bsp\\Infineon
 project_base_bsp=true
 hardware_adapter=KitProg3
 project_name=1111
 is_base_example_project=False
 board_name=psoc6-cy8ckit-062S2-43012
 device_vendor=Infineon 
-bsp_version=1.0.0
 bsp_path=repo/Extract/Board_Support_Packages/Infineon/PSOC62-IFX-PROTO-KIT/1.0.0
+bsp_version=1.0.0

bsp/Infineon/psoc6-evaluationkit-062S2/.settings/project.OpenOCD.Debug.rttlaunch

@@ -12,7 +12,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd_debugger_relative_path}openocd/bin/openocd.exe"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-infineon_debugger_relative_path}/bin/openocd.exe"/>
 <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s ../scripts -f interface/kitprog3.cfg -f target/psoc6_2m.cfg -c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot; -c &quot;gdb_port 3332&quot; -c &quot;psoc6 sflash_restrictions 1&quot; -c &quot;init; reset init&quot;"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
@@ -21,7 +21,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon psoc6 reset_halt sysresetreq&#13;&#10;flushregs&#13;&#10;mon gdb_sync&#13;&#10;stepi"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.hex}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
@@ -31,23 +31,23 @@
 <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="entry"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
 <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="E:\software\RT-ThreadStudio\repo\Extract\ToolChain_Support_Packages\ARM\GNU_Tools_for_ARM_Embedded_Processors\10.2.1\bin\arm-none-eabi-gdb.exe"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
 <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
 <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
 <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
 <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/dist_ide_project"/>
+<listEntry value="/project"/>
 </listAttribute>
 <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
 <listEntry value="4"/>

bsp/Infineon/psoc6-evaluationkit-062S2/board/Kconfig

@@ -250,4 +250,11 @@ menu "On-chip Peripheral Drivers"
         endif
 endmenu
 
+menu "Board extended module Drivers"
+
+    config BSP_USING_SLIDER
+        bool "Enable Slider Demo"
+        default n
+endmenu
+
 endmenu

bsp/Infineon/psoc6-evaluationkit-062S2/board/ports/slider_sample.c

@@ -38,6 +38,7 @@ typedef struct
 } led_data_t;
 
 static rt_sem_t trans_done_semphr = RT_NULL;
+static rt_thread_t sld_thread = RT_NULL;
 
 #ifndef RT_USING_PWM
     #error You need enable PWM to use this sample
@@ -222,15 +223,15 @@ int Slider_ctrl_sample(void)
 {
     rt_err_t ret = RT_EOK;
 
-    rt_thread_t thread = rt_thread_create("slider_th",
-                                          Slider_thread_entry,
-                                          RT_NULL,
-                                          1024,
-                                          25,
-                                          10);
-    if (thread != RT_NULL)
+    sld_thread = rt_thread_create("slider_th",
+                                  Slider_thread_entry,
+                                  RT_NULL,
+                                  1024,
+                                  25,
+                                  10);
+    if (sld_thread != RT_NULL)
     {
-        rt_thread_startup(thread);
+        rt_thread_startup(sld_thread);
     }
     else
     {

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -5,12 +5,12 @@
 * Wrapper function to initialize all generated code.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -5,12 +5,12 @@
 * Simple wrapper header containing all generated files.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -5,12 +5,12 @@
 * Sentinel file for determining if generated source is up to date.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h

@@ -11,7 +11,7 @@
 * CapSense Configurator 4.0.0.6195
 *
 ********************************************************************************
-* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
+* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company)
 * or an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -34,13 +34,13 @@
 #include <stddef.h>
 
 /* General */
-#define CY_CAPSENSE_WIDGET_COUNT                                                 (3u)
-#define CY_CAPSENSE_SENSOR_COUNT                                                 (7u)
-#define CY_CAPSENSE_ELTD_COUNT                                                   (9u)
+#define CY_CAPSENSE_WIDGET_COUNT                                                 (1u)
+#define CY_CAPSENSE_SENSOR_COUNT                                                 (5u)
+#define CY_CAPSENSE_ELTD_COUNT                                                   (5u)
 #define CY_CAPSENSE_PIN_COUNT                                                    (5u)
 #define CY_CAPSENSE_SHIELD_PIN_COUNT                                             (0u)
 #define CY_CAPSENSE_POSITION_SIZE                                                (1u)
-#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (3u)
+#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (1u)
 #define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (5u)
 #define CY_CAPSENSE_MFS_CH_NUMBER                                                (1u)
 #define CY_CAPSENSE_RAW_HISTORY_SIZE                                             (0u)
@@ -56,9 +56,9 @@
 
 /* Sensing Methods */
 #define CY_CAPSENSE_CSD_EN                                                       (1u)
-#define CY_CAPSENSE_CSX_EN                                                       (1u)
+#define CY_CAPSENSE_CSX_EN                                                       (0u)
 #define CY_CAPSENSE_CSD_CALIBRATION_EN                                           (1u)
-#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (0u)
 #define CY_CAPSENSE_SMARTSENSE_FULL_EN                                           (1u)
 #define CY_CAPSENSE_SMARTSENSE_HW_EN                                             (0u)
 #define CY_CAPSENSE_SMARTSENSE_DISABLED                                          (0u)

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -5,12 +5,12 @@
 * Clock configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -26,26 +26,16 @@
 * See the License for the specific language governing permissions and
 * limitations under the License.
 ********************************************************************************/
-#include <rtthread.h>
 
 #include "cycfg_clocks.h"
 
 #if defined (CY_USING_HAL)
-const cyhal_resource_inst_t CLK_PWM_obj =
-{
-    .type = CYHAL_RSC_CLOCK,
-    .block_num = CLK_PWM_HW,
-    .channel_num = CLK_PWM_NUM,
-};
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
-{
-    .type = CYHAL_RSC_CLOCK,
-    .block_num = CYBSP_CSD_CLK_DIV_HW,
-    .channel_num = CYBSP_CSD_CLK_DIV_NUM,
-};
+    const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
+    {
+        .type = CYHAL_RSC_CLOCK,
+        .block_num = CYBSP_CSD_CLK_DIV_HW,
+        .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+    };
 #endif //defined (CY_USING_HAL)
 
 

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -5,12 +5,12 @@
 * Clock configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -40,10 +40,6 @@
 extern "C" {
 #endif
 
-#define CLK_PWM_ENABLED 1U
-#define CLK_PWM_HW CY_SYSCLK_DIV_16_BIT
-#define CLK_PWM_NUM 0U
-
 #define CYBSP_CSD_CLK_DIV_ENABLED 1U
 #define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
 #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c

@@ -5,12 +5,12 @@
 * Connectivity BT configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h

@@ -5,12 +5,12 @@
 * Connectivity BT configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -37,14 +37,14 @@
 extern "C" {
 #endif
 
-#define bt_0_power_0_ENABLED 1U
-#define CYCFG_BT_LP_ENABLED (1u)
+#define bt_0_power_0_ENABLED (0)
+#define CYCFG_BT_LP_ENABLED 0
 #define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
 #define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
-#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
-#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
-#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
-#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_HOST_WAKE_GPIO CYHAL_NC_PIN_VALUE
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT 0
+#define CYCFG_BT_DEV_WAKE_GPIO CYHAL_NC_PIN_VALUE
+#define CYCFG_BT_DEV_WAKE_POLARITY 0
 
 
 #if defined(__cplusplus)

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -6,12 +6,12 @@
 * design.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -5,12 +5,12 @@
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -26,7 +26,6 @@
 * See the License for the specific language governing permissions and
 * limitations under the License.
 ********************************************************************************/
-#include <rtthread.h>
 
 #include "cycfg_peripherals.h"
 
@@ -35,32 +34,8 @@ cy_stc_csd_context_t cy_csd_0_context =
     .lockKey = CY_CSD_NONE_KEY,
 };
 
+
 void init_cycfg_peripherals(void)
 {
     Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-
-#ifdef BSP_USING_UART0
-    /* UART0 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART1
-    /* UART1 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART2
-    /* UART2 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#if defined(BSP_USING_UART3) || defined(BSP_USING_HW_I2C3)
-    /* UART3 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART4
-    /* UART4 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
-#ifdef BSP_USING_UART5
-    /* UART5 Device Clock*/
-    Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-#endif
 }

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -5,12 +5,12 @@
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -46,24 +46,18 @@ extern "C" {
 #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
 #define CY_CAPSENSE_PERI_DIV_INDEX 0u
 #define Cmod_PORT GPIO_PRT7
-#define CintA_PORT GPIO_PRT7
-#define CintB_PORT GPIO_PRT7
 #define LinearSlider0_Sns0_PORT GPIO_PRT7
 #define LinearSlider0_Sns1_PORT GPIO_PRT8
 #define LinearSlider0_Sns2_PORT GPIO_PRT8
 #define LinearSlider0_Sns3_PORT GPIO_PRT9
 #define LinearSlider0_Sns4_PORT GPIO_PRT9
 #define Cmod_PIN 7u
-#define CintA_PIN 1u
-#define CintB_PIN 2u
 #define LinearSlider0_Sns0_PIN 3u
 #define LinearSlider0_Sns1_PIN 0u
 #define LinearSlider0_Sns2_PIN 1u
 #define LinearSlider0_Sns3_PIN 2u
 #define LinearSlider0_Sns4_PIN 3u
 #define Cmod_PORT_NUM 7u
-#define CintA_PORT_NUM 7u
-#define CintB_PORT_NUM 7u
 #define CYBSP_CSD_HW CSD0
 #define CYBSP_CSD_IRQ csd_interrupt_IRQn
 

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -5,12 +5,12 @@
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -33,12 +33,12 @@
 
 void init_cycfg_routing(void)
 {
-    HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
-        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
-        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
-        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
     HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
         HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
         HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
         HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+    HSIOM->AMUX_SPLIT_CTL[5] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
 }

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -5,12 +5,12 @@
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -37,22 +37,15 @@ extern "C" {
 #include "cycfg_notices.h"
 void init_cycfg_routing(void);
 #define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
-#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
 #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_AMUXA
 
 #if defined(__cplusplus)
 }

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -10,7 +10,7 @@
 * udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -34,13 +34,6 @@
 #define CY_CFG_SYSCLK_PLL_ERROR 3
 #define CY_CFG_SYSCLK_FLL_ERROR 4
 #define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_LF
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 0
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 32768
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((0)/1000000.0)*32768
-#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
 #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
 #define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
 #define CY_CFG_SYSCLK_FLL_ENABLED 1
@@ -62,7 +55,6 @@
 #define CY_CFG_SYSCLK_ILO_ENABLED 1
 #define CY_CFG_SYSCLK_ILO_HIBERNATE true
 #define CY_CFG_SYSCLK_IMO_ENABLED 1
-#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
@@ -95,12 +87,6 @@
 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
 #define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO
 #define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U
-//#define CY_CFG_SYSCLK_WCO_ENABLED 0
-//#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0
-//#define CY_CFG_SYSCLK_WCO_IN_PIN 0U
-//#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0
-//#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
-//#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED
 #define CY_CFG_PWR_ENABLED 1
 #define CY_CFG_PWR_INIT 1
 #define CY_CFG_PWR_USING_PMIC 0
@@ -664,16 +650,6 @@ __WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
         #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */
     }
 #endif //defined (CY_DEVICE_SECURE)
-__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
-{
- Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS);
-}
-#if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_ClkBakInit()
-    {
-        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
 #if (!defined(CY_DEVICE_SECURE))
     __STATIC_INLINE void Cy_SysClk_ClkFastInit()
     {
@@ -708,13 +684,6 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
         Cy_SysClk_IloHibernateOn(true);
     }
 #endif //(!defined(CY_DEVICE_SECURE))
-#if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_ClkLfInit()
-    {
-        /* The WDT is unlocked in the default startup code */
-        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
 #if (!defined(CY_DEVICE_SECURE))
     __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
     {
@@ -785,17 +754,6 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
         Cy_SysClk_ClkTimerEnable();
     }
 #endif //(!defined(CY_DEVICE_SECURE))
-#if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_WcoInit()
-    {
-        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-        if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
-        {
-            cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
-        }
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
 #if (!defined(CY_DEVICE_SECURE))
     __STATIC_INLINE void init_cycfg_power(void)
     {

bsp/Infineon/psoc6-evaluationkit-062S2/libs/TARGET_RTT-062S2/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -5,12 +5,12 @@
 * System configuration
 * This file was automatically generated and should not be modified.
 * Tools Package 2.4.0.5972
-* mtb-pdl-cat1 2.4.0.13881
+* mtb-pdl-cat1 2.4.0.14850
 * personalities 6.0.0.0
-* udd 3.0.0.1974
+* udd 3.0.0.2024
 *
 ********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -34,11 +34,9 @@
 #include "cy_sysclk.h"
 #include "cy_pra.h"
 #include "cy_pra_cfg.h"
-#include "cy_systick.h"
 #if defined (CY_USING_HAL)
     #include "cyhal_hwmgr.h"
 #endif //defined (CY_USING_HAL)
-#include "cy_gpio.h"
 #include "cy_syspm.h"
 
 #if defined(__cplusplus)
@@ -47,8 +45,6 @@ extern "C" {
 
 #define cpuss_0_dap_0_ENABLED 1U
 #define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
-#define srss_0_clock_0_bakclk_0_ENABLED 1U
 #define srss_0_clock_0_fastclk_0_ENABLED 1U
 #define srss_0_clock_0_fll_0_ENABLED 1U
 #define srss_0_clock_0_hfclk_0_ENABLED 1U
@@ -56,9 +52,6 @@ extern "C" {
 #define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
 #define srss_0_clock_0_ilo_0_ENABLED 1U
 #define srss_0_clock_0_imo_0_ENABLED 1U
-#define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
 #define srss_0_clock_0_pathmux_0_ENABLED 1U
 #define srss_0_clock_0_pathmux_1_ENABLED 1U
 #define srss_0_clock_0_pathmux_2_ENABLED 1U
@@ -69,7 +62,6 @@ extern "C" {
 #define srss_0_clock_0_pll_0_ENABLED 1U
 #define srss_0_clock_0_slowclk_0_ENABLED 1U
 #define srss_0_clock_0_timerclk_0_ENABLED 1U
-#define srss_0_clock_0_wco_0_ENABLED 1U
 #define srss_0_power_0_ENABLED 1U
 #define CY_CFG_PWR_MODE_LP 0x01UL
 #define CY_CFG_PWR_MODE_ULP 0x02UL

bsp/Infineon/psoc6-evaluationkit-062S2/project.uvprojx

@@ -340,7 +340,7 @@
               <MiscControls></MiscControls>
               <Define>COMPONENT_CAT1A, RT_USING_LIBC, RT_USING_ARMLIBC, CY_USING_HAL, __CLK_TCK=RT_TICK_PER_SECOND, COMPONENT_BSP_DESIGN_MODUS, __STDC_LIMIT_MACROS, __RTTHREAD__, COMPONENT_CAT1, CY8C624ALQI_S2D42</Define>
               <Undefine></Undefine>
-              <IncludePath>..\..\..\components\finsh;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;libs\TARGET_RTT-062S2;..\..\..\components\utilities\libadt;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;..\..\..\include;applications;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\..\..\components\libc\posix\io\poll;..\libraries\IFX_PSOC6_HAL\core-lib\include;..\..\..\components\libc\posix\ipc;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;..\..\..\libcpu\arm\common;..\libraries\IFX_PSOC6_HAL\retarget-io;board\ports;.;..\..\..\components\libc\posix\io\stdio;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\libraries\HAL_Drivers\config;libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\libraries\IFX_PSOC6_HAL\capsense;board;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include</IncludePath>
+              <IncludePath>..\..\..\components\finsh;..\libraries\HAL_Drivers\config;..\libraries\IFX_PSOC6_HAL\psoc6cm0p;libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource;..\..\..\components\utilities\libadt;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\COMPONENT_CAT1A\include;applications;..\..\..\include;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include_pvt;..\..\..\components\libc\posix\io\poll;..\libraries\IFX_PSOC6_HAL\core-lib\include;..\..\..\components\libc\posix\ipc;..\libraries\IFX_PSOC6_HAL\mtb_shared\usbdev;..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\include;libs\TARGET_RTT-062S2;..\..\..\libcpu\arm\common;..\libraries\IFX_PSOC6_HAL\retarget-io;board\ports;board;..\..\..\components\libc\posix\io\stdio;.;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\serial-flash;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\capsense;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\include;..\libraries\IFX_PSOC6_HAL\mtb_shared\csdidac;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\include;..\..\..\components\drivers\include;..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\cmsis\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -669,6 +669,11 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\retarget-io\cy_retarget_io.c</FilePath>
             </File>
+            <File>
+              <FileName>psoc6_01_cm0p_sleep.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
+            </File>
             <File>
               <FileName>cy_scb_i2c.c</FileName>
               <FileType>1</FileType>
@@ -749,6 +754,11 @@
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_ipc_pipe.c</FilePath>
             </File>
+            <File>
+              <FileName>psoc6_04_cm0p_sleep.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
+            </File>
             <File>
               <FileName>cyhal_lptimer.c</FileName>
               <FileType>1</FileType>
@@ -770,20 +780,15 @@
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_sysclk.c</FilePath>
             </File>
             <File>
-              <FileName>psoc6_04_cm0p_sleep.c</FileName>
+              <FileName>psoc6_02_cm0p_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_04_cm0p_sleep.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
             </File>
             <File>
               <FileName>cyhal_syspm.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-hal-cat1\source\cyhal_syspm.c</FilePath>
             </File>
-            <File>
-              <FileName>psoc6_01_cm0p_sleep.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_01_cm0p_sleep.c</FilePath>
-            </File>
             <File>
               <FileName>cyhal_uart.c</FileName>
               <FileType>1</FileType>
@@ -815,90 +820,85 @@
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\devices\COMPONENT_CAT1A\source\cy_device.c</FilePath>
             </File>
             <File>
-              <FileName>psoc6_02_cm0p_sleep.c</FileName>
+              <FileName>psoc6_03_cm0p_sleep.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_02_cm0p_sleep.c</FilePath>
+              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
             </File>
             <File>
               <FileName>cy_syspm.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\libraries\IFX_PSOC6_HAL\mtb-pdl-cat1\drivers\source\cy_syspm.c</FilePath>
             </File>
-            <File>
-              <FileName>psoc6_03_cm0p_sleep.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\libraries\IFX_PSOC6_HAL\psoc6cm0p\COMPONENT_CM0P_SLEEP\psoc6_03_cm0p_sleep.c</FilePath>
-            </File>
           </Files>
         </Group>
         <Group>
           <GroupName>libs</GroupName>
           <Files>
             <File>
-              <FileName>cycfg_connectivity_bt.c</FileName>
+              <FileName>cycfg_pins.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c</FilePath>
-            </File>
-            <File>
-              <FileName>system_psoc6_cm4.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c</FilePath>
-            </File>
-            <File>
-              <FileName>cybsp.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\cybsp.c</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_clocks.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_qspi_memslot.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_routing.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</FilePath>
-            </File>
-            <File>
-              <FileName>startup_psoc6_02_cm4.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</FilePath>
-            </File>
-            <File>
-              <FileName>cycfg_capsense.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c</FilePath>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</FilePath>
             </File>
             <File>
               <FileName>cycfg.c</FileName>
               <FileType>1</FileType>
               <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg.c</FilePath>
             </File>
+            <File>
+              <FileName>startup_psoc6_02_cm4.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\TOOLCHAIN_ARM\startup_psoc6_02_cm4.S</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_qspi_memslot.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_qspi_memslot.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_clocks.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_clocks.c</FilePath>
+            </File>
             <File>
               <FileName>cycfg_system.c</FileName>
               <FileType>1</FileType>
               <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_system.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_dmas.c</FileName>
+              <FileName>cycfg_routing.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</FilePath>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_routing.c</FilePath>
             </File>
             <File>
-              <FileName>cycfg_pins.c</FileName>
+              <FileName>cybsp.c</FileName>
               <FileType>1</FileType>
-              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_pins.c</FilePath>
+              <FilePath>libs\TARGET_RTT-062S2\cybsp.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_capsense.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_capsense.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_connectivity_bt.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_connectivity_bt.c</FilePath>
             </File>
             <File>
               <FileName>cycfg_peripherals.c</FileName>
               <FileType>1</FileType>
               <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_peripherals.c</FilePath>
             </File>
+            <File>
+              <FileName>system_psoc6_cm4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_CM4\system_psoc6_cm4.c</FilePath>
+            </File>
+            <File>
+              <FileName>cycfg_dmas.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libs\TARGET_RTT-062S2\COMPONENT_BSP_DESIGN_MODUS\GeneratedSource\cycfg_dmas.c</FilePath>
+            </File>
           </Files>
         </Group>
       </Groups>

bsp/Infineon/psoc6-evaluationkit-062S2/rtconfig.h

@@ -214,4 +214,7 @@
 #define BSP_USING_UART
 #define BSP_USING_UART0
 
+/* Board extended module Drivers */
+
+
 #endif