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[bsp/nuvoton] Support NuMaker-M467HJ BSP and update drivers. (#6416)

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* [bsp/nuvoton] Support NuMaker-M467HJ BSP and update drivers.

* Format files.

Co-authored-by: Wayne Lin <wclin@nuvoton.com>
This commit is contained in:
Wayne
2022-09-12 19:36:11 +08:00
committed by GitHub
parent 4a83592596
commit c9db6ed151
387 changed files with 197642 additions and 1240 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
bsp/nuvoton/README.md
View File

@@ -10,3 +10,4 @@ Current supported BSP shown in below table:
| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
| [nk-n9h30](nk-n9h30) | Nuvoton NK-N9H30 |
| [numaker-m032ki](numaker-m032ki) | Nuvoton NuMaker-M032KI |
| [numaker-m467hj](numaker-m467hj) | Nuvoton NuMaker-M467HJ |

1
bsp/nuvoton/docs/LVGL_Notes.md
View File

@@ -10,6 +10,7 @@ Current supported LVGL running environment on Nuvoton's boards shown in below ta
| numaker-m2354 | Music | Nu-TFT v1.3 | config_lvgl |
| nk-n9h30 | Music | No | .config |
| numaker-m032ki | Widgets | Nu-TFT v1.3 | config_lvgl |
| numaker-m467hj | Widgets | NuMaker-TFT-LCD43 v1.0 | config_lvgl |
## Download related packages

6
bsp/nuvoton/libraries/m031/Device/Nuvoton/M031/Include/spi_reg.h
View File

@@ -488,7 +488,11 @@ typedef struct
__O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */
__I uint32_t RESERVE1[3];
__I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */
__I uint32_t RESERVE2[11];
__I uint32_t RESERVE2[5]; /*!< [0x0034] Reserved */
__IO uint32_t INTERNAL; /*!< [0x0048] SPI Internal Control Register */
__I uint32_t RESERVE3; /*!< [0x004C] Reserved */
__I uint32_t VER_NUM; /*!< [0x0050] SPI Version Number Register */
__I uint32_t RESERVE4[3]; /*!< [0x0054] Reserved */
__IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */
__IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */
__IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */

12
bsp/nuvoton/libraries/m031/rtt_port/drv_crc.c
View File

@@ -45,8 +45,10 @@ static rt_uint32_t nu_crc_run(
{
uint32_t u32CalChecksum = 0;
uint32_t i = 0;
rt_err_t result;
rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
result = rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
RT_ASSERT(result == RT_EOK);
/* Configure CRC controller */
CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_WDATA_8);
@@ -86,7 +88,9 @@ static rt_uint32_t nu_crc_run(
/* Get checksum value */
u32CalChecksum = CRC_GetChecksum();
rt_mutex_release(&s_CRC_mutex);
result = rt_mutex_release(&s_CRC_mutex);
RT_ASSERT(result == RT_EOK);
return u32CalChecksum;
}
@@ -94,9 +98,7 @@ static rt_uint32_t nu_crc_run(
rt_err_t nu_crc_init(void)
{
SYS_ResetModule(CRC_RST);
rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
return RT_EOK;
return rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_PRIO);
}
rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)

9
bsp/nuvoton/libraries/m031/rtt_port/drv_pdma.c
View File

@@ -201,10 +201,13 @@ static void nu_pdma_init(void)
/* Assign first SG table address as PDMA SG table base address */
PDMA->SCATBA = (uint32_t)&nu_pdma_sgtbl_arr[0];
/* Initializa token pool. */
/* Initialize token pool. */
rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
if (NU_PDMA_SGTBL_POOL_SIZE % 32)
{
latest = (NU_PDMA_SGTBL_POOL_SIZE) / 32;
nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
}
nu_pdma_inited = 1;
}

92
bsp/nuvoton/libraries/m031/rtt_port/drv_uart.c
View File

@@ -288,7 +288,6 @@ static struct nu_uart nu_uart_arr [] =
#endif
},
#endif
{0}
}; /* uart nu_uart */
/* Interrupt Handle Function ----------------------------------------------------*/
@@ -378,7 +377,7 @@ void UART57_IRQHandler(void)
static void nu_uart_isr(nu_uart_t serial)
{
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = serial->uart_base;
/* Get interrupt event */
uint32_t u32IntSts = uart_base->INTSTS;
@@ -413,12 +412,15 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
uint32_t uart_stop_bit = 0;
uint32_t uart_parity = 0;
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
RT_ASSERT(serial);
RT_ASSERT(cfg);
/* Check baudrate */
RT_ASSERT(cfg->baud_rate != 0);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
/* Check word len */
switch (cfg->data_bits)
{
@@ -439,7 +441,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported data length");
rt_kprintf("Unsupported data length\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@@ -456,7 +458,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported stop bit");
rt_kprintf("Unsupported stop bit\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@@ -477,7 +479,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported parity");
rt_kprintf("Unsupported parity\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@@ -545,13 +547,12 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
rt_size_t transferred_rxbyte = 0;
struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
nu_uart_t puart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = puart->uart_base;
transferred_rxbyte = nu_pdma_transferred_byte_get(puart->pdma_chanid_rx, puart->rxdma_trigger_len);
if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT))
{
if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
@@ -576,8 +577,10 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = transferred_rxbyte - puart->rx_write_offset;
puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
if (recv_len > 0)
{
puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
}
}
if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
@@ -585,7 +588,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = puart->rxdma_trigger_len;
}
if (recv_len)
if (recv_len > 0)
{
rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
}
@@ -594,7 +597,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
static rt_err_t nu_pdma_uart_tx_config(struct rt_serial_device *serial)
{
rt_err_t result = RT_EOK;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
result = nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_tx,
nu_pdma_uart_tx_cb,
@@ -608,7 +611,7 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
{
nu_uart_t puart = (nu_uart_t)pvOwner;
RT_ASSERT(puart != RT_NULL);
RT_ASSERT(puart);
UART_DISABLE_INT(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
@@ -624,15 +627,16 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
rt_err_t result = RT_EOK;
nu_uart_t psNuUart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(buf != RT_NULL);
RT_ASSERT(serial);
RT_ASSERT(buf);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
if (direction == RT_SERIAL_DMA_TX)
{
result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx,
result = nu_pdma_transfer(psNuUart->pdma_chanid_tx,
8,
(uint32_t)buf,
(uint32_t)uart_base,
@@ -645,8 +649,8 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_RXPDMAEN_Msk);
// If config.bufsz = 0, serial will trigger once.
((nu_uart_t)serial)->rxdma_trigger_len = size;
((nu_uart_t)serial)->rx_write_offset = 0;
psNuUart->rxdma_trigger_len = size;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, buf, size);
}
else
@@ -659,7 +663,7 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
{
RT_ASSERT(pusrt != RT_NULL);
RT_ASSERT(pusrt);
/* Allocate UART_TX nu_dma channel */
if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
@@ -690,30 +694,31 @@ static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
*/
static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
nu_uart_t psNuUart = (nu_uart_t)serial;
rt_err_t result = RT_EOK;
rt_uint32_t flag;
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_DISABLE_INT(uart_base, flag);
UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
{
/* Disable Receive Line interrupt & Stop DMA RX transfer. */
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_RXPDMAEN_Msk);
if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
#endif
}
break;
@@ -721,8 +726,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_SET_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_ENABLE_INT(uart_base, flag);
UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
break;
@@ -731,9 +735,10 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
{
struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
((nu_uart_t)serial)->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len); // Config & trigger
psNuUart->rxdma_trigger_len = serial->config.bufsz;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len); // Config & trigger
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
{
@@ -744,15 +749,18 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_CLOSE:
/* Disable NVIC interrupt. */
NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
NVIC_DisableIRQ(psNuUart->uart_irq_n);
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
#endif
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
/* Reset this module */
SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
if (psNuUart->dma_flag != 0)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx);
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
#endif
/* Close UART port */
UART_Close(uart_base);
@@ -772,7 +780,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
*/
static int nu_uart_send(struct rt_serial_device *serial, char c)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
@@ -791,7 +799,7 @@ static int nu_uart_send(struct rt_serial_device *serial, char c)
*/
static int nu_uart_receive(struct rt_serial_device *serial)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;

7
bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c
View File

@@ -234,8 +234,11 @@ static void nu_pdma_init(void)
/* Initialize token pool. */
rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
if (NU_PDMA_SGTBL_POOL_SIZE % 32)
{
latest = (NU_PDMA_SGTBL_POOL_SIZE) / 32;
nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
}
nu_pdma_inited = 1;
}

93
bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c
View File

@@ -238,7 +238,6 @@ static struct nu_uart nu_uart_arr [] =
#endif
},
#endif
{0}
}; /* uart nu_uart */
/* Interrupt Handle Function ----------------------------------------------------*/
@@ -332,7 +331,7 @@ void UART5_IRQHandler(void)
static void nu_uart_isr(nu_uart_t serial)
{
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = serial->uart_base;
/* Get interrupt event */
uint32_t u32IntSts = uart_base->INTSTS;
@@ -367,12 +366,15 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
uint32_t uart_stop_bit = 0;
uint32_t uart_parity = 0;
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
RT_ASSERT(serial);
RT_ASSERT(cfg);
/* Check baudrate */
RT_ASSERT(cfg->baud_rate != 0);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
/* Check word len */
switch (cfg->data_bits)
{
@@ -393,7 +395,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported data length");
rt_kprintf("Unsupported data length\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@@ -410,7 +412,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported stop bit");
rt_kprintf("Unsupported stop bit\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@@ -431,7 +433,7 @@ static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial
break;
default:
rt_kprintf("Unsupported parity");
rt_kprintf("Unsupported parity\n");
ret = RT_EINVAL;
goto exit_nu_uart_configure;
}
@@ -488,7 +490,6 @@ static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t
UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_PDMA_ENABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
exit_nu_pdma_uart_rx_config:
return result;
@@ -500,7 +501,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
rt_size_t transferred_rxbyte = 0;
struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
nu_uart_t puart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = puart->uart_base;
@@ -531,8 +532,10 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = transferred_rxbyte - puart->rx_write_offset;
puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
if (recv_len > 0)
{
puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
}
}
if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
@@ -540,7 +543,7 @@ static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
recv_len = puart->rxdma_trigger_len;
}
if (recv_len)
if (recv_len > 0)
{
rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
}
@@ -563,7 +566,7 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
{
nu_uart_t puart = (nu_uart_t)pvOwner;
RT_ASSERT(puart != RT_NULL);
RT_ASSERT(puart);
UART_PDMA_DISABLE(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
@@ -579,29 +582,31 @@ static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
rt_err_t result = RT_EOK;
nu_uart_t psNuUart = (nu_uart_t)serial;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(buf != RT_NULL);
RT_ASSERT(serial);
RT_ASSERT(buf);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
if (direction == RT_SERIAL_DMA_TX)
{
result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx,
result = nu_pdma_transfer(psNuUart->pdma_chanid_tx,
8,
(uint32_t)buf,
(uint32_t)uart_base,
size,
0); // wait-forever
UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk); // Start DMA TX transfer
// Start DMA TX transfer
UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk);
}
else if (direction == RT_SERIAL_DMA_RX)
{
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
// If config.bufsz = 0, serial will trigger once.
((nu_uart_t)serial)->rxdma_trigger_len = size;
((nu_uart_t)serial)->rx_write_offset = 0;
psNuUart->rxdma_trigger_len = size;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, buf, size);
}
else
@@ -614,7 +619,7 @@ static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_
static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
{
RT_ASSERT(pusrt != RT_NULL);
RT_ASSERT(pusrt);
/* Allocate UART_TX nu_dma channel */
if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
@@ -645,30 +650,31 @@ static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
*/
static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
nu_uart_t psNuUart = (nu_uart_t)serial;
rt_err_t result = RT_EOK;
rt_uint32_t flag;
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
UART_T *uart_base = psNuUart->uart_base;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_DISABLE_INT(uart_base, flag);
UART_DISABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
{
/* Disable Receive Line interrupt & Stop DMA RX transfer. */
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
if (psNuUart->dma_flag & RT_DEVICE_FLAG_DMA_RX)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
#endif
}
break;
@@ -676,8 +682,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_SET_INT:
if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
{
flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
UART_ENABLE_INT(uart_base, flag);
UART_ENABLE_INT(uart_base, UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk);
}
break;
@@ -686,9 +691,10 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
{
struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
((nu_uart_t)serial)->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len); // Config & trigger
psNuUart->rxdma_trigger_len = serial->config.bufsz;
psNuUart->rx_write_offset = 0;
result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], psNuUart->rxdma_trigger_len); // Config & trigger
}
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
{
@@ -699,15 +705,18 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
case RT_DEVICE_CTRL_CLOSE:
/* Disable NVIC interrupt. */
NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
NVIC_DisableIRQ(psNuUart->uart_irq_n);
#if defined(RT_SERIAL_USING_DMA)
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
#endif
UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk | UART_INTEN_RXPDMAEN_Msk);
UART_DISABLE_INT(uart_base, UART_INTEN_TXPDMAEN_Msk);
/* Reset this module */
SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
if (psNuUart->dma_flag != 0)
{
nu_pdma_channel_terminate(psNuUart->pdma_chanid_tx);
nu_pdma_channel_terminate(psNuUart->pdma_chanid_rx);
}
#endif
/* Close UART port */
UART_Close(uart_base);
@@ -727,7 +736,7 @@ static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *
*/
static int nu_uart_send(struct rt_serial_device *serial, char c)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
@@ -746,7 +755,7 @@ static int nu_uart_send(struct rt_serial_device *serial, char c)
*/
static int nu_uart_receive(struct rt_serial_device *serial)
{
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(serial);
/* Get base address of uart register */
UART_T *uart_base = ((nu_uart_t)serial)->uart_base;

121
bsp/nuvoton/libraries/m460/CMSIS/Include/arm_common_tables.h Normal file
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@@ -0,0 +1,121 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

66
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@@ -0,0 +1,66 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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814
bsp/nuvoton/libraries/m460/CMSIS/Include/cmsis_armcc.h Normal file
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1804
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1809
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368
bsp/nuvoton/libraries/m460/CMSIS/Include/cmsis_compiler.h Normal file
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@@ -0,0 +1,368 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.2
* @date 13. February 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
/* CMSIS compiler control architecture macros */
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
#ifndef __ARM_ARCH_6M__
#define __ARM_ARCH_6M__ 1
#endif
#elif (__CORE__ == __ARM7M__)
#ifndef __ARM_ARCH_7M__
#define __ARM_ARCH_7M__ 1
#endif
#elif (__CORE__ == __ARM7EM__)
#ifndef __ARM_ARCH_7EM__
#define __ARM_ARCH_7EM__ 1
#endif
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
__packed struct T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
//#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
//#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
// Workaround for missing __CLZ intrinsic in
// various versions of the IAR compilers.
// __IAR_FEATURE_CLZ__ should be defined by
// the compiler that supports __CLZ internally.
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
__STATIC_INLINE uint32_t __CLZ(uint32_t data)
{
if (data == 0u)
{
return 32u;
}
uint32_t count = 0;
uint32_t mask = 0x80000000;
while ((data & mask) == 0)
{
count += 1u;
mask = mask >> 1u;
}
return (count);
}
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32
{
uint32_t v;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for ARMv7 MPU
* @version V5.0.2
* @date 09. June 2017
******************************************************************************/
/*
* Copyright (c) 2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
#define ARM_MPU_AP_NONE 0u
#define ARM_MPU_AP_PRIV 1u
#define ARM_MPU_AP_URO 2u
#define ARM_MPU_AP_FULL 3u
#define ARM_MPU_AP_PRO 5u
#define ARM_MPU_AP_RO 6u
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
/**
* MPU Region Attribut and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
((DisableExec << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
((AccessPermission << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
((TypeExtField << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
((IsShareable << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
((IsCacheable << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
((IsBufferable << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
((SubRegionDisable << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
((Size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
((1UL << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
/**
* Struct for a single MPU Region
*/
typedef struct _ARM_MPU_Region_t
{
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable()
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0u;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0u; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
{
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt * sizeof(ARM_MPU_Region_t) / 4u);
}
#endif

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/*
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------------
*
* $Date: 21. September 2016
* $Revision: V1.0
*
* Project: TrustZone for ARMv8-M
* Title: Context Management for ARMv8-M TrustZone
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S(void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S(TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S(TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
""")
path = [cwd + '/Include',]
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
Return('group')

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/**************************************************************************//**
* @file NuMicro.h
* @version V1.00
* @brief NuMicro peripheral access layer header file.
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __NUMICRO_H__
#define __NUMICRO_H__
#include "m460.h"
#endif /* __NUMICRO_H__ */

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/**************************************************************************//**
* @file ccap_reg.h
* @version V3.00
* @brief CCAP register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CCAP_REG_H__
#define __CCAP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup CCAP Camera Capture Interface Controller (CCAP)
Memory Mapped Structure for CCAP Controller
@{ */
typedef struct
{
/**
* @var CCAP_T::CTL
* Offset: 0x00 Camera Capture Interface Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CCAPEN |Camera Capture Interface Enable Bit
* | | |0 = Camera Capture Interface Disabled.
* | | |1 = Camera Capture Interface Enabled.
* |[6] |PKTEN |Packet Output Enable Bit
* | | |0 = Packet output Disabled.
* | | |1 = Packet output Enabled.
* |[7] |MONO |Monochrome CMOS Sensor Select
* | | |0 = Color CMOS Sensor.
* | | |1 = Monochrome CMOS Sensor. The U/V components are ignored when the MONO is enabled.
* |[16] |SHUTTER |Camera Capture Interface Automatically Disable the Capture Interface After a Frame Had Been Captured
* | | |0 = Shutter Disabled.
* | | |1 = Shutter Enabled.
* |[17] |MY4_SWAP |Monochrome CMOS Sensor 4-bit Data Nibble Swap
* | | |0 = The 4-bit data input sequence: 1st Pixel is for 1st Nibble (1st pixel at MSB).
* | | |1 = The 4-bit data input sequence: 1st Pixel is for 2nd Nibble (1st pixel at LSB).
* |[18] |MY8_MY4 |Monochrome CMOS Sensor Data I/O Interface
* | | |0 = Monochrome CMOS sensor is by the 4-bit data I/O interface.
* | | |1 = Monochrome CMOS sensor is by the 8-bit data I/O interface.
* |[19] |Luma_Y_One|Color/Monochrome CMOS Sensor Luminance 8-bit Y to 1-bit Y Conversion
* | | |0 = Color/Monochrome CMOS sensor Luma-Y-One bit Disabled.
* | | |1 = Color/Monochrome CMOS sensor Luma-Y-One bit Enabled.
* | | |Note: Color CMOS sensor U/V components are ignored when the Luma_Y_One is enabled.
* |[20] |UPDATE |Update Register at New Frame
* | | |0 = Update register at new frame Disabled.
* | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
* |[24] |VPRST |Capture Interface Reset
* | | |0 = Capture interface reset Disabled.
* | | |1 = Capture interface reset Enabled.
* @var CCAP_T::PAR
* Offset: 0x04 Camera Capture Interface Parameter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |INFMT |Sensor Input Data Format
* | | |0 = YCbCr422.
* | | |1 = RGB565.
* |[1] |SENTYPE |Sensor Input Type
* | | |0 = CCIR601.
* | | |1 = CCIR656, VSync & Hsync embedded in the data signal.
* |[3:2] |INDATORD |Sensor Input Data Order
* | | |If INFMT (CCAP_PAR[0]) = 0 (YCbCr):
* | | |00 = Sensor input data (Byte 0 1 2 3) is Y0 U0 Y1 V0.
* | | |01 = Sensor input data (Byte 0 1 2 3) is Y0 V0 Y1 U0.
* | | |10 = Sensor input data (Byte 0 1 2 3) is U0 Y0 V0 Y1.
* | | |11 = Sensor input data (Byte 0 1 2 3) is V0 Y0 U0 Y1.
* | | |If INFMT (CCAP_PAR[0]) = 1 (RGB565):
* | | |00 = Sensor input data (Byte 0) is {R[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], B[4:0]}.
* | | |01 = Sensor input data (Byte 0) is {B[4:0],G[5:3]}. Sensor input data (Byte 1) is {G[2:0], R[4:0]}.
* | | |10 = Sensor input data (Byte 0) is {G[2:0],B[4:0]}. Sensor input data (Byte 1) is {R[4:0], G[5:3]}.
* | | |11 = Sensor input data (Byte 0) is {G[2:0],R[4:0]}. Sensor input data (Byte 1) is {B[4:0], G[5:3]}.
* |[5:4] |OUTFMT |Image Data Format Output to System Memory
* | | |00 = YCbCr422.
* | | |01 = Only output Y. (Select this format when CCAP_CTL "Luma_Y_One" or "MONO" enabled).
* | | |10 = RGB555.
* | | |11 = RGB565.
* |[6] |RANGE |Scale Input YUV CCIR601 Color Range to Full Range
* | | |0 = Default.
* | | |1 = Scale to full range.
* |[8] |PCLKP |Sensor Pixel Clock Polarity
* | | |0 = Input video data and signals are latched by falling edge of Pixel Clock.
* | | |1 = Input video data and signals are latched by rising edge of Pixel Clock.
* |[9] |HSP |Sensor Hsync Polarity
* | | |0 = Sync Low.
* | | |1 = Sync High.
* |[10] |VSP |Sensor Vsync Polarity
* | | |0 = Sync Low.
* | | |1 = Sync High.
* |[18] |FBB |Field by Blank
* | | |Field by Blank (only in ccir-656 mode) means blanking pixel data(0x80108010) have to transfer to system memory or not.
* | | |0 = Field by blank Disabled. (blank pixel data will transfer to system memory).
* | | |1 = Field by blank Enabled. (only active data will transfer to system memory).
* @var CCAP_T::INT
* Offset: 0x08 Camera Capture Interface Interrupt Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |VINTF |Video Frame End Interrupt
* | | |0 = Did not receive a frame completely.
* | | |1 = Received a frame completely.
* | | |Note: This bit is cleared by writing 1 to it.
* |[1] |MEINTF |Bus Master Transfer Error Interrupt
* | | |0 = Transfer Error did not occur.
* | | |1 = Transfer Error occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[3] |ADDRMINTF |Memory Address Match Interrupt
* | | |0 = Memory Address Match Interrupt did not occur.
* | | |1 = Memory Address Match Interrupt occurred.
* | | |Note: This bit is cleared by writing 1 to it.
* |[16] |VIEN |Video Frame End Interrupt Enable Bit
* | | |0 = Video frame end interrupt Disabled.
* | | |1 = Video frame end interrupt Enabled.
* |[17] |MEIEN |Bus Master Transfer Error Interrupt Enable Bit
* | | |0 = Bus Master Transfer error interrupt Disabled.
* | | |1 = Bus Master Transfer error interrupt Enabled.
* |[19] |ADDRMIEN |Memory Address Match Interrupt Enable Bit
* | | |0 = Memory address match interrupt Disabled.
* | | |1 = Memory address match interrupt Enabled.
* @var CCAP_T::CWSP
* Offset: 0x20 Cropping Window Starting Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CWSADDRH |Cropping Window Horizontal Starting Address
* | | |Specify the value of the cropping window horizontal start address.
* |[26:16] |CWSADDRV |Cropping Window Vertical Starting Address
* | | |Specify the value of the cropping window vertical start address.
* @var CCAP_T::CWS
* Offset: 0x24 Cropping Window Size Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |CWW |Cropping Window Width
* | | |Specify the size of the cropping window width.
* |[26:16] |CWH |Cropping Window Height
* | | |Specify the size of the cropping window height.
* @var CCAP_T::PKTSL
* Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PKTSHML |Packet Scaling Horizontal Factor M
* | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
* | | |The output image width will be equal to the image width * N/M.
* | | |Note: The value of N must be equal to or less than M.
* |[15:8] |PKTSHNL |Packet Scaling Horizontal Factor N
* | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
* |[23:16] |PKTSVML |Packet Scaling Vertical Factor M
* | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
* | | |The output image width will be equal to the image height * N/M.
* | | |Note: The value of N must be equal to or less than M.
* |[31:24] |PKTSVNL |Packet Scaling Vertical Factor N
* | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
* | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor.
* @var CCAP_T::FRCTL
* Offset: 0x30 Scaling Frame Rate Factor Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[5:0] |FRM |Scaling Frame Rate Factor M
* | | |Specify the denominator part (M) of the frame rate scaling factor.
* | | |The output image frame rate will be equal to input image frame rate * (N/M).
* | | |Note: The value of N must be equal to or less than M.
* |[13:8] |FRN |Scaling Frame Rate Factor N
* | | |Specify the numerator part (N) of the frame rate scaling factor.
* @var CCAP_T::STRIDE
* Offset: 0x34 Frame Output Pixel Stride Width Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[13:0] |PKTSTRIDE |Packet Frame Output Pixel Stride Width
* | | |The output pixel stride size of packet pipe.
* | | |It is a 32-pixel aligned stride width for the Luma-Y-One bit format or a 4-pixel aligned stride with for the Luma-Y-Eight bit format when color or monochrome CMOS sensors used.
* | | |This means that every new captured line is by word alignment address when color or monochrome CMOS sensors used.
* @var CCAP_T::FIFOTH
* Offset: 0x3C FIFO Threshold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[28:24] |PKTFTH |Packet FIFO Threshold
* | | |Specify the 5-bit value of the packet FIFO threshold.
* |[31] |OVF |FIFO Overflow Flag
* | | |Indicate the FIFO overflow flag.
* @var CCAP_T::CMPADDR
* Offset: 0x40 Compare Memory Base Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CMPADDR |Compare Memory Base Address
* | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0].
* @var CCAP_T::LUMA_Y1_THD
* Offset: 0x44 Luminance Y8 to Y1 Threshold Value Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :-----------: | :---- |
* |[7:0] |LUMA_Y1_THRESH |Luminance Y8 to Y1 Threshold Value
* | | |Specify the 8-bit threshold value for the luminance Y bit-8 to the luminance Y 1-bit conversion.
* @var CCAP_T::PKTSM
* Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |PKTSHMH |Packet Scaling Horizontal Factor M
* | | |Specify the higher 8-bit of denominator part (M) of the horizontal scaling factor.
* | | |Please refer to the register CCAP_PKTSL for the detailed operation.
* |[15:8] |PKTSHNH |Packet Scaling Horizontal Factor N
* | | |Specify the higher 8-bit of numerator part (N) of the horizontal scaling factor.
* | | |Please refer to the register CCAP_PKTSL for the detailed operation.
* |[23:16] |PKTSVMH |Packet Scaling Vertical Factor M
* | | |Specify the higher 8-bit of denominator part (M) of the vertical scaling factor.
* | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
* |[31:24] |PKTSVNH |Packet Scaling Vertical Factor N
* | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
* | | |Please refer to the register CCAP_PKTSL to check the cooperation between these two registers.
* @var CCAP_T::CURADDRP
* Offset: 0x50 Current Packet System Memory Address Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CURADDR |Current Packet Output Memory Address
* | | |Specify the 32-bit value of the current packet output memory address.
* @var CCAP_T::PKTBA0
* Offset: 0x60 System Memory Packet Base Address 0 Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |BASEADDR |System Memory Packet Base Address 0
* | | |It is a word alignment address, that is, the address is aligned by ignoring the 2 LSB bits [1:0].
*/
__IO uint32_t CTL; /*!< [0x0000] Camera Capture Interface Control Register */
__IO uint32_t PAR; /*!< [0x0004] Camera Capture Interface Parameter Register */
__IO uint32_t INT; /*!< [0x0008] Camera Capture Interface Interrupt Register */
__I uint32_t RESERVE0[5];
__IO uint32_t CWSP; /*!< [0x0020] Cropping Window Starting Address Register */
__IO uint32_t CWS; /*!< [0x0024] Cropping Window Size Register */
__IO uint32_t PKTSL; /*!< [0x0028] Packet Scaling Vertical/Horizontal Factor Register (LSB) */
__IO uint32_t PLNSL; /*!< [0x002C] Planar Scaling Vertical/Horizontal Factor Register (LSB) */
__IO uint32_t FRCTL; /*!< [0x0030] Scaling Frame Rate Factor Register */
__IO uint32_t STRIDE; /*!< [0x0034] Frame Output Pixel Stride Width Register */
__I uint32_t RESERVE1[1];
__IO uint32_t FIFOTH; /*!< [0x003C] FIFO Threshold Register */
__IO uint32_t CMPADDR; /*!< [0x0040] Compare Memory Base Address Register */
__IO uint32_t LUMA_Y1_THD; /*!< [0x0044] Luminance Y8 to Y1 Threshold Value Register */
__IO uint32_t PKTSM; /*!< [0x0048] Packet Scaling Vertical/Horizontal Factor Register (MSB) */
__IO uint32_t PLNSM; /*!< [0x004C] Planar Scaling Vertical/Horizontal Factor Register (MSB) */
__I uint32_t CURADDRP; /*!< [0x0050] Current Packet System Memory Address Register */
__I uint32_t CURADDRY; /*!< [0x0054] Current Planar Y System Memory Address Register */
__I uint32_t CURADDRU; /*!< [0x0058] Current Planar U System Memory Address Register */
__I uint32_t CURADDRV; /*!< [0x005C] Current Planar V System Memory Address Register */
__IO uint32_t PKTBA0; /*!< [0x0060] System Memory Packet Base Address 0 Register */
__I uint32_t RESERVE4[7];
__IO uint32_t YBA; /*!< [0x0080] System Memory Planar Y Base Address Register */
__IO uint32_t UBA; /*!< [0x0084] System Memory Planar U Base Address Register */
__IO uint32_t VBA; /*!< [0x0088] System Memory Planar V Base Address Register */
} CCAP_T;
/**
@addtogroup CCAP_CONST CCAP Bit Field Definition
Constant Definitions for CCAP Controller
@{ */
#define CCAP_CTL_CCAPEN_Pos (0) /*!< CCAP_T::CTL: CCAPEN Position */
#define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) /*!< CCAP_T::CTL: CCAPEN Mask */
#define CCAP_CTL_PLNEN_Pos (5) /*!< CCAP_T::CTL: PLNEN Position */
#define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) /*!< CCAP_T::CTL: PLNEN Mask */
#define CCAP_CTL_PKTEN_Pos (6) /*!< CCAP_T::CTL: PKTEN Position */
#define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) /*!< CCAP_T::CTL: PKTEN Mask */
#define CCAP_CTL_MONO_Pos (7) /*!< CCAP_T::CTL: MONO Position */
#define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) /*!< CCAP_T::CTL: MONO Mask */
#define CCAP_CTL_SHUTTER_Pos (16) /*!< CCAP_T::CTL: SHUTTER Position */
#define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) /*!< CCAP_T::CTL: SHUTTER Mask */
#define CCAP_CTL_MY4_SWAP_Pos (17) /*!< CCAP_T::CTL: MY4_SWAP Position */
#define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) /*!< CCAP_T::CTL: MY4_SWAP Mask */
#define CCAP_CTL_MY8_MY4_Pos (18) /*!< CCAP_T::CTL: MY8_MY4 Position */
#define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) /*!< CCAP_T::CTL: MY8_MY4 Mask */
#define CCAP_CTL_Luma_Y_One_Pos (19) /*!< CCAP_T::CTL: Luma_Y_One Position */
#define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) /*!< CCAP_T::CTL: Luma_Y_One Mask */
#define CCAP_CTL_UPDATE_Pos (20) /*!< CCAP_T::CTL: UPDATE Position */
#define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) /*!< CCAP_T::CTL: UPDATE Mask */
#define CCAP_CTL_VPRST_Pos (24) /*!< CCAP_T::CTL: VPRST Position */
#define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) /*!< CCAP_T::CTL: VPRST Mask */
#define CCAP_PAR_INFMT_Pos (0) /*!< CCAP_T::PAR: INFMT Position */
#define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) /*!< CCAP_T::PAR: INFMT Mask */
#define CCAP_PAR_SENTYPE_Pos (1) /*!< CCAP_T::PAR: SENTYPE Position */
#define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) /*!< CCAP_T::PAR: SENTYPE Mask */
#define CCAP_PAR_INDATORD_Pos (2) /*!< CCAP_T::PAR: INDATORD Position */
#define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) /*!< CCAP_T::PAR: INDATORD Mask */
#define CCAP_PAR_PLNFMT_Pos (7) /*!< CCAP_T::PAR: OUTFMT Position */
#define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
#define CCAP_PAR_OUTFMT_Pos (4) /*!< CCAP_T::PAR: OUTFMT Position */
#define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) /*!< CCAP_T::PAR: OUTFMT Mask */
#define CCAP_PAR_RANGE_Pos (6) /*!< CCAP_T::PAR: RANGE Position */
#define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) /*!< CCAP_T::PAR: RANGE Mask */
#define CCAP_PAR_PCLKP_Pos (8) /*!< CCAP_T::PAR: PCLKP Position */
#define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) /*!< CCAP_T::PAR: PCLKP Mask */
#define CCAP_PAR_HSP_Pos (9) /*!< CCAP_T::PAR: HSP Position */
#define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) /*!< CCAP_T::PAR: HSP Mask */
#define CCAP_PAR_VSP_Pos (10) /*!< CCAP_T::PAR: VSP Position */
#define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) /*!< CCAP_T::PAR: VSP Mask */
#define CCAP_PAR_FBB_Pos (18) /*!< CCAP_T::PAR: FBB Position */
#define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) /*!< CCAP_T::PAR: FBB Mask */
#define CCAP_INT_VINTF_Pos (0) /*!< CCAP_T::INT: VINTF Position */
#define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) /*!< CCAP_T::INT: VINTF Mask */
#define CCAP_INT_MEINTF_Pos (1) /*!< CCAP_T::INT: MEINTF Position */
#define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) /*!< CCAP_T::INT: MEINTF Mask */
#define CCAP_INT_ADDRMINTF_Pos (3) /*!< CCAP_T::INT: ADDRMINTF Position */
#define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) /*!< CCAP_T::INT: ADDRMINTF Mask */
#define CCAP_INT_VIEN_Pos (16) /*!< CCAP_T::INT: VIEN Position */
#define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) /*!< CCAP_T::INT: VIEN Mask */
#define CCAP_INT_MEIEN_Pos (17) /*!< CCAP_T::INT: MEIEN Position */
#define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) /*!< CCAP_T::INT: MEIEN Mask */
#define CCAP_INT_ADDRMIEN_Pos (19) /*!< CCAP_T::INT: ADDRMIEN Position */
#define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) /*!< CCAP_T::INT: ADDRMIEN Mask */
#define CCAP_CWSP_CWSADDRH_Pos (0) /*!< CCAP_T::CWSP: CWSADDRH Position */
#define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) /*!< CCAP_T::CWSP: CWSADDRH Mask */
#define CCAP_CWSP_CWSADDRV_Pos (16) /*!< CCAP_T::CWSP: CWSADDRV Position */
#define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) /*!< CCAP_T::CWSP: CWSADDRV Mask */
#define CCAP_CWS_CWW_Pos (0) /*!< CCAP_T::CWS: CWW Position */
#define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) /*!< CCAP_T::CWS: CWW Mask */
#define CCAP_CWS_CWH_Pos (16) /*!< CCAP_T::CWS: CIWH Position */
#define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) /*!< CCAP_T::CWS: CIWH Mask */
#define CCAP_PKTSL_PKTSHML_Pos (0) /*!< CCAP_T::PKTSL: PKTSHML Position */
#define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) /*!< CCAP_T::PKTSL: PKTSHML Mask */
#define CCAP_PKTSL_PKTSHNL_Pos (8) /*!< CCAP_T::PKTSL: PKTSHNL Position */
#define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) /*!< CCAP_T::PKTSL: PKTSHNL Mask */
#define CCAP_PKTSL_PKTSVML_Pos (16) /*!< CCAP_T::PKTSL: PKTSVML Position */
#define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) /*!< CCAP_T::PKTSL: PKTSVML Mask */
#define CCAP_PKTSL_PKTSVNL_Pos (24) /*!< CCAP_T::PKTSL: PKTSVNL Position */
#define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) /*!< CCAP_T::PKTSL: PKTSVNL Mask */
#define CCAP_PLNSL_PLNSHML_Pos (0) /*!< CCAP_T::PLNSL: PLNSHML Position */
#define CCAP_PLNSL_PLNSHML_Msk (0xfful << CCAP_PLNSL_PLNSHML_Pos) /*!< CCAP_T::PLNSL: PLNSHML Mask */
#define CCAP_PLNSL_PLNSHNL_Pos (8) /*!< CCAP_T::PLNSL: PLNSHNL Position */
#define CCAP_PLNSL_PLNSHNL_Msk (0xfful << CCAP_PLNSL_PLNSHNL_Pos) /*!< CCAP_T::PLNSL: PLNSHNL Mask */
#define CCAP_PLNSL_PLNSVML_Pos (16) /*!< CCAP_T::PLNSL: PLNSVML Position */
#define CCAP_PLNSL_PLNSVML_Msk (0xfful << CCAP_PLNSL_PLNSVML_Pos) /*!< CCAP_T::PLNSL: PLNSVML Mask */
#define CCAP_PLNSL_PLNSVNL_Pos (24) /*!< CCAP_T::PLNSL: PLNSVNL Position */
#define CCAP_PLNSL_PLNSVNL_Msk (0xfful << CCAP_PLNSL_PLNSVNL_Pos) /*!< CCAP_T::PLNSL: PLNSVNL Mask */
#define CCAP_FRCTL_FRM_Pos (0) /*!< CCAP_T::FRCTL: FRM Position */
#define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) /*!< CCAP_T::FRCTL: FRM Mask */
#define CCAP_FRCTL_FRN_Pos (8) /*!< CCAP_T::FRCTL: FRN Position */
#define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) /*!< CCAP_T::FRCTL: FRN Mask */
#define CCAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CCAP_T::STRIDE: PKTSTRIDE Position */
#define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) /*!< CCAP_T::STRIDE: PKTSTRIDE Mask */
#define CCAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CCAP_T::STRIDE: PLNSTRIDE Position */
#define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) /*!< CCAP_T::STRIDE: PLNSTRIDE Mask */
#define CCAP_FIFOTH_PKTFTH_Pos (24) /*!< CCAP_T::FIFOTH: PKTFTH Position */
#define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) /*!< CCAP_T::FIFOTH: PKTFTH Mask */
#define CCAP_FIFOTH_OVF_Pos (31) /*!< CCAP_T::FIFOTH: OVF Position */
#define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) /*!< CCAP_T::FIFOTH: OVF Mask */
#define CCAP_CMPADDR_CMPADDR_Pos (0) /*!< CCAP_T::CMPADDR: CMPADDR Position */
#define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) /*!< CCAP_T::CMPADDR: CMPADDR Mask */
#define CCAP_PKTSM_PKTSHMH_Pos (0) /*!< CCAP_T::PKTSM: PKTSHMH Position */
#define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) /*!< CCAP_T::PKTSM: PKTSHMH Mask */
#define CCAP_PKTSM_PKTSHNH_Pos (8) /*!< CCAP_T::PKTSM: PKTSHNH Position */
#define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) /*!< CCAP_T::PKTSM: PKTSHNH Mask */
#define CCAP_PKTSM_PKTSVMH_Pos (16) /*!< CCAP_T::PKTSM: PKTSVMH Position */
#define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) /*!< CCAP_T::PKTSM: PKTSVMH Mask */
#define CCAP_PKTSM_PKTSVNH_Pos (24) /*!< CCAP_T::PKTSM: PKTSVNH Position */
#define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) /*!< CCAP_T::PKTSM: PKTSVNH Mask */
#define CCAP_PLNSM_PLNSHMH_Pos (0) /*!< CCAP_T::PLNSM: PLNSHMH Position */
#define CCAP_PLNSM_PLNSHMH_Msk (0xfful << CCAP_PLNSM_PLNSHMH_Pos) /*!< CCAP_T::PLNSM: PLNSHMH Mask */
#define CCAP_PLNSM_PLNSHNH_Pos (8) /*!< CCAP_T::PLNSM: PLNSHNH Position */
#define CCAP_PLNSM_PLNSHNH_Msk (0xfful << CCAP_PLNSM_PLNSHNH_Pos) /*!< CCAP_T::PLNSM: PLNSHNH Mask */
#define CCAP_PLNSM_PLNSVMH_Pos (16) /*!< CCAP_T::PLNSM: PLNSVMH Position */
#define CCAP_PLNSM_PLNSVMH_Msk (0xfful << CCAP_PLNSM_PLNSVMH_Pos) /*!< CCAP_T::PLNSM: PLNSVMH Mask */
#define CCAP_PLNSM_PLNSVNH_Pos (24) /*!< CCAP_T::PLNSM: PLNSVNH Position */
#define CCAP_PLNSM_PLNSVNH_Msk (0xfful << CCAP_PLNSM_PLNSVNH_Pos) /*!< CCAP_T::PLNSM: PLNSVNH Mask */
#define CCAP_CURADDRP_CURADDR_Pos (0) /*!< CCAP_T::CURADDRP: CURADDR Position */
#define CCAP_CURADDRP_CURADDR_Msk (0xfffffffful << CCAP_CURADDRP_CURADDR_Pos) /*!< CCAP_T::CURADDRP: CURADDR Mask */
#define CCAP_PKTBA0_BASEADDR_Pos (0) /*!< CCAP_T::PKTBA0: BASEADDR Position */
#define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) /*!< CCAP_T::PKTBA0: BASEADDR Mask */
/**@}*/ /* CCAP_CONST */
/**@}*/ /* end of CCAP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __CCAP_REG_H__ */

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/**************************************************************************//**
* @file crc_reg.h
* @version V3.00
* @brief CRC register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CRC_REG_H__
#define __CRC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
/**
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
Memory Mapped Structure for CRC Controller
@{
*/
typedef struct
{
/**
* @var CRC_T::CTL
* Offset: 0x00 CRC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CRCEN |CRC Channel Enable Bit
* | | |0 = No effect.
* | | |1 = CRC operation Enabled.
* |[1] |CHKSINIT |Checksum Initialization
* | | |0 = No effect.
* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
* | | |Note: This bit will be cleared automatically and written only.
* |[24] |DATREV |Write Data Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
* | | |0 = Bit order reversed for CRC write data in Disabled.
* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
* |[25] |CHKSREV |Checksum Bit Order Reverse
* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
* | | |0 = Bit order reverse for CRC checksum Disabled.
* | | |1 = Bit order reverse for CRC checksum Enabled.
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
* |[26] |DATFMT |Write Data 1's Complement
* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
* | | |0 = 1's complement for CRC writes data in Disabled.
* | | |1 = 1's complement for CRC writes data in Enabled.
* |[27] |CHKSFMT |Checksum 1's Complement
* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
* | | |0 = 1's complement for CRC checksum Disabled.
* | | |0 = 1's complement for CRC checksum Enabled.
* |[29:28] |DATLEN |CPU Write Data Length
* | | |This field indicates the write data length.
* | | |00 = Data length is 8-bit mode.
* | | |01 = Data length is 16-bit mode.
* | | |1x = Data length is 32-bit mode.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* |[31:30] |CRCMODE |CRC Polynomial Mode
* | | |This field indicates the CRC operation polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |01 = CRC-8 Polynomial mode.
* | | |10 = CRC-16 Polynomial mode.
* | | |11 = CRC-32 Polynomial mode.
* | | |Note: User must program the polynomial value in CRC_POLYNOMIAL register to specify the polynomial used for CRC calculation.
* @var CRC_T::DAT
* Offset: 0x04 CRC Write Data Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |DATA |CRC Write Data Bits
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
* @var CRC_T::SEED
* Offset: 0x08 CRC Seed Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SEED |CRC Seed Value
* | | |This field indicates the CRC seed value.
* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
* @var CRC_T::CHECKSUM
* Offset: 0x0C CRC Checksum Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CHECKSUM |CRC Checksum Results
* | | |This field indicates the CRC checksum result.
* | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
* @var CRC_T::POLYNOMIAL
* Offset: 0x10 CRC Polynomial Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |POLYNOMIAL |CRC Polynomial Register
* | | |This field indicates the value of CRC polynomial.
*/
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
__IO uint32_t POLYNOMIAL; /*!< [0x0010] CRC Polynomial Register */
} CRC_T;
/**
@addtogroup CRC_CONST CRC Bit Field Definition
Constant Definitions for CRC Controller
@{
*/
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
#define CRC_POLYNOMIAL_POLYNOMIAL_Pos (0) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Position */
#define CRC_POLYNOMIAL_POLYNOMIAL_Msk (0xfffffffful << CRC_POLYNOMIAL_POLYNOMIAL_Pos) /*!< CRC_T::POLYNOMIAL: POLYNOMIAL Mask */
/**@}*/ /* CRC_CONST */
/**@}*/ /* end of CRC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __CRC_REG_H__ */

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/**************************************************************************//**
* @file dac_reg.h
* @version V1.00
* @brief DAC register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __DAC_REG_H__
#define __DAC_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup DAC Digital to Analog Converter(DAC)
Memory Mapped Structure for DAC Controller
@{ */
typedef struct
{
/**
* @var DAC_T::CTL
* Offset: 0x00 DAC Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |DACEN |DAC Enable Bit
* | | |0 = DAC is Disabled.
* | | |1 = DAC is Enabled.
* |[1] |DACIEN |DAC Interrupt Enable Bit
* | | |0 = Interrupt is Disabled.
* | | |1 = Interrupt is Enabled.
* |[2] |DMAEN |DMA Mode Enable Bit
* | | |0 = DMA mode Disabled.
* | | |1 = DMA mode Enabled.
* |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit
* | | |0 = DMA under-run interrupt Disabled.
* | | |1 = DMA under-run interrupt Enabled.
* |[4] |TRGEN |Trigger Mode Enable Bit
* | | |0 = DAC event trigger mode Disabled.
* | | |1 = DAC event trigger mode Enabled.
* |[7:5] |TRGSEL |Trigger Source Selection
* | | |000 = Software trigger.
* | | |001 = External pin DAC0_ST trigger.
* | | |010 = Timer 0 trigger.
* | | |011 = Timer 1 trigger.
* | | |100 = Timer 2 trigger.
* | | |101 = Timer 3 trigger.
* | | |110 = EPWM0 trigger.
* | | |111 = EPWM1 trigger.
* |[8] |BYPASS |Bypass Buffer Mode
* | | |0 = Output voltage buffer Enabled.
* | | |1 = Output voltage buffer Disabled.
* |[10] |LALIGN |DAC Data Left-aligned Enabled Control
* | | |0 = Right alignment.
* | | |1 = Left alignment.
* |[13:12] |ETRGSEL |External Pin Trigger Selection
* | | |00 = Low level trigger.
* | | |01 = High level trigger.
* | | |10 = Falling edge trigger.
* | | |11 = Rising edge trigger.
* |[15:14] |BWSEL |DAC Data Bit-width Selection
* | | |00 = data is 12 bits.
* | | |01 = data is 8 bits.
* | | |Others = reserved.
* |[16] |GRPEN |DAC Group Mode Enable Bit
* | | |0 = DAC0 and DAC1 are not grouped.
* | | |1 = DAC0 and DAC1 are grouped.
* @var DAC_T::SWTRG
* Offset: 0x04 DAC Software Trigger Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWTRG |Software Trigger
* | | |0 = Software trigger Disabled.
* | | |1 = Software trigger Enabled.
* | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
* @var DAC_T::DAT
* Offset: 0x08 DAC Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DACDAT |DAC 12-bit Holding Data
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output
* | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
* @var DAC_T::DATOUT
* Offset: 0x0C DAC Data Output Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[11:0] |DATOUT |DAC 12-bit Output Data
* | | |These bits are current digital data for DAC output conversion.
* | | |It is loaded from DAC_DAT register and user cannot write it directly.
* @var DAC_T::STATUS
* Offset: 0x10 DAC Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |FINISH |DAC Conversion Complete Finish Flag
* | | |0 = DAC is in conversion state.
* | | |1 = DAC conversion finish.
* | | |This bit set to 1 when conversion time counter counts to SETTLET
* | | |It is cleared to 0 when DAC starts a new conversion
* | | |User writes 1 to clear this bit to 0.
* |[1] |DMAUDR |DMA Under-run Interrupt Flag
* | | |0 = No DMA under-run error condition occurred.
* | | |1 = DMA under-run error condition occurred.
* | | |User writes 1 to clear this bit.
* |[8] |BUSY |DAC Busy Flag (Read Only)
* | | |0 = DAC is ready for next conversion.
* | | |1 = DAC is busy in conversion.
* | | |This is read only bit.
* @var DAC_T::TCTL
* Offset: 0x14 DAC Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[9:0] |SETTLET |DAC Output Settling Time
* | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
* | | |For example, DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us, SETTLETvalue must be greater than 0x50.
* | | |SELTTLET = DAC controller clock speed x settling time.
* @var DAC_T::GRPDAT
* Offset: 0x30 DAC Group Mode Data Holding Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |DAC0DAT |DAC0 12-bit Holding Data
* | | |These bits are written by user software which specifies 12-bit conversion data for DAC output
* | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits.
* | | |Note: In group mode, user can write 12-bit conversion data for DAC0 in DAC_GRPDAT[15:0] or DAC0_DAT[15:0]
* | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[15:0] is that can share one PDMA transfer mechanism.
* | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs
* |[31:16] |DAC1DAT |DAC1 12-bit Holding Data
* | | |In group mode, user can write these bits for DAC1 12-bit conversion data
* | | |The unused bits (DAC_GRPDAT[3:0] in left-alignment mode and DAC_GRPDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
* | | |12 bit left alignment: user has to load data into DAC_GRPDAT[15:4] bits.
* | | |12 bit right alignment: user has to load data into DAC_GRPDAT[11:0] bits.
* | | |Note: In group mode, user can write 12-bit conversion data for DAC1 in DAC_GRPDAT[31:16] or DAC1_DAT[15:0]
* | | |The advantage of writing 12-bit conversion data in DAC_GRPDAT[31:16] is that can share one PDMA transfer mechanism.
* | | |Note: Write 12-bit conversion data in DAC0_DAT[15:0] or DAC1_DAT[15:0] have individual PDMA transfer mechanism between two DACs
*/
__IO uint32_t CTL; /*!< [0x0000] DAC Control Register */
__IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */
__IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */
__I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */
__IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */
__IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */
__I uint32_t RESERVE0[6];
__IO uint32_t GRPDAT; /*!< [0x0030] DAC Group Mode Data Holding Register */
} DAC_T;
/**
@addtogroup DAC_CONST DAC Bit Field Definition
Constant Definitions for DAC Controller
@{ */
#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */
#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */
#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */
#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */
#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */
#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */
#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */
#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */
#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */
#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */
#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */
#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */
#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */
#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */
#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */
#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */
#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */
#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */
#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */
#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */
#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */
#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */
#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */
#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */
#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */
#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */
#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */
#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */
#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */
#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */
#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */
#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */
#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */
#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */
#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */
#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */
#define DAC_GRPDAT_DAC0DAT_Pos (0) /*!< DAC_T::GRPDAT: DAC0DAT Position */
#define DAC_GRPDAT_DAC0DAT_Msk (0xfffful << DAC_GRPDAT_DAC0DAT_Pos) /*!< DAC_T::GRPDAT: DAC0DAT Mask */
#define DAC_GRPDAT_DAC1DAT_Pos (16) /*!< DAC_T::GRPDAT: DAC1DAT Position */
#define DAC_GRPDAT_DAC1DAT_Msk (0xfffful << DAC_GRPDAT_DAC1DAT_Pos) /*!< DAC_T::GRPDAT: DAC1DAT Mask */
/**@}*/ /* DAC_CONST */
/**@}*/ /* end of DAC register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __DAC_REG_H__ */

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/**************************************************************************//**
* @file ebi_reg.h
* @version V3.00
* @brief EBI register definition header file
*
* @copyright SPDX-License-Identifier: Apache-2.0
* @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EBI_REG_H__
#define __EBI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- External Bus Interface Controller -------------------------*/
/**
@addtogroup EBI External Bus Interface Controller(EBI)
Memory Mapped Structure for EBI Controller
@{
*/
typedef struct
{
/**
* @var EBI_T::CTL
* Offset: 0x00 External Bus Interface Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |EN |EBI Enable Bit
* | | |This bit is the functional enable bit for EBI.
* | | |0 = EBI function Disabled.
* | | |1 = EBI function Enabled.
* |[1] |DW16 |EBI Data Width 16-bit Select
* | | |This bit defines if the EBI data width is 8-bit or 16-bit.
* | | |0 = EBI data width is 8-bit.
* | | |1 = EBI data width is 16-bit.
* |[2] |CSPOLINV |Chip Select Pin Polar Inverse
* | | |This bit defines the active level of EBI chip select pin (EBI_nCS).
* | | |0 = Chip select pin (EBI_nCS) is active low.
* | | |1 = Chip select pin (EBI_nCS) is active high.
* |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit
* | | |0 = Address/Data Bus Separating Mode Disabled.
* | | |1 = Address/Data Bus Separating Mode Enabled.
* |[4] |CACCESS |Continuous Data Access Mode
* | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
* | | |0 = Continuous data access mode Disabled.
* | | |1 = Continuous data access mode Enabled.
* |[10:8] |MCLKDIV |External Output Clock Divider
* | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
* | | |000 = HCLK/1.
* | | |001 = HCLK/2.
* | | |010 = HCLK/4.
* | | |011 = HCLK/8.
* | | |100 = HCLK/16.
* | | |101 = HCLK/32.
* | | |110 = HCLK/64.
* | | |111 = HCLK/128.
* |[18:16] |TALE |Extend Time of ALE
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register
* |[24] |WBUFEN |EBI Write Buffer Enable Bit
* | | |0 = EBI write buffer Disabled.
* | | |1 = EBI write buffer Enabled.
* | | |Note: This bit only available in EBI_CTL0 register
* @var EBI_T::TCTL
* Offset: 0x04 External Bus Interface Timing Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:3] |TACC |EBI Data Access Time
* | | |TACC define data access time (tACC).
* | | |tACC = (TACC+1) * EBI_MCLK.
* |[10:8] |TAHD |EBI Data Access Hold Time
* | | |TAHD define data access hold time (tAHD).
* | | |tAHD = (TAHD+1) * EBI_MCLK.
* |[15:12] |W2X |Idle Cycle After Write
* | | |This field defines the number of W2X idle cycle.
* | | |W2X idle cycle = (W2X * EBI_MCLK).
* | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
* |[22] |RAHDOFF |Access Hold Time Disable Control When Read
* | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
* |[23] |WAHDOFF |Access Hold Time Disable Control When Write
* | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
* | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
* |[27:24] |R2R |Idle Cycle Between Read-to-read
* | | |This field defines the number of R2R idle cycle.
* | | |R2R idle cycle = (R2R * EBI_MCLK).
* | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
*/
__IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */
__IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */
__I uint32_t RESERVE0[2];
__IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */
__IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */
__I uint32_t RESERVE1[2];
__IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */
__IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */
} EBI_T;
/**
@addtogroup EBI_CONST EBI Bit Field Definition
Constant Definitions for EBI Controller
@{
*/
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */
#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */
#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */
/**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __EBI_REG_H__ */

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/**************************************************************************//**
* @file ecap_reg.h
* @version V1.00
* @brief ECAP register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ECAP_REG_H__
#define __ECAP_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup ECAP Enhanced Input Capture Timer(ECAP)
Memory Mapped Structure for ECAP Controller
@{ */
typedef struct
{
/**
* @var ECAP_T::CNT
* Offset: 0x00 Input Capture Counter (24-bit up counter)
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNT |Input Capture Timer/Counter
* | | |The input Capture Timer/Counter is a 24-bit up-counting counter
* | | |The clock source for the counter is from the clock divider
* @var ECAP_T::HLD0
* Offset: 0x04 Input Capture Hold Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD1
* Offset: 0x08 Input Capture Hold Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::HLD2
* Offset: 0x0C Input Capture Hold Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |HOLD |Input Capture Counter Hold Register
* | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
* | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
* @var ECAP_T::CNTCMP
* Offset: 0x10 Input Capture Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[23:0] |CNTCMP |Input Capture Counter Compare Register
* | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
* | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
* @var ECAP_T::CTL0
* Offset: 0x14 Input Capture Control Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock
* | | |000 = CAP_CLK.
* | | |001 = CAP_CLK/2.
* | | |010 = CAP_CLK/4.
* | | |011 = CAP_CLK/16.
* | | |100 = CAP_CLK/32.
* | | |101 = CAP_CLK/64.
* |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control
* | | |0 = Noise filter of Input Capture Enabled.
* | | |1 = Noise filter of Input Capture Disabled (Bypass).
* |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control
* | | |0 = IC0 input to Input Capture Unit Disabled.
* | | |1 = IC0 input to Input Capture Unit Enabled.
* |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control
* | | |0 = IC1 input to Input Capture Unit Disabled.
* | | |1 = IC1 input to Input Capture Unit Enabled.
* |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control
* | | |0 = IC2 input to Input Capture Unit Disabled.
* | | |1 = IC2 input to Input Capture Unit Enabled.
* |[9:8] |CAPSEL0 |CAP0 Input Source Selection
* | | |00 = CAP0 input is from port pin ICAP0.
* | | |01 = Reserved.
* | | |10 = CAP0 input is from signal CHA of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[11:10] |CAPSEL1 |CAP1 Input Source Selection
* | | |00 = CAP1 input is from port pin ICAP1.
* | | |01 = Reserved.
* | | |10 = CAP1 input is from signal CHB of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[13:12] |CAPSEL2 |CAP2 Input Source Selection
* | | |00 = CAP2 input is from port pin ICAP2.
* | | |01 = Reserved.
* | | |10 = CAP2 input is from signal CHX of QEI controller unit n.
* | | |11 = Reserved.
* | | |Note: Input capture unit n matches QEIn, where n = 0~1.
* |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
* | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
* |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
* | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
* |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
* | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
* |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
* |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control
* | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
* | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
* |[24] |CNTEN |Input Capture Counter Start Counting Control
* | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
* | | |0 = ECAP_CNT stop counting.
* | | |1 = ECAP_CNT starts up-counting.
* |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control
* | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
* | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
* |[28] |CMPEN |Compare Function Enable Control
* | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
* | | |0 = The compare function Disabled.
* | | |1 = The compare function Enabled.
* |[29] |CAPEN |Input Capture Timer/Counter Enable Control
* | | |0 = Input Capture function Disabled.
* | | |1 = Input Capture function Enabled.
* @var ECAP_T::CTL1
* Offset: 0x18 Input Capture Control Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection
* | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection
* | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection
* | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
* | | |00 = Detect rising edge only.
* | | |01 = Detect falling edge only.
* | | |1x = Detect both rising and falling edge.
* |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
* | | |0 = The reload triggered by Event CAPTE0 Disabled.
* | | |1 = The reload triggered by Event CAPTE0 Enabled.
* |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
* | | |0 = The reload triggered by Event CAPTE1 Disabled.
* | | |1 = The reload triggered by Event CAPTE1 Enabled.
* |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
* | | |0 = The reload triggered by Event CAPTE2 Disabled.
* | | |1 = The reload triggered by Event CAPTE2 Enabled.
* |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
* | | |0 = The reload triggered by CAPOV Disabled.
* | | |1 = The reload triggered by CAPOV Enabled.
* |[14:12] |CLKSEL |Capture Timer Clock Divide Selection
* | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
* | | |000 = CAP_CLK/1.
* | | |001 = CAP_CLK/4.
* | | |010 = CAP_CLK/16.
* | | |011 = CAP_CLK/32.
* | | |100 = CAP_CLK/64.
* | | |101 = CAP_CLK/96.
* | | |110 = CAP_CLK/112.
* | | |111 = CAP_CLK/128.
* |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
* | | |Select the capture timer/counter clock source.
* | | |00 = CAP_CLK (default).
* | | |01 = CAP0.
* | | |10 = CAP1.
* | | |11 = CAP2.
* |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
* | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
* |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
* | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
* |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
* | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
* | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
* @var ECAP_T::STATUS
* Offset: 0x1C Input Capture Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag
* | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
* | | |0 = No valid edge change has been detected at CAP0 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP0 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag
* | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
* | | |0 = No valid edge change has been detected at CAP1 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP1 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag
* | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
* | | |0 = No valid edge change has been detected at CAP2 input since last clear.
* | | |1 = At least a valid edge change has been detected at CAP2 input since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[4] |CAPCMPF |Input Capture Compare-match Flag
* | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
* | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
* | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[5] |CAPOVF |Input Capture Counter Overflow Flag
* | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
* | | |0 = No overflow event has occurred since last clear.
* | | |1 = Overflow event(s) has/have occurred since last clear.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only)
* | | |Reflecting the value of input channel 0, CAP0
* | | |(The bit is read only and write is ignored)
* |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only)
* | | |Reflecting the value of input channel 1, CAP1
* | | |(The bit is read only and write is ignored)
* |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only)
* | | |Reflecting the value of input channel 2, CAP2.
* | | |(The bit is read only and write is ignored)
*/
__IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */
__IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */
__IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */
__IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */
__IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */
__IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */
__IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */
__IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */
} ECAP_T;
/**
@addtogroup ECAP_CONST ECAP Bit Field Definition
Constant Definitions for ECAP Controller
@{ */
#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */
#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */
#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */
#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */
#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */
#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */
#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */
#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */
#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */
#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */
#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */
#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */
#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */
#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */
#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */
#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */
#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */
#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */
#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */
#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */
#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */
#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */
#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */
#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */
#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */
#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */
#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */
#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */
#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */
#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */
#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */
#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */
#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */
#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */
#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */
#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */
#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */
#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */
#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */
#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */
#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */
#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */
#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */
#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */
#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */
#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */
#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */
#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */
#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */
#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */
#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */
#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */
#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */
#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */
#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */
#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */
#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */
#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */
#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */
#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */
#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */
#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */
#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */
#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */
#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */
#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */
#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */
#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */
#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */
#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */
#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */
#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */
#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */
#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */
#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */
#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */
#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */
#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */
#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */
#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */
#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */
#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */
#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */
#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */
/**@}*/ /* ECAP_CONST */
/**@}*/ /* end of ECAP register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __ECAP_REG_H__ */

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/**************************************************************************//**
* @file qei_reg.h
* @version V1.00
* @brief EQEI register definition header file
*
* SPDX-License-Identifier: Apache-2.0
* @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __EQEI_REG_H__
#define __EQEI_REG_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/**
@addtogroup REGISTER Control Register
@{
*/
/**
@addtogroup EQEI Quadrature Encoder Interface(EQEI)
Memory Mapped Structure for EQEI Controller
@{ */
typedef struct
{
/**
* @var EQEI_T::CNT
* Offset: 0x00 EQEI Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNT |Quadrature Encoder Interface Counter
* | | |A 32-bit up/down counter
* | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (EQEI_STATUS[8]) is one or decreased by one if the bit DIRF(EQEI_STATUS[8]) is zero
* | | |This register performs an integrator which count value is proportional to the encoder position
* | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:
* | | |1. Software is written if EQEIEN (EQEI_CTL[29]) = 0.
* | | |2. Compare-match event if EQEIEN(EQEI_CTL[29])=1 and EQEI is in compare-counting mode.
* | | |3. Index signal change if EQEIEN(EQEI_CTL[29])=1 and IDXRLDEN (EQEI_CTL[27])=1.
* @var EQEI_T::CNTHOLD
* Offset: 0x04 EQEI Counter Hold Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold
* | | |When bit HOLDCNT (EQEI_CTL[24]) goes from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD (EQEI_CNTHOLD[31:0]) register.
* @var EQEI_T::CNTLATCH
* Offset: 0x08 EQEI Counter Index Latch Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch
* | | |When the IDXF (EQEI_STATUS[0]) bit is set, the CNT(EQEI_CNT[31:0]) is copied into CNTLATCH (EQEI_CNTLATCH[31:0]) register.
* @var EQEI_T::CNTCMP
* Offset: 0x0C EQEI Counter Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare
* | | |If the EQEI controller is in the compare-counting mode CMPEN (EQEI_CTL[28]) =1, when the value of CNT(EQEI_CNT[31:0]) matches CNTCMP(EQEI_CNTCMP[31:0]), CMPF will be set
* | | |This register is software writable.
* @var EQEI_T::CNTMAX
* Offset: 0x14 EQEI Pre-set Maximum Count Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count
* | | |This register value determined by user stores the maximum value which may be the number of the EQEI counter for the EQEI controller compare-counting mode
* @var EQEI_T::CTL
* Offset: 0x18 EQEI Controller Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection
* | | |To determine the sampling frequency of the Noise Filter clock .
* | | |000 = EQEI_CLK.
* | | |001 = EQEI_CLK/2.
* | | |010 = EQEI_CLK/4.
* | | |011 = EQEI_CLK/16.
* | | |100 = EQEI_CLK/32.
* | | |101 = EQEI_CLK/64.
* |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit
* | | |0 = The noise filter of EQEI controller Enabled.
* | | |1 = The noise filter of EQEI controller Disabled.
* |[4] |CHAEN |QEA Input to EQEI Controller Enable Bit
* | | |0 = QEA input to EQEI Controller Disabled.
* | | |1 = QEA input to EQEI Controller Enabled.
* |[5] |CHBEN |QEB Input to EQEI Controller Enable Bit
* | | |0 = QEB input to EQEI Controller Disabled.
* | | |1 = QEB input to EQEI Controller Enabled.
* |[6] |IDXEN |IDX Input to EQEI Controller Enable Bit
* | | |0 = IDX input to EQEI Controller Disabled.
* | | |1 = IDX input to EQEI Controller Enabled.
* |[7] |IDXRSTEN |IDX Reset EQEI Position Counter Enable Bit
* | | |0 = Reset EQEI position counter in every time IDX signal.
* | | |1 = Reset EQEI position counter in first time IDX signal.
* | | |Note: IDXRLDEN(EQEI_CTL[27]) should be set 1.
* |[10:8] |MODE |QEI Counting Mode Selection
* | | |There are seven quadrature encoder pulse counter operation modes.
* | | |000 = X4 Free-counting Mode.
* | | |001 = X2 Free-counting Mode.
* | | |010 = X4 Compare-counting Mode.
* | | |011 = X2 Compare-counting Mode.
* | | |100 = Phase Counting Mode Type 1. (PCMT1).
* | | |101 = Phase Counting Mode Type 2. (PCMT2).
* | | |110 = Directional Counting Mode.
* | | |111 = Reserved.
* | | |Note: User needs to set DIRSRC(EQEI_CTL2[5:4]) when MODE(EQEI_CTL[10:8]) selects to directional counting mode.
* |[12] |CHAINV |Inverse QEA Input Polarity
* | | |0 = Not inverse QEA input polarity.
* | | |1 = QEA input polarity is inversed to EQEI controller.
* |[13] |CHBINV |Inverse QEB Input Polarity
* | | |0 = Not inverse QEB input polarity.
* | | |1 = QEB input polarity is inversed to EQEI controller.
* |[14] |IDXINV |Inverse IDX Input Polarity
* | | |0 = Not inverse IDX input polarity.
* | | |1 = IDX input polarity is inversed to EQEI controller.
* |[15] |IDXRSTEV |IDX Signal Resets Enable Bit in First IDX Reset Event (Write Only)
* | | |0 = The next IDX level high signal reset function is disabled.
* | | |1 = The next IDX level high signal reset function is enabled.
* | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1.
* |[16] |OVUNIEN |OVUNF Trigger EQEI Interrupt Enable Bit
* | | |0 = OVUNF can trigger EQEI controller interrupt Disabled.
* | | |1 = OVUNF can trigger EQEI controller interrupt Enabled.
* |[17] |DIRIEN |DIRCHGF Trigger EQEI Interrupt Enable Bit
* | | |0 = DIRCHGF can trigger EQEI controller interrupt Disabled.
* | | |1 = DIRCHGF can trigger EQEI controller interrupt Enabled.
* |[18] |CMPIEN |CMPF Trigger EQEI Interrupt Enable Bit
* | | |0 = CMPF can trigger EQEI controller interrupt Disabled.
* | | |1 = CMPF can trigger EQEI controller interrupt Enabled.
* |[19] |IDXIEN |IDXF Trigger EQEI Interrupt Enable Bit
* | | |0 = The IDXF can trigger EQEI interrupt Disabled.
* | | |1 = The IDXF can trigger EQEI interrupt Enabled.
* |[20] |HOLDTMR0 |Hold EQEI_CNT by Timer 0
* | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
* |[21] |HOLDTMR1 |Hold EQEI_CNT by Timer 1
* | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
* |[22] |HOLDTMR2 |Hold EQEI_CNT by Timer 2
* | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
* |[23] |HOLDTMR3 |Hold EQEI_CNT by Timer 3
* | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
* | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
* |[24] |HOLDCNT |Hold EQEI_CNT Control
* | | |When this bit is set from low to high, the CNT(EQEI_CNT[31:0]) is copied into CNTHOLD(EQEI_CNTHOLD[31:0])
* | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
* | | |0 = No operation.
* | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]).
* | | |Note: This bit is automatically cleared after EQEI_CNTHOLD holds EQEI_CNT value.
* |[25] |IDXLATEN |Index Latch EQEI_CNT Enable Bit
* | | |If this bit is set to high, the CNT(EQEI_CNT[31:0]) content will be latched into CNTLATCH (EQEI_CNTLATCH[31:0]) at every rising on signal CHX.
* | | |0 = The index signal latch EQEI counter function Disabled.
* | | |1 = The index signal latch EQEI counter function Enabled.
* |[27] |IDXRLDEN |Index Trigger EQEI_CNT Reload Enable Bit
* | | |When this bit is high and a rising edge comes on signal CHX, the CNT(EQEI_CNT[31:0]) will be reset to zero if the counter is in up-counting type (DIRF(EQEI_STATUS[8]) = 1); while the CNT(EQEI_CNT[31:0]) will be reloaded with CNTMAX (EQEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF(EQEI_STATUS[8]) = 0).
* | | |0 = Reload function Disabled.
* | | |1 = EQEI_CNT re-initialized by Index signal Enabled.
* |[28] |CMPEN |The Compare Function Enable Bit
* | | |The compare function in EQEI controller is to compare the dynamic counting EQEI_CNT with the compare register CNTCMP( EQEI_CNTCMP[31:0]), if CNT(EQEI_CNT[31:0]) reaches CNTCMP( EQEI_CNTCMP[31:0]), the flag CMPF will be set.
* | | |0 = Compare function Disabled.
* | | |1 = Compare function Enabled.
* |[29] |EQEIEN |Enhanced Quadrature Encoder Interface Controller Enable Bit
* | | |0 = EQEI controller function Disabled.
* | | |1 = EQEI controller function Enabled.
* @var EQEI_T::CTL2
* Offset: 0x1C EQEI Controller Control Register2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SWAPEN |Swap Function Enable Bit
* | | |0 = EQEI swap function Disabled.
* | | |1 = EQEI swap function Enabled.
* |[2:1] |CRS |Clock Rate Setting without Quadrature Mode
* | | |00 = EQEI counter only counts the falling edge.
* | | |01 = EQEI counter only counts the rising edge.
* | | |10 = EQEI counter counts the rising and falling edge.
* | | |11 = reserved.
* |[5:4] |DIRSRC |Direction Signal Source Select
* | | |00 = Direction signal is determined from EQEI system calculation.
* | | |01 = reserved.
* | | |10 = Direction signal is tied 1 only for direction up count mode.
* | | |11 = Direction signal is tied 0 only for down count mode.
* |[8] |UTEN |Unit Timer Function Enable Bit
* | | |0 = EQEI unit timer function is disable.
* | | |1 = EQEI unit timer function is enable.
* |[9] |UTHOLDEN |Unit Timer Counter Hold Enable Bit
* | | |0 = No operation.
* | | |1 = EQEI_CNT content is captured and stored in CNTHOLD(EQEI_CNTHOLD[31:0]) when UTCNT matches UTCMP(EQEI_UTCMP[31:0]).
* |[10] |UTEVTRST |Enable Bit to Reset EQEI Position Counter by Unit Timer Event
* | | |0 = Disable to reset EQEI position counter feature when unit timer counter event occurs.
* | | |1 = Enable to reset EQEI position counter feature when unit timer counter event occurs.
* |[11] |IDXRSTUTS |IDX Resets Unit Timer Select Bit
* | | |0 = Unit timer will not be reset when IDX reset event happens.
* | | |1 = Resets unit timer or not will follow EQEI_CNT when IDX reset event happens.
* |[16] |PHEIEN |PHEF Trigger EQEI Interrupt Enable Bit
* | | |0 = PHEF can trigger EQEI controller interrupt Disabled.
* | | |1 = PHEF can trigger EQEI controller interrupt Enabled.
* |[17] |UTIEIEN |UTIEF Trigger EQEI Interrupt Enable Bit
* | | |0 = UTIEF can trigger EQEI controller interrupt Disabled.
* | | |1 = UTIEF can trigger EQEI controller interrupt Enabled.
* @var EQEI_T::UTCNT
* Offset: 0x20 EQEI Unit Timer Counter Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |UTCNT |Unit Timer Counter
* | | |A 32-bit unit timer counter which may be reset to an initial value when any of the following events occur:
* | | |1. Software is written if UTEN (EQEI_CTL2[8]) = 0.
* | | |2. UT_EN (EQEI_CTL2[8]) =1, and the unit timer counter value matches UTCMP(EQEI_UTCMP[31:0]).
* | | |3. IDXRLDEN(EQEI_CTL[27]) =1 and IDXRSTUTS(EQEI_CTL2[11]=1, determine the unit timer to be reset or not will follow EQEI_CNT when IDX reset event happens.
* @var EQEI_T::UTCMP
* Offset: 0x24 EQEI Unit Timer Compare Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |UTCMP |Unit Timer Counter Compare
* | | |If the EQEI unit timer is enable (EQEI_CTL2[8]) =1, and the unit timer counter value also matches UTCMP(EQEI_UTCMP[31:0]), then UTIEF (EQEI_STATUS[10]) will be set. This register is software writable.
* @var EQEI_T::STATUS
* Offset: 0x2C EQEI Controller Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |IDXF |IDX Detected Flag
* | | |When the EQEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
* | | |0 = No rising edge detected on signal CHX.
* | | |1 = A rising edge occurs on signal CHX.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[1] |CMPF |Compare-match Flag
* | | |If the EQEI compare function is enabled, the flag is set by hardware while EQEI counter up or down counts and reach to the CNTCMP(EQEI_CNTCMP[31:0]).
* | | |0 = EQEI counter does not match with CNTCMP(EQEI_CNTCMP[31:0]).
* | | |1 = EQEI counter counts to the same as CNTCMP(EQEI_CNTCMP[31:0]).
* | | |Note: This bit is only cleared by writing 1 to it.
* |[2] |OVUNF |QEI Counter Overflow or Underflow Flag
* | | |Flag is set by hardware while CNT(EQEI_CNT[31:0]) overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (EQEI_CNTMAX[31:0]) to zero in compare-counting mode
* | | |Similarly, the flag is set while EQEI counter underflows from zero to 0xFFFF_FFFF or CNTMAX (EQEI_CNTMAX[31:0]).
* | | |0 = No overflow or underflow occurs in EQEI counter.
* | | |1 = EQEI counter occurs counting overflow or underflow.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[3] |DIRCHGF |Direction Change Flag
* | | |Flag is set by hardware while EQEI counter counting direction is changed.
* | | |Software can clear this bit by writing 1 to it.
* | | |0 = No change in EQEI counter counting direction.
* | | |1 = EQEI counter counting direction is changed.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[8] |DIRF |QEI Counter Counting Direction Indication
* | | |0 = EQEI Counter is in down-counting.
* | | |1 = EQEI Counter is in up-counting.
* | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
* |[9] |FIDXEF |First IDX Signal Reset Event Flag (Read Only)
* | | |0 = The first IDX reset event has not happened yet.
* | | |1 = The first IDX reset event has happened.
* | | |Note: This bit only effective when IDXRSTEN (EQEI_CTL[7])=1 and IDXRLDEN (EQEI_CTL[27])=1.
* |[16] |PHEF EQEI |Phase Error Flag
* | | |0 = No Phase error occurs in EQEI CHA and CHB.
* | | |1 = Phase error occurs in EQEI CHA and CHB.
* | | |Note: This bit is only cleared by writing 1 to it.
* |[17] |UTIEF |EQEI Unit Timer Event Flag
* | | |0 = No timer event occurs in EQEI unit timer counter.
* | | |1 = Unit timer event occurs in EQEI unit timer counter.
* | | |Note: This bit is only cleared by writing 1 to it.
*/
__IO uint32_t CNT; /*!< [0x0000] EQEI Counter Register */
__IO uint32_t CNTHOLD; /*!< [0x0004] EQEI Counter Hold Register */
__IO uint32_t CNTLATCH; /*!< [0x0008] EQEI Counter Index Latch Register */
__IO uint32_t CNTCMP; /*!< [0x000c] EQEI Counter Compare Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE0[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t CNTMAX; /*!< [0x0014] EQEI Pre-set Maximum Count Register */
__IO uint32_t CTL; /*!< [0x0018] EQEI Controller Control Register */
__IO uint32_t CTL2; /*!< [0x001C] EQEI Controller Control Register2 */
__IO uint32_t UTCNT; /*!< [0x0020] EQEI Unit Timer Counter Register */
__IO uint32_t UTCMP; /*!< [0x0024] EQEI Unit Timer Compare Register */
/// @cond HIDDEN_SYMBOLS
__I uint32_t RESERVE1[1];
/// @endcond //HIDDEN_SYMBOLS
__IO uint32_t STATUS; /*!< [0x002c] EQEI Controller Status Register */
} EQEI_T;
/**
@addtogroup EQEI_CONST EQEI Bit Field Definition
Constant Definitions for EQEI Controller
@{ */
#define EQEI_CNT_CNT_Pos (0) /*!< EQEI_T::CNT: CNT Position */
#define EQEI_CNT_CNT_Msk (0xfffffffful << EQEI_CNT_CNT_Pos) /*!< EQEI_T::CNT: CNT Mask */
#define EQEI_CNTHOLD_CNTHOLD_Pos (0) /*!< EQEI_T::CNTHOLD: CNTHOLD Position */
#define EQEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << EQEI_CNTHOLD_CNTHOLD_Pos) /*!< EQEI_T::CNTHOLD: CNTHOLD Mask */
#define EQEI_CNTLATCH_CNTLATCH_Pos (0) /*!< EQEI_T::CNTLATCH: CNTLATCH Position */
#define EQEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << EQEI_CNTLATCH_CNTLATCH_Pos) /*!< EQEI_T::CNTLATCH: CNTLATCH Mask */
#define EQEI_CNTCMP_CNTCMP_Pos (0) /*!< EQEI_T::CNTCMP: CNTCMP Position */
#define EQEI_CNTCMP_CNTCMP_Msk (0xfffffffful << EQEI_CNTCMP_CNTCMP_Pos) /*!< EQEI_T::CNTCMP: CNTCMP Mask */
#define EQEI_CNTMAX_CNTMAX_Pos (0) /*!< EQEI_T::CNTMAX: CNTMAX Position */
#define EQEI_CNTMAX_CNTMAX_Msk (0xfffffffful << EQEI_CNTMAX_CNTMAX_Pos) /*!< EQEI_T::CNTMAX: CNTMAX Mask */
#define EQEI_CTL_NFCLKSEL_Pos (0) /*!< EQEI_T::CTL: NFCLKSEL Position */
#define EQEI_CTL_NFCLKSEL_Msk (0x7ul << EQEI_CTL_NFCLKSEL_Pos) /*!< EQEI_T::CTL: NFCLKSEL Mask */
#define EQEI_CTL_NFDIS_Pos (3) /*!< EQEI_T::CTL: NFDIS Position */
#define EQEI_CTL_NFDIS_Msk (0x1ul << EQEI_CTL_NFDIS_Pos) /*!< EQEI_T::CTL: NFDIS Mask */
#define EQEI_CTL_CHAEN_Pos (4) /*!< EQEI_T::CTL: CHAEN Position */
#define EQEI_CTL_CHAEN_Msk (0x1ul << EQEI_CTL_CHAEN_Pos) /*!< EQEI_T::CTL: CHAEN Mask */
#define EQEI_CTL_CHBEN_Pos (5) /*!< EQEI_T::CTL: CHBEN Position */
#define EQEI_CTL_CHBEN_Msk (0x1ul << EQEI_CTL_CHBEN_Pos) /*!< EQEI_T::CTL: CHBEN Mask */
#define EQEI_CTL_IDXEN_Pos (6) /*!< EQEI_T::CTL: IDXEN Position */
#define EQEI_CTL_IDXEN_Msk (0x1ul << EQEI_CTL_IDXEN_Pos) /*!< EQEI_T::CTL: IDXEN Mask */
#define EQEI_CTL_IDXRSTEN_Pos (7) /*!< EQEI_T::CTL: IDXRSTEN Position */
#define EQEI_CTL_IDXRSTEN_Msk (0x1ul << EQEI_CTL_IDXRSTEN_Pos) /*!< EQEI_T::CTL: IDXRSTEN Mask */
#define EQEI_CTL_MODE_Pos (8) /*!< EQEI_T::CTL: MODE Position */
#define EQEI_CTL_MODE_Msk (0x7ul << EQEI_CTL_MODE_Pos) /*!< EQEI_T::CTL: MODE Mask */
#define EQEI_CTL_CHAINV_Pos (12) /*!< EQEI_T::CTL: CHAINV Position */
#define EQEI_CTL_CHAINV_Msk (0x1ul << EQEI_CTL_CHAINV_Pos) /*!< EQEI_T::CTL: CHAINV Mask */
#define EQEI_CTL_CHBINV_Pos (13) /*!< EQEI_T::CTL: CHBINV Position */
#define EQEI_CTL_CHBINV_Msk (0x1ul << EQEI_CTL_CHBINV_Pos) /*!< EQEI_T::CTL: CHBINV Mask */
#define EQEI_CTL_IDXINV_Pos (14) /*!< EQEI_T::CTL: IDXINV Position */
#define EQEI_CTL_IDXINV_Msk (0x1ul << EQEI_CTL_IDXINV_Pos) /*!< EQEI_T::CTL: IDXINV Mask */
#define EQEI_CTL_IDXRSTEV_Pos (15) /*!< EQEI_T::CTL: IDXRSTEV Position */
#define EQEI_CTL_IDXRSTEV_Msk (0x1ul << EQEI_CTL_IDXRSTEV_Pos) /*!< EQEI_T::CTL: IDXRSTEV Mask */
#define EQEI_CTL_OVUNIEN_Pos (16) /*!< EQEI_T::CTL: OVUNIEN Position */
#define EQEI_CTL_OVUNIEN_Msk (0x1ul << EQEI_CTL_OVUNIEN_Pos) /*!< EQEI_T::CTL: OVUNIEN Mask */
#define EQEI_CTL_DIRIEN_Pos (17) /*!< EQEI_T::CTL: DIRIEN Position */
#define EQEI_CTL_DIRIEN_Msk (0x1ul << EQEI_CTL_DIRIEN_Pos) /*!< EQEI_T::CTL: DIRIEN Mask */
#define EQEI_CTL_CMPIEN_Pos (18) /*!< EQEI_T::CTL: CMPIEN Position */
#define EQEI_CTL_CMPIEN_Msk (0x1ul << EQEI_CTL_CMPIEN_Pos) /*!< EQEI_T::CTL: CMPIEN Mask */
#define EQEI_CTL_IDXIEN_Pos (19) /*!< EQEI_T::CTL: IDXIEN Position */
#define EQEI_CTL_IDXIEN_Msk (0x1ul << EQEI_CTL_IDXIEN_Pos) /*!< EQEI_T::CTL: IDXIEN Mask */
#define EQEI_CTL_HOLDTMR0_Pos (20) /*!< EQEI_T::CTL: HOLDTMR0 Position */
#define EQEI_CTL_HOLDTMR0_Msk (0x1ul << EQEI_CTL_HOLDTMR0_Pos) /*!< EQEI_T::CTL: HOLDTMR0 Mask */
#define EQEI_CTL_HOLDTMR1_Pos (21) /*!< EQEI_T::CTL: HOLDTMR1 Position */
#define EQEI_CTL_HOLDTMR1_Msk (0x1ul << EQEI_CTL_HOLDTMR1_Pos) /*!< EQEI_T::CTL: HOLDTMR1 Mask */
#define EQEI_CTL_HOLDTMR2_Pos (22) /*!< EQEI_T::CTL: HOLDTMR2 Position */
#define EQEI_CTL_HOLDTMR2_Msk (0x1ul << EQEI_CTL_HOLDTMR2_Pos) /*!< EQEI_T::CTL: HOLDTMR2 Mask */
#define EQEI_CTL_HOLDTMR3_Pos (23) /*!< EQEI_T::CTL: HOLDTMR3 Position */
#define EQEI_CTL_HOLDTMR3_Msk (0x1ul << EQEI_CTL_HOLDTMR3_Pos) /*!< EQEI_T::CTL: HOLDTMR3 Mask */
#define EQEI_CTL_HOLDCNT_Pos (24) /*!< EQEI_T::CTL: HOLDCNT Position */
#define EQEI_CTL_HOLDCNT_Msk (0x1ul << EQEI_CTL_HOLDCNT_Pos) /*!< EQEI_T::CTL: HOLDCNT Mask */
#define EQEI_CTL_IDXLATEN_Pos (25) /*!< EQEI_T::CTL: IDXLATEN Position */
#define EQEI_CTL_IDXLATEN_Msk (0x1ul << EQEI_CTL_IDXLATEN_Pos) /*!< EQEI_T::CTL: IDXLATEN Mask */
#define EQEI_CTL_IDXRLDEN_Pos (27) /*!< EQEI_T::CTL: IDXRLDEN Position */
#define EQEI_CTL_IDXRLDEN_Msk (0x1ul << EQEI_CTL_IDXRLDEN_Pos) /*!< EQEI_T::CTL: IDXRLDEN Mask */
#define EQEI_CTL_CMPEN_Pos (28) /*!< EQEI_T::CTL: CMPEN Position */
#define EQEI_CTL_CMPEN_Msk (0x1ul << EQEI_CTL_CMPEN_Pos) /*!< EQEI_T::CTL: CMPEN Mask */
#define EQEI_CTL_QEIEN_Pos (29) /*!< EQEI_T::CTL: EQEIEN Position */
#define EQEI_CTL_QEIEN_Msk (0x1ul << EQEI_CTL_QEIEN_Pos) /*!< EQEI_T::CTL: EQEIEN Mask */
#define EQEI_CTL2_SWAPEN_Pos (0) /*!< EQEI_T::CTL2: SWAPEN Position */
#define EQEI_CTL2_SWAPEN_Msk (0x1ul << EQEI_CTL2_SWAPEN_Pos) /*!< EQEI_T::CTL2: SWAPEN Mask */
#define EQEI_CTL2_CRS_Pos (1) /*!< EQEI_T::CTL2: CRS Position */
#define EQEI_CTL2_CRS_Msk (0x3ul << EQEI_CTL2_CRS_Pos) /*!< EQEI_T::CTL2: CRS Mask */
#define EQEI_CTL2_DIRSRC_Pos (4) /*!< EQEI_T::CTL2: DIRSRC Position */
#define EQEI_CTL2_DIRSRC_Msk (0x3ul << EQEI_CTL2_DIRSRC_Pos) /*!< EQEI_T::CTL2: DIRSRC Mask */
#define EQEI_CTL2_UTEN_Pos (8) /*!< EQEI_T::CTL2: UTEN Position */
#define EQEI_CTL2_UTEN_Msk (0x1ul << EQEI_CTL2_UTEN_Pos) /*!< EQEI_T::CTL2: UTEN Mask */
#define EQEI_CTL2_UTHOLDEN_Pos (9) /*!< EQEI_T::CTL2: UTHOLDEN Position */
#define EQEI_CTL2_UTHOLDEN_Msk (0x1ul << EQEI_CTL2_UTHOLDEN_Pos) /*!< EQEI_T::CTL2: UTHOLDEN Mask */
#define EQEI_CTL2_UTEVTRST_Pos (10) /*!< EQEI_T::CTL2: UTEVTRST Position */
#define EQEI_CTL2_UTEVTRST_Msk (0x1ul << EQEI_CTL2_UTEVTRST_Pos) /*!< EQEI_T::CTL2: UTEVTRST Mask */
#define EQEI_CTL2_IDXRSTUTS_Pos (11) /*!< EQEI_T::CTL2: IDXRSTUTS Position */
#define EQEI_CTL2_IDXRSTUTS_Msk (0x1ul << EQEI_CTL2_IDXRSTUTS_Pos) /*!< EQEI_T::CTL2: IDXRSTUTS Mask */
#define EQEI_CTL2_PHEIEN_Pos (16) /*!< EQEI_T::CTL2: PHEIEN Position */
#define EQEI_CTL2_PHEIEN_Msk (0x1ul << EQEI_CTL2_PHEIEN_Pos) /*!< EQEI_T::CTL2: PHEIEN Mask */
#define EQEI_CTL2_UTIEIEN_Pos (17) /*!< EQEI_T::CTL2: UTIEIEN Position */
#define EQEI_CTL2_UTIEIEN_Msk (0x1ul << EQEI_CTL2_UTIEIEN_Pos) /*!< EQEI_T::CTL2: UTIEIEN Mask */
#define EQEI_UTCNT_UTCNT_Pos (0) /*!< EQEI_T::UTCNT: UTCNT Position */
#define EQEI_UTCNT_UTCNT_Msk (0xfffffffful << EQEI_UTCNT_UTCNT_Pos) /*!< EQEI_T::UTCNT: UTCNT Mask */
#define EQEI_UTCMP_UTCMP_Pos (0) /*!< EQEI_T::UTCMP: UTCMP Position */
#define EQEI_UTCMP_UTCMP_Msk (0xfffffffful << EQEI_UTCMP_UTCMP_Pos) /*!< EQEI_T::UTCMP: UTCMP Mask */
#define EQEI_STATUS_IDXF_Pos (0) /*!< EQEI_T::STATUS: IDXF Position */
#define EQEI_STATUS_IDXF_Msk (0x1ul << EQEI_STATUS_IDXF_Pos) /*!< EQEI_T::STATUS: IDXF Mask */
#define EQEI_STATUS_CMPF_Pos (1) /*!< EQEI_T::STATUS: CMPF Position */
#define EQEI_STATUS_CMPF_Msk (0x1ul << EQEI_STATUS_CMPF_Pos) /*!< EQEI_T::STATUS: CMPF Mask */
#define EQEI_STATUS_OVUNF_Pos (2) /*!< EQEI_T::STATUS: OVUNF Position */
#define EQEI_STATUS_OVUNF_Msk (0x1ul << EQEI_STATUS_OVUNF_Pos) /*!< EQEI_T::STATUS: OVUNF Mask */
#define EQEI_STATUS_DIRCHGF_Pos (3) /*!< EQEI_T::STATUS: DIRCHGF Position */
#define EQEI_STATUS_DIRCHGF_Msk (0x1ul << EQEI_STATUS_DIRCHGF_Pos) /*!< EQEI_T::STATUS: DIRCHGF Mask */
#define EQEI_STATUS_DIRF_Pos (8) /*!< EQEI_T::STATUS: DIRF Position */
#define EQEI_STATUS_DIRF_Msk (0x1ul << EQEI_STATUS_DIRF_Pos) /*!< EQEI_T::STATUS: DIRF Mask */
#define EQEI_STATUS_FIDXEF_Pos (9) /*!< EQEI_T::STATUS: FIDXEF Position */
#define EQEI_STATUS_FIDXEF_Msk (0x1ul << EQEI_STATUS_FIDXEF_Pos) /*!< EQEI_T::STATUS: FIDXEF Mask */
#define EQEI_STATUS_PHEF_Pos (16) /*!< EQEI_T::STATUS: PHEF Position */
#define EQEI_STATUS_PHEF_Msk (0x1ul << EQEI_STATUS_PHEF_Pos) /*!< EQEI_T::STATUS: PHEF Mask */
#define EQEI_STATUS_UTIEF_Pos (17) /*!< EQEI_T::STATUS: UTIEF Position */
#define EQEI_STATUS_UTIEF_Msk (0x1ul << EQEI_STATUS_UTIEF_Pos) /*!< EQEI_T::STATUS: UTIEF Mask */
/**@}*/ /* EQEI_CONST */
/**@}*/ /* end of EQEI register group */
/**@}*/ /* end of REGISTER group */
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif /* __EQEI_REG_H__ */

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