bsp/nuclei: Add more drivers support for gd32vf103

* More drivers are supported for rvstar board, see README.md
* If user want to use these supported drivers, menuconfig is required
* User also need to setup pinmux for its coresponding driver in
board/board.c

Signed-off-by: Huaqi Fang <578567190@qq.com>

bsp/nuclei/gd32vf103_rvstar/.config

@@ -78,7 +78,7 @@ CONFIG_ARCH_RISCV32=y
 #
 CONFIG_RT_USING_COMPONENTS_INIT=y
 CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024
 CONFIG_RT_MAIN_THREAD_PRIORITY=10
 
 #
@@ -97,7 +97,7 @@ CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_THREAD_STACK_SIZE=2048
 CONFIG_FINSH_CMD_SIZE=80
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_USING_MSH=y
@@ -108,27 +108,18 @@ CONFIG_FINSH_ARG_MAX=10
 #
 # Device virtual file system
 #
-CONFIG_RT_USING_DFS=y
-CONFIG_DFS_USING_WORKDIR=y
-CONFIG_DFS_FILESYSTEMS_MAX=2
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
-# CONFIG_RT_USING_DFS_ELMFAT is not set
-CONFIG_RT_USING_DFS_DEVFS=y
-# CONFIG_RT_USING_DFS_ROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
@@ -163,10 +154,6 @@ CONFIG_RT_USING_PIN=y
 #
 CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_PTHREADS is not set
-CONFIG_RT_USING_POSIX=y
-# CONFIG_RT_USING_POSIX_MMAP is not set
-# CONFIG_RT_USING_POSIX_TERMIOS is not set
-# CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
 
 #
@@ -218,6 +205,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -244,6 +232,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -320,6 +309,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_URLENCODE is not set
 
 #
 # system packages
@@ -330,6 +320,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -361,6 +352,7 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_LITTLED is not set
 # CONFIG_PKG_USING_LKDGUI is not set
 # CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
@@ -386,10 +378,15 @@ CONFIG_RT_USING_POSIX=y
 # CONFIG_PKG_USING_EASYBLINK is not set
 # CONFIG_PKG_USING_PMS_SERIES is not set
 CONFIG_PKG_USING_NUCLEI_SDK=y
+
+#
+# !!!Nuclei SDK only works with Nuclei RISC-V Processor IP!!!
+#
 CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk"
 # CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set
 CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y
 CONFIG_PKG_NUCLEI_SDK_VER="latest"
+# CONFIG_PKG_USING_CAN_YMODEM is not set
 
 #
 # miscellaneous packages
@@ -446,6 +443,13 @@ CONFIG_BSP_USING_UART=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
 CONFIG_BSP_USING_UART4=y
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_HWTIMER is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_PWM is not set
 
 #
 # Board extended module Drivers

bsp/nuclei/gd32vf103_rvstar/README.md

@@ -195,12 +195,34 @@ ELF文件, 然后配置OPENOCD和GDB即可, OPENOCD配置文件路径为**bsp\nu
 
 | 驱动 | 支持情况  |  备注  |
 | ------ | ----  | :------:  |
-| UART | 支持 | RV-STAR板载串口是UART4 |
+| UART | 支持 | RV-STAR板载串口是UART4, 默认使能 |
+| GPIO | 支持 | 默认使能，支持中断控制 |
+| SPI | 支持 | 默认关闭 |
+| I2C | 支持 | 默认关闭 |
+| HWTIMER | 支持 | 默认关闭 |
+| PWM | 支持 | 默认关闭 |
+| WDT | 支持 | 默认关闭 |
+| RTC | 支持 | 默认关闭 |
+| ADC | 支持 | 默认关闭 |
+
+由于针对不同的外设接口GPIO的pinux配置不一样，开发者需要根据自己的需求
+在 `board/board.c` 中的 `rt_hw_drivers_init`入口函数中使用到这个子函数
+中进行功能适配。
+
+例如需要将I2C1的SCL和SDA配置在PB10和PB11，则配置代码在`rt_hw_i2c_drvinit`
+函数中，则需要进行如下设定。
+
+~~~c
+/* Configure PB10 PB11 (I2C1 SCL SDA) as alternate function  */
+gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11);
+~~~
 
 **注:**
 
 - 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。
 - 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。
+- GD32VF103的驱动适配开关在 `menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers` 可以找到。
+- HWTIMER和PWM都是采用的TIMER模块进行功能实现，所以在使用驱动时，请务必注意不要重叠使用相同模块。
 
 ## 联系人信息
 

bsp/nuclei/gd32vf103_rvstar/SConstruct

@@ -24,7 +24,8 @@ DefaultEnvironment(tools=[])
 env = Environment(tools = ['mingw'],
     AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
     CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc', LIBS = rtconfig.LIBS,
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 env['ASCOM'] = env['ASPPCOM']
@@ -50,7 +51,11 @@ objs = PrepareBuilding(env, RTT_ROOT)
 bsp_library_type = rtconfig.NUCLEI_SDK_SOC
 rtconfig.BSP_LIBRARY_TYPE = bsp_library_type
 
-openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/')
+if hasattr(rtconfig, 'NUCLEI_SDK_OPENOCD_CFG'):
+    openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/')
+else:
+    print("ERROR: Nuclei SDK package is not yet downloaded, please execute <pkgs --update> in command line first!")
+    exit(0)
 
 # include hal drivers
 hal_sconscript = os.path.join(libraries_path_prefix, bsp_library_type, 'HAL_Drivers', 'SConscript')

bsp/nuclei/gd32vf103_rvstar/board/Kconfig

@@ -38,6 +38,108 @@ menu "On-chip Peripheral Drivers"
                 default n
         endif
 
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C"
+        default n
+        select RT_USING_I2C
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+                default n
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+                default n
+        endif
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI0
+                bool "Enable SPI0"
+                default n
+            config BSP_USING_SPI1
+                bool "Enable SPI1"
+                default n
+            config BSP_USING_SPI2
+                bool "Enable SPI2"
+                default n
+        endif
+
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable TIMER"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_HWTIMER
+            config BSP_USING_HWTIMER0
+                bool "Enable TIMER0"
+                default n
+            config BSP_USING_HWTIMER1
+                bool "Enable TIMER1"
+                default n
+            config BSP_USING_HWTIMER2
+                bool "Enable TIMER2"
+                default n
+            config BSP_USING_HWTIMER3
+                bool "Enable TIMER3"
+                default n
+            config BSP_USING_HWTIMER4
+                bool "Enable TIMER4"
+                default n
+            config BSP_USING_HWTIMER5
+                bool "Enable TIMER5"
+                default n
+            config BSP_USING_HWTIMER6
+                bool "Enable TIMER6"
+                default n
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC0
+                bool "Enable ADC0"
+                default n
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+        endif
+
+    menuconfig BSP_USING_WDT
+        bool "Enable WDT"
+        default n
+        select RT_USING_WDT
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        default n
+        select RT_USING_RTC
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+            config BSP_USING_PWM0
+                bool "Enable PWM0"
+                default n
+            config BSP_USING_PWM1
+                bool "Enable PWM1"
+                default n
+            config BSP_USING_PWM2
+                bool "Enable PWM2"
+                default n
+            config BSP_USING_PWM3
+                bool "Enable PWM3"
+                default n
+            config BSP_USING_PWM4
+                bool "Enable PWM4"
+                default n
+        endif
+
 endmenu
 
 menu "Board extended module Drivers"

bsp/nuclei/gd32vf103_rvstar/board/board.c

@@ -32,6 +32,125 @@ extern void *_heap_end;
  */
 extern void _init(void);
 
+// Check pin assignment here https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html
+
+void rt_hw_spi_drvinit(void)
+{
+    // rcu_periph_clock_enable(RCU_GPIOA);
+    // rcu_periph_clock_enable(RCU_GPIOE);
+    // rcu_periph_clock_enable(RCU_AF);
+    // /* Configure PA5 PA6 PA7 (SPI0 SCK MISO MOSI) as alternate function  */
+    // gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7);
+    // gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
+    // /* Configure PE2 PE3 PE4 (CS OLED_DC OLED_RES ) as output  */
+    // gpio_init(GPIOE, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4);
+
+    // rcu_periph_clock_enable(RCU_GPIOB);
+
+    // /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */
+    // gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15);
+    // gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14);
+    // /* SPI1_CS(PB12) GPIO pin configuration */
+    // gpio_init(GPIOB, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_12);
+}
+
+void rt_hw_adc_drvinit(void)
+{
+
+}
+
+void rt_hw_gpio_drvinit(void)
+{
+
+}
+
+void rt_hw_hwtimer_drvinit(void)
+{
+
+}
+
+void rt_hw_i2c_drvinit(void)
+{
+    // rcu_periph_clock_enable(RCU_GPIOB);
+    // rcu_periph_clock_enable(RCU_AF);
+    // /* Configure PB10 PB11 (I2C1 SCL SDA) as alternate function  */
+    // gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11);
+    // /* Configure PB6 PB7 (I2C0 SCL SDA) as alternate function  */
+    // gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7);
+}
+
+void rt_hw_pwm_drvinit(void)
+{
+    // rcu_periph_clock_enable(RCU_GPIOA);
+    // rcu_periph_clock_enable(RCU_GPIOB);
+    // rcu_periph_clock_enable(RCU_AF);
+
+    /* Configure PA0 PA1 PA2 PA3(TIMER1 CH0 CH1 CH2 CH3) as alternate function */
+    // gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0);
+    // gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1);
+    // gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
+    // gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3);
+
+    /* Configure PA6 PA7 PB0 PB1(TIMER2 CH0 CH1 CH2 CH3) as alternate function */
+    // gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
+    // gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7);
+    // gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0);
+    // gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_1);
+}
+
+void rt_hw_rtc_drvinit(void)
+{
+
+}
+
+void rt_hw_uart_drvinit(void)
+{
+    // Debug UART4 GPIO pins are already initialized in nuclei_sdk
+
+    // rcu_periph_clock_enable(RCU_GPIOC);
+    // rcu_periph_clock_enable(RCU_AF);
+
+    // /* Configure PC10 PC11(UART3 TX RX) as alternate function */
+    // gpio_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_10);
+    // gpio_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_11);
+}
+
+void rt_hw_wdt_drvinit(void)
+{
+
+}
+
+void rt_hw_drivers_init(void)
+{
+#ifdef RT_USING_PIN
+    rt_hw_gpio_drvinit();
+#endif
+#ifdef BSP_USING_UART
+    rt_hw_uart_drvinit();
+#endif
+#ifdef BSP_USING_SPI
+    rt_hw_spi_drvinit();
+#endif
+#ifdef BSP_USING_I2C
+    rt_hw_i2c_drvinit();
+#endif
+#ifdef BSP_USING_ADC
+    rt_hw_adc_drvinit();
+#endif
+#ifdef BSP_USING_WDT
+    rt_hw_wdt_drvinit();
+#endif
+#ifdef BSP_USING_RTC
+    rt_hw_rtc_drvinit();
+#endif
+#ifdef BSP_USING_HWTIMER
+    rt_hw_hwtimer_drvinit();
+#endif
+#ifdef BSP_USING_PWM
+    rt_hw_pwm_drvinit();
+#endif
+}
+
 /**
  * @brief Setup hardware board for rt-thread
  *
@@ -47,6 +166,9 @@ void rt_hw_board_init(void)
 
     _init(); // __libc_init_array is not used in RT-Thread
 
+    /* Board hardware drivers initialization */
+    rt_hw_drivers_init();
+
     /* USART driver initialization is open by default */
 #ifdef RT_USING_SERIAL
     rt_hw_usart_init();
@@ -61,6 +183,7 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
+
 }
 
 /******************** end of file *******************/

bsp/nuclei/gd32vf103_rvstar/rtconfig.h

@@ -52,7 +52,7 @@
 
 #define RT_USING_COMPONENTS_INIT
 #define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_STACK_SIZE 1024
 #define RT_MAIN_THREAD_PRIORITY 10
 
 /* C++ features */
@@ -67,7 +67,7 @@
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
 #define FINSH_THREAD_PRIORITY 20
-#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_THREAD_STACK_SIZE 2048
 #define FINSH_CMD_SIZE 80
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
@@ -75,19 +75,15 @@
 
 /* Device virtual file system */
 
-#define RT_USING_DFS
-#define DFS_USING_WORKDIR
-#define DFS_FILESYSTEMS_MAX 2
-#define DFS_FILESYSTEM_TYPES_MAX 2
-#define DFS_FD_MAX 16
-#define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 
@@ -97,7 +93,6 @@
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
-#define RT_USING_POSIX
 
 /* Network */
 
@@ -153,6 +148,9 @@
 /* peripheral libraries and drivers */
 
 #define PKG_USING_NUCLEI_SDK
+
+/* !!!Nuclei SDK only works with Nuclei RISC-V Processor IP!!! */
+
 #define PKG_USING_NUCLEI_SDK_LATEST_VERSION
 
 /* miscellaneous packages */

bsp/nuclei/gd32vf103_rvstar/rtconfig.py

@@ -23,7 +23,6 @@ else:
 BUILD = 'debug'
 
 # Fixed configurations below
-NUCLEI_SDK_OPENOCD_CFG = "type in your config"
 NUCLEI_SDK_SOC = "gd32vf103"
 NUCLEI_SDK_BOARD = "gd32vf103v_rvstar"
 NUCLEI_SDK_DOWNLOAD = "flashxip"
@@ -46,13 +45,14 @@ if PLATFORM == 'gcc':
     CFLAGS  = ' -ffunction-sections -fdata-sections -fno-common '
     AFLAGS  = CFLAGS
     LFLAGS  = ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections '
-    LFLAGS += ' -Wl,-cref,-Map=rtthread.map'
+    LFLAGS  += ' -Wl,-cref,-Map=rtthread.map '
     LFLAGS  += ' -u _isatty -u _write -u _sbrk -u _read -u _close -u _fstat -u _lseek '
     CPATH   = ''
     LPATH   = ''
+    LIBS = ['stdc++']
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0 -ggdb'
+        CFLAGS += ' -O2 -Os -ggdb'
         AFLAGS += ' -ggdb'
     else:
         CFLAGS += ' -O2 -Os'
@@ -62,9 +62,9 @@ if PLATFORM == 'gcc':
 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
 POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
 
-def dist_handle(BSP_ROOT):
+def dist_handle(BSP_ROOT, dist_dir):
     import sys
     cwd_path = os.getcwd()
     sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
     from sdk_dist import dist_do_building
-    dist_do_building(BSP_ROOT)
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript

@@ -14,6 +14,28 @@ if GetDepend(['RT_USING_PIN']):
 if GetDepend(['RT_USING_SERIAL']):
     src += ['drv_usart.c']
 
+if GetDepend(['RT_USING_I2C']):
+    src += ['drv_i2c.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['drv_rtc.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+
 path =  [cwd]
 
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_adc.c

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-03     hqfang       the first version.
+ *
+ */
+#include "drv_adc.h"
+
+#ifdef BSP_USING_ADC
+
+#if !defined(BSP_USING_ADC0) && !defined(BSP_USING_ADC1)
+    #error "Please define at least one BSP_USING_ADCx"
+    /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable ADC */
+#endif
+
+
+static struct gd32_adc_config adc_config[] =
+{
+#ifdef BSP_USING_ADC0
+    {
+        "adc0",
+        ADC0,
+    },
+#endif
+#ifdef BSP_USING_ADC1
+    {
+        "adc1",
+        ADC1,
+    },
+#endif
+};
+
+static struct gd32_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])] = {0};
+
+static void gd32_adc_init(struct gd32_adc_config *config)
+{
+    RT_ASSERT(config != RT_NULL);
+    adc_deinit(config->adc_periph);
+
+    ADC_CTL0(config->adc_periph) &= ~(ADC_CTL0_SYNCM);
+    ADC_CTL0(config->adc_periph) |= ADC_MODE_FREE;
+
+    ADC_CTL1(config->adc_periph) |= ADC_CTL1_TSVREN;
+
+    adc_resolution_config(config->adc_periph, ADC_RESOLUTION_12B);
+    /* ADC contineous function enable */
+    adc_special_function_config(config->adc_periph, ADC_SCAN_MODE, ENABLE);
+    /* ADC data alignment config */
+    adc_data_alignment_config(config->adc_periph, ADC_DATAALIGN_RIGHT);
+    /* ADC channel length config */
+    adc_channel_length_config(config->adc_periph, ADC_REGULAR_CHANNEL, 1);
+    adc_external_trigger_source_config(config->adc_periph, ADC_REGULAR_CHANNEL, ADC0_1_EXTTRIG_REGULAR_NONE);
+
+    /* ADC enable */
+    adc_external_trigger_config(config->adc_periph, ADC_REGULAR_CHANNEL, ENABLE);
+    adc_enable(config->adc_periph);
+
+    adc_calibration_enable(config->adc_periph);
+}
+
+static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    if (channel > ADC_CHANNEL_17)
+    {
+        return RT_EINVAL;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    struct gd32_adc_config *config;
+    RT_ASSERT(device != RT_NULL);
+
+    if (channel > ADC_CHANNEL_17)
+    {
+        return RT_EINVAL;
+    }
+    config = (struct gd32_adc_config *)(device->parent.user_data);
+
+    if (channel > ADC_CHANNEL_15)
+    {
+        adc_regular_channel_config(config->adc_periph, 0, channel, ADC_SAMPLETIME_239POINT5);
+    }
+    else
+    {
+        adc_regular_channel_config(config->adc_periph, 0, channel, ADC_SAMPLETIME_55POINT5);
+    }
+    adc_software_trigger_enable(config->adc_periph, ADC_REGULAR_CHANNEL);
+
+    while (SET != adc_flag_get(config->adc_periph, ADC_FLAG_EOC));
+    adc_flag_clear(config->adc_periph, ADC_FLAG_EOC);
+
+    *value = ADC_RDATA(config->adc_periph);
+
+    return RT_EOK;
+}
+
+static struct rt_adc_ops gd32_adc_ops =
+{
+    .enabled = gd32_adc_enabled,
+    .convert = gd32_adc_convert,
+};
+
+int rt_hw_adc_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+#if defined(BSP_USING_ADC0)
+    rcu_periph_clock_enable(RCU_ADC0);
+#endif
+#if defined(BSP_USING_ADC1)
+    rcu_periph_clock_enable(RCU_ADC1);
+#endif
+
+    rcu_adc_clock_config(RCU_CKADC_CKAPB2_DIV8);
+
+    for (i = 0; i < sizeof(adc_obj) / sizeof(adc_obj[0]); i++)
+    {
+        adc_obj[i].config = &adc_config[i];
+        gd32_adc_init(&adc_config[i]);
+        rt_hw_adc_register(&adc_obj[i].adc_device, \
+                           adc_obj[i].config->name, &gd32_adc_ops, adc_obj[i].config);
+    }
+
+    return result;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_adc_init);
+
+#endif /* BSP_USING_ADC */
+

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_adc.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-03     hqfang       first implementation.
+ */
+
+#ifndef __DRV_ADC__
+#define __DRV_ADC__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_adc_config
+{
+    const char *name;
+    rt_uint32_t adc_periph;
+};
+
+struct gd32_adc
+{
+    struct rt_adc_device adc_device;
+    struct gd32_adc_config *config;
+};
+
+#endif

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c

@@ -337,8 +337,11 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
     const struct pin_irq_map *irqmap;
     rt_base_t level;
     rt_int32_t irqindex = -1;
+    rt_uint8_t portsrc = 0, pinsrc = 0;
     exti_trig_type_enum trigger_mode;
 
+    portsrc = pin >> 4;
+    pinsrc = pin % 16;
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -378,8 +381,9 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
             rt_hw_interrupt_enable(level);
             return RT_EINVAL;
         }
+
         /* connect EXTI line to  GPIO pin */
-        gpio_exti_source_select(index->gpio, index->pin);
+        gpio_exti_source_select(portsrc, pinsrc);
 
         /* configure EXTI line */
         exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
@@ -391,6 +395,8 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         ECLIC_EnableIRQ(irqmap->irqno);
         pin_irq_enable_mask |= irqmap->pinbit;
 
+        exti_interrupt_enable((exti_line_enum)(index->pin));
+
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
@@ -405,6 +411,7 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
             if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
             {
                 ECLIC_DisableIRQ(irqmap->irqno);
+                exti_interrupt_disable((exti_line_enum)(index->pin));
             }
         }
         else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
@@ -412,11 +419,13 @@ static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
             if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
             {
                 ECLIC_DisableIRQ(irqmap->irqno);
+                exti_interrupt_disable((exti_line_enum)(index->pin));
             }
         }
         else
         {
             ECLIC_DisableIRQ(irqmap->irqno);
+            exti_interrupt_disable((exti_line_enum)(index->pin));
         }
     }
     else
@@ -515,6 +524,7 @@ int rt_hw_pin_init(void)
     rcu_periph_clock_enable(RCU_AF);
     return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
 }
-INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+INIT_DEVICE_EXPORT(rt_hw_pin_init);
 
 #endif /* RT_USING_PIN */

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_hwtimer.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2029-05-06     hqfang       first implementation.
+ */
+
+#ifndef __DRV_HWTIMER__
+#define __DRV_HWTIMER__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_hwtimer_config
+{
+    const char *name;
+    rt_uint32_t timer_periph;
+    IRQn_Type irqn;
+};
+
+struct gd32_hwtimer
+{
+    rt_hwtimer_t time_device;
+    struct gd32_hwtimer_config *config;
+};
+
+#endif

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_i2c.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-27     hqfang       first implementation.
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_i2c_config
+{
+    const char *name;
+    rt_uint32_t i2c_periph;
+    rt_uint32_t speed;
+};
+
+struct gd32_i2c
+{
+    struct rt_i2c_bus_device bus;
+    struct gd32_i2c_config *config;
+};
+
+#endif

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_pwm.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2029-06-02     hqfang       first implementation.
+ */
+
+#ifndef __DRV_PWM__
+#define __DRV_PWM__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_pwm_config
+{
+    const char *name;
+    rt_uint32_t periph;
+    rt_uint32_t period;
+    rt_uint32_t pulse;
+};
+
+struct gd32_pwm
+{
+    struct rt_device_pwm pwm_device;
+    struct gd32_pwm_config *config;
+};
+
+#endif

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_rtc.c

@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-08     hqfang       first implementation.
+ */
+
+#include "drv_rtc.h"
+
+#ifdef BSP_USING_RTC
+
+static time_t get_timestamp(void)
+{
+    return (time_t)rtc_counter_get();
+}
+
+static int set_timestamp(time_t timestamp)
+{
+    /* wait until last write operation on RTC registers has finished */
+    rtc_lwoff_wait();
+    /* change the current time */
+    rtc_counter_set((uint32_t)timestamp);
+    /* wait until last write operation on RTC registers has finished */
+    rtc_lwoff_wait();
+    return RT_EOK;
+}
+
+static void rtc_configuration(void)
+{
+    /* enable PMU and BKPI clocks */
+    rcu_periph_clock_enable(RCU_BKPI);
+    rcu_periph_clock_enable(RCU_PMU);
+    /* allow access to BKP domain */
+    pmu_backup_write_enable();
+
+    /* reset backup domain */
+    bkp_deinit();
+
+    /* enable LXTAL */
+    rcu_osci_on(RCU_LXTAL);
+    /* wait till LXTAL is ready */
+    rcu_osci_stab_wait(RCU_LXTAL);
+
+    /* select RCU_LXTAL as RTC clock source */
+    rcu_rtc_clock_config(RCU_RTCSRC_LXTAL);
+
+    /* enable RTC Clock */
+    rcu_periph_clock_enable(RCU_RTC);
+
+    /* wait for RTC registers synchronization */
+    rtc_register_sync_wait();
+
+    /* wait until last write operation on RTC registers has finished */
+    rtc_lwoff_wait();
+
+    /* wait until last write operation on RTC registers has finished */
+    rtc_lwoff_wait();
+
+    /* set RTC prescaler: set RTC period to 1s */
+    rtc_prescaler_set(32767);
+
+    /* wait until last write operation on RTC registers has finished */
+    rtc_lwoff_wait();
+}
+
+static rt_err_t gd32_rtc_init(rt_device_t dev)
+{
+    if (bkp_data_read(BKP_DATA_0) != 0xA5A5)
+    {
+        rtc_configuration();
+        bkp_data_write(BKP_DATA_0, 0xA5A5);
+    }
+    else
+    {
+        /* allow access to BKP domain */
+        rcu_periph_clock_enable(RCU_PMU);
+        pmu_backup_write_enable();
+
+        /* wait for RTC registers synchronization */
+        rtc_register_sync_wait();
+        /* wait until last write operation on RTC registers has finished */
+        rtc_lwoff_wait();
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_rtc_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t gd32_rtc_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t gd32_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    return RT_EOK;
+}
+
+static rt_size_t gd32_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    return RT_EOK;
+}
+
+static rt_err_t gd32_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+    {
+        *(uint32_t *)args = get_timestamp();
+    }
+    break;
+
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+    {
+        set_timestamp(*(time_t *)args);
+    }
+    break;
+
+    default:
+        return RT_EINVAL;
+    }
+
+    return RT_EOK;
+}
+
+static struct rt_device rtc_device =
+{
+    .type    = RT_Device_Class_RTC,
+    .init    = gd32_rtc_init,
+    .open    = gd32_rtc_open,
+    .close   = gd32_rtc_close,
+    .read    = gd32_rtc_read,
+    .write   = gd32_rtc_write,
+    .control = gd32_rtc_control,
+};
+
+int rt_hw_rtc_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+    ret = rt_device_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR);
+
+    rt_device_open(&rtc_device, RT_DEVICE_OFLAG_RDWR);
+
+    return RT_EOK;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+
+#endif /* BSP_USING_RTC */

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_rtc.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-08     hqfang       first implementation.
+ */
+
+#ifndef DRV_RTC_H__
+#define DRV_RTC_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+#endif

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_spi.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2029-04-29     hqfang       first implementation.
+ */
+
+#ifndef __DRV_SPI__
+#define __DRV_SPI__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_spi_config
+{
+    const char *name;
+    rt_uint32_t spi_periph;
+};
+
+struct gd32_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+struct gd32_spi
+{
+    struct rt_spi_bus bus;
+    struct gd32_spi_config *config;
+};
+
+int rt_hw_spi_init(void);
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin);
+
+#endif

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c

@@ -16,7 +16,7 @@
 #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
     && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4)
     #error "Please define at least one BSP_USING_UARTx"
-    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+    /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */
 #endif
 
 enum
@@ -64,8 +64,8 @@ static struct gd32_uart_config uart_config[] =
 #ifdef BSP_USING_UART3
     {
         "uart3",
-        USART3,
-        USART3_IRQn,
+        UART3,
+        UART3_IRQn,
     },
 #endif
 #ifdef BSP_USING_UART4
@@ -137,7 +137,7 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial,
         break;
     }
     usart_hardware_flow_rts_config(usart->uart_base, USART_RTS_DISABLE);
-    usart_hardware_flow_cts_config(usart->uart_base, USART_RTS_DISABLE);
+    usart_hardware_flow_cts_config(usart->uart_base, USART_CTS_DISABLE);
     usart_receive_config(usart->uart_base, USART_RECEIVE_ENABLE);
     usart_transmit_config(usart->uart_base, USART_TRANSMIT_ENABLE);
     usart_enable(usart->uart_base);
@@ -320,6 +320,22 @@ int rt_hw_usart_init(void)
     rt_size_t obj_num;
     int index;
 
+#ifdef BSP_USING_UART0
+    rcu_periph_clock_enable(RCU_USART0);
+#endif
+#ifdef BSP_USING_UART1
+    rcu_periph_clock_enable(RCU_USART1);
+#endif
+#ifdef BSP_USING_UART2
+    rcu_periph_clock_enable(RCU_USART2);
+#endif
+#ifdef BSP_USING_UART3
+    rcu_periph_clock_enable(RCU_UART3);
+#endif
+#ifdef BSP_USING_UART4
+    rcu_periph_clock_enable(RCU_UART4);
+#endif
+
     obj_num = sizeof(uart_obj) / sizeof(struct gd32_uart);
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     rt_err_t result = 0;

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h

@@ -25,8 +25,8 @@ struct gd32_uart_config
 /* gd32 uart dirver class */
 struct gd32_uart
 {
-    struct gd32_uart_config *config;
     struct rt_serial_device serial;
+    struct gd32_uart_config *config;
 };
 
 int rt_hw_usart_init(void);

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_wdt.c

@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-08     hqfang       the first version.
+ *
+ */
+#include "drv_wdt.h"
+
+#ifdef BSP_USING_WDT
+
+
+static rt_err_t gd32_wdog_close(rt_watchdog_t *wdt)
+{
+    rt_uint32_t level;
+
+    level = rt_hw_interrupt_disable();
+    rcu_osci_off(RCU_IRC40K);
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag)
+{
+    rt_uint32_t level;
+
+    level = rt_hw_interrupt_disable();
+    /* enable IRC40K */
+    rcu_osci_on(RCU_IRC40K);
+    /* wait till IRC40K is ready */
+    while (SUCCESS != rcu_osci_stab_wait(RCU_IRC40K));
+    fwdgt_counter_reload();
+    fwdgt_enable();
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_wdog_init(rt_watchdog_t *wdt)
+{
+    /* confiure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */
+    fwdgt_config(FWDGT_RLD_RLD, FWDGT_PSC_DIV256);
+    fwdgt_enable();
+    return RT_EOK;
+}
+
+static rt_err_t gd32_wdog_refresh(rt_watchdog_t *wdt)
+{
+    rt_uint32_t level;
+
+    level = rt_hw_interrupt_disable();
+    fwdgt_counter_reload();
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+/**
+ * @function control wdog
+ *
+ * @param
+ *    wdt  whick wdog used
+ *    cmd  control wdog options
+ *    args argument of conrtol
+ * @retval rt_err_t the status of control result
+ *
+ *
+ */
+#define WDT_RELOAD_SECOND       ((FWDGT_RLD & FWDGT_RLD_RLD) / 156)
+static rt_err_t gd32_wdog_control(rt_watchdog_t *wdt, int cmd, void *args)
+{
+    RT_ASSERT(wdt != NULL);
+
+    uint16_t reload_value;
+    static uint16_t wdt_started = 0;
+    static rt_tick_t last_tick = 0;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+    {
+        *(uint16_t *)args = WDT_RELOAD_SECOND;
+    }
+    break;
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+    {
+        RT_ASSERT(*(uint16_t *)args != 0);
+        reload_value = *(uint16_t *)args;
+        // 6.4ms 1 tick, 1s -> 1000 / 6.4 = 625 / 4 ticks
+        reload_value = ((uint32_t)reload_value * 625) / 4;
+        fwdgt_write_enable();
+        while (FWDGT_STAT & FWDGT_STAT_RUD);
+        FWDGT_RLD = FWDGT_RLD_RLD & reload_value;
+        fwdgt_write_disable();
+    }
+    break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+        *(uint16_t *)args = WDT_RELOAD_SECOND - \
+                            (rt_tick_get() - last_tick) / RT_TICK_PER_SECOND;
+
+        break;
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+    {
+        last_tick = rt_tick_get();
+        gd32_wdog_refresh(wdt);
+    }
+    break;
+    case RT_DEVICE_CTRL_WDT_START:
+    {
+        gd32_wdog_open(wdt, *(rt_uint32_t *)args);
+        last_tick = rt_tick_get();
+        wdt_started = 1;
+        while (FWDGT_STAT & FWDGT_STAT_RUD);
+    }
+    break;
+    case RT_DEVICE_CTRL_WDT_STOP:
+    {
+        gd32_wdog_close(wdt);
+        wdt_started = 0;
+    }
+    break;
+    default:
+        return RT_EINVAL;
+    }
+
+    return RT_EOK;
+}
+
+static struct rt_watchdog_ops gd32_wdog_ops =
+{
+    .init = gd32_wdog_init,
+    .control = gd32_wdog_control,
+};
+
+static struct rt_watchdog_device gd32_wdt_device;
+
+int rt_hw_wdt_init(void)
+{
+    int result = RT_EOK;
+
+    rcu_osci_off(RCU_IRC40K);
+    gd32_wdt_device.ops = &gd32_wdog_ops;
+    result = rt_hw_watchdog_register(&gd32_wdt_device, "wdt", \
+                                     RT_DEVICE_FLAG_RDWR, (void *)FWDGT);
+
+    return result;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_wdt_init);
+
+#endif /* BSP_USING_WDT */
+

bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_wdt.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2029-06-08     hqfang       first implementation.
+ */
+
+#ifndef __DRV_WDT__
+#define __DRV_WDT__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+
+#endif

bsp/nuclei/tools/sdk_dist.py

@@ -5,11 +5,10 @@ cwd_path = os.getcwd()
 sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
 
 # BSP dist function
-def dist_do_building(BSP_ROOT):
+def dist_do_building(BSP_ROOT, dist_dir):
     from mkdist import bsp_copy_files
     import rtconfig
 
-    dist_dir  = os.path.join(BSP_ROOT, 'dist', os.path.basename(BSP_ROOT))
     library_dir  = os.path.join(dist_dir, 'libraries')
 
     print("=> copy nuclei bsp library")