mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-14 12:57:45 +08:00
add at91sam926x porting.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1364 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
luohui2320@gmail.com
Executable
+22
@@ -0,0 +1,22 @@
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import rtconfig
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Import('RTT_ROOT')
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from building import *
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src_bsp = ['application.c', 'startup.c', 'board.c']
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src_drv = ['console.c']
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if GetDepend('RT_USING_LED'):
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src_drv += ['led.c']
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#if GetDepend('RT_USING_DFS'):
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#src_drv += ['sdcard.c']
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if GetDepend('RT_USING_LWIP'):
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src_drv += ['macb.c']
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src = File(src_bsp + src_drv)
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CPPPATH = [RTT_ROOT + '/bsp/at91sam9260']
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group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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Executable
+37
@@ -0,0 +1,37 @@
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import os
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import sys
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import rtconfig
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-at91sam9260.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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if GetDepend('RT_USING_WEBSERVER'):
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objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
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if GetDepend('RT_USING_RTGUI'):
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objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
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# libc testsuite
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objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
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# build program
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env.Program(TARGET, objs)
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# end building
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EndBuilding(TARGET)
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Executable
+101
@@ -0,0 +1,101 @@
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/*
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||||
* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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||||
*
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||||
* The license and distribution terms for this file may be
|
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* found in the file LICENSE in this distribution or at
|
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* http://www.rt-thread.org/license/LICENSE
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||||
*
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||||
* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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/**
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* @addtogroup at91sam9260
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*/
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/*@{*/
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#include <rtthread.h>
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#ifdef RT_USING_LED
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#include "led.h"
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#endif
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#ifdef RT_USING_LED
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void rt_led_thread_entry(void* parameter)
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{
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rt_uint8_t cnt = 0;
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led_init();
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while(1)
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{
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/* light on leds for one second */
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rt_thread_delay(40);
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cnt++;
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if (cnt&0x01)
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led_on(1);
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else
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led_off(1);
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if (cnt&0x02)
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led_on(2);
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else
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led_off(2);
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if (cnt&0x04)
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led_on(3);
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else
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led_off(3);
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}
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}
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#endif
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int rt_application_init()
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{
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#ifdef RT_USING_LED
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rt_thread_t led_thread;
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#if (RT_THREAD_PRIORITY_MAX == 32)
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led_thread = rt_thread_create("led",
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rt_led_thread_entry, RT_NULL,
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512, 20, 20);
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#else
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led_thread = rt_thread_create("led",
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rt_led_thread_entry, RT_NULL,
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512, 200, 20);
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#endif
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if(led_thread != RT_NULL)
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rt_thread_startup(led_thread);
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#endif
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return 0;
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}
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/* NFSv3 Initialization */
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||||
#if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS)
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#include <dfs_nfs.h>
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void nfs_start(void)
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||||
{
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||||
nfs_init();
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||||
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if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
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{
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rt_kprintf("NFSv3 File System initialized!\n");
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||||
}
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||||
else
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rt_kprintf("NFSv3 File System initialzation failed!\n");
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||||
}
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#include "finsh.h"
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FINSH_FUNCTION_EXPORT(nfs_start, start net filesystem);
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#endif
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/*@}*/
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Executable
+85
@@ -0,0 +1,85 @@
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_start)
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SECTIONS
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||||
{
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||||
. = 0x20000000;
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||||
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||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.init)
|
||||
*(.text)
|
||||
*(.gnu.linkonce.t*)
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||||
|
||||
/* section information for finsh shell */
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||||
. = ALIGN(4);
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||||
__fsymtab_start = .;
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||||
KEEP(*(FSymTab))
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||||
__fsymtab_end = .;
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||||
. = ALIGN(4);
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||||
__vsymtab_start = .;
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||||
KEEP(*(VSymTab))
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||||
__vsymtab_end = .;
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||||
. = ALIGN(4);
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||||
|
||||
/* section information for modules */
|
||||
. = ALIGN(4);
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||||
__rtmsymtab_start = .;
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KEEP(*(RTMSymTab))
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||||
__rtmsymtab_end = .;
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||||
}
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||||
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. = ALIGN(4);
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.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
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. = ALIGN(4);
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.ctors :
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||||
{
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||||
PROVIDE(__ctors_start__ = .);
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KEEP(*(SORT(.ctors.*)))
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KEEP(*(.ctors))
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PROVIDE(__ctors_end__ = .);
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}
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||||
.dtors :
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||||
{
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||||
PROVIDE(__dtors_start__ = .);
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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||||
PROVIDE(__dtors_end__ = .);
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}
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||||
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. = ALIGN(4);
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.data :
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||||
{
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||||
*(.data)
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||||
*(.data.*)
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||||
*(.gnu.linkonce.d*)
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||||
}
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||||
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||||
. = ALIGN(4);
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||||
.nobss : { *(.nobss) }
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||||
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||||
. = 0x20300000;
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||||
. = ALIGN(4);
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||||
__bss_start = .;
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||||
.bss : { *(.bss) }
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||||
__bss_end = .;
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||||
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||||
/* stabs debugging sections. */
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||||
.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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||||
.stab.excl 0 : { *(.stab.excl) }
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||||
.stab.exclstr 0 : { *(.stab.exclstr) }
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||||
.stab.index 0 : { *(.stab.index) }
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||||
.stab.indexstr 0 : { *(.stab.indexstr) }
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||||
.comment 0 : { *(.comment) }
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||||
.debug_abbrev 0 : { *(.debug_abbrev) }
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||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
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||||
.debug_aranges 0 : { *(.debug_aranges) }
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||||
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_end = .;
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}
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Executable
+247
File diff suppressed because it is too large
Load Diff
Executable
+24
@@ -0,0 +1,24 @@
|
||||
/*
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||||
* File : board.h
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||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety add board.h to this bsp
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||||
*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <at91sam926x.h>
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#include <serial.h>
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void rt_hw_board_init(void);
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//void rt_hw_sdcard_init(void);
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#endif
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Executable
+180
@@ -0,0 +1,180 @@
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#include <rtthread.h>
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#include <serial.h>
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#define RT_CONSOLE_WIDTH 240
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#define RT_CONSOLE_HEIGHT 320
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#define RT_CONSOLE_FONT_WIDTH 8
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#define RT_CONSOLE_FONT_HEIGHT 16
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#define RT_CONSOLE_COL (RT_CONSOLE_WIDTH/RT_CONSOLE_FONT_WIDTH)
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#define RT_CONSOLE_ROW (RT_CONSOLE_HEIGHT/RT_CONSOLE_FONT_HEIGHT)
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#define RT_CONSOLE_TAB 4
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#define RT_CONSOLE_FOREPIXEL (0x001f)
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extern struct serial_device uart0;
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struct rt_console
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{
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rt_uint8_t* video_ptr;
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rt_uint8_t* font_ptr;
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||||
/* bpp and pixel of width */
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rt_uint8_t bpp;
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rt_uint32_t pitch;
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/* current cursor */
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rt_uint8_t current_col;
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||||
rt_uint8_t current_row;
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};
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struct rt_console console;
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void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp);
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void rt_hw_console_newline(void);
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void rt_hw_console_putc(char c);
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void rt_hw_console_clear(void);
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||||
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||||
void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp)
|
||||
{
|
||||
rt_memset(&console, 0, sizeof(struct rt_console));
|
||||
|
||||
console.video_ptr = video_ptr;
|
||||
console.font_ptr = font_ptr;
|
||||
console.bpp = bpp;
|
||||
console.pitch = console.bpp * RT_CONSOLE_WIDTH;
|
||||
|
||||
rt_hw_console_clear();
|
||||
}
|
||||
|
||||
void rt_hw_console_putc(char c)
|
||||
{
|
||||
switch (c)
|
||||
{
|
||||
case 10:
|
||||
case 11:
|
||||
case 12:
|
||||
case 13:
|
||||
/* to next line */
|
||||
rt_hw_console_newline();
|
||||
console.current_col = 0;
|
||||
break;
|
||||
|
||||
case 9:
|
||||
console.current_col += RT_CONSOLE_TAB;
|
||||
break;
|
||||
|
||||
default:
|
||||
{
|
||||
rt_uint8_t* font_ptr;
|
||||
register rt_uint32_t cursor;
|
||||
register rt_uint32_t i, j;
|
||||
|
||||
if (console.current_col == RT_CONSOLE_COL)
|
||||
{
|
||||
rt_hw_console_newline();
|
||||
console.current_col = 0;
|
||||
|
||||
rt_hw_console_putc(c);
|
||||
return;
|
||||
}
|
||||
|
||||
font_ptr = console.font_ptr + c * RT_CONSOLE_FONT_HEIGHT;
|
||||
cursor = (console.current_row * RT_CONSOLE_FONT_HEIGHT) * console.pitch
|
||||
+ console.current_col * RT_CONSOLE_FONT_WIDTH * console.bpp;
|
||||
|
||||
for (i = 0; i < RT_CONSOLE_FONT_HEIGHT; i ++ )
|
||||
{
|
||||
for (j = 0; j < RT_CONSOLE_FONT_WIDTH; j ++)
|
||||
{
|
||||
if ( ((font_ptr[i] >> (7-j)) & 0x01) != 0 )
|
||||
{
|
||||
/* draw a pixel */
|
||||
rt_uint8_t *ptr = &(console.video_ptr[cursor + i * console.pitch + j * console.bpp]);
|
||||
switch(console.bpp)
|
||||
{
|
||||
case 1:
|
||||
*ptr = RT_CONSOLE_FOREPIXEL;
|
||||
break;
|
||||
case 2:
|
||||
*(rt_uint16_t*)ptr = RT_CONSOLE_FOREPIXEL;
|
||||
break;
|
||||
case 3:
|
||||
ptr[0] = RT_CONSOLE_FOREPIXEL & 0xff;
|
||||
ptr[1] = (RT_CONSOLE_FOREPIXEL >> 8) & 0xff;
|
||||
ptr[2] = (RT_CONSOLE_FOREPIXEL >> 16) & 0xff;
|
||||
break;
|
||||
case 4:
|
||||
*(rt_uint32_t*)ptr = RT_CONSOLE_FOREPIXEL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
console.current_col ++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_console_newline()
|
||||
{
|
||||
console.current_row ++;
|
||||
if (console.current_row >= RT_CONSOLE_ROW)
|
||||
{
|
||||
rt_uint32_t i;
|
||||
|
||||
/* scroll to next line */
|
||||
for (i = 0; i < RT_CONSOLE_ROW - 1; i ++)
|
||||
{
|
||||
rt_memcpy(console.video_ptr + i * RT_CONSOLE_FONT_HEIGHT * console.pitch,
|
||||
console.video_ptr + (i + 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch,
|
||||
RT_CONSOLE_FONT_HEIGHT * console.pitch);
|
||||
}
|
||||
|
||||
/* clear last line */
|
||||
rt_memset(console.video_ptr + (RT_CONSOLE_ROW - 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch,
|
||||
0,
|
||||
RT_CONSOLE_FONT_HEIGHT * console.pitch);
|
||||
|
||||
console.current_row = RT_CONSOLE_ROW - 1;
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_console_clear()
|
||||
{
|
||||
console.current_col = 0;
|
||||
console.current_row = 0;
|
||||
|
||||
rt_memset(console.video_ptr, 0, RT_CONSOLE_HEIGHT * console.pitch);
|
||||
}
|
||||
|
||||
/* write one character to serial, must not trigger interrupt */
|
||||
void rt_hw_serial_putc(const char c)
|
||||
{
|
||||
/*
|
||||
to be polite with serial console add a line feed
|
||||
to the carriage return character
|
||||
*/
|
||||
if (c=='\n')rt_hw_serial_putc('\r');
|
||||
|
||||
while (!(uart0.uart_device->USART_CSR & TXRDY));
|
||||
uart0.uart_device->USART_THR = (c & 0x1FF);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function is used by rt_kprintf to display a string on console.
|
||||
*
|
||||
* @param str the displayed string
|
||||
*/
|
||||
void rt_hw_console_output(const char* str)
|
||||
{
|
||||
while (*str)
|
||||
{
|
||||
rt_hw_serial_putc(*str++);
|
||||
}
|
||||
}
|
||||
|
||||
Executable
+63
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* File : led.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <at91sam926x.h>
|
||||
#include "led.h"
|
||||
|
||||
void led_init(void)
|
||||
{
|
||||
at91_sys_write(AT91_PIOC, (1<<8)|(1<<11)|(1<<6));
|
||||
at91_sys_write(AT91_PIOC+0x10, (1<<8)|(1<<11)|(1<<6));
|
||||
at91_sys_write(AT91_PIOC+0x64, (1<<8)|(1<<11)|(1<<6));
|
||||
at91_sys_write(AT91_PIOC+0x30, (1<<8)|(1<<11)|(1<<6));
|
||||
}
|
||||
|
||||
void led_on(int num)
|
||||
{
|
||||
switch(num)
|
||||
{
|
||||
case 1:
|
||||
at91_sys_write(AT91_PIOC+0x34, 1<<8);
|
||||
break;
|
||||
case 2:
|
||||
at91_sys_write(AT91_PIOC+0x34, 1<<11);
|
||||
break;
|
||||
case 3:
|
||||
at91_sys_write(AT91_PIOC+0x34, 1<<6);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void led_off(int num)
|
||||
{
|
||||
switch(num)
|
||||
{
|
||||
case 1:
|
||||
at91_sys_write(AT91_PIOC+0x30, 1<<8);
|
||||
break;
|
||||
case 2:
|
||||
at91_sys_write(AT91_PIOC+0x30, 1<<11);
|
||||
break;
|
||||
case 3:
|
||||
at91_sys_write(AT91_PIOC+0x30, 1<<6);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
//at91_sys_write(AT91_PIOC+0x30, 1<<8);
|
||||
}
|
||||
Executable
+8
@@ -0,0 +1,8 @@
|
||||
#ifndef __LED_H__
|
||||
#define __LED_H__
|
||||
|
||||
void led_init(void);
|
||||
void led_on(int num);
|
||||
void led_off(int num);
|
||||
|
||||
#endif
|
||||
Executable
+239
File diff suppressed because it is too large
Load Diff
Executable
+82
@@ -0,0 +1,82 @@
|
||||
|
||||
# toolchains options
|
||||
ARCH = 'arm'
|
||||
CPU = 'at91sam926x'
|
||||
TextBase = '0x20000000'
|
||||
|
||||
CROSS_TOOL = 'gcc'
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = '/opt/arm-2010q1/bin/'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = 'E:/Keil'
|
||||
#BUILD = 'debug'
|
||||
BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
#PREFIX = 'arm-none-linux-gnueabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'axf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=arm926ej-s'
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + ' -DTEXT_BASE=' + TextBase
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_at91sam9260.map,-cref,-u,_start -T at91sam9260_ram.ld' + ' -Ttext ' + TextBase
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --device DARMSS9'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --strict --info sizes --info totals --info unused --info veneers --list rtthread-at91sam9260.map --ro-base 0x20000000 --entry Entry_Point --first Entry_Point'
|
||||
|
||||
CFLAGS += ' -I"' + EXEC_PATH + '/ARM/RV31/INC"'
|
||||
LFLAGS += ' --libpath "' + EXEC_PATH + '/ARM/RV31/LIB"'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
|
||||
CFLAGS = ''
|
||||
AFLAGS = ''
|
||||
LFLAGS = ''
|
||||
Executable
+150
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* File : startup.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include <at91sam926x.h>
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
#endif
|
||||
|
||||
extern void rt_hw_interrupt_init(void);
|
||||
extern void rt_hw_board_init(void);
|
||||
extern void rt_serial_init(void);
|
||||
extern void rt_system_timer_init(void);
|
||||
extern void rt_system_scheduler_init(void);
|
||||
extern void rt_thread_idle_init(void);
|
||||
extern void rt_hw_cpu_icache_enable(void);
|
||||
extern void rt_show_version(void);
|
||||
extern void rt_system_heap_init(void*, void*);
|
||||
extern void rt_hw_finsh_init(void);
|
||||
extern void rt_application_init(void);
|
||||
|
||||
extern struct serial_device uart0;
|
||||
extern struct rt_device uart0_device;
|
||||
|
||||
/**
|
||||
* @addtogroup at91sam9260
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
#if defined(__CC_ARM)
|
||||
extern int Image$$ER_ZI$$ZI$$Base;
|
||||
extern int Image$$ER_ZI$$ZI$$Length;
|
||||
extern int Image$$ER_ZI$$ZI$$Limit;
|
||||
#elif (defined (__GNUC__))
|
||||
rt_uint8_t _irq_stack_start[1024];
|
||||
rt_uint8_t _fiq_stack_start[1024];
|
||||
rt_uint8_t _undefined_stack_start[512];
|
||||
rt_uint8_t _abort_stack_start[512];
|
||||
rt_uint8_t _svc_stack_start[1024] SECTION(".nobss");
|
||||
extern unsigned char __bss_start;
|
||||
extern unsigned char __bss_end;
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
extern void finsh_system_init(void);
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* This function will startup RT-Thread RTOS.
|
||||
*/
|
||||
void rtthread_startup(void)
|
||||
{
|
||||
rt_uint32_t UNUSED level;
|
||||
|
||||
/* disable interrupt first */
|
||||
level = rt_hw_interrupt_disable();
|
||||
/* enable cpu cache */
|
||||
rt_hw_cpu_icache_enable();
|
||||
rt_hw_cpu_dcache_enable();
|
||||
|
||||
/* initialize hardware interrupt */
|
||||
rt_hw_interrupt_init();
|
||||
|
||||
/* initialize board */
|
||||
rt_hw_board_init();
|
||||
|
||||
/* show version */
|
||||
rt_show_version();
|
||||
|
||||
/* initialize tick */
|
||||
rt_system_tick_init();
|
||||
|
||||
/* initialize kernel object */
|
||||
rt_system_object_init();
|
||||
|
||||
/* initialize timer system */
|
||||
rt_system_timer_init();
|
||||
|
||||
/* initialize heap memory system */
|
||||
#ifdef __CC_ARM
|
||||
rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x24000000);
|
||||
#else
|
||||
rt_system_heap_init((void*)&__bss_end, (void*)0x23f00000);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_MODULE
|
||||
/* initialize module system*/
|
||||
rt_system_module_init();
|
||||
#endif
|
||||
|
||||
/* initialize scheduler system */
|
||||
rt_system_scheduler_init();
|
||||
|
||||
#ifdef RT_USING_DEVICE
|
||||
/* register uart1 */
|
||||
rt_hw_serial_register(&uart0_device, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX,
|
||||
&uart0);
|
||||
|
||||
#ifdef RT_USING_DFS
|
||||
//rt_hw_sdcard_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_LWIP
|
||||
rt_hw_macb_init();
|
||||
#endif
|
||||
|
||||
/*init all registed devices */
|
||||
rt_device_init_all();
|
||||
#endif
|
||||
|
||||
/* initialize application */
|
||||
rt_application_init();
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
/* initialize finsh */
|
||||
finsh_system_init();
|
||||
#ifdef RT_USING_DEVICE
|
||||
finsh_set_device("uart0");
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* initialize system timer thread */
|
||||
rt_system_timer_thread_init();
|
||||
|
||||
/* initialize idle thread */
|
||||
rt_thread_idle_init();
|
||||
|
||||
/* start scheduler */
|
||||
rt_system_scheduler_start();
|
||||
|
||||
/* never reach here */
|
||||
return ;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
Executable
+61
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* File : at91_aic.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_AIC_H
|
||||
#define AT91_AIC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
|
||||
#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
|
||||
#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
|
||||
#define AT91_AIC_SRCTYPE_LOW (0 << 5)
|
||||
#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
|
||||
#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
|
||||
#define AT91_AIC_SRCTYPE_RISING (3 << 5)
|
||||
|
||||
#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
|
||||
#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
|
||||
#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
|
||||
#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
|
||||
#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
|
||||
|
||||
#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
|
||||
#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
|
||||
#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
|
||||
#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
|
||||
#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
|
||||
|
||||
#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
|
||||
#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
|
||||
#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
|
||||
#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
|
||||
#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
|
||||
#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
|
||||
#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
|
||||
#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
|
||||
#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
|
||||
|
||||
#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
|
||||
#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
|
||||
#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+57
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* File : at91_pio.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_PIO_H
|
||||
#define AT91_PIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PIO_PER 0x00 /* Enable Register */
|
||||
#define PIO_PDR 0x04 /* Disable Register */
|
||||
#define PIO_PSR 0x08 /* Status Register */
|
||||
#define PIO_OER 0x10 /* Output Enable Register */
|
||||
#define PIO_ODR 0x14 /* Output Disable Register */
|
||||
#define PIO_OSR 0x18 /* Output Status Register */
|
||||
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
|
||||
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
|
||||
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
|
||||
#define PIO_SODR 0x30 /* Set Output Data Register */
|
||||
#define PIO_CODR 0x34 /* Clear Output Data Register */
|
||||
#define PIO_ODSR 0x38 /* Output Data Status Register */
|
||||
#define PIO_PDSR 0x3c /* Pin Data Status Register */
|
||||
#define PIO_IER 0x40 /* Interrupt Enable Register */
|
||||
#define PIO_IDR 0x44 /* Interrupt Disable Register */
|
||||
#define PIO_IMR 0x48 /* Interrupt Mask Register */
|
||||
#define PIO_ISR 0x4c /* Interrupt Status Register */
|
||||
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
|
||||
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
|
||||
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
|
||||
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
|
||||
#define PIO_PUER 0x64 /* Pull-up Enable Register */
|
||||
#define PIO_PUSR 0x68 /* Pull-up Status Register */
|
||||
#define PIO_ASR 0x70 /* Peripheral A Select Register */
|
||||
#define PIO_BSR 0x74 /* Peripheral B Select Register */
|
||||
#define PIO_ABSR 0x78 /* AB Status Register */
|
||||
#define PIO_OWER 0xa0 /* Output Write Enable Register */
|
||||
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
|
||||
#define PIO_OWSR 0xa8 /* Output Write Status Register */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+40
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* File : at91_pit.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_PIT_H
|
||||
#define AT91_PIT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
|
||||
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
|
||||
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
|
||||
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
|
||||
|
||||
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
|
||||
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
|
||||
|
||||
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
|
||||
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
|
||||
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
|
||||
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+141
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* File : at91_pmc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_PMC_H
|
||||
#define AT91_PMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
|
||||
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
|
||||
|
||||
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
|
||||
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
|
||||
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
|
||||
#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */
|
||||
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
|
||||
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
|
||||
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
|
||||
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
|
||||
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
|
||||
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
|
||||
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
|
||||
|
||||
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
|
||||
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
|
||||
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
|
||||
|
||||
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
|
||||
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
|
||||
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
|
||||
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
|
||||
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
|
||||
|
||||
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
|
||||
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
|
||||
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
|
||||
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
|
||||
|
||||
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
|
||||
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
|
||||
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
|
||||
|
||||
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
|
||||
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
|
||||
#define AT91_PMC_DIV (0xff << 0) /* Divider */
|
||||
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
||||
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
|
||||
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
|
||||
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
|
||||
#define AT91_PMC_USBDIV_1 (0 << 28)
|
||||
#define AT91_PMC_USBDIV_2 (1 << 28)
|
||||
#define AT91_PMC_USBDIV_4 (2 << 28)
|
||||
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
|
||||
|
||||
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
|
||||
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
|
||||
#define AT91_PMC_CSS_SLOW (0 << 0)
|
||||
#define AT91_PMC_CSS_MAIN (1 << 0)
|
||||
#define AT91_PMC_CSS_PLLA (2 << 0)
|
||||
#define AT91_PMC_CSS_PLLB (3 << 0)
|
||||
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
|
||||
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
|
||||
#define AT91_PMC_PRES_1 (0 << 2)
|
||||
#define AT91_PMC_PRES_2 (1 << 2)
|
||||
#define AT91_PMC_PRES_4 (2 << 2)
|
||||
#define AT91_PMC_PRES_8 (3 << 2)
|
||||
#define AT91_PMC_PRES_16 (4 << 2)
|
||||
#define AT91_PMC_PRES_32 (5 << 2)
|
||||
#define AT91_PMC_PRES_64 (6 << 2)
|
||||
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
|
||||
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
|
||||
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
|
||||
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
|
||||
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
|
||||
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
|
||||
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
|
||||
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
|
||||
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
|
||||
#define AT91_PMC_PDIV_1 (0 << 12)
|
||||
#define AT91_PMC_PDIV_2 (1 << 12)
|
||||
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
|
||||
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
|
||||
#define AT91_PMC_PLLADIV2_ON (1 << 12)
|
||||
|
||||
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
|
||||
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
|
||||
#define AT91_PMC_USBS_PLLA (0 << 0)
|
||||
#define AT91_PMC_USBS_UPLL (1 << 0)
|
||||
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
|
||||
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
|
||||
#define AT91_PMC_CSSMCK_CSS (0 << 8)
|
||||
#define AT91_PMC_CSSMCK_MCK (1 << 8)
|
||||
|
||||
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
|
||||
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
|
||||
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
|
||||
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
|
||||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
||||
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */
|
||||
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
|
||||
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
|
||||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
|
||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
||||
|
||||
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+49
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* File : at91_rstc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_RSTC_H
|
||||
#define AT91_RSTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
|
||||
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
|
||||
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
|
||||
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
|
||||
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
|
||||
|
||||
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
|
||||
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
|
||||
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
|
||||
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
|
||||
#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
|
||||
#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
|
||||
#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
|
||||
#define AT91_RSTC_RSTTYP_USER (4 << 8)
|
||||
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
|
||||
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
|
||||
|
||||
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
|
||||
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
|
||||
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
|
||||
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+135
@@ -0,0 +1,135 @@
|
||||
/*
|
||||
* File : at91_serial.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_SERIAL_H
|
||||
#define AT91_SERIAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_US_CR 0x00 /* Control Register */
|
||||
#define AT91_US_RSTRX (1 << 2) /* Reset Receiver */
|
||||
#define AT91_US_RSTTX (1 << 3) /* Reset Transmitter */
|
||||
#define AT91_US_RXEN (1 << 4) /* Receiver Enable */
|
||||
#define AT91_US_RXDIS (1 << 5) /* Receiver Disable */
|
||||
#define AT91_US_TXEN (1 << 6) /* Transmitter Enable */
|
||||
#define AT91_US_TXDIS (1 << 7) /* Transmitter Disable */
|
||||
#define AT91_US_RSTSTA (1 << 8) /* Reset Status Bits */
|
||||
#define AT91_US_STTBRK (1 << 9) /* Start Break */
|
||||
#define AT91_US_STPBRK (1 << 10) /* Stop Break */
|
||||
#define AT91_US_STTTO (1 << 11) /* Start Time-out */
|
||||
#define AT91_US_SENDA (1 << 12) /* Send Address */
|
||||
#define AT91_US_RSTIT (1 << 13) /* Reset Iterations */
|
||||
#define AT91_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
|
||||
#define AT91_US_RETTO (1 << 15) /* Rearm Time-out */
|
||||
#define AT91_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
|
||||
#define AT91_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
|
||||
#define AT91_US_RTSEN (1 << 18) /* Request To Send Enable */
|
||||
#define AT91_US_RTSDIS (1 << 19) /* Request To Send Disable */
|
||||
|
||||
#define AT91_US_MR 0x04 /* Mode Register */
|
||||
#define AT91_US_USMODE (0xf << 0) /* Mode of the USART */
|
||||
#define AT91_US_USMODE_NORMAL 0
|
||||
#define AT91_US_USMODE_RS485 1
|
||||
#define AT91_US_USMODE_HWHS 2
|
||||
#define AT91_US_USMODE_MODEM 3
|
||||
#define AT91_US_USMODE_ISO7816_T0 4
|
||||
#define AT91_US_USMODE_ISO7816_T1 6
|
||||
#define AT91_US_USMODE_IRDA 8
|
||||
#define AT91_US_USCLKS (3 << 4) /* Clock Selection */
|
||||
#define AT91_US_USCLKS_MCK (0 << 4)
|
||||
#define AT91_US_USCLKS_MCK_DIV8 (1 << 4)
|
||||
#define AT91_US_USCLKS_SCK (3 << 4)
|
||||
#define AT91_US_CHRL (3 << 6) /* Character Length */
|
||||
#define AT91_US_CHRL_5 (0 << 6)
|
||||
#define AT91_US_CHRL_6 (1 << 6)
|
||||
#define AT91_US_CHRL_7 (2 << 6)
|
||||
#define AT91_US_CHRL_8 (3 << 6)
|
||||
#define AT91_US_SYNC (1 << 8) /* Synchronous Mode Select */
|
||||
#define AT91_US_PAR (7 << 9) /* Parity Type */
|
||||
#define AT91_US_PAR_EVEN (0 << 9)
|
||||
#define AT91_US_PAR_ODD (1 << 9)
|
||||
#define AT91_US_PAR_SPACE (2 << 9)
|
||||
#define AT91_US_PAR_MARK (3 << 9)
|
||||
#define AT91_US_PAR_NONE (4 << 9)
|
||||
#define AT91_US_PAR_MULTI_DROP (6 << 9)
|
||||
#define AT91_US_NBSTOP (3 << 12) /* Number of Stop Bits */
|
||||
#define AT91_US_NBSTOP_1 (0 << 12)
|
||||
#define AT91_US_NBSTOP_1_5 (1 << 12)
|
||||
#define AT91_US_NBSTOP_2 (2 << 12)
|
||||
#define AT91_US_CHMODE (3 << 14) /* Channel Mode */
|
||||
#define AT91_US_CHMODE_NORMAL (0 << 14)
|
||||
#define AT91_US_CHMODE_ECHO (1 << 14)
|
||||
#define AT91_US_CHMODE_LOC_LOOP (2 << 14)
|
||||
#define AT91_US_CHMODE_REM_LOOP (3 << 14)
|
||||
#define AT91_US_MSBF (1 << 16) /* Bit Order */
|
||||
#define AT91_US_MODE9 (1 << 17) /* 9-bit Character Length */
|
||||
#define AT91_US_CLKO (1 << 18) /* Clock Output Select */
|
||||
#define AT91_US_OVER (1 << 19) /* Oversampling Mode */
|
||||
#define AT91_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
|
||||
#define AT91_US_DSNACK (1 << 21) /* Disable Successive NACK */
|
||||
#define AT91_US_MAX_ITER (7 << 24) /* Max Iterations */
|
||||
#define AT91_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
|
||||
|
||||
#define AT91_US_IER 0x08 /* Interrupt Enable Register */
|
||||
#define AT91_US_RXRDY (1 << 0) /* Receiver Ready */
|
||||
#define AT91_US_TXRDY (1 << 1) /* Transmitter Ready */
|
||||
#define AT91_US_RXBRK (1 << 2) /* Break Received / End of Break */
|
||||
#define AT91_US_ENDRX (1 << 3) /* End of Receiver Transfer */
|
||||
#define AT91_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
|
||||
#define AT91_US_OVRE (1 << 5) /* Overrun Error */
|
||||
#define AT91_US_FRAME (1 << 6) /* Framing Error */
|
||||
#define AT91_US_PARE (1 << 7) /* Parity Error */
|
||||
#define AT91_US_TIMEOUT (1 << 8) /* Receiver Time-out */
|
||||
#define AT91_US_TXEMPTY (1 << 9) /* Transmitter Empty */
|
||||
#define AT91_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
|
||||
#define AT91_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
|
||||
#define AT91_US_RXBUFF (1 << 12) /* Reception Buffer Full */
|
||||
#define AT91_US_NACK (1 << 13) /* Non Acknowledge */
|
||||
#define AT91_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
|
||||
#define AT91_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
|
||||
#define AT91_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
|
||||
#define AT91_US_CTSIC (1 << 19) /* Clear to Send Input Change */
|
||||
#define AT91_US_RI (1 << 20) /* RI */
|
||||
#define AT91_US_DSR (1 << 21) /* DSR */
|
||||
#define AT91_US_DCD (1 << 22) /* DCD */
|
||||
#define AT91_US_CTS (1 << 23) /* CTS */
|
||||
|
||||
#define AT91_US_IDR 0x0c /* Interrupt Disable Register */
|
||||
#define AT91_US_IMR 0x10 /* Interrupt Mask Register */
|
||||
#define AT91_US_CSR 0x14 /* Channel Status Register */
|
||||
#define AT91_US_RHR 0x18 /* Receiver Holding Register */
|
||||
#define AT91_US_THR 0x1c /* Transmitter Holding Register */
|
||||
#define AT91_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
|
||||
|
||||
#define AT91_US_BRGR 0x20 /* Baud Rate Generator Register */
|
||||
#define AT91_US_CD (0xffff << 0) /* Clock Divider */
|
||||
|
||||
#define AT91_US_RTOR 0x24 /* Receiver Time-out Register */
|
||||
#define AT91_US_TO (0xffff << 0) /* Time-out Value */
|
||||
|
||||
#define AT91_US_TTGR 0x28 /* Transmitter Timeguard Register */
|
||||
#define AT91_US_TG (0xff << 0) /* Timeguard Value */
|
||||
|
||||
#define AT91_US_FIDI 0x40 /* FI DI Ratio Register */
|
||||
#define AT91_US_NER 0x44 /* Number of Errors Register */
|
||||
#define AT91_US_IF 0x4c /* IrDA Filter Register */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+46
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* File : at91_shdwc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_SHDWC_H
|
||||
#define AT91_SHDWC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
|
||||
#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
|
||||
#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
|
||||
|
||||
#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
|
||||
#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
|
||||
#define AT91_SHDW_WKMODE0_NONE 0
|
||||
#define AT91_SHDW_WKMODE0_HIGH 1
|
||||
#define AT91_SHDW_WKMODE0_LOW 2
|
||||
#define AT91_SHDW_WKMODE0_ANYLEVEL 3
|
||||
#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
|
||||
#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
|
||||
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
|
||||
|
||||
#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
|
||||
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
|
||||
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
|
||||
#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+154
@@ -0,0 +1,154 @@
|
||||
/*
|
||||
* File : at91_tc.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91_TC_H
|
||||
#define AT91_TC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
|
||||
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
|
||||
|
||||
#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
|
||||
#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
|
||||
#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
|
||||
#define AT91_TC_TC0XC0S_NONE (1 << 0)
|
||||
#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
|
||||
#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
|
||||
#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
|
||||
#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
|
||||
#define AT91_TC_TC1XC1S_NONE (1 << 2)
|
||||
#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
|
||||
#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
|
||||
#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
|
||||
#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
|
||||
#define AT91_TC_TC2XC2S_NONE (1 << 4)
|
||||
#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
|
||||
#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
|
||||
|
||||
|
||||
#define AT91_TC_CCR 0x00 /* Channel Control Register */
|
||||
#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
|
||||
#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
|
||||
#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
|
||||
|
||||
#define AT91_TC_CMR 0x04 /* Channel Mode Register */
|
||||
#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
|
||||
#define AT91_TC_TIMER_CLOCK1 (0 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK2 (1 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK3 (2 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK4 (3 << 0)
|
||||
#define AT91_TC_TIMER_CLOCK5 (4 << 0)
|
||||
#define AT91_TC_XC0 (5 << 0)
|
||||
#define AT91_TC_XC1 (6 << 0)
|
||||
#define AT91_TC_XC2 (7 << 0)
|
||||
#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
|
||||
#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
|
||||
#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
|
||||
#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
|
||||
#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
|
||||
#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
|
||||
#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
|
||||
#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
|
||||
#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
|
||||
#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
|
||||
|
||||
#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
|
||||
#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
|
||||
#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
|
||||
#define AT91_TC_EEVTEDG_NONE (0 << 8)
|
||||
#define AT91_TC_EEVTEDG_RISING (1 << 8)
|
||||
#define AT91_TC_EEVTEDG_FALLING (2 << 8)
|
||||
#define AT91_TC_EEVTEDG_BOTH (3 << 8)
|
||||
#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
|
||||
#define AT91_TC_EEVT_TIOB (0 << 10)
|
||||
#define AT91_TC_EEVT_XC0 (1 << 10)
|
||||
#define AT91_TC_EEVT_XC1 (2 << 10)
|
||||
#define AT91_TC_EEVT_XC2 (3 << 10)
|
||||
#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
|
||||
#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
|
||||
#define AT91_TC_WAVESEL_UP (0 << 13)
|
||||
#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
|
||||
#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
|
||||
#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
|
||||
#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
|
||||
#define AT91_TC_ACPA_NONE (0 << 16)
|
||||
#define AT91_TC_ACPA_SET (1 << 16)
|
||||
#define AT91_TC_ACPA_CLEAR (2 << 16)
|
||||
#define AT91_TC_ACPA_TOGGLE (3 << 16)
|
||||
#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
|
||||
#define AT91_TC_ACPC_NONE (0 << 18)
|
||||
#define AT91_TC_ACPC_SET (1 << 18)
|
||||
#define AT91_TC_ACPC_CLEAR (2 << 18)
|
||||
#define AT91_TC_ACPC_TOGGLE (3 << 18)
|
||||
#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
|
||||
#define AT91_TC_AEEVT_NONE (0 << 20)
|
||||
#define AT91_TC_AEEVT_SET (1 << 20)
|
||||
#define AT91_TC_AEEVT_CLEAR (2 << 20)
|
||||
#define AT91_TC_AEEVT_TOGGLE (3 << 20)
|
||||
#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
|
||||
#define AT91_TC_ASWTRG_NONE (0 << 22)
|
||||
#define AT91_TC_ASWTRG_SET (1 << 22)
|
||||
#define AT91_TC_ASWTRG_CLEAR (2 << 22)
|
||||
#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
|
||||
#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
|
||||
#define AT91_TC_BCPB_NONE (0 << 24)
|
||||
#define AT91_TC_BCPB_SET (1 << 24)
|
||||
#define AT91_TC_BCPB_CLEAR (2 << 24)
|
||||
#define AT91_TC_BCPB_TOGGLE (3 << 24)
|
||||
#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
|
||||
#define AT91_TC_BCPC_NONE (0 << 26)
|
||||
#define AT91_TC_BCPC_SET (1 << 26)
|
||||
#define AT91_TC_BCPC_CLEAR (2 << 26)
|
||||
#define AT91_TC_BCPC_TOGGLE (3 << 26)
|
||||
#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
|
||||
#define AT91_TC_BEEVT_NONE (0 << 28)
|
||||
#define AT91_TC_BEEVT_SET (1 << 28)
|
||||
#define AT91_TC_BEEVT_CLEAR (2 << 28)
|
||||
#define AT91_TC_BEEVT_TOGGLE (3 << 28)
|
||||
#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
|
||||
#define AT91_TC_BSWTRG_NONE (0 << 30)
|
||||
#define AT91_TC_BSWTRG_SET (1 << 30)
|
||||
#define AT91_TC_BSWTRG_CLEAR (2 << 30)
|
||||
#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
|
||||
|
||||
#define AT91_TC_CV 0x10 /* Counter Value */
|
||||
#define AT91_TC_RA 0x14 /* Register A */
|
||||
#define AT91_TC_RB 0x18 /* Register B */
|
||||
#define AT91_TC_RC 0x1c /* Register C */
|
||||
|
||||
#define AT91_TC_SR 0x20 /* Status Register */
|
||||
#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
|
||||
#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
|
||||
#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
|
||||
#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
|
||||
#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
|
||||
#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
|
||||
#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
|
||||
#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
|
||||
#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
|
||||
#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
|
||||
#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
|
||||
|
||||
#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
|
||||
#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
|
||||
#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+89
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* File : at91sam9260_matrix.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9260_MATRIX_H
|
||||
#define AT91SAM9260_MATRIX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+209
File diff suppressed because it is too large
Load Diff
Executable
+100
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* File : context.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety copy from mini2440
|
||||
*/
|
||||
|
||||
/*!
|
||||
* \addtogroup AT91SAM926X
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#define NOINT 0xc0
|
||||
|
||||
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable();
|
||||
*/
|
||||
.globl rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
mrs r0, cpsr
|
||||
orr r1, r0, #NOINT
|
||||
msr cpsr_c, r1
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t level);
|
||||
*/
|
||||
.globl rt_hw_interrupt_enable
|
||||
rt_hw_interrupt_enable:
|
||||
msr cpsr, r0
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||
* r0 --> from
|
||||
* r1 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
|
||||
stmfd sp!, {r0-r12, lr} @ push lr & register file
|
||||
|
||||
mrs r4, cpsr
|
||||
stmfd sp!, {r4} @ push cpsr
|
||||
mrs r4, spsr
|
||||
stmfd sp!, {r4} @ push spsr
|
||||
|
||||
str sp, [r0] @ store sp in preempted tasks TCB
|
||||
ldr sp, [r1] @ get new task stack pointer
|
||||
|
||||
ldmfd sp!, {r4} @ pop new task spsr
|
||||
msr spsr_cxsf, r4
|
||||
ldmfd sp!, {r4} @ pop new task cpsr
|
||||
msr cpsr_cxsf, r4
|
||||
|
||||
ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to);
|
||||
* r0 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
ldr sp, [r0] @ get new task stack pointer
|
||||
|
||||
ldmfd sp!, {r4} @ pop new task spsr
|
||||
msr spsr_cxsf, r4
|
||||
ldmfd sp!, {r4} @ pop new task cpsr
|
||||
msr cpsr_cxsf, r4
|
||||
|
||||
ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
|
||||
*/
|
||||
.globl rt_thread_switch_interrput_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
ldr r2, =rt_thread_switch_interrput_flag
|
||||
ldr r3, [r2]
|
||||
cmp r3, #1
|
||||
beq _reswitch
|
||||
mov r3, #1 @ set rt_thread_switch_interrput_flag to 1
|
||||
str r3, [r2]
|
||||
ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
|
||||
str r0, [r2]
|
||||
_reswitch:
|
||||
ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
|
||||
str r1, [r2]
|
||||
mov pc, lr
|
||||
Executable
+193
@@ -0,0 +1,193 @@
|
||||
/*
|
||||
* File : cpu.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety modified from mini2440
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "at91sam926x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup AT91SAM926X
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
|
||||
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
|
||||
|
||||
#ifdef __GNUC__
|
||||
rt_inline rt_uint32_t cp15_rd(void)
|
||||
{
|
||||
rt_uint32_t i;
|
||||
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
return i;
|
||||
}
|
||||
|
||||
rt_inline void cache_enable(rt_uint32_t bit)
|
||||
{
|
||||
__asm__ __volatile__( \
|
||||
"mrc p15,0,r0,c1,c0,0\n\t" \
|
||||
"orr r0,r0,%0\n\t" \
|
||||
"mcr p15,0,r0,c1,c0,0" \
|
||||
: \
|
||||
:"r" (bit) \
|
||||
:"memory");
|
||||
}
|
||||
|
||||
rt_inline void cache_disable(rt_uint32_t bit)
|
||||
{
|
||||
__asm__ __volatile__( \
|
||||
"mrc p15,0,r0,c1,c0,0\n\t" \
|
||||
"bic r0,r0,%0\n\t" \
|
||||
"mcr p15,0,r0,c1,c0,0" \
|
||||
: \
|
||||
:"r" (bit) \
|
||||
:"memory");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef __CC_ARM
|
||||
rt_inline rt_uint32_t cp15_rd(void)
|
||||
{
|
||||
rt_uint32_t i;
|
||||
|
||||
__asm
|
||||
{
|
||||
mrc p15, 0, i, c1, c0, 0
|
||||
}
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
rt_inline void cache_enable(rt_uint32_t bit)
|
||||
{
|
||||
rt_uint32_t value;
|
||||
|
||||
__asm
|
||||
{
|
||||
mrc p15, 0, value, c1, c0, 0
|
||||
orr value, value, bit
|
||||
mcr p15, 0, value, c1, c0, 0
|
||||
}
|
||||
}
|
||||
|
||||
rt_inline void cache_disable(rt_uint32_t bit)
|
||||
{
|
||||
rt_uint32_t value;
|
||||
|
||||
__asm
|
||||
{
|
||||
mrc p15, 0, value, c1, c0, 0
|
||||
bic value, value, bit
|
||||
mcr p15, 0, value, c1, c0, 0
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* enable I-Cache
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_icache_enable()
|
||||
{
|
||||
cache_enable(ICACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* disable I-Cache
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_icache_disable()
|
||||
{
|
||||
cache_disable(ICACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* return the status of I-Cache
|
||||
*
|
||||
*/
|
||||
rt_base_t rt_hw_cpu_icache_status()
|
||||
{
|
||||
return (cp15_rd() & ICACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* enable D-Cache
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_dcache_enable()
|
||||
{
|
||||
cache_enable(DCACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* disable D-Cache
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_dcache_disable()
|
||||
{
|
||||
cache_disable(DCACHE_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* return the status of D-Cache
|
||||
*
|
||||
*/
|
||||
rt_base_t rt_hw_cpu_dcache_status()
|
||||
{
|
||||
return (cp15_rd() & DCACHE_MASK);
|
||||
}
|
||||
|
||||
static void at91sam9260_reset(void)
|
||||
{
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
|
||||
}
|
||||
|
||||
static void at91sam9260_poweroff(void)
|
||||
{
|
||||
at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
|
||||
}
|
||||
|
||||
/**
|
||||
* reset cpu by dog's time-out
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_reset()
|
||||
{
|
||||
|
||||
rt_kprintf("Restarting system...\n");
|
||||
at91sam9260_reset();
|
||||
|
||||
while(1); /* loop forever and wait for reset to happen */
|
||||
|
||||
/* NEVER REACHED */
|
||||
}
|
||||
|
||||
/**
|
||||
* shutdown CPU
|
||||
*
|
||||
*/
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_uint32_t level;
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
at91sam9260_poweroff();
|
||||
while (level)
|
||||
{
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
Executable
+219
File diff suppressed because it is too large
Load Diff
Executable
+47
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* File : io.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#define AT91_BASE_SYS 0xffffe800
|
||||
|
||||
#define IO_SPACE_LIMIT 0xFFFFFFFF
|
||||
|
||||
#define readb(a) (*(volatile unsigned char *)(a))
|
||||
#define readw(a) (*(volatile unsigned short *)(a))
|
||||
#define readl(a) (*(volatile unsigned int *)(a))
|
||||
|
||||
#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||
#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||
#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
|
||||
|
||||
|
||||
static inline unsigned int at91_sys_read(unsigned int reg_offset)
|
||||
{
|
||||
void *addr = (void *)AT91_BASE_SYS;
|
||||
|
||||
return readl(addr + reg_offset);
|
||||
}
|
||||
|
||||
static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
|
||||
{
|
||||
void *addr = (void *)AT91_BASE_SYS;
|
||||
|
||||
writel(value, addr + reg_offset);
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+42
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* File : irq.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety first version
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_H__
|
||||
#define __IRQ_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IRQ line status.
|
||||
*
|
||||
* Bits 0-7 are reserved
|
||||
*
|
||||
* IRQ types
|
||||
*/
|
||||
#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
|
||||
#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
|
||||
#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
|
||||
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
|
||||
#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
|
||||
#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
|
||||
#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
|
||||
#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Executable
+395
File diff suppressed because it is too large
Load Diff
Executable
+106
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* File : rt_list.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006 - 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-15 weety copy from kservice APIs
|
||||
*/
|
||||
|
||||
#ifndef __RT_LIST_H__
|
||||
#define __RT_LIST_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @addtogroup rt_list
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* @brief initialize a list
|
||||
*
|
||||
* @param l list to be initialized
|
||||
*/
|
||||
rt_inline void rt_list_init(rt_list_t *l)
|
||||
{
|
||||
l->next = l->prev = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief insert a node after a list
|
||||
*
|
||||
* @param l list to insert it
|
||||
* @param n new node to be inserted
|
||||
*/
|
||||
rt_inline void rt_list_insert_after(rt_list_t *l, rt_list_t *n)
|
||||
{
|
||||
l->next->prev = n;
|
||||
n->next = l->next;
|
||||
|
||||
l->next = n;
|
||||
n->prev = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief insert a node before a list
|
||||
*
|
||||
* @param n new node to be inserted
|
||||
* @param l list to insert it
|
||||
*/
|
||||
rt_inline void rt_list_insert_before(rt_list_t *l, rt_list_t *n)
|
||||
{
|
||||
l->prev->next = n;
|
||||
n->prev = l->prev;
|
||||
|
||||
l->prev = n;
|
||||
n->next = l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief remove node from list.
|
||||
* @param n the node to remove from the list.
|
||||
*/
|
||||
rt_inline void rt_list_remove(rt_list_t *n)
|
||||
{
|
||||
n->next->prev = n->prev;
|
||||
n->prev->next = n->next;
|
||||
|
||||
n->next = n->prev = n;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief tests whether a list is empty
|
||||
* @param l the list to test.
|
||||
*/
|
||||
rt_inline int rt_list_isempty(const rt_list_t *l)
|
||||
{
|
||||
return l->next == l;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get the struct for this entry
|
||||
* @param node the entry point
|
||||
* @param type the type of structure
|
||||
* @param member the name of list in structure
|
||||
*/
|
||||
#define rt_list_entry(node, type, member) \
|
||||
((type *)((char *)(node) - (unsigned long)(&((type *)0)->member)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Executable
+282
File diff suppressed because it is too large
Load Diff
Executable
+76
@@ -0,0 +1,76 @@
|
||||
#ifndef __RT_HW_SERIAL_H__
|
||||
#define __RT_HW_SERIAL_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "at91sam926x.h"
|
||||
|
||||
#define RXRDY 0x01
|
||||
#define TXRDY (1 << 1)
|
||||
#define BPS 115200 /* serial baudrate */
|
||||
|
||||
#define UART_RX_BUFFER_SIZE 64
|
||||
#define UART_TX_BUFFER_SIZE 64
|
||||
|
||||
struct serial_int_rx
|
||||
{
|
||||
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
|
||||
rt_uint32_t read_index, save_index;
|
||||
};
|
||||
|
||||
struct serial_int_tx
|
||||
{
|
||||
rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
|
||||
rt_uint32_t write_index, save_index;
|
||||
};
|
||||
|
||||
typedef struct uartport
|
||||
{
|
||||
/* USART register offsets */
|
||||
volatile rt_uint32_t USART_CR;
|
||||
volatile rt_uint32_t USART_MR;
|
||||
volatile rt_uint32_t USART_IER;
|
||||
volatile rt_uint32_t USART_IDR;
|
||||
volatile rt_uint32_t USART_IMR;
|
||||
volatile rt_uint32_t USART_CSR;
|
||||
volatile rt_uint32_t USART_RHR;
|
||||
volatile rt_uint32_t USART_THR;
|
||||
volatile rt_uint32_t USART_BRGR;
|
||||
volatile rt_uint32_t USART_RTOR;
|
||||
volatile rt_uint32_t USART_TTGR;
|
||||
volatile rt_uint32_t reseverd0[5];
|
||||
volatile rt_uint32_t USART_FIDI;
|
||||
volatile rt_uint32_t USART_NER;
|
||||
volatile rt_uint32_t USART_XXR;
|
||||
volatile rt_uint32_t USART_IFR;
|
||||
volatile rt_uint32_t reserved1[44];
|
||||
volatile rt_uint32_t USART_RPR;
|
||||
volatile rt_uint32_t USART_RCR;
|
||||
volatile rt_uint32_t USART_TPR;
|
||||
volatile rt_uint32_t USART_TCR;
|
||||
volatile rt_uint32_t USART_RNPR;
|
||||
volatile rt_uint32_t USART_RNCR;
|
||||
volatile rt_uint32_t USART_TNPR;
|
||||
volatile rt_uint32_t USART_TNCR;
|
||||
volatile rt_uint32_t USART_PTCR;
|
||||
volatile rt_uint32_t USART_PTSR;
|
||||
}uartport;
|
||||
|
||||
|
||||
struct serial_device
|
||||
{
|
||||
uartport* uart_device;
|
||||
|
||||
/* rx structure */
|
||||
struct serial_int_rx* int_rx;
|
||||
|
||||
/* tx structure */
|
||||
struct serial_int_tx* int_tx;
|
||||
};
|
||||
|
||||
rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
|
||||
|
||||
void rt_hw_serial_isr(rt_device_t device);
|
||||
|
||||
#endif
|
||||
Executable
+60
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety copy from mini2440
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include "at91sam926x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup AT91SAM926X
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk;
|
||||
|
||||
stk = (rt_uint32_t*)stack_addr;
|
||||
*(stk) = (rt_uint32_t)tentry; /* entry point */
|
||||
*(--stk) = (rt_uint32_t)texit; /* lr */
|
||||
*(--stk) = 0; /* r12 */
|
||||
*(--stk) = 0; /* r11 */
|
||||
*(--stk) = 0; /* r10 */
|
||||
*(--stk) = 0; /* r9 */
|
||||
*(--stk) = 0; /* r8 */
|
||||
*(--stk) = 0; /* r7 */
|
||||
*(--stk) = 0; /* r6 */
|
||||
*(--stk) = 0; /* r5 */
|
||||
*(--stk) = 0; /* r4 */
|
||||
*(--stk) = 0; /* r3 */
|
||||
*(--stk) = 0; /* r2 */
|
||||
*(--stk) = 0; /* r1 */
|
||||
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
|
||||
*(--stk) = SVCMODE; /* cpsr */
|
||||
*(--stk) = SVCMODE; /* spsr */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
Executable
+385
File diff suppressed because it is too large
Load Diff
Executable
+277
File diff suppressed because it is too large
Load Diff
Executable
+173
@@ -0,0 +1,173 @@
|
||||
/*
|
||||
* File : trap.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://openlab.rt-thread.com/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-01-13 weety modified from mini2440
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#include "at91sam926x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup AT91SAM926X
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
extern struct rt_thread *rt_current_thread;
|
||||
#ifdef RT_USING_FINSH
|
||||
extern long list_thread(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* this function will show registers of CPU
|
||||
*
|
||||
* @param regs the registers point
|
||||
*/
|
||||
|
||||
void rt_hw_show_register (struct rt_hw_register *regs)
|
||||
{
|
||||
rt_kprintf("Execption:\n");
|
||||
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
|
||||
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
|
||||
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
|
||||
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
|
||||
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
|
||||
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
|
||||
}
|
||||
|
||||
/**
|
||||
* When ARM7TDMI comes across an instruction which it cannot handle,
|
||||
* it takes the undefined instruction trap.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_udef(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("undefined instruction\n");
|
||||
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* The software interrupt instruction (SWI) is used for entering
|
||||
* Supervisor mode, usually to request a particular supervisor
|
||||
* function.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_swi(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("software interrupt\n");
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* An abort indicates that the current memory access cannot be completed,
|
||||
* which occurs during an instruction prefetch.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_pabt(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("prefetch abort\n");
|
||||
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* An abort indicates that the current memory access cannot be completed,
|
||||
* which occurs during a data access.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_dabt(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_hw_show_register(regs);
|
||||
|
||||
rt_kprintf("data abort\n");
|
||||
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* Normally, system will never reach here
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_resv(struct rt_hw_register *regs)
|
||||
{
|
||||
rt_kprintf("not used\n");
|
||||
rt_hw_show_register(regs);
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
extern rt_isr_handler_t isr_table[];
|
||||
|
||||
void rt_hw_trap_irq()
|
||||
{
|
||||
rt_isr_handler_t isr_func;
|
||||
rt_uint32_t irqstat, irq, mask;
|
||||
//rt_kprintf("irq interrupt request\n");
|
||||
/* get irq number */
|
||||
irq = at91_sys_read(AT91_AIC_IVR);
|
||||
/* clear pending register */
|
||||
irqstat = at91_sys_read(AT91_AIC_ISR);
|
||||
if (irqstat == 0)
|
||||
{
|
||||
rt_kprintf("No interrupt occur\n");
|
||||
at91_sys_write(AT91_AIC_EOICR, 0);
|
||||
return;
|
||||
}
|
||||
//at91_sys_write(AT91_AIC_EOICR, 0x55555555);
|
||||
|
||||
/* get interrupt service routine */
|
||||
isr_func = isr_table[irq];
|
||||
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(irq);
|
||||
at91_sys_write(AT91_AIC_EOICR, 0x55555555); //EIOCR must be write any value after interrupt, or else can't response next interrupt
|
||||
}
|
||||
|
||||
void rt_hw_trap_fiq()
|
||||
{
|
||||
rt_kprintf("fast interrupt request\n");
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
Reference in New Issue
Block a user