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WCH CH569W-R0-1v0 evt board bsp port, first version (#6167)
WCH CH569W-R0-1v0 evt board bsp port, first version dev/test under Ubuntu 20.04 toolchain from MounRiver_Studio_Community_Linux_x64_V120 tested drivers : SysTick, gpio, gpio interrupt, uart1 (RX interrupt, TX polling) libcpu/risc-v/SConscript : group includes rtconfig.CPU only if folder exists libcpu/risc-v/common/cpuport.c/rt_hw_context_switch_interrupt() : make it RT_WEAK for customization
This commit is contained in:
emuzit
@@ -5,4 +5,11 @@ config SOC_RISCV_SERIES_CH32V103
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bool
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select ARCH_RISCV
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select SOC_RISCV_FAMILY_CH32
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config SOC_FAMILY_CH56X
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bool
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select ARCH_RISCV
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config SOC_SERIES_CH569
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bool
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select SOC_FAMILY_CH56X
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@@ -0,0 +1,28 @@
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from building import *
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cwd = GetCurrentDir()
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src = Split("""
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ch56x_sys.c
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swi_gcc.S
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""")
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if GetDepend('SOC_SERIES_CH569'):
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src += ['ch56x_pfic.c']
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if GetDepend('RT_USING_WDT'):
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src += ['ch56x_wdt.c']
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if GetDepend('RT_USING_HWTIMER'):
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src += ['ch56x_timer.c']
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if GetDepend('RT_USING_PIN'):
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src += ['ch56x_gpio.c']
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if GetDepend(['RT_USING_SERIAL', 'BSP_USING_UART']):
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src += ['ch56x_uart.c']
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path = [cwd]
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group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path)
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Return('group')
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,119 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-15 Emuzit first version
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*/
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#include <rthw.h>
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#include <rtdebug.h>
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#include "ch56x_pfic.h"
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#include "ch56x_sys.h"
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#include "isr_sp.h"
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void rt_hw_interrupt_mask(int vector)
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{
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pfic_interrupt_mask(vector);
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}
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void rt_hw_interrupt_umask(int vector)
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{
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pfic_interrupt_umask(vector);
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}
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/**
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* @brief Trigger software interrupt.
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*/
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void pfic_swi_pendset(void)
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{
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volatile struct pfic_registers *pfic = (void *)PFIC_REG_BASE;
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_pfic_ireg_bit_set(pfic, IPSR, SWI_IRQn);
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}
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/**
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* @brief Clear software interrupt.
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*/
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void pfic_swi_pendreset(void)
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{
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volatile struct pfic_registers *pfic = (void *)PFIC_REG_BASE;
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_pfic_ireg_bit_set(pfic, IPRR, SWI_IRQn);
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}
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/**
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* @brief Write PFIC interrupt configuration register.
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*
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* @param key_bit is (PFIC_CFGR_KEYx + bit_position), one of the following :
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* PFIC_CFGR_NMISET / PFIC_CFGR_NMIRESET
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* PFIC_CFGR_EXCSET / PFIC_CFGR_EXCRESET
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* PFIC_CFGR_PFICRESET
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* PFIC_CFGR_SYSRESET
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* All others are treated as NEST/HWSTK (B.1/B.0) write.
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*/
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void pfic_cfgr_set(uint32_t key_bit)
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{
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volatile struct pfic_registers *pfic = (void *)PFIC_REG_BASE;
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uint32_t u32v;
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switch (key_bit)
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{
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case PFIC_CFGR_NMISET:
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case PFIC_CFGR_NMIRESET:
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case PFIC_CFGR_EXCSET:
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case PFIC_CFGR_EXCRESET:
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case PFIC_CFGR_PFICRESET:
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case PFIC_CFGR_SYSRESET:
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pfic->CFGR = key_bit;
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default:
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/* B.1/B.0 hold NEST/HWSTK, key ignored */
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u32v = key_bit & (CFGR_NESTCTRL_MASK | CFGR_HWSTKCTRL_MASK);
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pfic->CFGR = cfgr_nest_hwstk(u32v);
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}
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}
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/**
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* @brief Make SysTick ready, systick/swi irq are enabled.
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*
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* @param count is (HCLK/8) clocks count to generate systick irq.
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* if 0 => calculate with current HCLK and RT_TICK_PER_SECOND
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*/
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void systick_init(uint32_t count)
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{
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volatile struct systick_registers *systick = (void *)SysTick_REG_BASE;
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volatile struct pfic_registers *pfic = (void *)PFIC_REG_BASE;
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if (count == 0)
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count = sys_hclk_get() / 8 / RT_TICK_PER_SECOND;
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_pfic_irqn_disable(pfic, SysTick_IRQn);
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pfic->IPRIOR[SysTick_IRQn] = 0xe0;
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pfic->IPRIOR[SWI_IRQn] = 0xf0;
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systick->CTLR.reg = 0;
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systick->CNTL = 0;
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systick->CNTH = 0;
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systick->CMPLR = count - 1;
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systick->CMPHR = 0;
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systick->CNTFG.cntif = 0;
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/* enable & reload SysTick, with HCLK/8 */
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systick->CTLR.reg = RB_STKCTL_STRELOAD | RB_STKCTL_STIE | RB_STKCTL_STE;
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_pfic_irqn_enable(pfic, SysTick_IRQn);
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_pfic_irqn_enable(pfic, SWI_IRQn);
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}
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void systick_handler(void) __attribute__((interrupt()));
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void systick_handler(void)
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{
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volatile struct systick_registers *systick;
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isr_sp_enter();
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rt_interrupt_enter();
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rt_tick_increase();
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systick = (struct systick_registers *)SysTick_REG_BASE;
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/* clear count-to-zero flag */
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systick->CNTFG.cntif = 0;
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rt_interrupt_leave();
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isr_sp_leave();
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}
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,138 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-15 Emuzit first version
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*/
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#ifndef __CH56X_TIMER_H__
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#define __CH56X_TIMER_H__
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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union _timer_ctrl_mod
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{
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uint8_t reg;
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struct
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{
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uint8_t mode_in : 1; // B.0 : RW, timer mode setting
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uint8_t all_clear : 1; // B.1 : RW, clear FIFO/count/int-flag
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uint8_t count_en : 1; // B.2 : RW, enable timer module
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uint8_t out_en : 1; // B.3 : RW, timer output enable
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uint8_t out_polar : 1; // B.4 : RW, output polarity for PWM mode
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uint8_t resv_5 : 1;
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uint8_t pwm_repeat : 2; // B.7-6 : RW, PWM repeat count, 1/4/8/16
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};
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struct
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{
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uint8_t stuff_0 : 6;
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uint8_t cap_edge : 2; // B.7-6 : RW, capture edge mode
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};
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};
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#define RB_TMR_MODE_IN 0x01
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#define RB_TMR_ALL_CLEAR 0x02
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#define RB_TMR_COUNT_EN 0x04
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#define RB_TMR_OUT_EN 0x08
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#define RB_TMR_OUT_POLAR 0x10
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#define RB_TMR_CAP_COUNT 0x10
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#define RB_TMR_PWM_REPEAT 0xc0
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#define RB_TMR_CAP_EDGE 0xc0
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#define TMR_MODE_TIMER_PWM 0
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#define TMR_MODE_CAP_COUNT 1
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#define TMR_PWM_REPEAT_1 0
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#define TMR_PWM_REPEAT_4 1
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#define TMR_PWM_REPEAT_8 2
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#define TMR_PWM_REPEAT_16 3
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#define TMR_CAP_EDGE_NONE 0
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#define TMR_CAP_EDGE_BOTH 1
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#define TMR_CAP_EDGE_F2F 2
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#define TMR_CAP_EDGE_R2R 3
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union _timer_ctrl_dma
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{
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uint8_t reg;
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struct
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{
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uint8_t dma_enable : 1; // B.0 : RW, enable DMA
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uint8_t resv_1 : 1;
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uint8_t dma_loop : 1; // B.2 : RW, enable DMA address looping
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uint8_t resv_3 : 5;
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};
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};
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#define RB_TMR_DMA_ENABLE 0x01
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#define RB_TMR_DMA_LOOP 0x04
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union _timer_interrupt
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{
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uint8_t reg;
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struct
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{
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uint8_t cyc_end : 1; // B.0
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uint8_t data_act : 1; // B.1
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uint8_t fifo_hf : 1; // B.2
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uint8_t dma_end : 1; // B.3
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uint8_t fifo_ov : 1; // B.4
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uint8_t resv_5 : 3;
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};
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};
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#define RB_TMR_IX_MASK 0x1f
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#define RB_TMR_IE_CYC_END 0x01 // RW, enable interrupt for timer capture count timeout or PWM cycle end
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#define RB_TMR_IE_DATA_ACT 0x02 // RW, enable interrupt for timer capture input action or PWM trigger
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#define RB_TMR_IE_FIFO_HF 0x04 // RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo <=3)
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#define RB_TMR_IE_DMA_END 0x08 // RW, enable interrupt for timer1/2 DMA completion
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#define RB_TMR_IE_FIFO_OV 0x10 // RW, enable interrupt for timer FIFO overflow
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#define RB_TMR_IF_CYC_END 0x01 // RW1, interrupt flag for timer capture count timeout or PWM cycle end
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#define RB_TMR_IF_DATA_ACT 0x02 // RW1, interrupt flag for timer capture input action or PWM trigger
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#define RB_TMR_IF_FIFO_HF 0x04 // RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo <=3)
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#define RB_TMR_IF_DMA_END 0x08 // RW1, interrupt flag for timer1/2 DMA completion
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#define RB_TMR_IF_FIFO_OV 0x10 // RW1, interrupt flag for timer FIFO overflow
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/*
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* 0x00 R8_TMRx_CTRL_MOD: mode setting register
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* 0x01 R8_TMRx_CTRL_DMA: DMA control register
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* 0x02 R8_TMRx_INTER_EN: interrupt enable register
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* 0x06 R8_TMRx_INT_FLAG: interrupt flag register
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* 0x07 R8_TMRx_FIFO_COUNT: RO, FIFO count register
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* 0x08 R32_TMRx_COUNT: RO, timer current count register
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* 0x0c R32_TMRx_CNT_END: RW, timer count end register
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* 0x10 R32_TMRx_FIFO: RO/WO, FIFO data register, LSB 26 bits
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* 0x14 R32_TMRx_DMA_NOW: RW, DMA buffer current address, LSB 18 bits
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* 0x18 R32_TMRx_DMA_BEG: RW, DMA buffer begin address, LSB 18 bits
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* 0x1c R32_TMRx_DMA_END: RW, DMA buffer end address (exclusive), LSB 18 bits
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*
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* Note: DMA related registers (0x10,0x14,0x18,0x1c) are TMR1/2 only
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*
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* CAVEAT: gcc (as of 8.2.0) tends to read 32-bit word for bit field test.
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* Be careful for those with side effect for read.
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*/
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struct timer_registers
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{
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union _timer_ctrl_mod CTRL_MOD;
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union _timer_ctrl_dma CTRL_DMA;
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union _timer_interrupt INTER_EN;
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uint8_t resv_3[3];
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union _timer_interrupt INT_FLAG;
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uint8_t FIFO_COUNT;
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uint32_t COUNT;
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uint32_t CNT_END;
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uint32_t FIFO;
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uint32_t DMA_NOW;
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uint32_t DMA_BEG;
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uint32_t DMA_END;
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} __packed;
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CHECK_STRUCT_SIZE(struct timer_registers, 0x20);
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#ifdef __cplusplus
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}
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#endif
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#endif
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-27 Emuzit first version
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*/
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#ifndef __ISR_SP_H__
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#define __ISR_SP_H__
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/* usrstack is no more in use right after rt_system_scheduler_start().
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* It is also the time global interrupt is enabled.
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*/
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#define isr_sp_enter() \
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asm("la t0, rt_interrupt_nest"); \
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asm("bnez t0, 1f"); \
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asm("la t0, _eusrstack"); \
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asm("sw sp, -4(t0)"); \
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asm("addi sp, t0, -4"); \
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asm("1:")
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#define isr_sp_leave() \
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asm("la t0, rt_interrupt_nest"); \
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asm("bnez t0, 1f"); \
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asm("la t0, _eusrstack"); \
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asm("lw sp, -4(t0)"); \
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asm("1:")
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#endif
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@@ -0,0 +1,152 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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||||
* Date Author Notes
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* 2022-07-15 Emuzit first version
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*/
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#ifndef __SOC_H__
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#define __SOC_H__
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#if !defined(SOC_CH567) && \
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!defined(SOC_CH568) && \
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!defined(SOC_SERIES_CH569)
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#define SOC_SERIES_CH569
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#endif
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#define CHECK_STRUCT_SIZE(s, size) \
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static_assert(sizeof(s) == size, #s " has wrong size")
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#define BITS_SET(x, bits) do x |= bits; while(0)
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#define BITS_CLR(x, bits) do x &= ~bits; while(0)
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#define FLASH_BASE_ADDRESS 0x00000000
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#define RAMS_BASE_ADDRESS 0x20000000
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#define RAMX_BASE_ADDRESS 0x20020000
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#define BUS8_BASE_ADDRESS 0x80000000
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#ifdef SOC_SERIES_CH569
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#define RAMS_SIZE 16
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#else
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#define RAMS_SIZE 32
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#endif
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#define RAMS_END (RAMS_BASE_ADDRESS + RAMS_SIZE * 1024)
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#define SYS_REG_BASE 0x40001000
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#define GPIO_REG_BASE 0x40001000
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#define GPIO_REG_BASE_PA 0x40001040
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#define GPIO_REG_BASE_PB 0x40001060
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#define GPIO_PORTS 2 // 2 ports : PA & PB
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#define GPIO_PA_PIN_START 0 // PA : pin number 0~31
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#define GPIO_PB_PIN_START 32 // PB : pin number 32~63
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#ifdef SOC_SERIES_CH569
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#define GPIO_PA_PIN_MARK 0x00ffffff // PA : bits 0~23
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#define GPIO_PB_PIN_MARK 0x01ffffff // PB : bits 0~24
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#else
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#define GPIO_PA_PIN_MARK 0x0000ffff // PA : bits 0~15
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#define GPIO_PB_PIN_MARK 0x00003fff // PB : bits 0~13
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#endif
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#define TMR0_REG_BASE 0x40002000
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#define TMR1_REG_BASE 0x40002400
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#define TMR2_REG_BASE 0x40002800
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#define UART0_REG_BASE 0x40003000
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#define UART1_REG_BASE 0x40003400
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#define UART2_REG_BASE 0x40003800
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#define UART3_REG_BASE 0x40003c00
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#define SPI0_REG_BASE 0x40004000
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#define SPI1_REG_BASE 0x40004400
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#define PWMX_REG_BASE 0x40005000
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#define PFIC_REG_BASE 0xe000e000
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#define SysTick_REG_BASE 0xe000f000
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#ifdef SOC_SERIES_CH569
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#define HSPI_REG_BASE 0x40006000 // CH569W
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#define ECDC_REG_BASE 0x40007000
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#define USBSS_REG_BASE 0x40008000
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||||
#define USBHS_REG_BASE 0x40009000
|
||||
#define EMMC_REG_BASE 0x4000a000
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#define SERDES_REG_BASE 0x4000b000
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#define ETH_REG_BASE 0x4000c000 // CH565W/CH569W
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#define DVP_REG_BASE 0x4000e000 // CH565W/CH565M
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#else
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#define LED_REG_BASE 0x40006000
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#define USB0_REG_BASE 0x40008000 // CH567
|
||||
#define USB1_REG_BASE 0x40009000 // CH567
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||||
#define USB_REG_BASE 0x40009000 // CH568
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||||
#define SDC_REG_BASE 0x4000a000
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#define SATA_REG_BASE 0x4000b000 // CH568
|
||||
#define ECDC_REG_BASE 0x4000c400
|
||||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_CH569)
|
||||
typedef enum
|
||||
{
|
||||
PWMX_OFFn = 0,
|
||||
NMI_IRQn = 2,
|
||||
EXC_IRQn = 3,
|
||||
SysTick_IRQn = 12,
|
||||
SWI_IRQn = 14,
|
||||
WDOG_IRQn = 16,
|
||||
TMR0_IRQn = 17,
|
||||
GPIO_IRQn = 18,
|
||||
SPI0_IRQn = 19,
|
||||
USBSS_IRQn = 20,
|
||||
LINK_IRQn = 21,
|
||||
TMR1_IRQn = 22,
|
||||
TMR2_IRQn = 23,
|
||||
UART0_IRQn = 24,
|
||||
USBHS_IRQn = 25,
|
||||
EMMC_IRQn = 26,
|
||||
DVP_IRQn = 27,
|
||||
HSPI_IRQn = 28,
|
||||
SPI1_IRQn = 29,
|
||||
UART1_IRQn = 30,
|
||||
UART2_IRQn = 31,
|
||||
UART3_IRQn = 32,
|
||||
SerDes_IRQn = 33,
|
||||
ETH_IRQn = 34,
|
||||
PMT_IRQn = 35,
|
||||
ECDC_IRQn = 36,
|
||||
END_OF_IRQn
|
||||
} irq_number_t;
|
||||
|
||||
#else
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PWMX_OFFn = 0,
|
||||
SOFT_IRQn = 0,
|
||||
TMR0_IRQn = 1,
|
||||
GPIO_IRQn = 2,
|
||||
SPI0_IRQn = 3,
|
||||
USB0_IRQn = 4, // CH567
|
||||
SATA_IRQn = 4, // CH568
|
||||
TMR1_IRQn = 5,
|
||||
TMR2_IRQn = 6,
|
||||
UART0_IRQn = 7,
|
||||
USB1_IRQn = 8,
|
||||
SDC_IRQn = 9,
|
||||
ECDC_IRQn = 10,
|
||||
LED_IRQn = 11,
|
||||
SPI1_IRQn = 12,
|
||||
UART1_IRQn = 13,
|
||||
UART2_IRQn = 14,
|
||||
UART3_IRQn = 15,
|
||||
END_OF_IRQn
|
||||
} irq_number_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,190 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-09-09 WCH the first version
|
||||
* 2022-07-15 Emuzit adapt to ch569w-evt
|
||||
*/
|
||||
|
||||
#include "cpuport.h"
|
||||
|
||||
.global swi_handler
|
||||
.align 2
|
||||
swi_handler:
|
||||
/* save all from thread context */
|
||||
#ifdef ARCH_RISCV_FPU
|
||||
addi sp, sp, -32 * FREGBYTES
|
||||
FSTORE f0, 0 * FREGBYTES(sp)
|
||||
FSTORE f1, 1 * FREGBYTES(sp)
|
||||
FSTORE f2, 2 * FREGBYTES(sp)
|
||||
FSTORE f3, 3 * FREGBYTES(sp)
|
||||
FSTORE f4, 4 * FREGBYTES(sp)
|
||||
FSTORE f5, 5 * FREGBYTES(sp)
|
||||
FSTORE f6, 6 * FREGBYTES(sp)
|
||||
FSTORE f7, 7 * FREGBYTES(sp)
|
||||
FSTORE f8, 8 * FREGBYTES(sp)
|
||||
FSTORE f9, 9 * FREGBYTES(sp)
|
||||
FSTORE f10, 10 * FREGBYTES(sp)
|
||||
FSTORE f11, 11 * FREGBYTES(sp)
|
||||
FSTORE f12, 12 * FREGBYTES(sp)
|
||||
FSTORE f13, 13 * FREGBYTES(sp)
|
||||
FSTORE f14, 14 * FREGBYTES(sp)
|
||||
FSTORE f15, 15 * FREGBYTES(sp)
|
||||
FSTORE f16, 16 * FREGBYTES(sp)
|
||||
FSTORE f17, 17 * FREGBYTES(sp)
|
||||
FSTORE f18, 18 * FREGBYTES(sp)
|
||||
FSTORE f19, 19 * FREGBYTES(sp)
|
||||
FSTORE f20, 20 * FREGBYTES(sp)
|
||||
FSTORE f21, 21 * FREGBYTES(sp)
|
||||
FSTORE f22, 22 * FREGBYTES(sp)
|
||||
FSTORE f23, 23 * FREGBYTES(sp)
|
||||
FSTORE f24, 24 * FREGBYTES(sp)
|
||||
FSTORE f25, 25 * FREGBYTES(sp)
|
||||
FSTORE f26, 26 * FREGBYTES(sp)
|
||||
FSTORE f27, 27 * FREGBYTES(sp)
|
||||
FSTORE f28, 28 * FREGBYTES(sp)
|
||||
FSTORE f29, 29 * FREGBYTES(sp)
|
||||
FSTORE f30, 30 * FREGBYTES(sp)
|
||||
FSTORE f31, 31 * FREGBYTES(sp)
|
||||
#endif
|
||||
|
||||
addi sp, sp, -32 * REGBYTES
|
||||
|
||||
STORE x1, 1 * REGBYTES(sp)
|
||||
|
||||
/* saved MPIE */
|
||||
li x1, 0x80
|
||||
STORE x1, 2 * REGBYTES(sp)
|
||||
|
||||
STORE x4, 4 * REGBYTES(sp)
|
||||
STORE x5, 5 * REGBYTES(sp)
|
||||
STORE x6, 6 * REGBYTES(sp)
|
||||
STORE x7, 7 * REGBYTES(sp)
|
||||
STORE x8, 8 * REGBYTES(sp)
|
||||
STORE x9, 9 * REGBYTES(sp)
|
||||
STORE x10, 10 * REGBYTES(sp)
|
||||
STORE x11, 11 * REGBYTES(sp)
|
||||
STORE x12, 12 * REGBYTES(sp)
|
||||
STORE x13, 13 * REGBYTES(sp)
|
||||
STORE x14, 14 * REGBYTES(sp)
|
||||
STORE x15, 15 * REGBYTES(sp)
|
||||
STORE x16, 16 * REGBYTES(sp)
|
||||
STORE x17, 17 * REGBYTES(sp)
|
||||
STORE x18, 18 * REGBYTES(sp)
|
||||
STORE x19, 19 * REGBYTES(sp)
|
||||
STORE x20, 20 * REGBYTES(sp)
|
||||
STORE x21, 21 * REGBYTES(sp)
|
||||
STORE x22, 22 * REGBYTES(sp)
|
||||
STORE x23, 23 * REGBYTES(sp)
|
||||
STORE x24, 24 * REGBYTES(sp)
|
||||
STORE x25, 25 * REGBYTES(sp)
|
||||
STORE x26, 26 * REGBYTES(sp)
|
||||
STORE x27, 27 * REGBYTES(sp)
|
||||
STORE x28, 28 * REGBYTES(sp)
|
||||
STORE x29, 29 * REGBYTES(sp)
|
||||
STORE x30, 30 * REGBYTES(sp)
|
||||
STORE x31, 31 * REGBYTES(sp)
|
||||
|
||||
/* rt_thread_switch_interrupt_flag not 0 => clear & switch thread */
|
||||
la t0, rt_thread_switch_interrupt_flag
|
||||
lw t1, 0(t0)
|
||||
beqz t1, .L_restore
|
||||
sw zero, 0(t0)
|
||||
|
||||
/* prepare to switch to rt_interrupt_to_thread */
|
||||
csrr t1, mepc
|
||||
STORE t1, 0 * REGBYTES(sp)
|
||||
|
||||
la t0, rt_interrupt_from_thread
|
||||
LOAD t1, 0(t0)
|
||||
STORE sp, 0(t1)
|
||||
|
||||
la t0, rt_interrupt_to_thread
|
||||
LOAD t1, 0(t0)
|
||||
LOAD sp, 0(t1)
|
||||
|
||||
LOAD t1, 0 * REGBYTES(sp)
|
||||
csrw mepc, t1
|
||||
|
||||
.L_restore:
|
||||
|
||||
/* clear software interrupt */
|
||||
jal pfic_swi_pendreset
|
||||
|
||||
LOAD x1, 1 * REGBYTES(sp)
|
||||
|
||||
li t0, 0x1800
|
||||
csrs mstatus, t0
|
||||
LOAD t0, 2 * REGBYTES(sp)
|
||||
csrs mstatus, t0
|
||||
|
||||
LOAD x4, 4 * REGBYTES(sp)
|
||||
LOAD x5, 5 * REGBYTES(sp)
|
||||
LOAD x6, 6 * REGBYTES(sp)
|
||||
LOAD x7, 7 * REGBYTES(sp)
|
||||
LOAD x8, 8 * REGBYTES(sp)
|
||||
LOAD x9, 9 * REGBYTES(sp)
|
||||
LOAD x10, 10 * REGBYTES(sp)
|
||||
LOAD x11, 11 * REGBYTES(sp)
|
||||
LOAD x12, 12 * REGBYTES(sp)
|
||||
LOAD x13, 13 * REGBYTES(sp)
|
||||
LOAD x14, 14 * REGBYTES(sp)
|
||||
LOAD x15, 15 * REGBYTES(sp)
|
||||
LOAD x16, 16 * REGBYTES(sp)
|
||||
LOAD x17, 17 * REGBYTES(sp)
|
||||
LOAD x18, 18 * REGBYTES(sp)
|
||||
LOAD x19, 19 * REGBYTES(sp)
|
||||
LOAD x20, 20 * REGBYTES(sp)
|
||||
LOAD x21, 21 * REGBYTES(sp)
|
||||
LOAD x22, 22 * REGBYTES(sp)
|
||||
LOAD x23, 23 * REGBYTES(sp)
|
||||
LOAD x24, 24 * REGBYTES(sp)
|
||||
LOAD x25, 25 * REGBYTES(sp)
|
||||
LOAD x26, 26 * REGBYTES(sp)
|
||||
LOAD x27, 27 * REGBYTES(sp)
|
||||
LOAD x28, 28 * REGBYTES(sp)
|
||||
LOAD x29, 29 * REGBYTES(sp)
|
||||
LOAD x30, 30 * REGBYTES(sp)
|
||||
LOAD x31, 31 * REGBYTES(sp)
|
||||
addi sp, sp, 32 * REGBYTES
|
||||
|
||||
/* load float reg */
|
||||
#ifdef ARCH_RISCV_FPU
|
||||
FLOAD f0, 0 * FREGBYTES(sp)
|
||||
FLOAD f1, 1 * FREGBYTES(sp)
|
||||
FLOAD f2, 2 * FREGBYTES(sp)
|
||||
FLOAD f3, 3 * FREGBYTES(sp)
|
||||
FLOAD f4, 4 * FREGBYTES(sp)
|
||||
FLOAD f5, 5 * FREGBYTES(sp)
|
||||
FLOAD f6, 6 * FREGBYTES(sp)
|
||||
FLOAD f7, 7 * FREGBYTES(sp)
|
||||
FLOAD f8, 8 * FREGBYTES(sp)
|
||||
FLOAD f9, 9 * FREGBYTES(sp)
|
||||
FLOAD f10, 10 * FREGBYTES(sp)
|
||||
FLOAD f11, 11 * FREGBYTES(sp)
|
||||
FLOAD f12, 12 * FREGBYTES(sp)
|
||||
FLOAD f13, 13 * FREGBYTES(sp)
|
||||
FLOAD f14, 14 * FREGBYTES(sp)
|
||||
FLOAD f15, 15 * FREGBYTES(sp)
|
||||
FLOAD f16, 16 * FREGBYTES(sp)
|
||||
FLOAD f17, 17 * FREGBYTES(sp)
|
||||
FLOAD f18, 18 * FREGBYTES(sp)
|
||||
FLOAD f19, 19 * FREGBYTES(sp)
|
||||
FLOAD f20, 20 * FREGBYTES(sp)
|
||||
FLOAD f21, 21 * FREGBYTES(sp)
|
||||
FLOAD f22, 22 * FREGBYTES(sp)
|
||||
FLOAD f23, 23 * FREGBYTES(sp)
|
||||
FLOAD f24, 24 * FREGBYTES(sp)
|
||||
FLOAD f25, 25 * FREGBYTES(sp)
|
||||
FLOAD f26, 26 * FREGBYTES(sp)
|
||||
FLOAD f27, 27 * FREGBYTES(sp)
|
||||
FLOAD f28, 28 * FREGBYTES(sp)
|
||||
FLOAD f29, 29 * FREGBYTES(sp)
|
||||
FLOAD f30, 30 * FREGBYTES(sp)
|
||||
FLOAD f31, 31 * FREGBYTES(sp)
|
||||
addi sp, sp, 32 * FREGBYTES
|
||||
#endif
|
||||
mret
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,21 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "../Libraries/Kconfig"
|
||||
source "board/Kconfig"
|
||||
@@ -0,0 +1,13 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
if os.path.isfile(os.path.join(cwd, d, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,38 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot find RT-Thread root directory, please check RTT_ROOT')
|
||||
print('RTT_ROOT: ' + RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
objs.extend(SConscript('../Libraries/ch56x_drivers/SConscript',
|
||||
variant_dir='build/libraries/ch56x_drivers', duplicate=0))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,13 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Split("""
|
||||
main.c
|
||||
""")
|
||||
|
||||
path = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend=[''], CPPPATH=path)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,64 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_CH569W
|
||||
bool
|
||||
select SOC_FAMILY_CH56X
|
||||
select SOC_SERIES_CH569
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_UART
|
||||
bool "using on-chip uart"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART0
|
||||
bool "using UART0"
|
||||
default n
|
||||
|
||||
config BSP_USING_UART1
|
||||
bool "using UART1"
|
||||
default y
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "using UART2"
|
||||
default n
|
||||
|
||||
config BSP_USING_UART3
|
||||
bool "using UART3"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_TIMER
|
||||
bool "using on-chip timer"
|
||||
select RT_USING_HWTIMER
|
||||
default n
|
||||
|
||||
if BSP_USING_TIMER
|
||||
config BSP_USING_TMR0
|
||||
bool "using TMR0"
|
||||
default y
|
||||
|
||||
config BSP_USING_TMR1
|
||||
bool "using TMR1"
|
||||
default n
|
||||
|
||||
config BSP_USING_TMR2
|
||||
bool "using TMR2"
|
||||
default n
|
||||
endif
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,13 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Split('''
|
||||
board.c
|
||||
startup_gcc.S
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path)
|
||||
Return('group')
|
||||
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-07-15 Emuzit first version
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <drivers/pin.h>
|
||||
#include "board.h"
|
||||
#include "ch56x_pfic.h"
|
||||
#include "ch56x_uart.h"
|
||||
|
||||
extern rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
/* FIXME: Use rt_interrupt_leave_hook to trigger SWI for context switch.
|
||||
* Hopefully there's a standard riscv way instead of this clumsy patch.
|
||||
*/
|
||||
static void irq_leave_hook(void)
|
||||
{
|
||||
if (rt_thread_switch_interrupt_flag)
|
||||
{
|
||||
pfic_swi_pendset();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* _start -> handle_reset
|
||||
* src/components.c/entry() -> rtthread_startup()
|
||||
* libcpu/risc-v/common/context_gcc.S/rt_hw_interrupt_disable
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
volatile struct pfic_registers *pfic = (void *)PFIC_REG_BASE;
|
||||
|
||||
/* disable all pfic interrupts */
|
||||
pfic->IRER[0] = PFIC_IREG1_MASK;
|
||||
pfic->IRER[1] = PFIC_IREG2_MASK;
|
||||
|
||||
/* disable hwstack push/pop & nested interrupt */
|
||||
pfic->CFGR = cfgr_nest_hwstk(CFGR_NESTCTRL_DISABLE | CFGR_HWSTKCTRL_DISABLE);
|
||||
|
||||
/* disable clock input for all peripheral devices */
|
||||
sys_slp_clk_off0(0xff, SYS_SLP_CLK_OFF);
|
||||
sys_slp_clk_off1(0xff, SYS_SLP_CLK_OFF);
|
||||
sys_clk_off_by_irqn(ETH_IRQn, SYS_SLP_CLK_OFF);
|
||||
sys_clk_off_by_irqn(ECDC_IRQn, SYS_SLP_CLK_OFF);
|
||||
|
||||
/* setup HCLK for systick & peripheral devices */
|
||||
sys_hclk_set(SYS_HCLK_FREQ);
|
||||
|
||||
/* set SysTick to RT_TICK_PER_SECOND with current HCLK */
|
||||
systick_init(0);
|
||||
|
||||
/* Note: keep MSTATUS_MIE disabled to prevent SysTick from processing
|
||||
* thread scheduling, which may not be ready upon 1st systick irq.
|
||||
* MSTATUS_MIE will be set when rt_system_scheduler_start() starts
|
||||
* the first thread and copies mstatus from stack_frame.
|
||||
*/
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
/* console is uart1, TXD1/RXD1 : PA8/PA7 */
|
||||
rt_pin_mode(GET_PIN(A, 8), PIN_MODE_OUTPUT);
|
||||
rt_pin_mode(GET_PIN(A, 7), PIN_MODE_INPUT_PULLUP);
|
||||
rt_hw_uart_init();
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
rt_interrupt_leave_sethook(irq_leave_hook);
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-07-15 Emuzit first version
|
||||
*/
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "ch56x_sys.h"
|
||||
#include "ch56x_gpio.h"
|
||||
|
||||
#define LED0_PIN GET_PIN(B, 24)
|
||||
#define LED1_PIN GET_PIN(B, 22)
|
||||
#define LED2_PIN GET_PIN(B, 23)
|
||||
|
||||
#define SYS_HCLK_FREQ 80000000 // 80 MHz
|
||||
|
||||
#define RAMX_SIZE 32 // USER_MEM 00/01/1x : 32/64/96 KB
|
||||
#define RAMX_END (RAMX_BASE_ADDRESS + RAMX_SIZE * 1024)
|
||||
|
||||
extern uint32_t _ebss, _heap_end;
|
||||
extern uint32_t _susrstack, _eusrstack;
|
||||
|
||||
#define HEAP_BEGIN ((void *)&_ebss)
|
||||
#define HEAP_END ((void *)&_heap_end)
|
||||
#define SUSRSTACK ((void *)&_susrstack)
|
||||
#define EUSRSTACK ((void *)&_eusrstack)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif /* __BOARD_H__ */
|
||||
@@ -0,0 +1,199 @@
|
||||
ENTRY( _start )
|
||||
|
||||
__stack_size = 2048;
|
||||
|
||||
PROVIDE( _stack_size = __stack_size );
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 96K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
RAMX (xrw) : ORIGIN = 0x20020000, LENGTH = 32K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.init :
|
||||
{
|
||||
_sinit = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(SORT_NONE(.init)))
|
||||
. = ALIGN(4);
|
||||
_einit = .;
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.vector :
|
||||
{
|
||||
*(.vector);
|
||||
. = ALIGN(64);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t.*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for modules */
|
||||
. = ALIGN(4);
|
||||
__rtmsymtab_start = .;
|
||||
KEEP(*(RTMSymTab))
|
||||
__rtmsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini :
|
||||
{
|
||||
KEEP(*(SORT_NONE(.fini)))
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
PROVIDE( _etext = . );
|
||||
PROVIDE( _eitcm = . );
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_vma = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.dlalign :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_lma = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _sbss = .);
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ebss = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
PROVIDE( _end = _ebss);
|
||||
PROVIDE( end = . );
|
||||
|
||||
.dmadata :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _dmadata_start = .);
|
||||
*(.dmadata*)
|
||||
*(.dmadata.*)
|
||||
. = ALIGN(16);
|
||||
PROVIDE( _dmadata_end = .);
|
||||
} >RAMX AT>FLASH /**/
|
||||
|
||||
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
|
||||
{
|
||||
PROVIDE( _heap_end = . );
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_susrstack = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _eusrstack = .);
|
||||
} >RAM
|
||||
}
|
||||
@@ -0,0 +1,174 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : startup_gcc.s
|
||||
* Author : WCH
|
||||
* Version : V1.0
|
||||
* Date : 2020/07/31
|
||||
* Description : CH56x vector table for eclipse toolchain.
|
||||
*******************************************************************************/
|
||||
|
||||
.section .init,"ax",@progbits
|
||||
.global _start
|
||||
.align 1
|
||||
_start:
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 1
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word 0
|
||||
.word 0
|
||||
j nmi_handler
|
||||
j hardfault_handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
j systick_handler
|
||||
.word 0
|
||||
j swi_handler
|
||||
.word 0
|
||||
/* External Interrupts */
|
||||
j wdog_irq_handler
|
||||
j tmr0_irq_handler
|
||||
j gpio_irq_handler
|
||||
j spi0_irq_handler
|
||||
j usbss_irq_handler
|
||||
j link_irq_handler
|
||||
j tmr1_irq_handler
|
||||
j tmr2_irq_handler
|
||||
j uart0_irq_handler
|
||||
j usbhs_irq_handler
|
||||
j emmc_irq_handler
|
||||
j dvp_irq_handler
|
||||
j hspi_irq_handler
|
||||
j spi1_irq_handler
|
||||
j uart1_irq_handler
|
||||
j uart2_irq_handler
|
||||
j uart3_irq_handler
|
||||
j serdes_irq_handler
|
||||
j eth_irq_handler
|
||||
j pmt_irq_handler
|
||||
j ecdc_irq_handler
|
||||
|
||||
.option rvc;
|
||||
|
||||
.section .text.vector_handler,"ax", @prsocogbits
|
||||
|
||||
.weak nmi_handler
|
||||
.weak hardfault_handler
|
||||
.weak systick_handler
|
||||
.weak swi_handler
|
||||
.weak wdog_irq_handler
|
||||
.weak tmr0_irq_handler
|
||||
.weak gpio_irq_handler
|
||||
.weak spi0_irq_handler
|
||||
.weak usbss_irq_handler
|
||||
.weak link_irq_handler
|
||||
.weak tmr1_irq_handler
|
||||
.weak tmr2_irq_handler
|
||||
.weak uart0_irq_handler
|
||||
.weak usbhs_irq_handler
|
||||
.weak emmc_irq_handler
|
||||
.weak dvp_irq_handler
|
||||
.weak hspi_irq_handler
|
||||
.weak spi1_irq_handler
|
||||
.weak uart1_irq_handler
|
||||
.weak uart2_irq_handler
|
||||
.weak uart3_irq_handler
|
||||
.weak serdes_irq_handler
|
||||
.weak eth_irq_handler
|
||||
.weak pmt_irq_handler
|
||||
.weak ecdc_irq_handler
|
||||
|
||||
nmi_handler: j .L_rip
|
||||
hardfault_handler: j .L_rip
|
||||
systick_handler: j .L_rip
|
||||
swi_handler: j .L_rip
|
||||
wdog_irq_handler: j .L_rip
|
||||
tmr0_irq_handler: j .L_rip
|
||||
gpio_irq_handler: j .L_rip
|
||||
spi0_irq_handler: j .L_rip
|
||||
usbss_irq_handler: j .L_rip
|
||||
link_irq_handler: j .L_rip
|
||||
tmr1_irq_handler: j .L_rip
|
||||
tmr2_irq_handler: j .L_rip
|
||||
uart0_irq_handler: j .L_rip
|
||||
usbhs_irq_handler: j .L_rip
|
||||
emmc_irq_handler: j .L_rip
|
||||
dvp_irq_handler: j .L_rip
|
||||
hspi_irq_handler: j .L_rip
|
||||
spi1_irq_handler: j .L_rip
|
||||
uart1_irq_handler: j .L_rip
|
||||
uart2_irq_handler: j .L_rip
|
||||
uart3_irq_handler: j .L_rip
|
||||
serdes_irq_handler: j .L_rip
|
||||
eth_irq_handler: j .L_rip
|
||||
pmt_irq_handler: j .L_rip
|
||||
ecdc_irq_handler: j .L_rip
|
||||
|
||||
.L_rip:
|
||||
csrr t0, mepc
|
||||
csrr t1, mstatus
|
||||
csrr t2, mcause
|
||||
csrr t3, mtval
|
||||
csrr t4, mscratch
|
||||
1: j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
1:
|
||||
la sp, _eusrstack
|
||||
|
||||
/* Load data section from flash to RAM */
|
||||
2:
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
/* clear bss section */
|
||||
2:
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
|
||||
/* clear dmadata section */
|
||||
2:
|
||||
la a0, _dmadata_start
|
||||
la a1, _dmadata_end
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
|
||||
2:
|
||||
/* leave all interrupt disabled */
|
||||
li t0, 0x1800
|
||||
csrs mstatus, t0
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 1
|
||||
csrw mtvec, t0
|
||||
la t0, entry
|
||||
csrw mepc, t0
|
||||
mret
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 112 KiB |
@@ -0,0 +1,192 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 200
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 384
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_KSERVICE_USING_STDLIB
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_MAILBOX
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_INTERRUPT_INFO
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40101
|
||||
#define ARCH_RISCV
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_HWTIMER
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_WDT
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
|
||||
/* Network */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
|
||||
/* PainterEngine: A cross-platform graphics application framework written in C language */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* AI packages */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
#define SOC_FAMILY_CH56X
|
||||
#define SOC_SERIES_CH569
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_CH569W
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART1
|
||||
#define BSP_USING_TIMER
|
||||
#define BSP_USING_TMR0
|
||||
#define BSP_USING_TMR1
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
import os
|
||||
ARCH = 'risc-v'
|
||||
CPU = 'ch56x'
|
||||
# toolchains options
|
||||
CROSS_TOOL = 'gcc'
|
||||
|
||||
#------- toolchains path -------------------------------------------------------
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/opt/mrs-riscv-none-embed/bin'
|
||||
else:
|
||||
print('Please make sure your toolchains is GNU GCC!')
|
||||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
#BUILD = 'debug'
|
||||
BUILD = 'release'
|
||||
|
||||
CORE = 'risc-v'
|
||||
MAP_FILE = 'rtthread.map'
|
||||
LINK_FILE = './board/linker_scripts/link.lds'
|
||||
TARGET_NAME = 'rtthread.bin'
|
||||
|
||||
#------- GCC settings ----------------------------------------------------------
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'riscv-none-embed-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX= PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L. -nostartfiles -lc '
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' -save-temps=obj'
|
||||
AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE
|
||||
LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
|
||||
LFLAGS += ' -T ' + LINK_FILE
|
||||
LFLAGS += ' -Wl,-wrap=memset'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -g3'
|
||||
AFLAGS += ' -g3'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
|
||||
POST_ACTION += SIZE + ' $TARGET\n'
|
||||
@@ -24,7 +24,7 @@ else :
|
||||
# cpu porting code files
|
||||
if rtconfig.CPU == "e9xx" :
|
||||
group = group + SConscript(os.path.join(rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
|
||||
else :
|
||||
elif rtconfig.CPU in list:
|
||||
group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
|
||||
@@ -138,7 +138,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
* #endif
|
||||
*/
|
||||
#ifndef RT_USING_SMP
|
||||
void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
|
||||
RT_WEAK void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
|
||||
{
|
||||
if (rt_thread_switch_interrupt_flag == 0)
|
||||
rt_interrupt_from_thread = from;
|
||||
|
||||
Reference in New Issue
Block a user