mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-02-06 00:45:22 +08:00
[add] add msp432e401y-LaunchPad BSP v0.1
This commit is contained in:
yby
committed by
Man, Jianting (Meco)
Man, Jianting (Meco)
parent
8f164529a3
commit
c7d1a0f7cd
1
.github/workflows/action.yml
vendored
1
.github/workflows/action.yml
vendored
@@ -263,6 +263,7 @@ jobs:
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- "lm4f232"
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- "tm4c123bsp"
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- "tm4c129x"
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- "msp432e401y-LaunchPad"
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- "microchip/samc21"
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- "microchip/same54"
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- "microchip/same70"
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@@ -51,6 +51,7 @@ RT-THREAD bsp company list
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- [lm3s8962](lm3s8962)
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- [dm365](dm365)
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- [beaglebone](beaglebone)
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- [msp432e401y-LaunchPad](msp432e401y-LaunchPad)
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- Samsung
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- [wh44b0](wh44b0)
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- [mini4020](mini4020)
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993
bsp/msp432e401y-LaunchPad/.config
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993
bsp/msp432e401y-LaunchPad/.config
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File diff suppressed because it is too large
Load Diff
42
bsp/msp432e401y-LaunchPad/.gitignore
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42
bsp/msp432e401y-LaunchPad/.gitignore
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@@ -0,0 +1,42 @@
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*.pyc
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*.map
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*.dblite
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*.elf
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*.bin
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*.hex
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*.axf
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*.exe
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*.pdb
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*.idb
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*.ilk
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*.old
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build
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Debug
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documentation/html
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packages/
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*~
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*.o
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*.obj
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*.out
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*.bak
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*.dep
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*.lib
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*.i
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*.d
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.DS_Stor*
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.config 3
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.config 4
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.config 5
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Midea-X1
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*.uimg
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GPATH
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GRTAGS
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GTAGS
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.vscode
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JLinkLog.txt
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JLinkSettings.ini
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DebugConfig/
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RTE/
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settings/
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*.uvguix*
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cconfig.h
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21
bsp/msp432e401y-LaunchPad/Kconfig
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21
bsp/msp432e401y-LaunchPad/Kconfig
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@@ -0,0 +1,21 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "board/Kconfig"
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123
bsp/msp432e401y-LaunchPad/README.md
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123
bsp/msp432e401y-LaunchPad/README.md
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@@ -0,0 +1,123 @@
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# MSP432E401Y BSP
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## 简介
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本文档为 MSP-EXP432E401Y LaunchPad 开发板的 BSP (板级支持包) 说明。
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主要内容如下：
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- 开发板资源介绍
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- BSP 快速上手
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- 进阶使用方法
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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## 开发板介绍
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开发板外观如下图所示：
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该开发板常用 **板载资源** 如下：
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- MCU：SimpleLink MSP432E401Y ARM® Cortex® -M4F 微控制器，主频 120MHz，1024KB FLASH ，256KB RAM
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- 外部 RAM：型号，xMB
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- 外部 FLASH：型号，xMB
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- 常用外设
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- LED：4个，（PN0,PN1,PF0,PF4）
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- 按键：用户按键2个，SW1（PJ0），SW2（PJ1）
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- 常用接口：以太网 MAC，以太网 PHY，通用串行总线 (USB)，8 个通用异步接收器/发射器 (UART)， 个四通道同步串行接口 (QSSI)，提供高速模式支持的 10 个内部集成电路 (I2C) 模块，2 个 CAN 2.0 A 和 B 控制器等
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- 调试接口，板载 XDS-110 调试探针，JTAG 和串行线调试 (SWD)
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开发板更多详细信息请参考【TI】
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[MSP-EXP432E401Y 开发套件](https://www.ti.com.cn/tool/cn/MSP-EXP432E401Y#description)。
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[MSP-EXP432E401Y SDK包](https://www.ti.com/tool/SIMPLELINK-MSP432-SDK)。
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## 外设支持
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本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :----------------- | :----------: | :------------------------------------- |
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| USB 转串口 | 支持 | |
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| LED | 支持 | |
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| 以太网 | 暂不支持 | |
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| CAN | 暂不支持 | |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | 从PA0开始重新编号 |
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| UART | 支持 | UART0/1/2/3 |
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| SPI | 暂不支持 | |
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| I2C | 暂不支持 | |
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| SDIO | 暂不支持 | |
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| RTC | 暂不支持 | |
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| PWM | 暂不支持 | |
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| USB Device | 暂不支持 | |
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| USB Host | 暂不支持 | |
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| IWG | 暂不支持 | |
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| **扩展模块** | **支持情况** | **备注** |
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| xxx 模块 | 支持 | |
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## 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 快速上手
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本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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#### 硬件连接
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使用数据线连接开发板到 PC，打开电源开关。
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#### 编译下载
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双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
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> 工程默认配置使用 XDS 下载程序，在通过USB连接开发板的基础上，点击下载按钮即可下载程序到开发板
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#### 运行结果
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下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。
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连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 3.1.1 build Nov 19 2018
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2006 - 2018 Copyright by rt-thread team
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msh >
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```
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### 进阶使用
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此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
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1. 在 bsp 下打开 env 工具。
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2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
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3. 输入`pkgs --update`命令更新软件包。
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4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
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本章节更多详细的介绍请结合 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)学习使用。
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## 注意事项
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- 本BSP配置片上外设在board/board.c中进行配置。配置时钟在board.c文件中进行
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## 联系人信息
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维护人:
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- [yby](https://github.com/yby-oy), 邮箱：<1632443748@qq.com>
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15
bsp/msp432e401y-LaunchPad/SConscript
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15
bsp/msp432e401y-LaunchPad/SConscript
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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63
bsp/msp432e401y-LaunchPad/SConstruct
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63
bsp/msp432e401y-LaunchPad/SConstruct
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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# if not os.getenv("RTT_ROOT"):
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# RTT_ROOT="rt-thread"
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM in ['iccarm']:
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env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(SDK_ROOT + '/libraries'):
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libraries_path_prefix = SDK_ROOT + '/libraries'
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else:
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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msp432e401y_library = 'msp432e4'
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rtconfig.BSP_LIBRARY_TYPE = msp432e401y_library
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, msp432e401y_library, 'SConscript')))
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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11
bsp/msp432e401y-LaunchPad/applications/SConscript
Normal file
11
bsp/msp432e401y-LaunchPad/applications/SConscript
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@@ -0,0 +1,11 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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42
bsp/msp432e401y-LaunchPad/applications/main.c
Normal file
42
bsp/msp432e401y-LaunchPad/applications/main.c
Normal file
@@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-07-15 yby the first version
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*/
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#include "board.h"
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#define LED_N0 rt_pin_get("PN.0")
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#define LED_N1 rt_pin_get("PN.1")
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#define LED_F0 GET_PIN(F, 0)
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#define LED_F4 GET_PIN(F, 4)
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int main(void)
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{
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rt_uint32_t count = 1;
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rt_pin_mode(LED_N0, PIN_MODE_OUTPUT);
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rt_pin_mode(LED_N1, PIN_MODE_OUTPUT);
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rt_pin_mode(LED_F0, PIN_MODE_OUTPUT);
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rt_pin_mode(LED_F4, PIN_MODE_OUTPUT);
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while (count++)
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{
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rt_pin_write(LED_N0, PIN_HIGH);
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rt_pin_write(LED_N1, PIN_HIGH);
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rt_pin_write(LED_F0, PIN_HIGH);
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rt_pin_write(LED_F4, PIN_HIGH);
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rt_thread_mdelay(1000);
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rt_pin_write(LED_N0, PIN_LOW);
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rt_pin_write(LED_N1, PIN_LOW);
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rt_pin_write(LED_F0, PIN_LOW);
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rt_pin_write(LED_F4, PIN_LOW);
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rt_thread_mdelay(1000);
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}
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return RT_EOK;
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}
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58
bsp/msp432e401y-LaunchPad/board/Kconfig
Normal file
58
bsp/msp432e401y-LaunchPad/board/Kconfig
Normal file
@@ -0,0 +1,58 @@
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menu "Hardware Drivers Config"
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config msp432e401y
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bool
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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menu "On-chip Peripheral Drivers"
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config BSP_USING_GPIO
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bool "Enable GPIO"
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select RT_USING_PIN
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default y
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menuconfig BSP_USING_UART
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bool "Enable UART"
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default y
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select RT_USING_SERIAL
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if BSP_USING_UART
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config BSP_USING_UART0
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bool "Enable UART0"
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default y
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config BSP_USING_UART1
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bool "Enable UART1"
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default n
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config BSP_UART1_RX_USING_DMA
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bool "Enable UART1 RX DMA"
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depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
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default n
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config BSP_USING_UART2
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bool "Enable UART2"
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default n
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config BSP_UART2_RX_USING_DMA
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bool "Enable UART2 RX DMA"
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depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
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default n
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config BSP_USING_UART3
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bool "Enable UART3"
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default n
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config BSP_UART3_RX_USING_DMA
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bool "Enable UART3 RX DMA"
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depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
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default n
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endif
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endmenu
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menu "Board extended module Drivers"
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endmenu
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endmenu
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30
bsp/msp432e401y-LaunchPad/board/SConscript
Normal file
30
bsp/msp432e401y-LaunchPad/board/SConscript
Normal file
@@ -0,0 +1,30 @@
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import os
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import rtconfig
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from building import *
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Import('SDK_LIB')
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cwd = GetCurrentDir()
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# add general drivers
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src = Split('''
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board.c
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''')
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path = [cwd]
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startup_path_prefix = SDK_LIB
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if rtconfig.PLATFORM in ['gcc']:
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src += [startup_path_prefix + '/msp432e4/startup_system_files/gcc/startup_msp432e401y_gcc.c']
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elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
src += [startup_path_prefix + '/msp432e4/startup_system_files/keil/startup_msp432e401y_uvision.s']
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src += [startup_path_prefix + '/libraries/msp432e4/startup_system_files/iar/startup_msp432e401y_ewarm.c']
|
||||
|
||||
|
||||
CPPDEFINES = ['__MSP432E401Y__']
|
||||
if rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
CPPDEFINES += ['rvmdk']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
Return('group')
|
||||
77
bsp/msp432e401y-LaunchPad/board/board.c
Normal file
77
bsp/msp432e401y-LaunchPad/board/board.c
Normal file
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-07-15 yby the first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
void uart_hw_config(void)
|
||||
{
|
||||
#ifdef BSP_USING_UART0
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
|
||||
GPIOPinConfigure(GPIO_PA0_U0RX);
|
||||
GPIOPinConfigure(GPIO_PA1_U0TX);
|
||||
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* this funtion set the Systick and enable systick int */
|
||||
void SystemClock_Config()
|
||||
{
|
||||
/* System Clock Update */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
SysTickDisable();
|
||||
SysTickPeriodSet(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
SysTickIntEnable();
|
||||
SysTickEnable();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial your board.
|
||||
*/
|
||||
void rt_hw_board_init()
|
||||
{
|
||||
/* System clock initialization */
|
||||
SystemClock_Config();
|
||||
|
||||
/* Heap initialization */
|
||||
#if defined(RT_USING_HEAP)
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
/* Pin driver initialization is open by default */
|
||||
#ifdef RT_USING_PIN
|
||||
rt_hw_pin_init();
|
||||
#endif
|
||||
|
||||
/* USART driver initialization is open by default */
|
||||
#ifdef RT_USING_SERIAL
|
||||
rt_hw_usart_init();
|
||||
#endif
|
||||
|
||||
/* Set the shell console output device */
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
/* Board underlying hardware initialization */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
rt_tick_increase();
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
63
bsp/msp432e401y-LaunchPad/board/board.h
Normal file
63
bsp/msp432e401y-LaunchPad/board/board.h
Normal file
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-07-15 yby the first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <msp.h>
|
||||
#include "hw_sysctl.h"
|
||||
#include "sysctl.h"
|
||||
#include "systick.h"
|
||||
#include "gpio.h"
|
||||
#include "pin_map.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define MSP432_FLASH_START_ADRESS ((rt_uint32_t)0x00000000)
|
||||
#define MSP432_FLASH_SIZE (1024 * 1024)
|
||||
#define MSP432_FLASH_END_ADDRESS ((rt_uint32_t)(MSP432_FLASH_START_ADRESS + MSP432_FLASH_SIZE))
|
||||
|
||||
#define MSP432_SRAM_SIZE 256
|
||||
#define MSP432_SRAM_END (0x20000000 + MSP432_SRAM_SIZE * 1024)
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __end;
|
||||
#define HEAP_BEGIN ((void *)&__end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END MSP432_SRAM_END
|
||||
|
||||
void uart_hw_config(void);
|
||||
|
||||
#ifdef RT_USING_PIN
|
||||
#include "drv_gpio.h"
|
||||
#endif /* RT_USING_PIN */
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
#include "drv_uart.h"
|
||||
#endif /* RT_USING_SERIAL */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__BOARD_H__*/
|
||||
57
bsp/msp432e401y-LaunchPad/board/linker_scripts/link.icf
Normal file
57
bsp/msp432e401y-LaunchPad/board/linker_scripts/link.icf
Normal file
@@ -0,0 +1,57 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0000;
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
|
||||
define region EROM_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]
|
||||
| mem:[from __ICFEDIT_region_EROM2_start__ to __ICFEDIT_region_EROM2_end__]
|
||||
| mem:[from __ICFEDIT_region_EROM3_start__ to __ICFEDIT_region_EROM3_end__];
|
||||
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__]
|
||||
| mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__];
|
||||
|
||||
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in IROM_region { readonly };
|
||||
place in EROM_region { readonly section application_specific_ro };
|
||||
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
|
||||
place in ERAM_region { readwrite section application_specific_rw };
|
||||
157
bsp/msp432e401y-LaunchPad/board/linker_scripts/link.lds
Normal file
157
bsp/msp432e401y-LaunchPad/board/linker_scripts/link.lds
Normal file
@@ -0,0 +1,157 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00100000
|
||||
SRAM (WX) : ORIGIN = 0x20000000, LENGTH = 0x00040000
|
||||
}
|
||||
|
||||
REGION_ALIAS("REGION_TEXT", FLASH);
|
||||
REGION_ALIAS("REGION_BSS", SRAM);
|
||||
REGION_ALIAS("REGION_DATA", SRAM);
|
||||
REGION_ALIAS("REGION_STACK", SRAM);
|
||||
REGION_ALIAS("REGION_HEAP", SRAM);
|
||||
REGION_ALIAS("REGION_ARM_EXIDX", FLASH);
|
||||
REGION_ALIAS("REGION_ARM_EXTAB", FLASH);
|
||||
|
||||
SECTIONS {
|
||||
|
||||
/* section for the interrupt vector area */
|
||||
PROVIDE (_intvecs_base_address =
|
||||
DEFINED(_intvecs_base_address) ? _intvecs_base_address : 0x0);
|
||||
|
||||
.intvecs (_intvecs_base_address) : AT (_intvecs_base_address) {
|
||||
KEEP (*(.intvecs))
|
||||
} > REGION_TEXT
|
||||
|
||||
PROVIDE (_vtable_base_address =
|
||||
DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000);
|
||||
|
||||
.vtable (_vtable_base_address) : AT (_vtable_base_address) {
|
||||
KEEP (*(.vtable))
|
||||
} > REGION_DATA
|
||||
|
||||
.text : {
|
||||
CREATE_OBJECT_SYMBOLS
|
||||
KEEP (*(.text))
|
||||
*(.text.*)
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*(.ctors))
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*(.dtors))
|
||||
. = ALIGN(0x4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(.init_array*))
|
||||
__init_array_end = .;
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini*))
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
} > REGION_TEXT AT> REGION_TEXT
|
||||
|
||||
.rodata : {
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
} > REGION_TEXT AT> REGION_TEXT
|
||||
|
||||
.ARM.exidx : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
|
||||
|
||||
.ARM.extab : {
|
||||
KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*))
|
||||
} > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : {
|
||||
__data_load__ = LOADADDR (.data);
|
||||
__data_start__ = .;
|
||||
KEEP (*(.data))
|
||||
KEEP (*(.data*))
|
||||
. = ALIGN (4);
|
||||
__data_end__ = .;
|
||||
} > REGION_DATA AT> REGION_TEXT
|
||||
|
||||
.bss : {
|
||||
__bss_start__ = .;
|
||||
*(.shbss)
|
||||
KEEP (*(.bss))
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN (4);
|
||||
__bss_end__ = .;
|
||||
} > REGION_BSS AT> REGION_BSS
|
||||
|
||||
.heap : {
|
||||
__heap_start__ = .;
|
||||
end = __heap_start__;
|
||||
_end = end;
|
||||
__end = end;
|
||||
KEEP (*(.heap))
|
||||
__heap_end__ = .;
|
||||
__HeapLimit = __heap_end__;
|
||||
} > REGION_HEAP AT> REGION_HEAP
|
||||
|
||||
.stack (NOLOAD) : ALIGN(0x8) {
|
||||
_stack = .;
|
||||
KEEP(*(.stack))
|
||||
} > REGION_STACK AT> REGION_STACK
|
||||
|
||||
__StackTop = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
__end = .;
|
||||
}
|
||||
15
bsp/msp432e401y-LaunchPad/board/linker_scripts/link.sct
Normal file
15
bsp/msp432e401y-LaunchPad/board/linker_scripts/link.sct
Normal file
@@ -0,0 +1,15 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x00100000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00100000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00040000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
BIN
bsp/msp432e401y-LaunchPad/figures/board.jpg
Normal file
BIN
bsp/msp432e401y-LaunchPad/figures/board.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 169 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,267 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// MSP432 Family CMSIS Definitions
|
||||
//
|
||||
//****************************************************************************
|
||||
|
||||
#ifndef CMSIS_CCS_H_
|
||||
#define CMSIS_CCS_H_
|
||||
|
||||
#ifndef __TI_ARM__
|
||||
#error This file should only be compiled by TI compiler (minimum version 15.12.x)
|
||||
#endif
|
||||
|
||||
/** CMSIS compiler control architecture macros */
|
||||
#if defined ( __TI_ARM_V6M0__ )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if defined ( __TI_ARM_V7M3__ )
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if defined ( __TI_ARM_V7M4__ )
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
* \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Enable IRQ Interrupts
|
||||
* \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
* Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_irq _enable_IRQ
|
||||
|
||||
/**
|
||||
* \brief Disable IRQ Interrupts
|
||||
* \details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
* Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_irq _disable_IRQ
|
||||
|
||||
/** @} */ /* end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
* Access to dedicated instructions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Count leading zeros
|
||||
* \details Counts the number of leading zeros of a data value.
|
||||
* \param [in] VAL Value to count the leading zeros
|
||||
* \return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ(VAL) ((unsigned char)__clz(VAL))
|
||||
|
||||
/**
|
||||
* \brief Signed Saturate
|
||||
* \details Saturates a signed value.
|
||||
* \param [in] VAL Value to be saturated
|
||||
* \param [in] BITPOS Bit position to saturate to (1..32)
|
||||
* \return Saturated value
|
||||
*/
|
||||
#define __SSAT(VAL, BITPOS) _ssatl(VAL, 0, BITPOS)
|
||||
|
||||
/**
|
||||
* \brief No Operation
|
||||
* \details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
/**
|
||||
* \brief Wait For Interrupt
|
||||
* \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
* \brief Wait For Event
|
||||
* \details Wait For Event is a hint instruction that permits the processor to enter
|
||||
* a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
/**
|
||||
* \brief Data Synchronization Barrier
|
||||
* \details Acts as a special kind of Data Memory Barrier.
|
||||
* It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
|
||||
#define __DSB _dsb
|
||||
/**
|
||||
* \brief Instruction Synchronization Barrier
|
||||
* \details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
* so that all instructions following the ISB are fetched from cache or memory,
|
||||
* after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB _isb
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB _dmb
|
||||
/**
|
||||
* \brief Rotate Right in unsigned value (32 bit)
|
||||
* \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
* \param [in] VAL Value to rotate
|
||||
* \param [in] SHIFT Number of Bits to rotate
|
||||
* \return Rotated value
|
||||
*/
|
||||
#define __ROR(VAL, SHIFT) ((unsigned int)__ror(VAL, SHIFT))
|
||||
|
||||
/** @} */ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
* Access to dedicated SIMD instructions
|
||||
* @{
|
||||
*/
|
||||
#if (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))
|
||||
|
||||
#define __SADD8(VAL1, VAL2) ((unsigned int)_sadd8(VAL1, VAL2))
|
||||
#define __QADD8(VAL1, VAL2) ((unsigned int)_qadd8(VAL1, VAL2))
|
||||
#define __SHADD8(VAL1, VAL2) ((unsigned int)_shadd8(VAL1, VAL2))
|
||||
#define __UADD8(VAL1, VAL2) ((unsigned int)_uadd8(VAL1, VAL2))
|
||||
#define __UQADD8(VAL1, VAL2) ((unsigned int)_uqadd8(VAL1, VAL2))
|
||||
#define __UHADD8(VAL1, VAL2) ((unsigned int)_uhadd8(VAL1, VAL2))
|
||||
#define __SSUB8(VAL1, VAL2) ((unsigned int)_ssub8(VAL1, VAL2))
|
||||
#define __QSUB8(VAL1, VAL2) ((unsigned int)_qsub8(VAL1, VAL2))
|
||||
#define __SHSUB8(VAL1, VAL2) ((unsigned int)_shsub8(VAL1, VAL2))
|
||||
#define __USUB8(VAL1, VAL2) ((unsigned int)_usub8(VAL1, VAL2))
|
||||
#define __UQSUB8(VAL1, VAL2) ((unsigned int)_uqsub8(VAL1, VAL2))
|
||||
#define __UHSUB8(VAL1, VAL2) ((unsigned int)_uhsub8(VAL1, VAL2))
|
||||
#define __SADD16(VAL1, VAL2) ((unsigned int)_sadd16(VAL1, VAL2))
|
||||
#define __QADD16(VAL1, VAL2) ((unsigned int)_qadd16(VAL1, VAL2))
|
||||
#define __SHADD16(VAL1, VAL2) ((unsigned int)_shadd16(VAL1, VAL2))
|
||||
#define __UADD16(VAL1, VAL2) ((unsigned int)_uadd16(VAL1, VAL2))
|
||||
#define __UQADD16(VAL1, VAL2) ((unsigned int)_uqadd16(VAL1, VAL2))
|
||||
#define __UHADD16(VAL1, VAL2) ((unsigned int)_uhadd16(VAL1, VAL2))
|
||||
#define __SSUB16(VAL1, VAL2) ((unsigned int)_ssub16(VAL1, VAL2))
|
||||
#define __QSUB16(VAL1, VAL2) ((unsigned int)_qsub16(VAL1, VAL2))
|
||||
#define __SHSUB16(VAL1, VAL2) ((unsigned int)_shsub16(VAL1, VAL2))
|
||||
#define __USUB16(VAL1, VAL2) ((unsigned int)_usub16(VAL1, VAL2))
|
||||
#define __UQSUB16(VAL1, VAL2) ((unsigned int)_uqsub16(VAL1, VAL2))
|
||||
#define __UHSUB16(VAL1, VAL2) ((unsigned int)_uhsub16(VAL1, VAL2))
|
||||
#define __SASX(VAL1, VAL2) ((unsigned int)_saddsubx(VAL1, VAL2))
|
||||
#define __QASX(VAL1, VAL2) ((unsigned int)_qaddsubx(VAL1, VAL2))
|
||||
#define __SHASX(VAL1, VAL2) ((unsigned int)_shaddsubx(VAL1, VAL2))
|
||||
#define __UASX(VAL1, VAL2) ((unsigned int)_uaddsubx(VAL1, VAL2))
|
||||
#define __UQASX(VAL1, VAL2) ((unsigned int)_uqaddsubx(VAL1, VAL2))
|
||||
#define __UHASX(VAL1, VAL2) ((unsigned int)_uhaddsubx(VAL1, VAL2)))
|
||||
#define __SSAX(VAL1, VAL2) ((unsigned int)_ssubaddx(VAL1, VAL2))
|
||||
#define __QSAX(VAL1, VAL2) ((unsigned int)_qsubaddx(VAL1, VAL2))
|
||||
#define __SHSAX(VAL1, VAL2) ((unsigned int)_shsubaddx(VAL1, VAL2))
|
||||
#define __USAX(VAL1, VAL2) ((unsigned int)_usubaddx(VAL1, VAL2))
|
||||
#define __UQSAX(VAL1, VAL2) ((unsigned int)_uqsubaddx(VAL1, VAL2))
|
||||
#define __UHSAX(VAL1, VAL2) ((unsigned int)_uhsubaddx(VAL1, VAL2))
|
||||
#define __USAD8(VAL1, VAL2) ((unsigned int)_usad8(VAL1, VAL2))
|
||||
#define __USADA8(VAL1, VAL2, VAL3) ((unsigned int)_usada8(VAL1, VAL2, VAL3))
|
||||
#define __SSAT16(VAL, BITPOS) ((unsigned int)_ssat16(VAL, BITPOS))
|
||||
#define __USAT16(VAL, BITPOS) ((unsigned int)_usat16(VAL, BITPOS))
|
||||
#define __UXTB16(VAL) ((unsigned int)_uxtb16(VAL, 0))
|
||||
#define __UXTAB16(VAL1, VAL2) ((unsigned int)_uxtab16(VAL1, VAL2, 0))
|
||||
#define __SXTB16(VAL) ((unsigned int)_sxtb16(VAL, 0))
|
||||
#define __SXTAB16(VAL1, VAL2) ((unsigned int)_sxtab16(VAL1, VAL2, 0))
|
||||
#define __SMUAD(VAL1, VAL2) ((unsigned int)_smuad(VAL1, VAL2))
|
||||
#define __SMUADX(VAL1, VAL2) ((unsigned int)_smuadx(VAL1, VAL2))
|
||||
#define __SMLAD(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlad(VAL1, VAL2, ACCUMULATOR))
|
||||
#define __SMLADX(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smladx(VAL1, VAL2, ACCUMULATOR))
|
||||
#define __SMLALD(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlald(ACCUMULATOR, VAL1, VAL2))
|
||||
#define __SMLALDX(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlaldx(ACCUMULATOR, VAL1, VAL2))
|
||||
#define __SMUSD(VAL1, VAL2) ((unsigned int)_smusd(VAL1, VAL2))
|
||||
#define __SMUSDX(VAL1, VAL2) ((unsigned int)_smusdx(VAL1, VAL2))
|
||||
#define __SMLSD(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlsd(VAL1, VAL2, ACCUMULATOR))
|
||||
#define __SMLSDX(VAL1, VAL2, ACCUMULATOR) ((unsigned int)_smlsdx(VAL1, VAL2, ACCUMULATOR))
|
||||
#define __SMLSLD(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlsld(ACCUMULATOR, VAL1, VAL2))
|
||||
#define __SMLSLDX(VAL1, VAL2, ACCUMULATOR) ((unsigned long long)_smlsldx(ACCUMULATOR, VAL1, VAL2))
|
||||
#define __SEL(VAL1, VAL2) ((unsigned int)_sel(VAL1, VAL2))
|
||||
#define __QADD _sadd
|
||||
#define __QSUB _ssub
|
||||
#define __PKHBT _pkhbt
|
||||
#define __PKHTB _pkhtb
|
||||
#define __SMMLA _smmla
|
||||
|
||||
#define __QDADD _sdadd
|
||||
#define __QDSUB _sdsub
|
||||
#define __SMLABB _smlabb
|
||||
#define __SMLABT _smlabt
|
||||
#define __SMLALBB _smlalbb
|
||||
#define __SMLALBT _smlalbt
|
||||
#define __SMLALTB _smlaltb
|
||||
#define __SMLALTT _smlaltt
|
||||
#define __SMLATB _smlatb
|
||||
#define __SMLATT _smlatt
|
||||
#define __SMLAWB _smlawb
|
||||
#define __SMLAWT _smlawt
|
||||
#define __SMULBB _smulbb
|
||||
#define __SMULBT _smulbt
|
||||
#define __SMULTB _smultb
|
||||
#define __SMULTT _smultt
|
||||
#define __SMULWB _smulwb
|
||||
#define __SMULWT _smulwt
|
||||
#define __SMMLAR _smmlar
|
||||
#define __SMMLS _smmls
|
||||
#define __SMMLSR _smmlsr
|
||||
#define __SMMUL _smmul
|
||||
#define __SMMULR _smmulr
|
||||
#define __SXTAB _sxtab
|
||||
#define __SXTAH _sxtah
|
||||
#define __UMAAL _umaal
|
||||
#define __UXTAB _uxtab
|
||||
#define __UXTAH _uxtah
|
||||
#define __SUBC _subc
|
||||
|
||||
#endif /* (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) */
|
||||
|
||||
#if (defined (__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1))
|
||||
|
||||
#define __SXTB _sxtb
|
||||
#define __SXTH _sxth
|
||||
#define __UXTB _uxtb
|
||||
#define __UXTH _uxth
|
||||
|
||||
#endif /* (defined (__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1)) */
|
||||
|
||||
/** @} */ /* end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
#endif /* CMSIS_CCS_H_ */
|
||||
@@ -0,0 +1,280 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32
|
||||
{
|
||||
uint32_t v;
|
||||
};
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32
|
||||
{
|
||||
uint32_t v;
|
||||
};
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32
|
||||
{
|
||||
uint32_t v;
|
||||
};
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
1934
bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/core_cm3.h
Normal file
1934
bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
2121
bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/core_cm4.h
Normal file
2121
bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2720
bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/core_cm7.h
Normal file
2720
bsp/msp432e401y-LaunchPad/libraries/Drivers/CMSIS/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,274 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t) / 4U;
|
||||
while (cnt > MPU_TYPE_RALIASES)
|
||||
{
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES * rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt * rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,352 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type *mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0])))
|
||||
{
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type *mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t) / 4U;
|
||||
if (cnt == 1U)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES - 1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES)
|
||||
{
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR) + (rnrOffset * 2U), &(table->RBAR), c * rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR) + (rnrOffset * 2U), &(table->RBAR), cnt * rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S(void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S(TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S(TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S(TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S(TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
22
bsp/msp432e401y-LaunchPad/libraries/Drivers/SConscript
Normal file
22
bsp/msp432e401y-LaunchPad/libraries/Drivers/SConscript
Normal file
@@ -0,0 +1,22 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = []
|
||||
|
||||
if GetDepend(['RT_USING_PIN']):
|
||||
src += ['drv_gpio.c']
|
||||
|
||||
if GetDepend(['RT_USING_SERIAL']):
|
||||
src += ['drv_uart.c']
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/config',
|
||||
cwd + '/CMSIS/Include']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-07-15 yby the first version
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART0)
|
||||
#ifndef UART0_CONFIG
|
||||
#define UART0_CONFIG \
|
||||
{ \
|
||||
.name = "uart0", \
|
||||
.uartbase = UART0_BASE, \
|
||||
.baudrate = 115200, \
|
||||
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
|
||||
UART_CONFIG_PAR_NONE \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1*/
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.uartbase = UART1_BASE, \
|
||||
.baudrate = 115200, \
|
||||
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
|
||||
UART_CONFIG_PAR_NONE \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1*/
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.uartbase = UART2_BASE, \
|
||||
.baudrate = 115200, \
|
||||
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
|
||||
UART_CONFIG_PAR_NONE \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
#endif /* BSP_USING_UART2*/
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.uartbase = UART3_BASE, \
|
||||
.baudrate = 115200, \
|
||||
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
|
||||
UART_CONFIG_PAR_NONE \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
#endif /* BSP_USING_UART3*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __UART_CONFIG_H__ */
|
||||
|
||||
/************************** end of file ******************/
|
||||
383
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.c
Normal file
383
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.c
Normal file
@@ -0,0 +1,383 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-07-15 yby the first version
|
||||
*/
|
||||
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef RT_USING_PIN
|
||||
|
||||
#define _MSP432_PIN(index, gpioport, gpio_index) \
|
||||
{ \
|
||||
index, GPIO_PORT##gpioport##_BASE, GPIO_PIN_##gpio_index \
|
||||
}
|
||||
|
||||
static const struct pin_index _msp432_pins[] =
|
||||
{
|
||||
/* GPIOA 0~7 */
|
||||
_MSP432_PIN(0, A, 0),
|
||||
_MSP432_PIN(1, A, 1),
|
||||
_MSP432_PIN(2, A, 2),
|
||||
_MSP432_PIN(3, A, 3),
|
||||
_MSP432_PIN(4, A, 4),
|
||||
_MSP432_PIN(5, A, 5),
|
||||
_MSP432_PIN(6, A, 6),
|
||||
_MSP432_PIN(7, A, 7),
|
||||
/* GPIOB 0~5 */
|
||||
_MSP432_PIN(8, B, 0),
|
||||
_MSP432_PIN(9, B, 1),
|
||||
_MSP432_PIN(10, B, 2),
|
||||
_MSP432_PIN(11, B, 3),
|
||||
_MSP432_PIN(12, B, 4),
|
||||
_MSP432_PIN(13, B, 5),
|
||||
/* GPIOC 0~7 */
|
||||
_MSP432_PIN(14, C, 0),
|
||||
_MSP432_PIN(15, C, 1),
|
||||
_MSP432_PIN(16, C, 2),
|
||||
_MSP432_PIN(17, C, 3),
|
||||
_MSP432_PIN(18, C, 4),
|
||||
_MSP432_PIN(19, C, 5),
|
||||
_MSP432_PIN(20, C, 6),
|
||||
_MSP432_PIN(21, C, 7),
|
||||
/* GPIOD 0~7 */
|
||||
_MSP432_PIN(22, D, 0),
|
||||
_MSP432_PIN(23, D, 1),
|
||||
_MSP432_PIN(24, D, 2),
|
||||
_MSP432_PIN(25, D, 3),
|
||||
_MSP432_PIN(26, D, 4),
|
||||
_MSP432_PIN(27, D, 5),
|
||||
_MSP432_PIN(28, D, 6),
|
||||
_MSP432_PIN(29, D, 7),
|
||||
/* GPIOE 0~5 */
|
||||
_MSP432_PIN(30, E, 0),
|
||||
_MSP432_PIN(31, E, 1),
|
||||
_MSP432_PIN(32, E, 2),
|
||||
_MSP432_PIN(33, E, 3),
|
||||
_MSP432_PIN(34, E, 4),
|
||||
_MSP432_PIN(35, E, 5),
|
||||
/* GPIOF 0~4 */
|
||||
_MSP432_PIN(36, F, 0),
|
||||
_MSP432_PIN(37, F, 1),
|
||||
_MSP432_PIN(38, F, 2),
|
||||
_MSP432_PIN(39, F, 3),
|
||||
_MSP432_PIN(40, F, 4),
|
||||
/* GPIOG 0~1 */
|
||||
_MSP432_PIN(41, G, 0),
|
||||
_MSP432_PIN(42, G, 1),
|
||||
/* GPIOH 0~3 */
|
||||
_MSP432_PIN(43, H, 0),
|
||||
_MSP432_PIN(44, H, 1),
|
||||
_MSP432_PIN(45, H, 0),
|
||||
_MSP432_PIN(46, H, 1),
|
||||
/* GPIOJ 0~1 */
|
||||
_MSP432_PIN(47, J, 0),
|
||||
_MSP432_PIN(48, J, 1),
|
||||
/* GPIOK 0~7 */
|
||||
_MSP432_PIN(49, K, 0),
|
||||
_MSP432_PIN(50, K, 1),
|
||||
_MSP432_PIN(51, K, 2),
|
||||
_MSP432_PIN(52, K, 3),
|
||||
_MSP432_PIN(53, K, 4),
|
||||
_MSP432_PIN(54, K, 5),
|
||||
_MSP432_PIN(55, K, 6),
|
||||
_MSP432_PIN(56, K, 7),
|
||||
/* GPIOL 0~7 */
|
||||
_MSP432_PIN(57, L, 0),
|
||||
_MSP432_PIN(58, L, 1),
|
||||
_MSP432_PIN(59, L, 2),
|
||||
_MSP432_PIN(60, L, 3),
|
||||
_MSP432_PIN(61, L, 4),
|
||||
_MSP432_PIN(62, L, 5),
|
||||
_MSP432_PIN(63, L, 6),
|
||||
_MSP432_PIN(64, L, 7),
|
||||
/* GPIOM 0~7 */
|
||||
_MSP432_PIN(65, M, 0),
|
||||
_MSP432_PIN(66, M, 1),
|
||||
_MSP432_PIN(67, M, 2),
|
||||
_MSP432_PIN(68, M, 3),
|
||||
_MSP432_PIN(69, M, 4),
|
||||
_MSP432_PIN(70, M, 5),
|
||||
_MSP432_PIN(71, M, 6),
|
||||
_MSP432_PIN(72, M, 7),
|
||||
/* GPION 0~5 */
|
||||
_MSP432_PIN(73, N, 0),
|
||||
_MSP432_PIN(74, N, 1),
|
||||
_MSP432_PIN(75, N, 2),
|
||||
_MSP432_PIN(76, N, 3),
|
||||
_MSP432_PIN(77, N, 4),
|
||||
_MSP432_PIN(78, N, 5),
|
||||
/* GPIOP 0~5 */
|
||||
_MSP432_PIN(79, P, 0),
|
||||
_MSP432_PIN(80, P, 1),
|
||||
_MSP432_PIN(81, P, 2),
|
||||
_MSP432_PIN(82, P, 3),
|
||||
_MSP432_PIN(83, P, 4),
|
||||
_MSP432_PIN(84, P, 5),
|
||||
/* GPIOQ 0~4 */
|
||||
_MSP432_PIN(85, Q, 0),
|
||||
_MSP432_PIN(86, Q, 1),
|
||||
_MSP432_PIN(87, Q, 2),
|
||||
_MSP432_PIN(88, Q, 3),
|
||||
_MSP432_PIN(89, Q, 4)
|
||||
};
|
||||
|
||||
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
|
||||
|
||||
static const struct pin_index *_get_pin(rt_base_t pin)
|
||||
{
|
||||
const struct pin_index *index = RT_NULL;
|
||||
|
||||
if (pin < ITEM_NUM(_msp432_pins))
|
||||
{
|
||||
index = &_msp432_pins[pin];
|
||||
}
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
static rt_base_t msp432_pin_get(const char *name)
|
||||
{
|
||||
rt_base_t pin = -1;
|
||||
|
||||
if ((name[0] == 'P') || (name[2] == '.'))
|
||||
{
|
||||
if (name[1] == 'A')
|
||||
{
|
||||
pin = name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'B')
|
||||
{
|
||||
pin = 8 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'C')
|
||||
{
|
||||
pin = 14 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'D')
|
||||
{
|
||||
pin = 22 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'E')
|
||||
{
|
||||
pin = 30 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'F')
|
||||
{
|
||||
pin = 36 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'G')
|
||||
{
|
||||
pin = 41 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'H')
|
||||
{
|
||||
pin = 43 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'J')
|
||||
{
|
||||
pin = 47 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'K')
|
||||
{
|
||||
pin = 49 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'L')
|
||||
{
|
||||
pin = 57 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'M')
|
||||
{
|
||||
pin = 65 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'N')
|
||||
{
|
||||
pin = 73 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'P')
|
||||
{
|
||||
pin = 79 + name[3] - '0';
|
||||
}
|
||||
else if (name[1] == 'Q')
|
||||
{
|
||||
pin = 85 + name[3] - '0';
|
||||
}
|
||||
else {}
|
||||
}
|
||||
|
||||
return pin;
|
||||
}
|
||||
|
||||
static void msp432_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
|
||||
{
|
||||
const struct pin_index *index = RT_NULL;
|
||||
|
||||
index = _get_pin(pin);
|
||||
if (index != RT_NULL)
|
||||
{
|
||||
if (mode == PIN_MODE_INPUT)
|
||||
{
|
||||
GPIOPinTypeGPIOInput(index->gpioBaseAddress, index->pin);
|
||||
}
|
||||
else if (mode == PIN_MODE_OUTPUT)
|
||||
{
|
||||
GPIOPinTypeGPIOOutput(index->gpioBaseAddress, index->pin);
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT_PULLUP)
|
||||
{
|
||||
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
|
||||
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT_PULLDOWN)
|
||||
{
|
||||
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
|
||||
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
|
||||
}
|
||||
else if (mode == PIN_MODE_OUTPUT_OD)
|
||||
{
|
||||
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
|
||||
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_OUT);
|
||||
}
|
||||
else {}
|
||||
}
|
||||
}
|
||||
|
||||
static void msp432_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
|
||||
{
|
||||
const struct pin_index *index = RT_NULL;
|
||||
|
||||
index = _get_pin(pin);
|
||||
if (index != RT_NULL)
|
||||
{
|
||||
if (value == PIN_HIGH)
|
||||
{
|
||||
GPIOPinWrite(index->gpioBaseAddress, index->pin, index->pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOPinWrite(index->gpioBaseAddress, index->pin, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static rt_int8_t msp432_pin_read(struct rt_device *device, rt_base_t pin)
|
||||
{
|
||||
const struct pin_index *index = RT_NULL;
|
||||
rt_int8_t value = -1;
|
||||
|
||||
index = _get_pin(pin);
|
||||
if (index != RT_NULL)
|
||||
{
|
||||
value = (rt_int8_t)GPIOPinRead(index->gpioBaseAddress, index->pin);
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static rt_err_t msp432_pin_attach_irq(struct rt_device *device, rt_base_t pin,
|
||||
rt_uint8_t mode, void (*hdr)(void *args), void *args)
|
||||
{
|
||||
/* this is interface for pin_irq, reserved for update. */
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t msp432_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
|
||||
{
|
||||
/* this is interface for pin_irq, reserved for update. */
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t msp432_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
|
||||
{
|
||||
/* this is interface for pin_irq_enable, reserved for update. */
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
const static struct rt_pin_ops _msp432_pin_ops =
|
||||
{
|
||||
msp432_pin_mode,
|
||||
msp432_pin_write,
|
||||
msp432_pin_read,
|
||||
msp432_pin_attach_irq,
|
||||
msp432_pin_dettach_irq,
|
||||
msp432_pin_irq_enable,
|
||||
msp432_pin_get,
|
||||
};
|
||||
|
||||
int rt_hw_pin_init(void)
|
||||
{
|
||||
int ret = -1;
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOA)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOB)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOC)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOD)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOE)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOF)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOG)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOH)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOJ)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOK)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOL)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOM)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPION)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOP)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOP);
|
||||
#endif
|
||||
|
||||
#if defined(SYSCTL_PERIPH_GPIOQ)
|
||||
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOQ);
|
||||
#endif
|
||||
|
||||
ret = rt_device_pin_register("pin", &_msp432_pin_ops, RT_NULL);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /*RT_USING_PIN*/
|
||||
|
||||
/************************** end of file ******************/
|
||||
33
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.h
Normal file
33
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_gpio.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-07-15 yby the first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_GPIO_H__
|
||||
#define __DRV_GPIO_H__
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#define _MSP432_STRING(x) #x
|
||||
#define _MSP432_PIN_NAME(PORTx,PIN) \
|
||||
("P" _MSP432_STRING(PORTx) "." _MSP432_STRING(PIN))
|
||||
#define GET_PIN(PORTx,PIN) rt_pin_get(_MSP432_PIN_NAME(PORTx,PIN))
|
||||
|
||||
/* MSP432 GPIO driver*/
|
||||
struct pin_index
|
||||
{
|
||||
rt_uint8_t index;
|
||||
rt_uint32_t gpioBaseAddress;
|
||||
rt_uint32_t pin;
|
||||
};
|
||||
|
||||
int rt_hw_pin_init(void);
|
||||
|
||||
#endif /*__DRV_GPIO_H__*/
|
||||
|
||||
/************************** end of file ******************/
|
||||
27
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_log.h
Normal file
27
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_log.h
Normal file
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-15 SummerGift first version
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: DO NOT include this file on the header file.
|
||||
*/
|
||||
|
||||
#ifndef LOG_TAG
|
||||
#define DBG_TAG "drv"
|
||||
#else
|
||||
#define DBG_TAG LOG_TAG
|
||||
#endif /* LOG_TAG */
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
#define DBG_LVL DBG_LOG
|
||||
#else
|
||||
#define DBG_LVL DBG_INFO
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
#include <rtdbg.h>
|
||||
258
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_uart.c
Normal file
258
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_uart.c
Normal file
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-07-15 yby the first version
|
||||
*/
|
||||
|
||||
#include "drv_uart.h"
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
#include "uart_config.h"
|
||||
#include "interrupt.h"
|
||||
#include "uart.h"
|
||||
|
||||
#define LOG_TAG "drv.uart"
|
||||
#include <drv_log.h>
|
||||
|
||||
#if !defined(BSP_USING_UART0)&&!defined(BSP_USING_UART1)&&!defined(BSP_USING_UART2)&&!defined(BSP_USING_UART3)
|
||||
#error "Please define at least one BSP_USING_UARTx"
|
||||
#endif
|
||||
|
||||
enum
|
||||
{
|
||||
#ifdef BSP_USING_UART0
|
||||
UART0_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART1
|
||||
UART1_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART2
|
||||
UART2_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART3
|
||||
UART3_INDEX,
|
||||
#endif
|
||||
};
|
||||
|
||||
uint32_t uart_intbase[] =
|
||||
{
|
||||
#ifdef BSP_USING_UART0
|
||||
INT_UART0,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART1
|
||||
INT_UART1,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART2
|
||||
INT_UART2,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART3
|
||||
INT_UART3
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct msp432_uart_config uart_config[] =
|
||||
{
|
||||
#ifdef BSP_USING_UART0
|
||||
UART0_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART1
|
||||
UART1_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART2
|
||||
UART2_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_UART3
|
||||
UART3_CONFIG,
|
||||
#endif
|
||||
};
|
||||
static struct msp432_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
|
||||
|
||||
static rt_err_t msp432_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct msp432_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
uart = rt_container_of(serial, struct msp432_uart, serial);
|
||||
|
||||
UARTConfigSetExpClk(uart->config->uartbase, SystemCoreClock, uart->config->baudrate,
|
||||
uart->config->mode);
|
||||
UARTIntEnable(uart->config->uartbase, UART_INT_RX);
|
||||
UARTEnable(uart->config->uartbase);
|
||||
UARTFIFODisable(uart->config->uartbase);
|
||||
IntEnable(uart->uartintbase);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
static rt_err_t msp432_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct msp432_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = rt_container_of(serial, struct msp432_uart, serial);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
/* disable interrupt */
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
IntDisable(uart->uartintbase);
|
||||
UARTIntDisable(uart->config->uartbase, UART_INT_RX);
|
||||
break;
|
||||
/* enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
IntEnable(uart->uartintbase);
|
||||
UARTIntEnable(uart->config->uartbase, UART_INT_RX);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int msp432_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct msp432_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
uart = rt_container_of(serial, struct msp432_uart, serial);
|
||||
UARTCharPut(uart->config->uartbase, c);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int msp432_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch;
|
||||
struct msp432_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
uart = rt_container_of(serial, struct msp432_uart, serial);
|
||||
ch = -1;
|
||||
ch = UARTCharGetNonBlocking(uart->config->uartbase);
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static rt_ssize_t msp432_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
|
||||
{
|
||||
/* this is an interface for uart dma, reserved for uptate. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops msp432_uart_ops =
|
||||
{
|
||||
.configure = msp432_configure,
|
||||
.control = msp432_control,
|
||||
.putc = msp432_putc,
|
||||
.getc = msp432_getc,
|
||||
.dma_transmit = msp432_dma_transmit
|
||||
};
|
||||
|
||||
/**
|
||||
* Uart common interrupt process. This need add to uart ISR.
|
||||
*
|
||||
* @param serial serial device
|
||||
*/
|
||||
static void uart_isr(struct rt_serial_device *serial)
|
||||
{
|
||||
struct msp432_uart *uart;
|
||||
uint32_t ui32Ints;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = rt_container_of(serial, struct msp432_uart, serial);
|
||||
|
||||
ui32Ints = UARTIntStatus(uart->config->uartbase, true);
|
||||
UARTIntClear(uart->config->uartbase, ui32Ints);
|
||||
|
||||
/* UART in mode Receiver -------------------------------------------------*/
|
||||
if (ui32Ints & (UART_INT_RX | UART_INT_RT))
|
||||
{
|
||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(BSP_USING_UART0)
|
||||
void UART0_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART0_INDEX].serial));
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_UART0 */
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
void UART1_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART1_INDEX].serial));
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
void UART2_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART2_INDEX].serial));
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
void UART3_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART3_INDEX].serial));
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
int rt_hw_usart_init(void)
|
||||
{
|
||||
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct msp432_uart);
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
rt_err_t result = 0;
|
||||
|
||||
uart_hw_config();
|
||||
|
||||
for (int i = 0; i < obj_num; i++)
|
||||
{
|
||||
uart_obj[i].config = &uart_config[i];
|
||||
uart_obj[i].uartintbase = uart_intbase[i];
|
||||
uart_obj[i].serial.ops = &msp432_uart_ops;
|
||||
uart_obj[i].serial.config = config;
|
||||
/* register UART device */
|
||||
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
|
||||
RT_DEVICE_FLAG_RDWR
|
||||
| RT_DEVICE_FLAG_INT_RX
|
||||
| RT_DEVICE_FLAG_INT_TX
|
||||
| uart_obj[i].uart_dma_flag
|
||||
, NULL);
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif /* RT_USING_SERIAL */
|
||||
|
||||
/************************** end of file ******************/
|
||||
41
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_uart.h
Normal file
41
bsp/msp432e401y-LaunchPad/libraries/Drivers/drv_uart.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2023-07-15 yby the first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_UART_H__
|
||||
#define __DRV_UART_H__
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/* msp432 config class */
|
||||
struct msp432_uart_config
|
||||
{
|
||||
const char *name;
|
||||
uint32_t uartbase;
|
||||
uint32_t baudrate;
|
||||
uint32_t mode;
|
||||
};
|
||||
|
||||
/* msp432 uart dirver class */
|
||||
struct msp432_uart
|
||||
{
|
||||
struct msp432_uart_config *config;
|
||||
uint32_t uartintbase;
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
|
||||
#endif
|
||||
rt_uint16_t uart_dma_flag;
|
||||
struct rt_serial_device serial;
|
||||
};
|
||||
|
||||
extern int rt_hw_usart_init(void);
|
||||
|
||||
#endif /*__DRV_UART_H__*/
|
||||
|
||||
/************************** end of file ******************/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user