mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-11-07 08:39:40 +08:00
update V850 BSP, now supporting scons + IAR
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2306 bbd45198-f89e-11dd-88c7-29a3b14d5316
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dzzxzz@gmail.com committed
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@@ -0,0 +1,12 @@
|
||||
from building import *
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||||
|
||||
cwd = GetCurrentDir()
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||||
objs = []
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list = os.listdir(cwd)
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||||
|
||||
for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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|
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Return('objs')
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@@ -0,0 +1,37 @@
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import os
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import sys
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import rtconfig
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||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
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||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
from building import *
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|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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||||
|
||||
env = Environment(tools = ['mingw'],
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||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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||||
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -f lnk70f3454.xcl -l rtthread.map -Omotorola-s28=$TARGET'])
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||||
env.Replace(ARFLAGS = '')
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||||
|
||||
Export('RTT_ROOT')
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||||
Export('rtconfig')
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||||
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||||
# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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||||
|
||||
# build program
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env.Program(TARGET, objs)
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||||
|
||||
# end building
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EndBuilding(TARGET)
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||||
@@ -0,0 +1,9 @@
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||||
from building import *
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||||
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||||
cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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|
||||
Return('group')
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@@ -1,7 +1,7 @@
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||||
/*
|
||||
* File : application.c
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||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
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||||
@@ -28,19 +28,15 @@
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||||
|
||||
static struct rt_thread led;
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||||
|
||||
#if defined(__ICCM16C__) || defined(__ICCV850__)
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#pragma data_alignment=4
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#endif
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ALIGN(RT_ALIGN_SIZE)
|
||||
static rt_uint8_t led_stack[256];
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|
||||
static void rt_thread_entry_led(void* parameter)
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static void rt_thread_entry_led(void *parameter)
|
||||
{
|
||||
while (1)
|
||||
{
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/* led off */
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led_off();
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rt_thread_delay(20); /* sleep 1 second and switch to other thread */
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/* led on */
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rt_thread_delay(20);
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led_on();
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rt_thread_delay(40);
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}
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@@ -48,15 +44,19 @@ static void rt_thread_entry_led(void* parameter)
|
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|
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int rt_application_init(void)
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||||
{
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||||
/* create led thread */
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||||
rt_thread_init(&led,
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||||
"led",
|
||||
rt_thread_entry_led, RT_NULL,
|
||||
&led_stack[0], sizeof(led_stack),
|
||||
5, 32);
|
||||
|
||||
if (&led != RT_NULL)
|
||||
rt_err_t result;
|
||||
|
||||
result = rt_thread_init(&led,
|
||||
"led",
|
||||
rt_thread_entry_led,
|
||||
RT_NULL,
|
||||
&led_stack[0],
|
||||
sizeof(led_stack),
|
||||
RT_THREAD_PRIORITY_MAX / 2,
|
||||
32);
|
||||
|
||||
if (result == RT_EOK)
|
||||
rt_thread_startup(&led);
|
||||
|
||||
|
||||
return 0;
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||||
}
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File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_macrodriver.h
|
||||
* Abstract: This file implements general head file.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _MDSTATUS_
|
||||
#define _MDSTATUS_
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include <intrinsics.h>
|
||||
#include "io70f3454.h"
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||||
/*
|
||||
*******************************************************************************
|
||||
** Register bit define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Macro define
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define DI __disable_interrupt
|
||||
#define EI __enable_interrupt
|
||||
#define NOP __no_operation
|
||||
#define HALT __halt
|
||||
|
||||
/* Data type defintion */
|
||||
typedef unsigned long ULONG;
|
||||
typedef signed long SLONG;
|
||||
|
||||
typedef unsigned int UINT;
|
||||
typedef signed int SINT;
|
||||
|
||||
typedef unsigned short USHORT;
|
||||
typedef signed short SHORT;
|
||||
|
||||
typedef unsigned char UCHAR;
|
||||
typedef signed char SCHAR;
|
||||
|
||||
typedef unsigned char BOOL;
|
||||
typedef unsigned short MD_STATUS;
|
||||
|
||||
#define MD_ON 1U
|
||||
#define MD_OFF 0U
|
||||
|
||||
#define MD_TRUE 1U
|
||||
#define MD_FALSE 0U
|
||||
|
||||
#define MD_SET 1U
|
||||
#define MD_CLEAR 0U
|
||||
|
||||
/* Status list definition */
|
||||
#define MD_STATUSBASE 0x00U
|
||||
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
|
||||
#define MD_RESET (MD_STATUSBASE + 0x01U) /* reset input */
|
||||
#define MD_SENDCOMPLETE (MD_STATUSBASE + 0x02U) /* send data complete */
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#define MD_ADDRESSMATCH (MD_STATUSBASE + 0x03U) /* IIC slave address match */
|
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#define MD_OVF (MD_STATUSBASE + 0x04U) /* timer count overflow */
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||||
#define MD_SPT (MD_STATUSBASE + 0x07U) /* IIC stop */
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#define MD_NACK (MD_STATUSBASE + 0x08U) /* IIC no ACK */
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#define MD_SLAVE_SEND_END (MD_STATUSBASE + 0x09U) /* IIC slave send end */
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#define MD_SLAVE_RCV_END (MD_STATUSBASE + 0x0AU) /* IIC slave receive end */
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#define MD_MASTER_SEND_END (MD_STATUSBASE + 0x0BU) /* IIC master send end */
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#define MD_MASTER_RCV_END (MD_STATUSBASE + 0x0CU) /* IIC master receive end */
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#define MD_UNDEREXEC (MD_STATUSBASE + 0x0DU) /* DMA transfer under execute */
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#define MD_COMPLETED (MD_STATUSBASE + 0x0EU) /* DMA transfer completed */
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#define MD_BUSY1 (MD_STATUSBASE + 0x0FU) /* busy 1 */
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#define MD_BUSY2 (MD_STATUSBASE + 0x10U) /* busy 2 */
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||||
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/* Error list definition */
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#define MD_ERRORBASE 0x80U
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#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
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#define MD_RESOURCEERROR (MD_ERRORBASE + 0x01U) /* no resource available */
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#define MD_PARITYERROR (MD_ERRORBASE + 0x02U) /* UARTn parity error n=0,1,2 */
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#define MD_OVERRUNERROR (MD_ERRORBASE + 0x03U) /* UARTn overrun error n=0,1,2 */
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#define MD_FRAMEERROR (MD_ERRORBASE + 0x04U) /* UARTn frame error n=0,1,2 */
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#define MD_ARGERROR (MD_ERRORBASE + 0x05U) /* Error agrument input error */
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#define MD_TIMINGERROR (MD_ERRORBASE + 0x06U) /* Error timing operation error */
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#define MD_SETPROHIBITED (MD_ERRORBASE + 0x07U) /* setting prohibited */
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#define MD_ODDBUF (MD_ERRORBASE + 0x08U) /* in 16bit transfer mode,buffer size should be even */
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#define MD_DATAEXISTS (MD_ERRORBASE + 0x09U) /* Data to be transferred next exists in TXBn register */
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#define MD_STSERROR (MD_ERRORBASE + 0x0AU) /* CAN status error */
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#define MD_ALRDYSTART (MD_ERRORBASE + 0x0BU) /* CAN-controller is already started error */
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#define MD_NOMSG (MD_ERRORBASE + 0x0CU) /* CAN message not received */
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#define MD_ERROR1 (MD_ERRORBASE + 0x0DU) /* error 1 */
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#define MD_ERROR2 (MD_ERRORBASE + 0x0EU) /* error 2 */
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/*
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*******************************************************************************
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** Function define
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*******************************************************************************
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*/
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#endif
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@@ -0,0 +1,71 @@
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/*
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||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
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* Filename: CG_port.c
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||||
* Abstract: This file implements device driver for PORT module.
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||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
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* Device: uPD70F3746
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* Compiler: IAR Systems ICCV850
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* Creation date: 6/26/2010
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*******************************************************************************
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*/
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/*
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||||
*******************************************************************************
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||||
** Include files
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||||
*******************************************************************************
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||||
*/
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#include "CG_macrodriver.h"
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#include "CG_port.h"
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/* Start user code for include. Do not edit comment generated here */
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||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
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||||
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/*
|
||||
*******************************************************************************
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||||
** Global define
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||||
*******************************************************************************
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||||
*/
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||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
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||||
** This function initializes setting for Port I/O.
|
||||
**
|
||||
** Parameters:
|
||||
** None
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||||
**
|
||||
** Returns:
|
||||
** None
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||||
**
|
||||
**-----------------------------------------------------------------------------
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||||
*/
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void PORT_Init(void)
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||||
{
|
||||
PDLH = _10_Pn4_OUTPUT_1;
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PMDLH = _01_PMn0_MODE_UNUSED | _02_PMn1_MODE_UNUSED | _04_PMn2_MODE_UNUSED | _08_PMn3_MODE_UNUSED | _00_PMn4_MODE_OUTPUT | _20_PMn5_MODE_UNUSED | _40_PMn6_MODE_UNUSED | _80_PMn7_MODE_UNUSED;
|
||||
PMCDLH = _00_PMCn4_OPER_PORT;
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||||
}
|
||||
|
||||
void led_on(void)
|
||||
{
|
||||
PDLH = _10_Pn4_OUTPUT_1;
|
||||
}
|
||||
|
||||
void led_off(void)
|
||||
{
|
||||
PDLH = _00_Pn4_OUTPUT_0;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_port.h
|
||||
* Abstract: This file implements device driver for PORT module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _MDPORT_
|
||||
#define _MDPORT_
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Register bit define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Port mode control register (PMCn.7 - PMCn.0) */
|
||||
#define _00_PMCn0_OPER_PORT 0x00U /* Pn0 as port mode */
|
||||
#define _00_PMCn1_OPER_PORT 0x00U /* Pn1 as port mode */
|
||||
#define _00_PMCn2_OPER_PORT 0x00U /* Pn2 as port mode */
|
||||
#define _00_PMCn3_OPER_PORT 0x00U /* Pn3 as port mode */
|
||||
#define _00_PMCn4_OPER_PORT 0x00U /* Pn4 as port mode */
|
||||
#define _00_PMCn5_OPER_PORT 0x00U /* Pn5 as port mode */
|
||||
#define _00_PMCn6_OPER_PORT 0x00U /* Pn6 as port mode */
|
||||
#define _00_PMCn7_OPER_PORT 0x00U /* Pn7 as port mode */
|
||||
#define _01_PMCn0_OPER_ALTER 0x01U /* Pn0 as alternative mode */
|
||||
#define _02_PMCn1_OPER_ALTER 0x02U /* Pn1 as alternative mode */
|
||||
#define _04_PMCn2_OPER_ALTER 0x04U /* Pn2 as alternative mode */
|
||||
#define _08_PMCn3_OPER_ALTER 0x08U /* Pn3 as alternative mode */
|
||||
#define _10_PMCn4_OPER_ALTER 0x10U /* Pn4 as alternative mode */
|
||||
#define _20_PMCn5_OPER_ALTER 0x20U /* Pn5 as alternative mode */
|
||||
#define _40_PMCn6_OPER_ALTER 0x40U /* Pn6 as alternative mode */
|
||||
#define _80_PMCn7_OPER_ALTER 0x80U /* Pn7 as alternative mode */
|
||||
#define _00_PMCn0_OPER_OCD 0x00U /* PMC0 for MINI2 */
|
||||
|
||||
/* Port mode register (PMn.7 - PMn.0) */
|
||||
#define _01_PMn0_MODE_INPUT 0x01U /* Pn0 as input mode */
|
||||
#define _02_PMn1_MODE_INPUT 0x02U /* Pn1 as input mode */
|
||||
#define _04_PMn2_MODE_INPUT 0x04U /* Pn2 as input mode */
|
||||
#define _08_PMn3_MODE_INPUT 0x08U /* Pn3 as input mode */
|
||||
#define _10_PMn4_MODE_INPUT 0x10U /* Pn4 as input mode */
|
||||
#define _20_PMn5_MODE_INPUT 0x20U /* Pn5 as input mode */
|
||||
#define _40_PMn6_MODE_INPUT 0x40U /* Pn6 as input mode */
|
||||
#define _80_PMn7_MODE_INPUT 0x80U /* Pn7 as input mode */
|
||||
#define _00_PMn0_MODE_OUTPUT 0x00U /* Pn0 as output mode */
|
||||
#define _00_PMn1_MODE_OUTPUT 0x00U /* Pn1 as output mode */
|
||||
#define _00_PMn2_MODE_OUTPUT 0x00U /* Pn2 as output mode */
|
||||
#define _00_PMn3_MODE_OUTPUT 0x00U /* Pn3 as output mode */
|
||||
#define _00_PMn4_MODE_OUTPUT 0x00U /* Pn4 as output mode */
|
||||
#define _00_PMn5_MODE_OUTPUT 0x00U /* Pn5 as output mode */
|
||||
#define _00_PMn6_MODE_OUTPUT 0x00U /* Pn6 as output mode */
|
||||
#define _00_PMn7_MODE_OUTPUT 0x00U /* Pn7 as output mode */
|
||||
#define _01_PMn0_MODE_UNUSED 0x01U /* Pn0 as default mode */
|
||||
#define _02_PMn1_MODE_UNUSED 0x02U /* Pn1 as default mode */
|
||||
#define _04_PMn2_MODE_UNUSED 0x04U /* Pn2 as default mode */
|
||||
#define _08_PMn3_MODE_UNUSED 0x08U /* Pn3 as default mode */
|
||||
#define _10_PMn4_MODE_UNUSED 0x10U /* Pn4 as default mode */
|
||||
#define _20_PMn5_MODE_UNUSED 0x20U /* Pn5 as default mode */
|
||||
#define _40_PMn6_MODE_UNUSED 0x40U /* Pn6 as default mode */
|
||||
#define _80_PMn7_MODE_UNUSED 0x80U /* Pn7 as default mode */
|
||||
#define _00_PMn0_MODE_OCD 0x00U /* PMC0 for MINI2 */
|
||||
|
||||
/* Port register (Pn.7 - Pn.0) */
|
||||
#define _00_Pn0_OUTPUT_0 0x00U /* Pn0 output 0 */
|
||||
#define _00_Pn1_OUTPUT_0 0x00U /* Pn1 output 0 */
|
||||
#define _00_Pn2_OUTPUT_0 0x00U /* Pn2 output 0 */
|
||||
#define _00_Pn3_OUTPUT_0 0x00U /* Pn3 output 0 */
|
||||
#define _00_Pn4_OUTPUT_0 0x00U /* Pn4 output 0 */
|
||||
#define _00_Pn5_OUTPUT_0 0x00U /* Pn5 output 0 */
|
||||
#define _00_Pn6_OUTPUT_0 0x00U /* Pn6 output 0 */
|
||||
#define _00_Pn7_OUTPUT_0 0x00U /* Pn7 output 0 */
|
||||
#define _01_Pn0_OUTPUT_1 0x01U /* Pn0 output 1 */
|
||||
#define _02_Pn1_OUTPUT_1 0x02U /* Pn1 output 1 */
|
||||
#define _04_Pn2_OUTPUT_1 0x04U /* Pn2 output 1 */
|
||||
#define _08_Pn3_OUTPUT_1 0x08U /* Pn3 output 1 */
|
||||
#define _10_Pn4_OUTPUT_1 0x10U /* Pn4 output 1 */
|
||||
#define _20_Pn5_OUTPUT_1 0x20U /* Pn5 output 1 */
|
||||
#define _40_Pn6_OUTPUT_1 0x40U /* Pn6 output 1 */
|
||||
#define _80_Pn7_OUTPUT_1 0x80U /* Pn7 output 1 */
|
||||
|
||||
/* Function register resistor (PFn.7 - PFn.0) */
|
||||
#define _00_PFn0_FUN_NORMAL 0x00U /* Pn0 normal output */
|
||||
#define _00_PFn1_FUN_NORMAL 0x00U /* Pn1 normal output */
|
||||
#define _00_PFn2_FUN_NORMAL 0x00U /* Pn2 normal output */
|
||||
#define _00_PFn3_FUN_NORMAL 0x00U /* Pn3 normal output */
|
||||
#define _00_PFn4_FUN_NORMAL 0x00U /* Pn4 normal output */
|
||||
#define _00_PFn5_FUN_NORMAL 0x00U /* Pn5 normal output */
|
||||
#define _00_PFn6_FUN_NORMAL 0x00U /* Pn6 normal output */
|
||||
#define _00_PFn7_FUN_NORMAL 0x00U /* Pn7 normal output */
|
||||
#define _01_PFn0_FUN_OPEN 0x01U /* Pn0 open-drain output */
|
||||
#define _02_PFn1_FUN_OPEN 0x02U /* Pn1 open-drain output */
|
||||
#define _04_PFn2_FUN_OPEN 0x04U /* Pn2 open-drain output */
|
||||
#define _08_PFn3_FUN_OPEN 0x08U /* Pn3 open-drain output */
|
||||
#define _10_PFn4_FUN_OPEN 0x10U /* Pn4 open-drain output */
|
||||
#define _20_PFn5_FUN_OPEN 0x20U /* Pn5 open-drain output */
|
||||
#define _40_PFn6_FUN_OPEN 0x40U /* Pn6 open-drain output */
|
||||
#define _80_PFn7_FUN_OPEN 0x80U /* Pn7 open-drain output */
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Macro define
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define _80_PM0_DEFAULT 0x80U /* PM0 default value */
|
||||
#define _FC_PM1_DEFAULT 0xFCU /* PM1 default value */
|
||||
#define _FC_PM3H_DEFAULT 0xFCU /* PM3H default value */
|
||||
#define _F8_PM4_DEFAULT 0xF8U /* PM4 default value */
|
||||
#define _C0_PM5_DEFAULT 0xC0U /* PM5 default value */
|
||||
#define _FC_PM8_DEFAULT 0xFCU /* PM8 default value */
|
||||
#define _F0_PMCD_DEFAULT 0xF0U /* PMCD default value */
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Function define
|
||||
*******************************************************************************
|
||||
*/
|
||||
void PORT_Init(void);
|
||||
void led_on(void);
|
||||
void led_off(void);
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_port_user.c
|
||||
* Abstract: This file implements device driver for PORT module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_port.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_system.c
|
||||
* Abstract: This file implements device driver for System module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_system.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
void clock_pll_mode(void)
|
||||
{
|
||||
/* CPU operation clock selection */
|
||||
/* Set PLL mode. */
|
||||
PLLCTL = 0x03; /* bit 1: CPU clock selection (PLL mode/clock-through mode selection) */
|
||||
/* 1: PLL mode, 0: Clock-through mode */
|
||||
|
||||
__asm("_loop: set1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE )
|
||||
__asm(" tst1 1,0xF82C[r0]"); //__IO_REG8_BIT( PLLCTL, 0xFFFFF82C, __READ_WRITE )
|
||||
__asm(" bz _loop");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void clock_pcc_mode(void)
|
||||
{
|
||||
/* DMA is forcibly terminated in this sample since DMA transfer must be terminated
|
||||
before data is set to a special register. */
|
||||
|
||||
if(TC0 == 0 && E00 == 1){ /* DMA0 transfer judgment */
|
||||
INIT0 = 1; /* DMA0 forcible termination */
|
||||
}
|
||||
if(TC1 == 0 && E11 == 1){ /* DMA1 transfer judgment */
|
||||
INIT1 = 1; /* DMA1 forcible termination */
|
||||
}
|
||||
if(TC2 == 0 && E22 == 1){ /* DMA2 transfer judgment */
|
||||
INIT2 = 1; /* DMA2 forcible termination */
|
||||
}
|
||||
if(TC3 == 0 && E33 == 1){ /* DMA3 transfer judgment */
|
||||
INIT3 = 1; /* DMA3 forcible termination */
|
||||
}
|
||||
|
||||
/* The PCC register is a special register. Data can be written to this register only in a combination of specific sequences. */
|
||||
/* bit 1, bit 0: Clock selection, 11: fxx/8, 10: fxx/4, 01: fxx/2, 00: fxx */
|
||||
/* Clock selection: fxx */
|
||||
__asm("mov 0x00, r10"); /* Set general-purpose register data to be set to special register. */
|
||||
__asm("st.b r10, 0xF1FC[r0]"); /* Write to PRCMD register. */ //__IO_REG8(PRCMD, 0xFFFFF1FC, __WRITE)
|
||||
__asm("st.b r10, 0xF828[r0]"); /* Set PCC register. */ //__IO_REG8_BIT(PCC, 0xFFFFF828, __READ_WRITE)
|
||||
__asm("nop"); /* Insert five or more NOP instructions. */
|
||||
__asm("nop");
|
||||
__asm("nop");
|
||||
__asm("nop");
|
||||
__asm("nop");
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes the clock generator module.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void CLOCK_Init(void)
|
||||
{
|
||||
DI(); /* Maskable interrupt disabled */
|
||||
|
||||
do{
|
||||
clock_pll_mode(); /* PLL mode setting function */
|
||||
|
||||
clock_pcc_mode(); /* PCC register setting function */
|
||||
|
||||
}while(PRERR); /* Written in correct sequence? */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@@ -0,0 +1,172 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_system.h
|
||||
* Abstract: This file implements device driver for System module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _MDSYSTEM_
|
||||
#define _MDSYSTEM_
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Register bit define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/*
|
||||
Processor clock control register (PCC)
|
||||
*/
|
||||
#define _03_CG_PCC_INITIALVALUE 0x03U
|
||||
/* Use of subclock on-chip feedback resistor (FRC) */
|
||||
#define _00_CG_SUBCLK_FEEDBACK_USE 0x00U /* subclock on-chip feedback resistor connected */
|
||||
#define _08_CG_SUBCLK_FEEDBACK_UNUSE 0x80U /* subclock on-chip feedback resistor not connected */
|
||||
/* Main clock osillator control (MCK) */
|
||||
#define _00_CG_MAINCLK_ENABLE 0x00U /* main clock oscillation enabled */
|
||||
#define _04_CG_MAINCLK_STOP 0x40U /* main clock oscillation stopped */
|
||||
/* Use of main clock on-chip feedback resistor (MFRC) */
|
||||
#define _00_CG_MAINCLK_FEEDBACK_USE 0x00U /* main clock feedback resistor connected */
|
||||
#define _20_CG_MAINCLK_FEEDBACK_UNUSE 0x20U /* main clock feedback resistor not connected */
|
||||
/* Status of CPU clock fCPU (CLS) */
|
||||
#define _00_CG_CPUCLK_MAINCLK 0x00U /* main clock operation */
|
||||
#define _10_CG_CPUCLK_SUBCLK 0x10U /* subclock operation */
|
||||
/* Clock(fCLK/fCPU) selection (CK3 - CK0) */
|
||||
#define _0F_CG_CPUCLK 0x0FU
|
||||
#define _00_CG_CPUCLK_MAIN0 0x00U /* fCPU = fXX */
|
||||
#define _01_CG_CPUCLK_MAIN1 0x01U /* fCPU = fXX/2 */
|
||||
#define _02_CG_CPUCLK_MAIN2 0x02U /* fCPU = fXX/2^2 */
|
||||
#define _03_CG_CPUCLK_MAIN3 0x03U /* fCPU = fXX/2^3 */
|
||||
#define _04_CG_CPUCLK_MAIN4 0x04U /* fCPU = fXX/2^4 */
|
||||
#define _05_CG_CPUCLK_MAIN5 0x05U /* fCPU = fXX/2^5 */
|
||||
#define _0B_CG_CPUCLK_SUB 0x0BU /* fXT */
|
||||
|
||||
/*
|
||||
Internal oscillator mode register (RCM)
|
||||
*/
|
||||
/* Oscillation/stop of internal oscillator (RSTOP) */
|
||||
#define _00_CG_INTER_OSC_ON 0x00U /* internal oscillator oscillation */
|
||||
#define _01_CG_INTER_OSC_OFF 0x01U /* internal oscillator stopped */
|
||||
|
||||
/*
|
||||
CPU operation clock status register (CCLS)
|
||||
*/
|
||||
/* CPU operation clock status (CCLSF) */
|
||||
#define _00_CG_CPUCLK_STATUS_MAINORSUB 0x00U /* operating on main clock(fX) or subclock(fXT) */
|
||||
#define _01_CG_CPUCLK_STATUS_INTEROSC 0x01U /* operating on internal oscillation clock(fR) */
|
||||
|
||||
/*
|
||||
Lock register (LOCKR)
|
||||
*/
|
||||
/* PLL lock status check (LOCK) */
|
||||
#define _00_CG_PLLSTATUS_LOCK 0x00U /* locked status */
|
||||
#define _01_CG_PLLSTATUS_UNLOCK 0x01U /* unlocked status */
|
||||
|
||||
/*
|
||||
PLL control register (PLLCTL)
|
||||
*/
|
||||
#define _01_CG_PLLCTL_INITIALVALUE 0x01U
|
||||
/* CPU operation clock selection register (SELPLL) */
|
||||
#define _00_CG_CPUCLK_CLKTHROUGH 0x00U /* clock-through mode */
|
||||
#define _02_CG_CPUCLK_PLL 0x02U /* PLL mode */
|
||||
/* PLL operation stop register (PLLON) */
|
||||
#define _00_CG_CPUCLK_PLLOFF 0x00U /* PLL stopped */
|
||||
#define _01_CG_CPUCLK_PLLON 0x01U /* PLL operating */
|
||||
|
||||
/*
|
||||
Clock control register (CKC)
|
||||
*/
|
||||
#define _0A_CG_CKC_INITIALVALUE 0x0AU
|
||||
/* Internal system clock(fXX) in PLL mode */
|
||||
#define _00_CG_CPUCLK_4PLL 0x00U /* fXX = 4* fX (fX = 2.5 to 5.0 MHz) */
|
||||
#define _01_CG_CPUCLK_8PLL 0x01U /* fXX = 8* fX (fX = 2.5 to 4.0 MHz) */
|
||||
|
||||
/*
|
||||
PLL lockup time specification register (PLLS)
|
||||
*/
|
||||
#define _03_CG_PLLS_INITIALVALUE 0x03U
|
||||
/* PLL lockup time selection (PLLS2 - PLLS0) */
|
||||
#define _00_CG_PLLLOCKUP_SEL0 0x00U /* 2^10/fX */
|
||||
#define _01_CG_PLLLOCKUP_SEL1 0x01U /* 2^11/fX*/
|
||||
#define _02_CG_PLLLOCKUP_SEL2 0x02U /* 2^12/fX */
|
||||
#define _03_CG_PLLLOCKUP_SEL3 0x03U /* 2^13/fX (default value) */
|
||||
|
||||
/*
|
||||
Power save control register (PSC)
|
||||
*/
|
||||
/* Stand-by mode release control by occurrence of INTWDT2 signal (NMI1M) */
|
||||
#define _00_CG_STANDBY_INTWDT2EN 0x00U /* enable releasing stand-by mode by INTWDT2 signal */
|
||||
#define _40_CG_STANDBY_INTWDT2DIS 0x40U /* disable releasing stand-by mode by INTWDT2 signal */
|
||||
/* Stand-by mode release control by NMI pin input (NMI0M) */
|
||||
#define _00_CG_STANDBY_NMIEN 0x00U /* enable releasing stand-by mode by NMI pin input */
|
||||
#define _20_CG_STANDBY_NMIDIS 0x20U /* disable releasing stand-by mode by NMI pin input */
|
||||
/* Stand-by mode release control by maskable interrupt request signal (NMI0M) */
|
||||
#define _00_CG_STANDBY_MASKIEN 0x00U /* enable releasing stand-by mode by maskable interrupt request signal */
|
||||
#define _10_CG_STANDBY_MASKIDIS 0x10U /* disable releasing stand-by mode by maskable interrupt request signal */
|
||||
/* Setting of stand-by mode (STP) */
|
||||
#define _00_CG_STANDBY_UNUSE 0x00U /* normal mode */
|
||||
#define _02_CG_STANDBY_USE 0x02U /* stand-by mode */
|
||||
|
||||
/*
|
||||
Power save mode control register (PSMR)
|
||||
*/
|
||||
/* Specification of operation in software stand-by mode (PSM1,PSM0) */
|
||||
#define _00_CG_POWERSAVE_IDLE1 0x00U /* IDLE1, sub-IDLE modes */
|
||||
#define _01_CG_POWERSAVE_STOP1 0x01U /* STOP, sub-IDLE modes */
|
||||
#define _02_CG_POWERSAVE_IDLE2 0x02U /* IDLE2, sub-IDLE modes */
|
||||
#define _03_CG_POWERSAVE_STOP2 0x03U /* STOP mode */
|
||||
|
||||
/*
|
||||
Clock monitor mode register (CLM)
|
||||
*/
|
||||
/* Clock monitor operation enable or disable (CLME) */
|
||||
#define _01_CG_MONITOR_ENABLE 0x01U /* enable clock monitor operation */
|
||||
#define _00_CG_MONITOR_DISABLE 0x00U /* disable clock monitor operation */
|
||||
|
||||
/*
|
||||
Watchdog Timer 2 mode register (WDTM2)
|
||||
*/
|
||||
/* Selection of operation mode (WDM21, WDM20) */
|
||||
#define _00_WDT2_OPERMODE_STOP 0x00U /* stops operation */
|
||||
#define _20_WDT2_OPERMODE_NONMASK 0x20U /* non-maskable interrupt request mode (generation of INTWDT2) */
|
||||
#define _40_WDT2_OPERMODE_RESET 0x40U /* reset mode (generation of RESWDT2) */
|
||||
/* Selection of clock mode (WDCS24,WDCS23) */
|
||||
#define _00_WDT2_CLKMODE_INTEROSC 0x00U /* use internal oscillator */
|
||||
#define _08_WDT2_CLKMODE_MAINCLK 0x08U /* use Main clock */
|
||||
#define _10_WDT2_CLKMODE_SUBCLK 0x10U /* use subclock */
|
||||
/* Watchdog Timer 2 clock Selection (WDCS22 - WDCS20) */
|
||||
#define _00_WDT2_CLOCK_SEL0 0x00U /* 2^12/fR or 2^18/fXX or 2^9/fXT */
|
||||
#define _01_WDT2_CLOCK_SEL1 0x01U /* 2^13/fR or 2^19/fXX or 2^10/fXT */
|
||||
#define _02_WDT2_CLOCK_SEL2 0x02U /* 2^14/fR or 2^20/fXX or 2^11/fXT */
|
||||
#define _03_WDT2_CLOCK_SEL3 0x03U /* 2^15/fR or 2^21/fXX or 2^12/fXT */
|
||||
#define _04_WDT2_CLOCK_SEL4 0x04U /* 2^16/fR or 2^22/fXX or 2^13/fXT */
|
||||
#define _05_WDT2_CLOCK_SEL5 0x05U /* 2^17/fR or 2^23/fXX or 2^14/fXT */
|
||||
#define _06_WDT2_CLOCK_SEL6 0x06U /* 2^18/fR or 2^24/fXX or 2^15/fXT */
|
||||
#define _07_WDT2_CLOCK_SEL7 0x07U /* 2^19/fR or 2^25/fXX or 2^16/fXT */
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Macro define
|
||||
*******************************************************************************
|
||||
*/
|
||||
#define _00_CG_VSWC_VALUE 0x00U
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Function define
|
||||
*******************************************************************************
|
||||
*/
|
||||
void CLOCK_Init(void);
|
||||
void WDT2_Restart(void);
|
||||
void CG_ReadResetSource(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@@ -0,0 +1,62 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_system_user.c
|
||||
* Abstract: This file implements device driver for System module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_system.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function processes of Reset.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void CG_ReadResetSource( void )
|
||||
{
|
||||
UCHAR resetflag = RESF;
|
||||
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_systeminit.c
|
||||
* Abstract: This file implements system initializing function.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_system.h"
|
||||
#include "CG_port.h"
|
||||
#include "CG_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
UCHAR __low_level_init(void);
|
||||
void systeminit(void);
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes each macro.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void systeminit(void)
|
||||
{
|
||||
DI(); /* disable interrupt */
|
||||
CG_ReadResetSource();
|
||||
PORT_Init();
|
||||
TAB0_Init();
|
||||
EI(); /* enable interrupt */
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes hardware setting.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
UCHAR __low_level_init(void)
|
||||
{
|
||||
VSWC = 0x13U;
|
||||
CLOCK_Init(); /* call Clock_Init function */
|
||||
systeminit();
|
||||
|
||||
return MD_TRUE;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@@ -0,0 +1,200 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_timer.c
|
||||
* Abstract: This file implements device driver for Timer module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Count Clock (TABnCTL0) */
|
||||
#define TAB_CNT_CLK 0x00 /* Count Clock fxx */
|
||||
#define TAB_CNT_CLK_2 0x01 /* Count Clock fxx/2 */
|
||||
#define TAB_CNT_CLK_4 0x02 /* Count Clock fxx/4 */
|
||||
#define TAB_CNT_CLK_8 0x03 /* Count Clock fxx/8 */
|
||||
#define TAB_CNT_CLK_16 0x04 /* Count Clock fxx/16 */
|
||||
#define TAB_CNT_CLK_32 0x05 /* Count Clock fxx/32 */
|
||||
#define TAB_CNT_CLK_64 0x06 /* Count Clock fxx/64 */
|
||||
#define TAB_CNT_CLK_128 0x07 /* Count Clock fxx/128 */
|
||||
/* Mode (TABkMD2 + TABkMD1 + TABkMD0) */
|
||||
#define TAB_INTERVAL_MODE 0x00 /* Interval Timer Mode */
|
||||
/* TAB0I/O Control Register (TABmIOC0) */
|
||||
#define TAB_TOB00_DISABLE 0x00 /* TOB00 Output Disable */
|
||||
#define TAB_TOB00_ENABLE 0x01 /* TOB00 Output Enable */
|
||||
#define TAB_TOB00_HI_LEV_ST 0x00 /* TOB00 Output High Level Start */
|
||||
#define TAB_TOB00_LO_LEV_ST 0x02 /* TOB00 Output Low Level Start */
|
||||
#define TAB_TOB01_DISABLE 0x00 /* TOB01 Output Disable */
|
||||
#define TAB_TOB01_ENABLE 0x04 /* TOB01 Output Enable */
|
||||
#define TAB_TOB01_HI_LEV_ST 0x00 /* TOB01 Output High Level Start */
|
||||
#define TAB_TOB01_LO_LEV_ST 0x08 /* TOB01 Output Low Level Start */
|
||||
#define TAB_TOB02_DISABLE 0x00 /* TOB02 Output Disable */
|
||||
#define TAB_TOB02_ENABLE 0x10 /* TOB02 Output Enable */
|
||||
#define TAB_TOB02_HI_LEV_ST 0x00 /* TOB02 Output High Level Start */
|
||||
#define TAB_TOB02_LO_LEV_ST 0x20 /* TOB02 Output Low Level Start */
|
||||
#define TAB_TOB03_DISABLE 0x00 /* TOB03 Output Disable */
|
||||
#define TAB_TOB03_ENABLE 0x40 /* TOB03 Output Enable */
|
||||
#define TAB_TOB03_HI_LEV_ST 0x00 /* TOB03 Output High Level Start */
|
||||
#define TAB_TOB03_LO_LEV_ST 0x80 /* TOB03 Output Low Level Start */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
void timerab_interval(void)
|
||||
{
|
||||
TAB0CTL0 = TAB_CNT_CLK_32; /* TAB0CKS2 = 1 + TAB0CKS1 = 0 + TAB0CKS0 = 0 */
|
||||
/* : Clock Count = fxx/32 */
|
||||
TAB0CTL1 = TAB_INTERVAL_MODE; /* TAB0MD2 = 0 + TAB0MD1 = 0 + TAB0MD0 = 0 */
|
||||
/* : Interval Timer Mode */
|
||||
// TAB0IOC2 = TAB_TOB03_LO_LEV_ST | /* TAB0OL3 = 1 : TOB03 Low Level Start */
|
||||
// TAB_TOB03_DISABLE | /* TAB0OE3 = 0 : TOB03 Output Disable */
|
||||
// TAB_TOB02_LO_LEV_ST | /* TAB0OL2 = 1 : TOB02 Low Level Start */
|
||||
// TAB_TOB02_DISABLE | /* TAB0OE2 = 0 : TOB02 Output Disable */
|
||||
// TAB_TOB01_HI_LEV_ST | /* TAB0OL1 = 0 : TOB01 High Level Start */
|
||||
// TAB_TOB01_ENABLE | /* TAB0OE1 = 1 : TOB01 Output Enable */
|
||||
// TAB_TOB00_HI_LEV_ST | /* TAB0OL0 = 0 : TOB00 High Level Start */
|
||||
// TAB_TOB00_ENABLE; /* TAB0OE0 = 1 : TOB00 Output Enable */
|
||||
TAB0CCR0 = 19999; /* Compare Register */
|
||||
TAB0CCR1 = 0xFFFF; /* Compare Register */
|
||||
TAB0CCR2 = 0xFFFF; /* No Use */
|
||||
TAB0CCR3 = 0xFFFF; /* No Use */
|
||||
}
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function initializes the TAB0 module.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void TAB0_Init(void)
|
||||
{
|
||||
TAB0CE = 0; /* Stop TAB */
|
||||
|
||||
/* Port Definition */
|
||||
// PFC1 = 0x00; /* PFC17 = 0 : TOB00 Output */
|
||||
/* PFC10 = 0 : TOB01 Output */
|
||||
// PFCE1 = 0x01; /* PFCE10 = 1 : TOB01 Output */
|
||||
// PMC1 = 0x81; /* PMC17 = 1 : TOB00 Output/INTP09 Input */
|
||||
/* PMC10 = 1 : TOB0T1 Output/TIB01 Input/TOB01 Output */
|
||||
|
||||
/* Enable Interrupt */
|
||||
TB0CCMK0 = 0; /* TB0CCMK0 = 0 : INTTB0CC0 Enable */
|
||||
TB0CCMK1 = 1; /* TB0CCMK1 = 0 : INTTB0CC1 Enable */
|
||||
TB0CCMK2 = 1; /* TB0CCMK2 = 1 : INTTB0CC2 Disable */
|
||||
TB0CCMK3 = 1; /* TB0CCMK3 = 1 : INTTB0CC3 Disable */
|
||||
|
||||
timerab_interval();
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function starts TMP0 counter.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void TAB0_Start(void)
|
||||
{
|
||||
TB0CCIF0 = 0U; /* clear INTTP0CC0 interrupt flag */
|
||||
TB0CCMK0 = 0U; /* enable INTTP0CC0 interrupt */
|
||||
TAB0CE = 1U; /* enable TMP0 operation */
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function stops TMP0 counter.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
void TAB0_Stop(void)
|
||||
{
|
||||
TAB0CE = 0U; /* disable TMP0 operation */
|
||||
TB0CCMK0 = 1U; /* disable INTTP0CC0 interrupt */
|
||||
TB0CCIF0 = 0U; /* clear INTTP0CC0 interrupt flag */
|
||||
}
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function changes TMP0 register value.
|
||||
**
|
||||
** Parameters:
|
||||
** array_reg: register value buffer
|
||||
** array_num: register index to be changed
|
||||
**
|
||||
** Returns:
|
||||
** MD_OK
|
||||
** MD_ARGERROR
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
switch (array_num)
|
||||
{
|
||||
case 1U:
|
||||
TAB0CCR0 = array_reg[0U];
|
||||
status = MD_OK;
|
||||
break;
|
||||
case 2U:
|
||||
TAB0CCR0 = array_reg[0U];
|
||||
TAB0CCR1 = array_reg[1U];
|
||||
status = MD_OK;
|
||||
break;
|
||||
default:
|
||||
status = MD_ARGERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_timer_user.c
|
||||
* Abstract: This file implements device driver for Timer module.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Include files
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "CG_macrodriver.h"
|
||||
#include "CG_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "CG_userdefine.h"
|
||||
|
||||
/*
|
||||
*******************************************************************************
|
||||
** Global define
|
||||
*******************************************************************************
|
||||
*/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/*
|
||||
**-----------------------------------------------------------------------------
|
||||
**
|
||||
** Abstract:
|
||||
** This function is INTTP0CC0 interrupt service routine.
|
||||
**
|
||||
** Parameters:
|
||||
** None
|
||||
**
|
||||
** Returns:
|
||||
** None
|
||||
**
|
||||
**-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
///#pragma vector = INTTB0CC0_vector
|
||||
///__interrupt void MD_INTTB0CC0(void)
|
||||
///{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/// PDLH = ~PDLH;
|
||||
/* End user code. Do not edit comment generated here */
|
||||
///}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
*******************************************************************************
|
||||
* Copyright(C) NEC Electronics Corporation 2010
|
||||
* All rights reserved by NEC Electronics Corporation.
|
||||
* This program should be used on your own responsibility.
|
||||
* NEC Electronics Corporation assumes no responsibility for any losses
|
||||
* incurred by customers or third parties arising from the use of this file.
|
||||
*
|
||||
* This device driver was created by Applilet3 for V850ES/Jx3
|
||||
* 32-Bit Single-Chip Microcontrollers
|
||||
* Filename: CG_userdefine.h
|
||||
* Abstract: This file includes user definition.
|
||||
* APIlib: Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
|
||||
* Device: uPD70F3746
|
||||
* Compiler: IAR Systems ICCV850
|
||||
* Creation date: 6/26/2010
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef _MD_USER_DEF_
|
||||
#define _MD_USER_DEF_
|
||||
/*
|
||||
*******************************************************************************
|
||||
** User define
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src_c = Glob('*.c')
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src_asm = ['start_gcc.S', 'vectors_gcc.S', 'interrupts_gcc.S']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src_asm = ['cstartup.asm']
|
||||
|
||||
src = File(src_c + src_asm)
|
||||
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* File : board.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
@@ -21,13 +21,12 @@
|
||||
#include "uart.h"
|
||||
#include "board.h"
|
||||
|
||||
void rt_hw_board_init()
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
#ifdef RT_USING_UART0
|
||||
rt_hw_uart_init();
|
||||
rt_console_set_device("uart0");
|
||||
rt_hw_uart_init();
|
||||
rt_console_set_device("uart0");
|
||||
#endif
|
||||
|
||||
rt_kprintf("\r\n\r\nSystemInit......\r\n");
|
||||
}
|
||||
|
||||
File renamed without changes.
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File renamed without changes.
@@ -150,7 +150,7 @@
|
||||
|
||||
// Set up near RT_HEAP
|
||||
//fify 20100505 HEAP for RTT
|
||||
-Z(DATA)RT_HEAP+400=FFFFC000-FFFFEFFF
|
||||
-Z(DATA)RT_HEAP+800=FFFFC000-FFFFEFFF
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// End of File
|
||||
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,8 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\upd70f3454.ewp</path>
|
||||
</project>
|
||||
<batchBuild />
|
||||
</workspace>
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -86,67 +86,4 @@
|
||||
/* the max number of cached sector */
|
||||
///#define DFS_CACHE_MAX_NUM 4
|
||||
|
||||
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
|
||||
//#define RT_USING_LWIP
|
||||
|
||||
/* Enable ICMP protocol*/
|
||||
///#define RT_LWIP_ICMP
|
||||
/* Enable UDP protocol*/
|
||||
///#define RT_LWIP_UDP
|
||||
/* Enable TCP protocol*/
|
||||
///#define RT_LWIP_TCP
|
||||
/* Enable DNS */
|
||||
///#define RT_LWIP_DNS
|
||||
|
||||
/* the number of simulatenously active TCP connections*/
|
||||
///#define RT_LWIP_TCP_PCB_NUM 5
|
||||
|
||||
/* ip address of target*/
|
||||
///#define RT_LWIP_IPADDR0 192
|
||||
///#define RT_LWIP_IPADDR1 168
|
||||
///#define RT_LWIP_IPADDR2 1
|
||||
///#define RT_LWIP_IPADDR3 30
|
||||
|
||||
/* gateway address of target*/
|
||||
#define RT_LWIP_GWADDR0 192
|
||||
#define RT_LWIP_GWADDR1 168
|
||||
#define RT_LWIP_GWADDR2 1
|
||||
#define RT_LWIP_GWADDR3 1
|
||||
|
||||
/* mask address of target*/
|
||||
#define RT_LWIP_MSKADDR0 255
|
||||
#define RT_LWIP_MSKADDR1 255
|
||||
#define RT_LWIP_MSKADDR2 255
|
||||
#define RT_LWIP_MSKADDR3 0
|
||||
|
||||
/* tcp thread options */
|
||||
#define RT_LWIP_TCPTHREAD_PRIORITY 12
|
||||
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
|
||||
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
|
||||
|
||||
/* ethernet if thread options */
|
||||
#define RT_LWIP_ETHTHREAD_PRIORITY 15
|
||||
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
|
||||
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
|
||||
|
||||
/* SECTION: RT-Thread/GUI */
|
||||
/* #define RT_USING_RTGUI */
|
||||
|
||||
/* name length of RTGUI object */
|
||||
#define RTGUI_NAME_MAX 12
|
||||
/* support 16 weight font */
|
||||
#define RTGUI_USING_FONT16
|
||||
/* support Chinese font */
|
||||
#define RTGUI_USING_FONTHZ
|
||||
/* use DFS as file interface */
|
||||
#define RTGUI_USING_DFS_FILERW
|
||||
/* use font file as Chinese font */
|
||||
#define RTGUI_USING_HZ_FILE
|
||||
/* use small size in RTGUI */
|
||||
#define RTGUI_USING_SMALL_SIZE
|
||||
/* use mouse cursor */
|
||||
/* #define RTGUI_USING_MOUSE_CURSOR */
|
||||
/* default font size in RTGUI */
|
||||
#define RTGUI_DEFAULT_FONT_SIZE 16
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,111 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH = 'v850'
|
||||
CPU = '70f34'
|
||||
|
||||
CROSS_TOOL = 'iar'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
print '================ERROR============================'
|
||||
print 'Not support gcc yet!'
|
||||
print '================================================='
|
||||
exit(0)
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation_0'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
print '================ERROR============================'
|
||||
print 'Not support keil yet!'
|
||||
print '================================================='
|
||||
exit(0)
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'm32c-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'out'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=m16c'
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -nostartfiles' + ' -Wl,--gc-sections,-Map=rtthread_m16c.map,-cref,-u,_start -T m16c62p.ld'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O srec $TARGET rtthread.mot\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccv850'
|
||||
AS = 'av850'
|
||||
AR = 'xar'
|
||||
LINK = 'xlink'
|
||||
TARGET_EXT = 'hex'
|
||||
|
||||
DEVICE = '--cpu V850'
|
||||
|
||||
EXEC_PATH = IAR_PATH + '/v850/bin'
|
||||
|
||||
AFLAGS = '-s+'
|
||||
AFLAGS = ' -v1'
|
||||
# AFLAGS += ' -M<>'
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -DCODE_MODEL_NORMAL'
|
||||
AFLAGS += ' -DDATA_MODEL_TINY'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' -I"' + IAR_PATH + '/v850/INC"'
|
||||
|
||||
LFLAGS = '-xms'
|
||||
LFLAGS += ' -I"' + IAR_PATH + '/v850/LIB"'
|
||||
LFLAGS += ' -rt'
|
||||
LFLAGS += ' -s __program_start'
|
||||
LFLAGS += ' -D_CSTACK_SIZE=1000'
|
||||
LFLAGS += ' "' + IAR_PATH + '/v850/LIB/dl85nn1.r85"'
|
||||
LFLAGS += ' -D_HEAP_SIZE=0'
|
||||
|
||||
# LFLAGS += ' "' + IAR_PATH + '/v850/lib/CLIB/clm16cfnffwc.r34"'
|
||||
# LFLAGS += ' -e_small_write=_formatted_write'
|
||||
# LFLAGS += ' -e_medium_read=_formatted_read'
|
||||
|
||||
# CFLAGS = DEVICE
|
||||
CFLAGS = '--diag_suppress Pa050'
|
||||
CFLAGS += ' -v1'
|
||||
CFLAGS += ' -mt'
|
||||
CFLAGS += ' --code_model normal'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --dlib_config "' + IAR_PATH + '/v850/LIB/dl85nn1.h"'
|
||||
CFLAGS += ' -I"' + IAR_PATH + '/v850/INC"'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' --lock_regs 0'
|
||||
CFLAGS += ' --migration_preprocessor_extensions'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' -Ol'
|
||||
|
||||
POST_ACTION = ''
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File renamed without changes.
@@ -0,0 +1,174 @@
|
||||
#include "macdefs.inc"
|
||||
|
||||
name OS_Core
|
||||
|
||||
COMMON INTVEC:CODE
|
||||
|
||||
;********************************************************************
|
||||
;
|
||||
; function:
|
||||
; description: Trap 0x10 vector used for context switch
|
||||
; Right now, all TRAPs to $1x are trated the same way
|
||||
;
|
||||
org 50h
|
||||
jr OSCtxSW
|
||||
|
||||
|
||||
;********************************************************************
|
||||
;
|
||||
; function:
|
||||
; description: Timer 40 compare match interrupt used for system
|
||||
; tick interrupt
|
||||
;
|
||||
org 0x220
|
||||
jr OSTickIntr
|
||||
|
||||
org 0x0520
|
||||
jr uarta1_int_r
|
||||
|
||||
RSEG CODE(1)
|
||||
|
||||
EXTERN rt_thread_switch_interrupt_flag
|
||||
EXTERN rt_interrupt_from_thread
|
||||
EXTERN rt_interrupt_to_thread
|
||||
|
||||
EXTERN rt_interrupt_enter
|
||||
EXTERN rt_interrupt_leave
|
||||
EXTERN rt_tick_increase
|
||||
EXTERN uarta1_receive_handler
|
||||
|
||||
PUBLIC rt_hw_interrupt_disable
|
||||
PUBLIC rt_hw_interrupt_enable
|
||||
PUBLIC rt_hw_context_switch_to
|
||||
PUBLIC OSCtxSW
|
||||
PUBLIC OS_Restore_CPU_Context
|
||||
|
||||
rt_hw_interrupt_disable:
|
||||
stsr psw, r1
|
||||
di
|
||||
jmp [lp]
|
||||
|
||||
rt_hw_interrupt_enable:
|
||||
ldsr r1, psw
|
||||
jmp [lp]
|
||||
|
||||
OS_Restore_CPU_Context:
|
||||
mov sp, ep
|
||||
sld.w 4[ep], r2
|
||||
sld.w 8[ep], r5
|
||||
sld.w 12[ep],r6
|
||||
sld.w 16[ep],r7
|
||||
sld.w 20[ep],r8
|
||||
sld.w 24[ep],r9
|
||||
sld.w 28[ep],r10
|
||||
sld.w 32[ep],r11
|
||||
sld.w 36[ep],r12
|
||||
sld.w 40[ep],r13
|
||||
sld.w 44[ep],r14
|
||||
sld.w 48[ep],r15
|
||||
sld.w 52[ep],r16
|
||||
|
||||
;See what was the latest interruption (trap or interrupt)
|
||||
stsr ecr, r17 ;Move ecr to r17
|
||||
mov 0x050,r1
|
||||
cmp r1, r17 ;If latest break was due to TRAP, set EP
|
||||
be _SetEP
|
||||
|
||||
_ClrEP:
|
||||
mov 0x20, r17 ;Set only ID
|
||||
ldsr r17, psw
|
||||
|
||||
;Restore caller address
|
||||
sld.w 56[ep], r1
|
||||
ldsr r1, EIPC
|
||||
;Restore PSW
|
||||
sld.w 60[ep], r1
|
||||
andi 0xffdf,r1,r1
|
||||
ldsr r1, EIPSW
|
||||
sld.w 0[ep], r1
|
||||
dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
|
||||
|
||||
;Return from interrupt starts new task!
|
||||
reti
|
||||
|
||||
_SetEP:
|
||||
mov 0x60, r17 ;Set both EIPC and ID bits
|
||||
ldsr r17, psw
|
||||
|
||||
;Restore caller address
|
||||
sld.w 56[ep], r1
|
||||
ldsr r1, EIPC
|
||||
;Restore PSW
|
||||
sld.w 60[ep], r1
|
||||
andi 0xffdf,r1,r1
|
||||
ldsr r1, EIPSW
|
||||
sld.w 0[ep], r1
|
||||
dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31}
|
||||
|
||||
;Return from interrupt starts new task!
|
||||
reti
|
||||
|
||||
//rseg CODE:CODE
|
||||
//public rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
;Load stack pointer of the task to run
|
||||
ld.w 0[r1], sp ;load sp from struct
|
||||
|
||||
;Restore all Processor registers from stack and return from interrupt
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
OSCtxSW:
|
||||
SAVE_CPU_CTX ;Save all CPU registers
|
||||
|
||||
mov rt_interrupt_from_thread, r21
|
||||
ld.w 0[r21], r21
|
||||
st.w sp, 0[r21]
|
||||
|
||||
mov rt_interrupt_to_thread, r1
|
||||
ld.w 0[r1], r1
|
||||
ld.w 0[r1], sp
|
||||
|
||||
;Restore all Processor registers from stack and return from interrupt
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
rt_hw_context_switch_interrupt_do:
|
||||
mov rt_thread_switch_interrupt_flag, r8
|
||||
mov 0, r9
|
||||
st.b r9, 0[r8]
|
||||
|
||||
mov rt_interrupt_from_thread, r21
|
||||
ld.w 0[r21], r21
|
||||
st.w sp, 0[r21]
|
||||
|
||||
mov rt_interrupt_to_thread, r1
|
||||
ld.w 0[r1], r1
|
||||
ld.w 0[r1], sp
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
OSTickIntr:
|
||||
SAVE_CPU_CTX ;Save current task's registers
|
||||
jarl rt_interrupt_enter,lp
|
||||
jarl rt_tick_increase,lp
|
||||
jarl rt_interrupt_leave,lp
|
||||
|
||||
mov rt_thread_switch_interrupt_flag, r8
|
||||
ld.w 0[r8],r9
|
||||
cmp 1, r9
|
||||
be rt_hw_context_switch_interrupt_do
|
||||
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
uarta1_int_r:
|
||||
SAVE_CPU_CTX ;Save current task's registers
|
||||
jarl rt_interrupt_enter,lp
|
||||
jarl uarta1_receive_handler,lp
|
||||
jarl rt_interrupt_leave,lp
|
||||
|
||||
mov rt_thread_switch_interrupt_flag, r8
|
||||
ld.w 0[r8],r9
|
||||
cmp 1, r9
|
||||
be rt_hw_context_switch_interrupt_do
|
||||
|
||||
jr OS_Restore_CPU_Context
|
||||
|
||||
END
|
||||
@@ -10,7 +10,7 @@
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-02-23 Bernard the first version
|
||||
* 2012-09-23 lgnq initialize register r31(LP) with texit
|
||||
* 2012-09-23 lgnq set the texit to R31
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
File renamed without changes.
Reference in new issue
Block a user