Merge pull request #2324 from wangyq2018/es32f0654

[bsp] add bsp es32f0654
2026-11-09 20:45:41 +08:00 · 2019-02-14 12:13:18 +08:00
commit c621ff5389
@@ -0,0 +1,25 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ES32F0654LT
+    bool
+    default y
+
+source "drivers/Kconfig"
@@ -0,0 +1,95 @@
+# ES-PDS-ES32F0654 开发板 BSP 说明
+标签： EastSoft、国产MCU、Cortex-M0、ES32F0654LT
+
+## 1. 简介
+
+本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0654 开发板提供的 BSP (板级支持包) 说明。
+通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+主要内容如下：
+ES-PDS-ES32F0654 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48Mhz(实际使用24Mhz)，可满足基础功能测试及高端功能扩展等开发需求。
+
+开发板外观如下图所示：
+
+ES-PDS-ES32F0654-V1.0
+
+![ES32F0654](figures/ES-PDS-ES32F0654-V1.0.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：ES32F0654LT，主频 24MHz，256KB FLASH，32KB RAM，54 GPIOs
+- 外部 FLASH：W25Q128（SPI，16MB）、EEPROM（24c02）
+- 常用外设
+  - LED：2个，(红色，PC8-PC9)
+  - 按键：3个，K1(PF00)，K2（PF01)，RESET(MRST)
+- 常用接口：串口、GPIO、SPI、I2C
+- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
+
+外设支持:
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                              |
+| :---------------- | :----------: | :------------------------------------ |
+| GPIO              |     支持     | 54 GPIOs                              |
+| UART              |     支持     | UART0/1/2/3                           |
+
+| **片上外设**      | **支持情况** | **备注**                              |
+
+| **扩展模块**      | **支持情况** | **备注**                              |
+
+更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
+
+## 2. 快速上手
+
+本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+### 硬件连接
+
+使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART2_TX(PC12)、UART2_RX(PD2)、GND 接到串口工具上。
+
+使用ESlinkⅡ(mini)连接开发板如下图所示：
+
+ESLinkⅡ(mini) + ES-PDS-ES32F0654-V1.0
+
+![ESLinkII](figures/ESLinkII-mini.jpg)
+
+### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
+
+### 运行结果
+
+下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.0 build Jan 28 2019
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+## 3. 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 uart2 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+
+## 4. 联系人信息
+
+- [wangyongquan](https://github.com/wangyq2018) 
+
+## 5. 参考
+
+- [ EastSoft 官网](http://www.essemi.com)
+
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+objs = []
+cwd = str(Dir('#'))
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,39 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+
+CPPPATH = [cwd, str(Dir('#'))]
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,31 @@
+/*
+ * File      : main.c
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-01-28     wangyq        first implementation
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN 39
+
+int main(void)
+{
+    int count = 1;
+    /* set PC08 pin mode to output */
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}
@@ -0,0 +1,41 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        menu "UART Drivers"
+            config BSP_USING_UART0
+                bool "Enable UART0 PB10/PB11(T/R)"
+                select RT_USING_SERIAL
+                default n
+
+            config BSP_USING_UART1
+                bool "Enable UART1 PC10/PC11(T/R)"
+                select RT_USING_SERIAL
+                default n
+        
+            config BSP_USING_UART2
+                bool "Enable UART2 PC12/PD02(T/R)"
+                select RT_USING_SERIAL
+                default y
+
+            config BSP_USING_UART3
+                bool "Enable UART3 PC04/PC05(T/R)"
+                select RT_USING_SERIAL
+                default n
+        endmenu
+
+    endmenu
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "Offboard Peripheral Drivers"
+
+    endmenu
+
+endmenu
@@ -0,0 +1,19 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split('''
+board.c
+''')
+
+# add gpio drivers.
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+CPPPATH = [cwd]
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,114 @@
+/*
+ * File      : board.c
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-01-23     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include "drv_usart.h"
+#include "drv_gpio.h"
+#include <ald_cmu.h>
+#include <ald_gpio.h>
+
+/**
+ * @addtogroup es32f0
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+}
+
+/*******************************************************************************
+ * Function Name  : SystemClock_Configuration
+ * Description    : Configures the System Clock.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SystemClock_Config(void)
+{
+    /* hosc 8MHz, from hosc/2 pll to 48MHz */
+    cmu_pll1_config(CMU_PLL1_INPUT_HOSC_2, CMU_PLL1_OUTPUT_48M);
+
+    /*  MCLK 48MHz*/
+    cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
+
+    /* SYSCLK 24MHz */
+    cmu_div_config(CMU_SYS, CMU_DIV_2);
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    rt_uint32_t _mclk;
+    rt_uint32_t _sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
+
+    /* get hrc clock*/
+    _mclk = cmu_get_clock();
+
+    /* SYSCLK = MCLK/SYSDIV */
+    SysTick_Config(_mclk / (RT_TICK_PER_SECOND << _sys_div));
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void systick_irq_cbk(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/*@}*/
+/**
+ * This function will initial ES32F0 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* NVIC Configuration */
+    NVIC_Configuration();
+
+    /*System Clock Configuration */
+    SystemClock_Config();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
@@ -0,0 +1,36 @@
+/*
+ * File      : board.h
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-01-23     wangyq        the first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <es32f065x.h>
+
+#define ES32F0_SRAM_SIZE    0x8000
+#define ES32F0_SRAM_END     (0x20000000 + ES32F0_SRAM_SIZE)
+
+#ifdef __CC_ARM
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+    extern int __bss_end;
+    #define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+
+#define HEAP_END    ES32F0_SRAM_END
+
+void rt_hw_board_init(void);
+
+#endif
@@ -0,0 +1,17 @@
+/*
+ * File      : drv_gpio.h
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-01-23     wangyq        the first version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif
@@ -0,0 +1,17 @@
+/*
+ * File      : drv_usart.h
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-01-23     wangyq        the first version
+ */
+
+#ifndef DRV_USART_H__
+#define DRV_USART_H__
+
+int rt_hw_usart_init(void);
+
+#endif
@@ -0,0 +1,14 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
@@ -0,0 +1,28 @@
+/**
+  *********************************************************************************
+  *
+  * @file    system_es32f065x.c
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer
+  *
+  * @version V1.0
+  * @date    6 Dec 2018
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "utils.h"
+
+
+/**
+  * @brief  Configuring system clock before startup.
+  * @note   This function must be used after reset.
+  * @retval None
+  */
+void system_init (void)
+{
+	/* do nothing */
+}
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
@@ -0,0 +1,14 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<title>Redirect to the CMSIS main page after 0 seconds</title>
+<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
+<meta name="keywords" content="automatic redirection">
+</head>
+
+<body>
+
+If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
+
+</body>
+</html>
@@ -0,0 +1,186 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_bkpc.h
+  * @brief   Header file of BKPC module driver.
+  *
+  * @version V1.0
+  * @date    15 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ********************************************************************************
+  */
+
+#ifndef __ALD_BKPC_H__
+#define __ALD_BKPC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup BKPC
+  * @{
+  */
+
+/** @defgroup BKPC_Public_Macros BKPC Public Macros
+  * @{
+  */
+#define BKPC_LOCK()     (WRITE_REG(BKPC->PROT, 0))
+#define BKPC_UNLOCK()       (WRITE_REG(BKPC->PROT, 0x9669AA55))
+#define BKPC_LRC_ENABLE()           \
+do {                        \
+    BKPC_UNLOCK();              \
+    SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);   \
+    BKPC_LOCK();                \
+} while (0)
+#define BKPC_LRC_DISABLE()          \
+do {                        \
+    BKPC_UNLOCK();              \
+    CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
+    BKPC_LOCK();                \
+} while (0)
+#define BKPC_LOSM_ENABLE()          \
+do {                        \
+    BKPC_UNLOCK();              \
+    SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);  \
+    BKPC_LOCK();                \
+} while (0)
+#define BKPC_LOSM_DISABLE()         \
+do {                        \
+    BKPC_UNLOCK();              \
+    CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
+    BKPC_LOCK();                \
+} while (0)
+#define BKPC_LOSC_ENABLE()          \
+do {                        \
+    BKPC_UNLOCK();              \
+    SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);  \
+    BKPC_LOCK();                \
+} while (0)
+#define BKPC_LOSC_DISABLE()         \
+do {                        \
+    BKPC_UNLOCK();              \
+    CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
+    BKPC_LOCK();                \
+} while (0)
+/**
+  * @}
+  */
+
+/** @defgroup BKPC_Public_Types BKPC Public Types
+  * @{
+  */
+/**
+  * @brief BKPC ldo output select
+  */
+typedef enum
+{
+    BKPC_LDO_OUTPUT_1_6 = 0x0,  /**< 1.6V */
+    BKPC_LDO_OUTPUT_1_3 = 0x1,  /**< 1.3V */
+    BKPC_LDO_OUTPUT_1_4 = 0x2,  /**< 1.4V */
+    BKPC_LDO_OUTPUT_1_5 = 0x4,  /**< 1.5V */
+} bkpc_ldo_output_t;
+
+/**
+  * @brief BKPC BOR voltage select
+  */
+typedef enum
+{
+    BKPC_BOR_VOL_1_7  = 0x0,    /**< 1.7V */
+    BKPC_BOR_VOL_2_0  = 0x1,    /**< 2.0V */
+    BKPC_BOR_VOL_2_1  = 0x2,    /**< 2.1V */
+    BKPC_BOR_VOL_2_2  = 0x3,    /**< 2.2V */
+    BKPC_BOR_VOL_2_3  = 0x4,    /**< 2.3V */
+    BKPC_BOR_VOL_2_4  = 0x5,    /**< 2.4V */
+    BKPC_BOR_VOL_2_5  = 0x6,    /**< 2.5V */
+    BKPC_BOR_VOL_2_6  = 0x7,    /**< 2.6V */
+    BKPC_BOR_VOL_2_8  = 0x8,    /**< 2.8V */
+    BKPC_BOR_VOL_3_0  = 0x9,    /**< 3.0V */
+    BKPC_BOR_VOL_3_1  = 0xA,    /**< 3.1V */
+    BKPC_BOR_VOL_3_3  = 0xB,    /**< 3.3V */
+    BKPC_BOR_VOL_3_6  = 0xC,    /**< 3.6V */
+    BKPC_BOR_VOL_3_7  = 0xD,    /**< 3.7V */
+    BKPC_BOR_VOL_4_0  = 0xE,    /**< 4.0V */
+    BKPC_BOR_VOL_4_3  = 0xF,    /**< 4.3V */
+} bkpc_bor_vol_t;
+
+/**
+  * @}
+  */
+
+/**
+  * @defgroup BKPC_Private_Macros BKPC Private Macros
+  * @{
+  */
+#define IS_BKPC_LDO_OUTPUT(x)   (((x) == BKPC_LDO_OUTPUT_1_6) || \
+                                 ((x) == BKPC_LDO_OUTPUT_1_3) || \
+                                 ((x) == BKPC_LDO_OUTPUT_1_4) || \
+                                 ((x) == BKPC_LDO_OUTPUT_1_5))
+#define IS_BKPC_BOR_VOL(x)  (((x) == BKPC_BOR_VOL_1_7) || \
+                                 ((x) == BKPC_BOR_VOL_2_0) || \
+                                 ((x) == BKPC_BOR_VOL_2_1) || \
+                                 ((x) == BKPC_BOR_VOL_2_2) || \
+                                 ((x) == BKPC_BOR_VOL_2_3) || \
+                                 ((x) == BKPC_BOR_VOL_2_4) || \
+                                 ((x) == BKPC_BOR_VOL_2_5) || \
+                                 ((x) == BKPC_BOR_VOL_2_6) || \
+                                 ((x) == BKPC_BOR_VOL_2_8) || \
+                                 ((x) == BKPC_BOR_VOL_3_0) || \
+                                 ((x) == BKPC_BOR_VOL_3_1) || \
+                                 ((x) == BKPC_BOR_VOL_3_3) || \
+                                 ((x) == BKPC_BOR_VOL_3_6) || \
+                                 ((x) == BKPC_BOR_VOL_3_7) || \
+                                 ((x) == BKPC_BOR_VOL_4_0) || \
+                                 ((x) == BKPC_BOR_VOL_4_3))
+#define IS_BKPC_RAM_IDX(x)  ((x) < 32)
+/**
+  * @}
+  */
+
+/** @addtogroup BKPC_Public_Functions
+  * @{
+  */
+/** @addtogroup BKPC_Public_Functions_Group1
+  * @{
+  */
+/* control functions */
+extern void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
+extern void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
+/**
+  * @}
+  */
+/** @addtogroup BKPC_Public_Functions_Group2
+  * @{
+  */
+/* IO operation functions */
+extern void bkpc_write_ram(uint8_t idx, uint32_t value);
+extern uint32_t bkpc_read_ram(uint8_t idx);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_BKPC_H__ */
@@ -0,0 +1,57 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_calc.h
+  * @brief   Header file of CALC module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ********************************************************************************
+  */
+
+#ifndef __ALD_CALC_H__
+#define __ALD_CALC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup CALC
+  * @{
+  */
+
+/** @addtogroup CALC_Public_Functions
+  * @{
+  */
+extern uint32_t calc_sqrt(uint32_t data);
+extern uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder);
+extern int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder);
+extern flag_status_t calc_get_dz_status(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_CALC_H__ */
@@ -0,0 +1,55 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_conf.h
+  * @brief   Enable/Disable the peripheral module.
+  *
+  * @version V1.0
+  * @date    18 Apr 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+
+#ifndef __ALD_CONF_H__
+#define __ALD_CONF_H__
+
+
+#define ALD_DMA
+#define ALD_GPIO
+#define ALD_UART
+#define ALD_LPUART
+#define ALD_USART
+#define ALD_SMARTCARD   /* The ALD_SMARTCARD depend on ALD_USART */
+#define ALD_I2C
+#define ALD_CMU
+#define ALD_RMU
+#define ALD_PMU
+#define ALD_WDT
+#define ALD_LCD
+#define ALD_RTC
+#define ALD_CAN
+#define ALD_FLASH
+#define ALD_ADC
+#define ALD_CRC
+#define ALD_CRYPT
+#define ALD_TIMER
+#define ALD_LPTIM
+#define ALD_PIS
+#define ALD_SPI
+#define ALD_CALC
+#define ALD_ACMP
+#define ALD_OPAMP
+#define ALD_TRNG
+#define ALD_TEMP
+#define ALD_BKPC
+#define ALD_DAC
+#define ALD_IAP
+
+#define TICK_INT_PRIORITY   3
+
+#endif
@@ -0,0 +1,197 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_crc.h
+  * @brief   Header file of CRC module driver.
+  *
+  * @version V1.0
+  * @date    6 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#ifndef __ALD_CRC_H__
+#define __ALD_CRC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+#include "ald_dma.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Public_Types CRC Public Types
+  * @{
+  */
+
+/**
+  * @brief CRC mode
+  */
+typedef enum
+{
+    CRC_MODE_CCITT = 0, /**< Ccitt */
+    CRC_MODE_8     = 1, /**< Crc8 */
+    CRC_MODE_16    = 2, /**< Crc16 */
+    CRC_MODE_32    = 3, /**< Crc32 */
+} crc_mode_t;
+
+/**
+  * @brief CRC input length
+  */
+typedef enum
+{
+    CRC_LEN_AUTO    = 0,    /**< Auto */
+    CRC_DATASIZE_8  = 1,    /**< Byte */
+    CRC_DATASIZE_16 = 2,    /**< Half word */
+    CRC_DATASIZE_32 = 3,    /**< Word */
+} crc_datasize_t;
+
+/**
+  * @brief CRC whether write error or no
+  */
+typedef enum
+{
+    CRC_WERR_NO  = 0,   /**< No error */
+    CRC_WERR_ERR = 1,   /**< Error */
+} crc_werr_t;
+
+/**
+  * @brief CRC state structures definition
+  */
+typedef enum
+{
+    CRC_STATE_RESET = 0x0,  /**< Peripheral is not initialized */
+    CRC_STATE_READY = 0x1,  /**< Peripheral Initialized and ready for use */
+    CRC_STATE_BUSY  = 0x2,  /**< An internal process is ongoing */
+    CRC_STATE_ERROR = 0x4,  /**< Error */
+} crc_state_t;
+
+/**
+  * @brief CRC init structure definition
+  */
+typedef struct
+{
+    crc_mode_t mode;    /**< CRC mode */
+    type_func_t data_rev;   /**< CRC data reverse or no */
+    type_func_t data_inv;   /**< CRC data inverse or no */
+    type_func_t chs_rev;    /**< CRC check sum reverse or no */
+    type_func_t chs_inv;    /**< CRC check sum inverse or no */
+    uint32_t seed;      /**< CRC seed */
+} crc_init_t;
+
+/**
+  * @brief  CRC Handle Structure definition
+  */
+typedef struct crc_handle_s
+{
+    CRC_TypeDef *perh;  /**< Register base address */
+    crc_init_t init;    /**< CRC required parameters */
+    uint8_t *cal_buf;   /**< The pointer of preparing buffer */
+    uint32_t *cal_res;  /**< The pointer of result */
+#ifdef ALD_DMA
+    dma_handle_t hdma;  /**< CRC DMA handle parameters */
+#endif
+    lock_state_t lock;  /**< Locking object */
+    crc_state_t state;  /**< CRC operation state */
+
+    void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */
+    void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */
+} crc_handle_t;
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Public_Macros CRC Public Macros
+  * @{
+  */
+#define CRC_ENABLE(handle)      (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
+#define CRC_DISABLE(handle)     (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
+#define CRC_RESET(handle)       (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
+#define CRC_DMA_ENABLE(handle)      (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
+#define CRC_DMA_DISABLE(handle)     (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
+#define CRC_CLEAR_ERROR_FLAG(handle)    (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Private_Macros   CRC Private Macros
+  * @{
+  */
+#define IS_CRC(x)   ((x) == CRC)
+#define IS_CRC_MODE(x)  (((x) == CRC_MODE_CCITT) || \
+             ((x) == CRC_MODE_8)     || \
+             ((x) == CRC_MODE_16)    || \
+             ((x) == CRC_MODE_32))
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Public_Functions
+  * @{
+  */
+
+/** @addtogroup CRC_Public_Functions_Group1
+  * @{
+  */
+ald_status_t crc_init(crc_handle_t *hperh);
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Public_Functions_Group2
+  * @{
+  */
+uint32_t crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
+/**
+  * @}
+  */
+
+#ifdef ALD_DMA
+/** @addtogroup CRC_Public_Functions_Group3
+  * @{
+  */
+ald_status_t crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
+ald_status_t crc_dma_pause(crc_handle_t *hperh);
+ald_status_t crc_dma_resume(crc_handle_t *hperh);
+ald_status_t crc_dma_stop(crc_handle_t *hperh);
+/**
+  * @}
+  */
+#endif
+/** @addtogroup CRC_Public_Functions_Group4
+  * @{
+  */
+crc_state_t crc_get_state(crc_handle_t *hperh);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_CRC_H__ */
@@ -0,0 +1,160 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_dbgc.h
+  * @brief   DEBUGCON module driver.
+  *
+  * @version V1.0
+  * @date    04 Jun 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#ifndef __ALD_DBGC_H__
+#define __ALD_DBGC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup DBGC DBGC
+  * @brief DBGC module driver
+  * @{
+  */
+
+
+
+/** @defgroup DBGC_Public_Types DBGC Public Types
+  * @{
+  */
+/**
+  * @brief Debug mode select
+  */
+typedef enum
+{
+    DEBC_MODE_SLEEP   = (1u << 0),  /**< Sleep mode */
+    DEBC_MODE_STOP1   = (1u << 1),  /**< STOP1 mode */
+    DEBC_MODE_STOP2   = (1u << 2),  /**< STOP2 mode */
+    DEBC_MODE_STANDBY = (1u << 3),  /**< Standby mode */
+} dbgc_mode_t;
+
+/**
+  * @brief Debug peripheral select
+  */
+typedef enum
+{
+    DEBC_PERH_TIMER0  = (1u << 0),          /**< AD16C4T0 */
+    DEBC_PERH_TIMER1  = (1u << 1),          /**< BS16T0 */
+    DEBC_PERH_TIMER2  = (1u << 2),          /**< GP16C2T0 */
+    DEBC_PERH_TIMER3  = (1u << 3),          /**< GP16C2T1 */
+    DEBC_PERH_TIMER4  = (1u << 4),          /**< BS16T1 */
+    DEBC_PERH_TIMER5  = (1u << 5),          /**< BS16T2 */
+    DEBC_PERH_TIMER6  = (1u << 6),          /**< GP16C4T0 */
+    DEBC_PERH_TIMER7  = (1u << 7),          /**< BS16T3 */
+    DEBC_PERH_I2C0    = (1u << 8),          /**< I2C0 SMBUS */
+    DEBC_PERH_I2C1    = (1u << 9),          /**< I2C1 SMBUS */
+    DEBC_PERH_CAN     = (1u << 12),         /**< CAN */
+    DEBC_PERH_LPTIM0  = (1u << 0)  | (1u << 16),    /**< LPTIM0 */
+    DEBC_PERH_IWDT    = (1u << 8)  | (1u << 16),    /**< IWDT */
+    DEBC_PERH_WWDT    = (1u << 9)  | (1u << 16),    /**< WWDT */
+    DEBC_PERH_RTC     = (1u << 10) | (1u << 16),    /**< RTC */
+} dbgc_perh_t;
+/**
+  * @}
+  */
+
+/** @defgroup DBGC_Public_Functions DBGC Public Functions
+  * @{
+  */
+/**
+  * @brief  Gets version.
+  * @retval Version
+  */
+__INLINE uint32_t dbgc_get_rev_id(void)
+{
+    return (DBGC->IDCODE >> 16);
+}
+
+/**
+  * @brief  Gets core id.
+  * @retval Core id
+  */
+__INLINE uint32_t dbgc_get_core_id(void)
+{
+    return (DBGC->IDCODE >> 12) & 0xF;
+}
+
+/**
+  * @brief  Gets device id
+  * @retval device id
+  */
+__INLINE uint32_t dbgc_get_device_id(void)
+{
+    return DBGC->IDCODE & 0xFFF;
+}
+
+/**
+  * @brief  Configures low power debug mode
+  * @param  mode: The mode of low power.
+  * @param  state: ENABLE/DISABLE
+  * @retval None
+  */
+__INLINE void dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
+{
+    if (state)
+        SET_BIT(DBGC->CR, mode);
+    else
+        CLEAR_BIT(DBGC->CR, mode);
+}
+
+/**
+  * @brief  Configures peripheral debug mode
+  * @param  perh: The peripheral.
+  * @param  state: ENABLE/DISABLE
+  * @retval None
+  */
+__INLINE void dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
+{
+    if ((perh >> 16) & 0x1)
+    {
+        if (state)
+            SET_BIT(DBGC->APB2FZ, perh);
+        else
+            CLEAR_BIT(DBGC->APB2FZ, perh);
+    }
+    else
+    {
+        if (state)
+            SET_BIT(DBGC->APB1FZ, perh);
+        else
+            CLEAR_BIT(DBGC->APB1FZ, perh);
+    }
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,122 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_flash.h
+  * @brief   Header file of FLASH driver
+  *
+  * @version V1.0
+  * @date    20 Nov 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#ifndef __ALD_FLASH_H__
+#define __ALD_FLASH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/**
+  * @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+#define FLASH_REG_UNLOCK()              \
+do {                            \
+    if (op_cmd == OP_FLASH)  {          \
+        WRITE_REG(MSC->FLASHKEY, 0x8ACE0246);   \
+        WRITE_REG(MSC->FLASHKEY, 0x9BDF1357);   \
+    }                       \
+    else {                      \
+        WRITE_REG(MSC->INFOKEY, 0x7153BFD9);    \
+        WRITE_REG(MSC->INFOKEY, 0x0642CEA8);    \
+    }                       \
+} while (0)
+#define FLASH_REQ()         (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
+#define FLASH_REQ_FIN()         (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
+#define FLASH_IAP_ENABLE()      (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
+#define FLASH_IAP_DISABLE()     (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
+#define FLASH_BASE_ADDR         0x00000000
+#define FLASH_PAGE_SIZE         1024UL
+#define FLASH_WORD_SIZE         8UL
+#define FLASH_TOTAL_SIZE        256UL
+#define FLASH_PAGE_MASK         (FLASH_PAGE_SIZE - 1)
+#define FLASH_WORD_MASK         (FLASH_WORD_SIZE - 1)
+#define IS_FLASH_ADDRESS(ADDR)      ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
+#define IS_4BYTES_ALIGN(ADDR)       (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
+#define FLASH_PAGE_ADDR(ADDR)       ((ADDR) & (~FLASH_PAGE_MASK))
+#define FLASH_PAGEEND_ADDR(ADDR)    ((ADDR) | FLASH_PAGE_MASK)
+#define FLASH_WORD_ADDR(ADDR)       ((ADDR) & (~FLASH_WORD_MASK))
+#define FLASH_WORDEND_ADDR(ADDR)    ((ADDR) | FLASH_WORD_MASK)
+#define INFO_PAGE_SIZE          1024UL
+#define INFO_PAGE_MASK          (INFO_PAGE_SIZE - 1)
+#define INFO_PAGE_ADDR(ADDR)        ((ADDR) & (~INFO_PAGE_MASK))
+
+#ifdef USE_FLASH_FIFO
+#define FLASH_FIFO 1
+#else
+#define FLASH_FIFO 0
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Private_Types FLASH Private Types
+  * @{
+  */
+typedef enum
+{
+    FLASH_CMD_AE     = 0x000051AE,  /**< Program area erase all */
+    FLASH_CMD_PE     = 0x00005EA1,  /**< Page erase  */
+    FLASH_CMD_WP     = 0x00005DA2,  /**< Word program */
+    FLASH_CMD_DATAPE = 0x00005BA4,  /**< Data flash page page erase */
+    FLASH_CMD_DATAWP = 0x00005AA5,  /**< Data flash word program */
+} flash_cmd_type;
+
+typedef enum
+{
+    OP_FLASH = 0,   /**< Operate Pragram area */
+    OP_INFO  = 1,   /**< Operate info area */
+} op_cmd_type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Flash_Public_Functions
+  * @{
+  */
+ald_status_t flash_write(uint32_t addr, uint8_t *buf, uint16_t len);
+ald_status_t flash_erase(uint32_t addr, uint16_t len);
+ald_status_t flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_FLASH_H__ */
@@ -0,0 +1,80 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_iap.h
+  * @brief   Header file of IAP module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ********************************************************************************
+  */
+
+#ifndef __ALD_IAP_H__
+#define __ALD_IAP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup IAP
+  * @{
+  */
+
+/**
+  * @defgroup IAP_Private_Macros IAP Private Macros
+  * @{
+  */
+#define IAP_WSP_ADDR    0x10000000
+#define IAP_PE_ADDR 0x10000004
+#define IAP_WP_ADDR 0x10000008
+#define IAP_DWP_ADDR    0x1000000c
+/**
+  * @}
+  */
+
+/** @defgroup IAP_Private_Types IAP Private Types
+  * @{
+  */
+typedef uint32_t (*IAP_PE)(uint32_t addr);
+typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data);
+typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h);
+typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
+/**
+  * @}
+  */
+
+/** @addtogroup IAP_Public_Functions
+  * @{
+  */
+uint32_t iap_erase_page(uint32_t addr);
+uint32_t iap_program_word(uint32_t addr, uint32_t data);
+uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h);
+uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_IAP_H__ */
@@ -0,0 +1,107 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_syscfg.h
+  * @brief   SYSCFG module driver.
+  *
+  * @version V1.0
+  * @date    04 Jun 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#ifndef __ALD_SYSCFG_H__
+#define __ALD_SYSCFG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup SYSCFG SYSCFG
+  * @brief SYSCFG module driver
+  * @{
+  */
+
+/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros
+  * @{
+  */
+#define SYSCFG_LOCK()       WRITE_REG(SYSCFG->PROT, 0x0)
+#define SYSCFG_UNLOCK()     WRITE_REG(SYSCFG->PROT, 0x55AA6996)
+#define GET_SYSCFG_LOCK()   READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
+
+#define BOOT_FROM_BOOT_ROM()                    \
+do {                                \
+    SYSCFG_UNLOCK();                    \
+    SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
+    CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);   \
+    SYSCFG_LOCK();                      \
+} while (0)
+
+#define BOOT_FROM_BOOT_FLASH()                  \
+do {                                \
+    SYSCFG_UNLOCK();                    \
+    CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);   \
+    SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
+    SYSCFG_LOCK();                      \
+} while (0)
+
+#define BOOT_FROM_FLASH()                   \
+do {                                \
+    SYSCFG_UNLOCK();                    \
+    CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);   \
+    CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);   \
+    SYSCFG_LOCK();                      \
+} while (0)
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSCFG_Public_Functions SYSCFG Public Functions
+  * @{
+  */
+__STATIC_INLINE__ void vtor_config(uint32_t offset, type_func_t status)
+{
+    SYSCFG_UNLOCK();
+
+    if (status)
+    {
+        MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3F));
+        SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
+    }
+    else
+    {
+        CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
+    }
+
+    SYSCFG_LOCK();
+    return;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,182 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_trng.h
+  * @brief   Header file of TRNG module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ********************************************************************************
+  */
+
+#ifndef __ALD_TRNG_H__
+#define __ALD_TRNG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup TRNG
+  * @{
+  */
+
+/** @defgroup TRNG_Public_Macros TRNG Public Macros
+  * @{
+  */
+#define TRNG_ENABLE()       (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
+#define TRNG_DISABLE()      (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
+#define TRNG_ADJM_ENABLE()  (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
+#define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
+/**
+  * @}
+  */
+
+/** @defgroup TRNG_Public_Types TRNG Public Types
+  * @{
+  */
+/**
+  * @brief Data width
+  */
+typedef enum
+{
+    TRNG_DSEL_1B  = 0x0,    /**< 1-bit */
+    TRNG_DSEL_8B  = 0x1,    /**< 8-bit */
+    TRNG_DSEL_16B = 0x2,    /**< 16-bit */
+    TRNG_DSEL_32B = 0x3,    /**< 32-bit */
+} trng_data_width_t;
+
+/**
+  * @brief seed type
+  */
+typedef enum
+{
+    TRNG_SEED_TYPE_0    = 0x0,  /**< Using 0 as seed */
+    TRNG_SEED_TYPE_1    = 0x1,  /**< Using 1 as seed */
+    TRNG_SEED_TYPE_LAST = 0x2,  /**< Using last seed */
+    TRNG_SEED_TYPE_SEED = 0x3,  /**< Using value of register */
+} trng_seed_type_t;
+
+/**
+  * @brief TRNG init structure definition
+  */
+typedef struct
+{
+    trng_data_width_t data_width;   /**< The width of data */
+    trng_seed_type_t seed_type; /**< The seed type */
+    uint32_t seed;          /**< The value of seed */
+    uint16_t t_start;       /**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */
+    uint8_t adjc;           /**< Adjust parameter */
+    uint8_t posten;
+} trng_init_t;
+
+/**
+  * @brief State type
+  */
+typedef enum
+{
+    TRNG_STATUS_START = (1U << 0),  /**< Start state */
+    TRNG_STATUS_DAVLD = (1U << 1),  /**< Data valid state */
+    TRNG_STATUS_SERR  = (1U << 2),  /**< Error state */
+} trng_status_t;
+
+/**
+  * @brief Interrupt type
+  */
+typedef enum
+{
+    TRNG_IT_START = (1U << 0),  /**< Start */
+    TRNG_IT_DAVLD = (1U << 1),  /**< Data valid */
+    TRNG_IT_SERR  = (1U << 2),  /**< Error */
+} trng_it_t;
+
+/**
+  * @brief Interrupt flag type
+  */
+typedef enum
+{
+    TRNG_IF_START = (1U << 0),  /**< Start */
+    TRNG_IF_DAVLD = (1U << 1),  /**< Data valid */
+    TRNG_IF_SERR  = (1U << 2),  /**< Error */
+} trng_flag_t;
+/**
+  * @}
+  */
+
+/**
+  * @defgroup TRNG_Private_Macros TRNG Private Macros
+  * @{
+  */
+#define IS_TRNG_DATA_WIDTH(x)   (((x) == TRNG_DSEL_1B)  || \
+                                 ((x) == TRNG_DSEL_8B)  || \
+                                 ((x) == TRNG_DSEL_16B) || \
+                                 ((x) == TRNG_DSEL_32B))
+#define IS_TRNG_SEED_TYPE(x)    (((x) == TRNG_SEED_TYPE_0)    || \
+                                 ((x) == TRNG_SEED_TYPE_1)    || \
+                                 ((x) == TRNG_SEED_TYPE_LAST) || \
+                                 ((x) == TRNG_SEED_TYPE_SEED))
+#define IS_TRNG_STATUS(x)   (((x) == TRNG_STATUS_START)  || \
+                                 ((x) == TRNG_STATUS_DAVLD)  || \
+                                 ((x) == TRNG_STATUS_SERR))
+#define IS_TRNG_IT(x)   (((x) == TRNG_IT_START)  || \
+                         ((x) == TRNG_IT_DAVLD)  || \
+                         ((x) == TRNG_IT_SERR))
+#define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START)  || \
+                         ((x) == TRNG_IF_DAVLD)  || \
+                         ((x) == TRNG_IF_SERR))
+#define IS_TRNG_ADJC(x) ((x) < 4)
+/**
+  * @}
+  */
+
+/** @addtogroup TRNG_Public_Functions
+  * @{
+  */
+/** @addtogroup TRNG_Public_Functions_Group1
+  * @{
+  */
+/* Initialization functions */
+extern void trng_init(trng_init_t *init);
+/**
+  * @}
+  */
+/** @addtogroup TRNG_Public_Functions_Group2
+  * @{
+  */
+/* Control functions */
+extern uint32_t trng_get_result(void);
+extern void trng_interrupt_config(trng_it_t it, type_func_t state);
+extern flag_status_t trng_get_status(trng_status_t status);
+extern it_status_t trng_get_it_status(trng_it_t it);
+extern flag_status_t trng_get_flag_status(trng_flag_t flag);
+extern void trng_clear_flag_status(trng_flag_t flag);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_TRNG_H__ */
@@ -0,0 +1,117 @@
+/**
+ *********************************************************************************
+ *
+ * @file    ald_wdt.h
+ * @brief   Header file of WDT module driver.
+ *
+ * @version V1.0
+ * @date    18 Dec 2017
+ * @author  AE Team
+ * @note
+ *
+ * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+ *
+ ********************************************************************************
+ */
+
+#ifndef __ALD_WDT_H__
+#define __ALD_WDT_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+/** @addtogroup ES32FXXX_ALD
+ * @{
+ */
+
+/** @addtogroup WDT
+ * @{
+ */
+
+/** @defgroup WDT_Public_Types WDT Public Types
+ * @{
+ */
+
+/**
+  * @brief Wwdt no dog window
+  */
+typedef enum
+{
+    WWDT_WIN_25 = 0x0,  /**< No dog window size: 25% */
+    WWDT_WIN_50 = 0x1,  /**< No dog window size: 50% */
+    WWDT_WIN_75 = 0x2,  /**< No dog window size: 75% */
+    WWDT_WIN_00 = 0x3,  /**< No dog window size: 0% */
+} wwdt_win_t;
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup WDT_Private_Macros WDT Private Macros
+ * @{
+ */
+#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);}
+#define WWDT_LOCK()   {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);}
+#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);}
+#define IWDT_LOCK()   {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);}
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup WDT_Private_Macros WDT Private Macros
+ * @{
+ */
+#define IS_WWDT_WIN_TYPE(x)     ((x == WWDT_WIN_25) || \
+                                 (x == WWDT_WIN_50) || \
+                                 (x == WWDT_WIN_75) || \
+                                 (x == WWDT_WIN_00))
+#define IS_FUNC_STATE(x)    (((x) == DISABLE) || \
+                 ((x) == ENABLE))
+/**
+ * @}
+ */
+
+/** @addtogroup WWDT_Public_Functions
+ * @{
+ */
+void wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt);
+void wwdt_start(void);
+uint32_t wwdt_get_value(void);
+it_status_t wwdt_get_flag_status(void);
+void wwdt_clear_flag_status(void);
+void wwdt_feed_dog(void);
+/**
+ * @}
+ */
+
+/** @addtogroup IWDT_Public_Functions
+ * @{
+ */
+void iwdt_init(uint32_t load, type_func_t interrupt);
+void iwdt_start(void);
+uint32_t iwdt_get_value(void);
+it_status_t iwdt_get_flag_status(void);
+void iwdt_clear_flag_status(void);
+void iwdt_feed_dog(void);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_WDT_H__ */
@@ -0,0 +1,127 @@
+/**
+  *********************************************************************************
+  *
+  * @file    type.h
+  * @brief   define type
+  *
+  * @version V1.0
+  * @date    17 Apr 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#ifndef __TYPE_H__
+#define __TYPE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#if defined (__CC_ARM)
+#define __INLINE__      __inline
+#define __STATIC_INLINE__   static __inline
+#else
+#define __INLINE__      inline
+#define __STATIC_INLINE__   static inline
+#endif
+
+#define __isr__
+
+typedef enum
+{
+    RESET = 0x0,
+    SET   = 0x1,
+} flag_status_t, it_status_t;
+
+typedef enum
+{
+    BIT_RESET = 0x0,
+    BIT_SET   = 0x1,
+} bit_status_t;
+
+typedef enum
+{
+    DISABLE = 0x0,
+    ENABLE  = 0x1,
+} type_func_t;
+#define IS_FUNC_STATE(x)    (((x) == DISABLE) || ((x) == ENABLE))
+
+typedef enum
+{
+    FALSE = 0x0,
+    TRUE  = 0x1,
+} type_bool_t;
+
+typedef enum
+{
+    UNLOCK = 0x0,
+    LOCK   = 0x1,
+} lock_state_t;
+#define IS_LOCK_STATE(x)    (((x) == UNLOCK) || ((x) == LOCK))
+
+
+#define BIT(x)          ((1U << (x)))
+#define BITS(s, e)      ((0xffffffff << (s)) & (0xffffffff >> (31 - (e))))
+#define SET_BIT(reg, bit)   ((reg) |= (bit))
+#define CLEAR_BIT(reg, bit) ((reg) &= ~(bit))
+#define READ_BIT(reg, bit)  ((reg) & (bit))
+#define READ_BITS(reg, msk, s)  (((reg) & (msk)) >> (s))
+#define CLEAR_REG(reg)      ((reg) = (0x0))
+#define WRITE_REG(reg, val) ((reg) = (val))
+#define READ_REG(reg)       ((reg))
+#define MODIFY_REG(reg, clearmask, setmask) \
+    WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))
+#define UNUSED(x)   ((void)(x))
+
+#ifdef USE_ASSERT
+#define assert_param(x)         \
+do {                    \
+    if (!(x)) {         \
+        __disable_irq();    \
+        while (1)       \
+            ;       \
+    }               \
+} while (0)
+#else
+#define assert_param(x)
+#endif
+
+
+#define PER_MEM_BASE         ((uint32_t) 0x40000000UL)  /* PER base address  */
+#define RAM_MEM_BASE         ((uint32_t) 0x20000000UL)  /* RAM base address  */
+#define BITBAND_PER_BASE     ((uint32_t) 0x42000000UL)  /* Peripheral Address Space bit-band area */
+#define BITBAND_RAM_BASE     ((uint32_t) 0x22000000UL)  /* SRAM Address Space bit-band area */
+
+__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val)
+{
+    uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2);
+    *((volatile uint32_t *)tmp) = (uint32_t)val;
+}
+
+__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
+{
+    uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2);
+    *((volatile uint32_t *)tmp) = (uint32_t)val;
+}
+
+#if defined ( __GNUC__ )
+#ifndef __weak
+#define __weak   __attribute__((weak))
+#endif  /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif  /* __packed */
+#endif /* __GNUC__ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __TYPE_H__ */
@@ -0,0 +1,163 @@
+/**
+  *********************************************************************************
+  *
+  * @file    utils.h
+  * @brief   This file contains the Utilities functions/types for the driver.
+  *
+  * @version V1.0
+  * @date    07 Nov 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#ifndef __UTILS_H__
+#define __UTILS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdlib.h>
+#include "ald_conf.h"
+#include "type.h"
+#include "es32f065x.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup UTILS
+  * @{
+  */
+
+/** @defgroup ALD_Public_Types Public Types
+  * @{
+  */
+/**
+  * @brief  SysTick interval
+  */
+extern uint32_t __systick_interval;
+
+/**
+  * @brief  ALD Status structures definition
+  */
+typedef enum
+{
+    OK      = 0x0,
+    ERROR   = 0x1,
+    BUSY    = 0x2,
+    TIMEOUT = 0x3
+} ald_status_t;
+
+/**
+  * @brief  SysTick interval definition
+  */
+typedef enum
+{
+    SYSTICK_INTERVAL_1MS    = 1000, /**< Interval is 1ms */
+    SYSTICK_INTERVAL_10MS   = 100,  /**< Interval is 10ms */
+    SYSTICK_INTERVAL_100MS  = 10,   /**< Interval is 100ms */
+    SYSTICK_INTERVAL_1000MS = 1,    /**< Interval is 1s */
+} systick_interval_t;
+/**
+  * @}
+  */
+
+/** @defgroup ALD_Public_Macros Public Macros
+  * @{
+  */
+#define ALD_MAX_DELAY   0xFFFFFFFF
+
+#define IS_BIT_SET(reg, bit)    (((reg) & (bit)) != RESET)
+#define IS_BIT_CLR(reg, bit)    (((reg) & (bit)) == RESET)
+#define RESET_HANDLE_STATE(x)   ((x)->state = 0)
+#define __LOCK(x)               \
+    do {                    \
+        if ((x)->lock == LOCK) {    \
+            return BUSY;        \
+        }               \
+        else {              \
+            (x)->lock = LOCK;   \
+        }               \
+    } while (0)
+
+#define __UNLOCK(x)             \
+    do {                    \
+        (x)->lock = UNLOCK;     \
+    } while (0)
+
+/**
+  * @}
+  */
+
+/** @defgroup ALD_Private_Macros Private Macros
+  * @{
+  */
+#define IS_PRIO(x)  ((x) < 4)
+#define IS_SYSTICK_INTERVAL(x)  (((x) == SYSTICK_INTERVAL_1MS)   || \
+                                 ((x) == SYSTICK_INTERVAL_10MS)  || \
+                                 ((x) == SYSTICK_INTERVAL_100MS) || \
+                                 ((x) == SYSTICK_INTERVAL_1000MS))
+/**
+  * @}
+  */
+
+/** @addtogroup ALD_Public_Functions
+  * @{
+  */
+
+/** @addtogroup ALD_Public_Functions_Group1
+  * @{
+  */
+
+/* Initialization functions */
+void mcu_ald_init(void);
+void __init_tick(uint32_t prio);
+void systick_interval_select(systick_interval_t value);
+
+/**
+  * @}
+  */
+
+/** @addtogroup ALD_Public_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions */
+void __inc_tick(void);
+void __delay_ms(__IO uint32_t delay);
+uint32_t __get_tick(void);
+void __suspend_tick(void);
+void __resume_tick(void);
+void systick_irq_cbk(void);
+uint32_t get_ald_version(void);
+ald_status_t __wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout);
+void mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status);
+uint32_t mcu_get_tick(void);
+uint32_t mcu_get_cpu_id(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UTILS_H__ */
@@ -0,0 +1,14 @@
+<!doctype html>
+<html>
+<head>
+<meta charset='UTF-8'><meta name='viewport' content='width=device-width initial-scale=1'>
+<title>ReleaseNote</title></head>
+<body><h1>ES32F065x MD Release Note</h1>
+<h2>V1.00 2018-12-26</h2>
+<ol start='' >
+<li>First release</li>
+
+</ol>
+<p>&nbsp;</p>
+</body>
+</html>
@@ -0,0 +1,154 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_bkpc.c
+  * @brief   BKPC module driver.
+  *
+  * @version V1.0
+  * @date    15 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "ald_bkpc.h"
+#include "ald_rtc.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup BKPC BKPC
+  * @brief BKPC module driver
+  * @{
+  */
+#ifdef ALD_BKPC
+
+/** @defgroup BKPC_Public_Functions BKPC Public Functions
+  * @{
+  */
+
+/** @addtogroup BKPC_Public_Functions_Group1 Peripheral Control functions
+  * @brief Peripheral Control functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]  This section provides functions allowing to:
+    (+) bkpc_ldo_config() API can configure LDO in backup field.
+    (+) bkpc_bor_config() API can configure BOR in backup field.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure ldo in backup field
+  * @param  output: Output voltage select.
+  * @param  state: DISABLE/ENABLE.
+  * @retval None
+  */
+void bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state)
+{
+    assert_param(IS_BKPC_LDO_OUTPUT(output));
+    assert_param(IS_FUNC_STATE(state));
+
+    BKPC_UNLOCK();
+    MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS);
+
+    if (state)
+        MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS);
+
+    BKPC_LOCK();
+    return;
+}
+
+/**
+  * @brief  Configure bor voltage in backup field
+  * @param  vol: Voltage select.
+  * @param  state: DISABLE/ENABLE.
+  * @retval None
+  */
+void bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state)
+{
+    assert_param(IS_BKPC_BOR_VOL(vol));
+    assert_param(IS_FUNC_STATE(state));
+
+    BKPC_UNLOCK();
+    MODIFY_REG(BKPC->PCR, BKPC_PCR_BOREN_MSK, state << BKPC_PCR_BOREN_POS);
+
+    if (state)
+        MODIFY_REG(BKPC->PCR, BKPC_PCR_BORS_MSK, vol << BKPC_PCR_BORS_POSS);
+
+    BKPC_LOCK();
+    return;
+
+
+}
+/**
+  * @}
+  */
+
+/** @addtogroup BKPC_Public_Functions_Group2 IO operation functions
+  * @brief IO operation functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### IO operation functions #####
+  ==============================================================================
+  [..]  This section provides functions allowing to:
+    (+) bkpc_write_ram() API can write data in backup ram.
+    (+) bkpc_read_ram() API can read data from backup ram.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Write data into backup ram.
+  * @param  idx: Index of backup word.
+  * @param  value: Value which will be written to backup ram.
+  * @retval None
+  */
+void bkpc_write_ram(uint8_t idx, uint32_t value)
+{
+    assert_param(IS_BKPC_RAM_IDX(idx));
+
+    RTC_UNLOCK();
+    WRITE_REG(RTC->BKPR[idx], value);
+    RTC_LOCK();
+
+    return;
+}
+
+/**
+  * @brief  Read data from backup ram.
+  * @param  idx: Index of backup word.
+  * @retval The data.
+  */
+uint32_t bkpc_read_ram(uint8_t idx)
+{
+    assert_param(IS_BKPC_RAM_IDX(idx));
+
+    return READ_REG(RTC->BKPR[idx]);
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* ALD_BKPC */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
@@ -0,0 +1,121 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_calc.c
+  * @brief   CALC module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "ald_calc.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup CALC CALC
+  * @brief CALC module driver
+  * @{
+  */
+#ifdef ALD_CALC
+
+/** @defgroup CALC_Public_Functions CALC Public Functions
+  * @brief    Accelerating calculate functions
+  *
+  * @verbatim
+  ==============================================================================
+              ##### Accelerating calculate functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Square root operation.
+      (+) Division.
+      (+) Get DZ flag.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Square root operation.
+  * @param  data: The data;
+  * @retval The value of square root.
+  */
+uint32_t calc_sqrt(uint32_t data)
+{
+    WRITE_REG(CALC->RDCND, data);
+    while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
+
+    return READ_REG(CALC->SQRTRES);
+}
+
+/**
+  * @brief  Calculating division.
+  * @param  dividend: The value of the dividend.
+  * @param  divisor: The value of the divisor.
+  * @param  remainder: The value of the remainder.
+  * @retval The result of division.
+  */
+uint32_t calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder)
+{
+    CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
+    SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
+    WRITE_REG(CALC->DIVDR, dividend);
+    WRITE_REG(CALC->DIVSR, divisor);
+
+    while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
+
+    *remainder = READ_REG(CALC->DIVRR);
+    return READ_REG(CALC->DIVQR);
+}
+
+/**
+  * @brief  Calculating division.
+  * @param  dividend: The value of the dividend.
+  * @param  divisor: The value of the divisor.
+  * @param  remainder: The value of the remainder.
+  * @retval The result of division.
+  */
+int32_t calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder)
+{
+    SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
+    SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
+    WRITE_REG(CALC->DIVDR, dividend);
+    WRITE_REG(CALC->DIVSR, divisor);
+
+    while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
+
+    *remainder = READ_REG(CALC->DIVRR);
+    return READ_REG(CALC->DIVQR);
+}
+
+/**
+  * @brief  Get the flag of divisor is zero.
+  * @retval The status, SET/RESET.
+  */
+flag_status_t calc_get_dz_status(void)
+{
+    if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK))
+        return SET;
+
+    return RESET;
+}
+
+/**
+  * @}
+  */
+#endif /* ALD_CALC */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
@@ -0,0 +1,149 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_iap.c
+  * @brief   IAP module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "ald_iap.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup IAP IAP
+  * @brief IAP module driver
+  * @{
+  */
+#ifdef ALD_IAP
+
+
+/** @defgroup IAP_Public_Functions IAP Public Functions
+  *
+  * @verbatim
+  ==============================================================================
+              #####  Erase and Program flash functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Erase flash.
+      (+) Program flash.
+
+    @endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Erases a specified page.
+  * @param  addr: The beginning address of the page to be erased.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t iap_erase_page(uint32_t addr)
+{
+    uint32_t status;
+    IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR);
+
+    __disable_irq();
+    status = (*iap_pe)(addr);
+    __enable_irq();
+
+    return !status;
+}
+
+/**
+  * @brief  Programs a word at a specified address.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data: Specifies the data to be programmed.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t iap_program_word(uint32_t addr, uint32_t data)
+{
+    uint32_t status;
+    IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR);
+
+    if (addr & 0x3)
+        return 1;
+
+    __disable_irq();
+    status = (*iap_wp)(addr, data);
+    __enable_irq();
+
+    return !status;
+}
+
+/**
+  * @brief  Programs double words at a specified address.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data_l: Specifies the LSB data to be programmed.
+  * @param  data_h: Specifies the MSB data to be programmed.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
+{
+    uint32_t status;
+    IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR);
+
+    if (addr & 0x3)
+        return 1;
+
+    __disable_irq();
+    status = (*iap_dwp)(addr, data_l, data_h);
+    __enable_irq();
+
+    return !status;
+}
+
+/**
+  * @brief  Programs datas at a specified address.
+  * @param  addr: Specifies the address to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  data: Specifies the data to be programmed.
+  * @param  len: Specifies the data length to be programmed.
+  *         Bit0-1 must be zero.
+  * @param  erase: Erase page flag before programming.
+  * @retval The result:
+  *           - 0: SUCCESS
+  *           - 1: ERROR
+  */
+uint32_t iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
+{
+    uint32_t status;
+    IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR);
+
+    if ((addr & 0x3) || (len & 0x3))
+        return 1;
+
+    __disable_irq();
+    status = (*iap_wsp)(addr, data, len, erase);
+    __enable_irq();
+
+    return !status;
+}
+/**
+  * @}
+  */
+#endif /* ALD_IAP */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
@@ -0,0 +1,146 @@
+/**
+  *********************************************************************************
+  *
+  * @file    ald_rmu.c
+  * @brief   RMU module driver.
+  *
+  * @version V1.0
+  * @date    04 Dec 2017
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "ald_rmu.h"
+#include "ald_syscfg.h"
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @defgroup RMU RMU
+  * @brief RMU module driver
+  * @{
+  */
+#ifdef ALD_RMU
+
+/** @defgroup RMU_Public_Functions RMU Public Functions
+  * @{
+  */
+
+/**
+  * @brief  Configure BOR parameters.
+  * @param  flt: filter time.
+  * @param  vol: The voltage.
+  * @param  state: The new status: ENABLE/DISABLE.
+  * @retval None
+  */
+void rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
+{
+    assert_param(IS_FUNC_STATE(state));
+
+    SYSCFG_UNLOCK();
+
+    if (state)
+    {
+        assert_param(IS_RMU_BORFLT(flt));
+        assert_param(IS_RMU_BORVOL(vol));
+
+        MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
+        MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
+        SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
+    }
+    else
+    {
+        CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
+    }
+
+    SYSCFG_LOCK();
+    return;
+}
+
+/**
+  * @brief  Get specified reset status
+  * @param  state: Speicifies the type of the reset,
+  * @retval The status: SET/RESET.
+  */
+flag_status_t rmu_get_reset_status(rmu_state_t state)
+{
+    assert_param(IS_RMU_STATE(state));
+
+    if (READ_BIT(RMU->RSTSR, state))
+        return SET;
+
+    return RESET;
+}
+
+/**
+  * @brief  Clear the specified reset status
+  * @param  state: Specifies the type of the reset,
+  * @retval None
+  */
+void rmu_clear_reset_status(rmu_state_t state)
+{
+    assert_param(IS_RMU_STATE_CLEAR(state));
+
+    SYSCFG_UNLOCK();
+    WRITE_REG(RMU->CRSTSR, state);
+    SYSCFG_LOCK();
+
+    return;
+}
+/**
+  * @brief  Reset peripheral device
+  * @param  perh: The peripheral device,
+  * @retval None
+  */
+void rmu_reset_periperal(rmu_peripheral_t perh)
+{
+    uint32_t idx, pos;
+
+    assert_param(IS_RMU_PERH(perh));
+
+    idx = (perh >> 27) & 0x7;
+    pos = perh & ~(0x7 << 27);
+    SYSCFG_UNLOCK();
+
+    switch (idx)
+    {
+    case 0:
+        WRITE_REG(RMU->AHB1RSTR, pos);
+        break;
+
+    case 1:
+        WRITE_REG(RMU->AHB2RSTR, pos);
+        break;
+
+    case 2:
+        WRITE_REG(RMU->APB1RSTR, pos);
+        break;
+
+    case 4:
+        WRITE_REG(RMU->APB2RSTR, pos);
+        break;
+
+    default:
+        break;
+    }
+
+    SYSCFG_LOCK();
+    return;
+}
+
+/**
+  * @}
+  */
+#endif /* ALD_RMU */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
@@ -0,0 +1,28 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = []
+
+src += Glob('ES32F065x_ALD_StdPeriph_Driver/Source/*.c')
+
+
+#add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+     src = src + ['CMSIS/Device/EastSoft/ES32F065x/Startup/gcc/startup_es32f065x.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+     src = src + ['CMSIS/Device/EastSoft/ES32F065x/Startup/keil/startup_es32f065x.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['CMSIS/Device/EastSoft/ES32F065x/Startup/iar/startup_es32f065x.s']
+
+path = [cwd + '/CMSIS/Device/EastSoft/ES32F065x/Include', 
+    cwd + '/CMSIS/Include',
+    cwd + '/ES32F065x_ALD_StdPeriph_Driver/Include']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
+
+Return('group')