mirror of
https://github.com/RT-Thread/rt-thread.git
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bsp: Separate nuvoton drivers (#10435)
* bsp: Separate nuvoton drivers * bsp: update nuvoton series project.uvprojx
This commit is contained in:
沐攸
@@ -9,7 +9,7 @@ Current supported BSP shown in below table:
|
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| NK-980IOT | ARM926EJS | [nk-980iot](nk-980iot) |
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| NuMaker-M2354 | CORTEX-M23 | [numaker-m2354](numaker-m2354) |
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| NK-RTU980 | ARM926EJS | [nk-rtu980](nk-rtu980) |
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| NK-N9H30 | CORTEX-M4 | [nk-n9h30](nk-n9h30) |
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| NK-N9H30 | ARM926EJS | [nk-n9h30](nk-n9h30) |
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| NuMaker-M032KI | CORTEX-M0 | [numaker-m032ki](numaker-m032ki) |
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| NuMaker-M467HJ | CORTEX-M4 | [numaker-m467hj](numaker-m467hj) |
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| NuMaker-IoT-M467 | CORTEX-M4 | [numaker-iot-m467](numaker-iot-m467) |
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@@ -1,136 +0,0 @@
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
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||||
* $Date: 19. October 2015
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* $Revision: V.1.4.5 a
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*
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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*
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* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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||||
* -------------------------------------------------------------------- */
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#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern const uint16_t armBitRevTable[1024];
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extern const q15_t armRecipTableQ15[64];
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extern const q31_t armRecipTableQ31[64];
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/* extern const q31_t realCoefAQ31[1024]; */
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/* extern const q31_t realCoefBQ31[1024]; */
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extern const float32_t twiddleCoef_16[32];
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extern const float32_t twiddleCoef_32[64];
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extern const float32_t twiddleCoef_64[128];
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extern const float32_t twiddleCoef_128[256];
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extern const float32_t twiddleCoef_256[512];
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extern const float32_t twiddleCoef_512[1024];
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extern const float32_t twiddleCoef_1024[2048];
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extern const float32_t twiddleCoef_2048[4096];
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extern const float32_t twiddleCoef_4096[8192];
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#define twiddleCoef twiddleCoef_4096
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extern const q31_t twiddleCoef_16_q31[24];
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extern const q31_t twiddleCoef_32_q31[48];
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extern const q31_t twiddleCoef_64_q31[96];
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extern const q31_t twiddleCoef_128_q31[192];
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extern const q31_t twiddleCoef_256_q31[384];
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extern const q31_t twiddleCoef_512_q31[768];
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extern const q31_t twiddleCoef_1024_q31[1536];
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extern const q31_t twiddleCoef_2048_q31[3072];
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extern const q31_t twiddleCoef_4096_q31[6144];
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extern const q15_t twiddleCoef_16_q15[24];
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extern const q15_t twiddleCoef_32_q15[48];
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extern const q15_t twiddleCoef_64_q15[96];
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extern const q15_t twiddleCoef_128_q15[192];
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extern const q15_t twiddleCoef_256_q15[384];
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extern const q15_t twiddleCoef_512_q15[768];
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extern const q15_t twiddleCoef_1024_q15[1536];
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extern const q15_t twiddleCoef_2048_q15[3072];
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extern const q15_t twiddleCoef_4096_q15[6144];
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extern const float32_t twiddleCoef_rfft_32[32];
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extern const float32_t twiddleCoef_rfft_64[64];
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extern const float32_t twiddleCoef_rfft_128[128];
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extern const float32_t twiddleCoef_rfft_256[256];
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extern const float32_t twiddleCoef_rfft_512[512];
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extern const float32_t twiddleCoef_rfft_1024[1024];
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extern const float32_t twiddleCoef_rfft_2048[2048];
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extern const float32_t twiddleCoef_rfft_4096[4096];
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/* floating-point bit reversal tables */
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#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
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#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
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#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
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#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
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#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
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#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
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#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
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#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
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/* fixed-point bit reversal tables */
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#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
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#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
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#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
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#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
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#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
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#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
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#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
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#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
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/* Tables for Fast Math Sine and Cosine */
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extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
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extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
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extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
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#endif /* ARM_COMMON_TABLES_H */
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@@ -1,79 +0,0 @@
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/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. March 2015
|
||||
* $Revision: V.1.4.5
|
||||
*
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||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
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||||
*
|
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* Description: This file has constant structs that are initialized for
|
||||
* user convenience. For example, some can be given as
|
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* arguments to the arm_cfft_f32() function.
|
||||
*
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||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
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#ifndef _ARM_CONST_STRUCTS_H
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#define _ARM_CONST_STRUCTS_H
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#include "arm_math.h"
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#include "arm_common_tables.h"
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
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extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
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extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
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extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
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@@ -1,87 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
@@ -1,87 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
@@ -1,96 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,16 +0,0 @@
|
||||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
""")
|
||||
|
||||
path = [cwd + '/Include',]
|
||||
|
||||
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,17 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file NuMicro.h
|
||||
* @version V1.00
|
||||
* @brief NuMicro peripheral access layer header file.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NUMICRO_H__
|
||||
#define __NUMICRO_H__
|
||||
|
||||
#include "nutool_clkcfg.h"
|
||||
#include "M031Series.h"
|
||||
|
||||
#endif /* __NUMICRO_H__ */
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,151 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file crc_reg.h
|
||||
* @version V1.00
|
||||
* @brief CRC register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CRC_REG_H__
|
||||
#define __CRC_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup CRC Cyclic Redundancy Check Controller(CRC)
|
||||
Memory Mapped Structure for CRC Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var CRC_T::CTL
|
||||
* Offset: 0x00 CRC Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |CRCEN |CRC Channel Enable Bit
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = CRC operation Enabled.
|
||||
* |[1] |CHKSINIT |Checksum Initialization
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value.
|
||||
* | | |Note: This bit will be cleared automatically.
|
||||
* |[24] |DATREV |Write Data Bit Order Reverse
|
||||
* | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.
|
||||
* | | |0 = Bit order reversed for CRC write data in Disabled.
|
||||
* | | |1 = Bit order reversed for CRC write data in Enabled (per byte).
|
||||
* | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
|
||||
* |[25] |CHKSREV |Checksum Bit Order Reverse
|
||||
* | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.
|
||||
* | | |0 = Bit order reverse for CRC checksum Disabled.
|
||||
* | | |1 = Bit order reverse for CRC checksum Enabled.
|
||||
* | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
|
||||
* |[26] |DATFMT |Write Data 1's Complement
|
||||
* | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
|
||||
* | | |0 = 1's complement for CRC writes data in Disabled.
|
||||
* | | |1 = 1's complement for CRC writes data in Enabled.
|
||||
* |[27] |CHKSFMT |Checksum 1's Complement
|
||||
* | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
|
||||
* | | |0 = 1's complement for CRC checksum Disabled.
|
||||
* | | |1 = 1's complement for CRC checksum Enabled.
|
||||
* |[29:28] |DATLEN |CPU Write Data Length
|
||||
* | | |This field indicates the write data length.
|
||||
* | | |00 = Data length is 8-bit mode.
|
||||
* | | |01 = Data length is 16-bit mode.
|
||||
* | | |1x = Data length is 32-bit mode.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
|
||||
* |[31:30] |CRCMODE |CRC Polynomial Mode
|
||||
* | | |This field indicates the CRC operation polynomial mode.
|
||||
* | | |00 = CRC-CCITT Polynomial mode.
|
||||
* | | |01 = CRC-8 Polynomial mode.
|
||||
* | | |10 = CRC-16 Polynomial mode.
|
||||
* | | |11 = CRC-32 Polynomial mode.
|
||||
* @var CRC_T::DAT
|
||||
* Offset: 0x04 CRC Write Data Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DATA |CRC Write Data Bits
|
||||
* | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
|
||||
* | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
|
||||
* @var CRC_T::SEED
|
||||
* Offset: 0x08 CRC Seed Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |SEED |CRC Seed Value
|
||||
* | | |This field indicates the CRC seed value.
|
||||
* | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]).
|
||||
* @var CRC_T::CHECKSUM
|
||||
* Offset: 0x0C CRC Checksum Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |CHECKSUM |CRC Checksum Results
|
||||
* | | |This field indicates the CRC checksum result.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] CRC Control Register */
|
||||
__IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */
|
||||
__IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */
|
||||
__I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */
|
||||
|
||||
} CRC_T;
|
||||
|
||||
/**
|
||||
@addtogroup CRC_CONST CRC Bit Field Definition
|
||||
Constant Definitions for CRC Controller
|
||||
@{ */
|
||||
|
||||
|
||||
#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */
|
||||
#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */
|
||||
|
||||
#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */
|
||||
#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */
|
||||
|
||||
#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */
|
||||
#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */
|
||||
|
||||
#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */
|
||||
#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */
|
||||
|
||||
#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */
|
||||
#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */
|
||||
|
||||
#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */
|
||||
#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */
|
||||
|
||||
#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */
|
||||
#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */
|
||||
|
||||
#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */
|
||||
#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */
|
||||
|
||||
#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */
|
||||
#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */
|
||||
|
||||
#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */
|
||||
#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */
|
||||
|
||||
#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */
|
||||
#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */
|
||||
|
||||
/**@}*/ /* CRC_CONST */
|
||||
/**@}*/ /* end of CRC register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __CRC_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,130 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file hdiv_reg.h
|
||||
* @version V1.00
|
||||
* @brief HDIV register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __HDIV_REG_H__
|
||||
#define __HDIV_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup HDIV Hardware Divider (HDIV)
|
||||
Memory Mapped Structure for HDIV Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* DIVIDEND
|
||||
* ===================================================================================================
|
||||
* Offset: 0x00 Dividend Source Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |DIVIDEND |Dividend Source
|
||||
* | | |This register is given the dividend of divider before calculation starting.
|
||||
*/
|
||||
__IO uint32_t DIVIDEND;
|
||||
|
||||
/**
|
||||
* DIVISOR
|
||||
* ===================================================================================================
|
||||
* Offset: 0x04 Divisor Source Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[15:0] |DIVISOR |Divisor Source
|
||||
* | | |This register is given the divisor of divider before calculation starts.
|
||||
* | | |Note: When this register is written, hardware divider will start calculate.
|
||||
*/
|
||||
__IO uint32_t DIVISOR;
|
||||
|
||||
/**
|
||||
* QUOTIENT
|
||||
* ===================================================================================================
|
||||
* Offset: 0x08 Quotient Result Resister
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |QUOTIENT |Quotient Result
|
||||
* | | |This register holds the quotient result of divider after calculation complete.
|
||||
*/
|
||||
__IO uint32_t QUOTIENT;
|
||||
|
||||
/**
|
||||
* REM
|
||||
* ===================================================================================================
|
||||
* Offset: 0x0C Remainder Result Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |REM |Remainder Result
|
||||
* | | |The remainder of hardware divider is 16-bit sign integer (REM[15:0]) with sign extension
|
||||
* | | |(REM[31:16]) to 32-bit integer.
|
||||
*/
|
||||
__IO uint32_t REM;
|
||||
|
||||
/**
|
||||
* STATUS
|
||||
* ===================================================================================================
|
||||
* Offset: 0x10 Divider Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |DIVBYZERO |Divisor Zero Warning
|
||||
* | | |0 = The divisor is not 0.
|
||||
* | | |1 = The divisor is 0.
|
||||
* | | |Note: The DIVBYZERO flag is used to indicate divide-by-zero situation and updated whenever
|
||||
* | | |HDIV_DIVISOR is written.
|
||||
* | | |This register is read only.
|
||||
*/
|
||||
__I uint32_t STATUS;
|
||||
|
||||
} HDIV_T;
|
||||
|
||||
/**
|
||||
@addtogroup HDIV_CONST HDIV Bit Field Definition
|
||||
Constant Definitions for HDIV Controller
|
||||
@{ */
|
||||
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */
|
||||
#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */
|
||||
|
||||
#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */
|
||||
#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */
|
||||
|
||||
#define HDIV_QUOTIENT_QUOTIENT_Pos (0) /*!< HDIV_T::QUOTIENT: QUOTIENT Position */
|
||||
#define HDIV_QUOTIENT_QUOTIENT_Msk (0xfffffffful << HDIV_QUOTIENT_QUOTIENT_Pos) /*!< HDIV_T::QUOTIENT: QUOTIENT Mask */
|
||||
|
||||
#define HDIV_REM_REM_Pos (0) /*!< HDIV_T::REM: REM Position */
|
||||
#define HDIV_REM_REM_Msk (0xfffffffful << HDIV_REM_REM_Pos) /*!< HDIV_T::REM: REM Mask */
|
||||
|
||||
#define HDIV_STATUS_DIVBYZERO_Pos (1) /*!< HDIV_T::STATUS: DIVBYZERO Position */
|
||||
#define HDIV_STATUS_DIVBYZERO_Msk (0x1ul << HDIV_STATUS_DIVBYZERO_Pos) /*!< HDIV_T::STATUS: DIVBYZERO Mask */
|
||||
|
||||
/**@}*/ /* HDIV_CONST */
|
||||
/**@}*/ /* end of HDIV register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __HDIV_REG_H__ */
|
||||
|
||||
|
||||
/**@}*/ /* HDIV_CONST */
|
||||
/**@}*/ /* end of HDIV register group */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,105 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_M031Series.h
|
||||
* @version V3.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/05/29 5:31p $
|
||||
* @brief M031 Series System Setting Header File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __SYSTEM_M031_H__
|
||||
#define __SYSTEM_M031_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Macro Definition */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#ifndef DEBUG_PORT
|
||||
#define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
|
||||
#endif
|
||||
|
||||
/**
|
||||
*
|
||||
* @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
|
||||
* default clock source (External crystal or internal 22.1184MHz IRC).
|
||||
* Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to
|
||||
* user configuration setting in CONFIG0
|
||||
*
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define SYSCLK
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifndef __HXT
|
||||
#define __HXT (32000000UL) /*!< External Crystal Clock Frequency */
|
||||
#endif /*!defined(__HXT) */
|
||||
|
||||
#ifndef __LXT
|
||||
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
|
||||
#endif /*!defined(__LXT) */
|
||||
|
||||
#define __LIRC (38400UL) /*!< Internal 38.4KHz RC Oscillator Frequency */
|
||||
#define __HIRC (48000000UL) /*!< Internal 48M RC Oscillator Frequency */
|
||||
#define __HSI (96000000UL) /*!< PLL default output is 96MHz from HIRC */
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
|
||||
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
|
||||
|
||||
#if USE_ASSERT
|
||||
/**
|
||||
* @brief Assert Function
|
||||
*
|
||||
* @param[in] expr Expression to be evaluated
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details If the expression is false, an error message will be printed out
|
||||
* from debug port (UART0 or UART1).
|
||||
*/
|
||||
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
|
||||
|
||||
void AssertError(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define ASSERT_PARAM(expr)
|
||||
#endif
|
||||
|
||||
#define assert_param(expr) ASSERT_PARAM(expr)
|
||||
|
||||
|
||||
/**
|
||||
* @brief System Initialization
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The necessary initialization of system.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update the Variable SystemCoreClock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to update the variable SystemCoreClock
|
||||
* and must be called whenever the core clock is changed.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved. */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,174 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file wdt_reg.h
|
||||
* @version V1.00
|
||||
* @brief WDT register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WDT_REG_H__
|
||||
#define __WDT_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup WDT Watch Dog Timer Controller(WDT)
|
||||
Memory Mapped Structure for WDT Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @var WDT_T::CTL
|
||||
* Offset: 0x00 WDT Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect)
|
||||
* | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
|
||||
* | | |0 = WDT time-out reset function Disabled.
|
||||
* | | |1 = WDT time-out reset function Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[2] |RSTF |WDT Time-out Reset Flag
|
||||
* | | |This bit indicates the system has been reset by WDT time-out reset or not.
|
||||
* | | |0 = WDT time-out reset did not occur.
|
||||
* | | |1 = WDT time-out reset occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[3] |IF |WDT Time-out Interrupt Flag
|
||||
* | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.
|
||||
* | | |0 = WDT time-out interrupt did not occur.
|
||||
* | | |1 = WDT time-out interrupt occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect)
|
||||
* | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
|
||||
* | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
|
||||
* | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT.
|
||||
* |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect)
|
||||
* | | |This bit indicates the interrupt wake-up flag status of WDT.
|
||||
* | | |0 = WDT does not cause chip wake-up.
|
||||
* | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: This bit is cleared by writing 1 to it.
|
||||
* |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect)
|
||||
* | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
|
||||
* | | |0 = WDT time-out interrupt Disabled.
|
||||
* | | |1 = WDT time-out interrupt Enabled.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[7] |WDTEN |WDT Enable Bit (Write Protect)
|
||||
* | | |0 = WDT Disabled (This action will reset the internal up counter value).
|
||||
* | | |1 = WDT Enabled.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0.
|
||||
* |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect)
|
||||
* | | |These four bits select the time-out interval period for the WDT.
|
||||
* | | |0000 = 24 * WDT_CLK.
|
||||
* | | |0001 = 26 * WDT_CLK.
|
||||
* | | |0010 = 28 * WDT_CLK.
|
||||
* | | |0011 = 210 * WDT_CLK.
|
||||
* | | |0100 = 212 * WDT_CLK.
|
||||
* | | |0101 = 214 * WDT_CLK.
|
||||
* | | |0110 = 216 * WDT_CLK.
|
||||
* | | |0111 = 218 * WDT_CLK.
|
||||
* | | |1000 = 220 * WDT_CLK.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only)
|
||||
* | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not.
|
||||
* | | |0 = Set WDTEN bit is completed.
|
||||
* | | |1 = Set WDTEN bit is synchronizing and not become active yet.
|
||||
* | | |Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
|
||||
* | | |0 = ICE debug mode acknowledgement affects WDT counting.
|
||||
* | | |WDT up counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |WDT up counter will keep going no matter CPU is held by ICE or not.
|
||||
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* @var WDT_T::ALTCTL
|
||||
* Offset: 0x04 WDT Alternative Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect).
|
||||
* | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.
|
||||
* | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
|
||||
* | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
|
||||
* | | |01 = WDT Reset Delay Period is 130 * WDT_CLK.
|
||||
* | | |10 = WDT Reset Delay Period is 18 * WDT_CLK.
|
||||
* | | |11 = WDT Reset Delay Period is 3 * WDT_CLK.
|
||||
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
|
||||
* | | |Note2: This register will be reset to 0 if WDT time-out reset happened.
|
||||
* @var WDT_T::RSTCNT
|
||||
* Offset: 0x08 WDT Reset Counter Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RSTCNT |WDT Reset Counter Register
|
||||
* | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.
|
||||
* | | |Note1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
|
||||
*/
|
||||
__IO uint32_t CTL; /*!< [0x0000] WDT Control Register */
|
||||
__IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */
|
||||
__O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */
|
||||
|
||||
} WDT_T;
|
||||
|
||||
/**
|
||||
@addtogroup WDT_CONST WDT Bit Field Definition
|
||||
Constant Definitions for WDT Controller
|
||||
@{ */
|
||||
|
||||
#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */
|
||||
#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */
|
||||
|
||||
#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */
|
||||
#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */
|
||||
|
||||
#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */
|
||||
#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */
|
||||
|
||||
#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */
|
||||
#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */
|
||||
|
||||
#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */
|
||||
#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */
|
||||
|
||||
#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */
|
||||
#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */
|
||||
|
||||
#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */
|
||||
#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */
|
||||
|
||||
#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */
|
||||
#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */
|
||||
|
||||
#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */
|
||||
#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */
|
||||
|
||||
#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */
|
||||
#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */
|
||||
#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */
|
||||
|
||||
#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */
|
||||
#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */
|
||||
|
||||
/**@}*/ /* WDT_CONST */
|
||||
/**@}*/ /* end of WDT register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __WDT_REG_H__ */
|
||||
|
||||
@@ -1,148 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file wwdt_reg.h
|
||||
* @version V1.00
|
||||
* @brief WWDT register definition header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WWDT_REG_H__
|
||||
#define __WWDT_REG_H__
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/**
|
||||
@addtogroup REGISTER Control Register
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup WWDT Window Watchdog Timer(WWDT)
|
||||
Memory Mapped Structure for WWDT Controller
|
||||
@{ */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
|
||||
/**
|
||||
* @var WWDT_T::RLDCNT
|
||||
* Offset: 0x00 WWDT Reload Counter Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[31:0] |RLDCNT |WWDT Reload Counter Register
|
||||
* | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
|
||||
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
|
||||
* | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately.
|
||||
* @var WWDT_T::CTL
|
||||
* Offset: 0x04 WWDT Control Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WWDTEN |WWDT Enable Bit
|
||||
* | | |0 = WWDT counter is stopped.
|
||||
* | | |1 = WWDT counter starts counting.
|
||||
* |[1] |INTEN |WWDT Interrupt Enable Bit
|
||||
* | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
|
||||
* | | |0 = WWDT counter compare match interrupt Disabled.
|
||||
* | | |1 = WWDT counter compare match interrupt Enabled.
|
||||
* |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection
|
||||
* | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
|
||||
* | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
|
||||
* | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
|
||||
* | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
|
||||
* | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
|
||||
* | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
|
||||
* | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
|
||||
* | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
|
||||
* | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
|
||||
* | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
|
||||
* | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
|
||||
* | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
|
||||
* | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
|
||||
* | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
|
||||
* | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
|
||||
* | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
|
||||
* |[21:16] |CMPDAT |WWDT Window Compare Register
|
||||
* | | |Set this register to adjust the valid reload window.
|
||||
* | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
|
||||
* | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
|
||||
* |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit
|
||||
* | | |0 = ICE debug mode acknowledgement effects WWDT counting.
|
||||
* | | |WWDT down counter will be held while CPU is held by ICE.
|
||||
* | | |1 = ICE debug mode acknowledgement Disabled.
|
||||
* | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not.
|
||||
* @var WWDT_T::STATUS
|
||||
* Offset: 0x08 WWDT Status Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
|
||||
* | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
|
||||
* | | |0 = No effect.
|
||||
* | | |1 = WWDT counter value matches CMPDAT.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* |[1] |WWDTRF |WWDT Timer-out Reset Flag
|
||||
* | | |This bit indicates the system has been reset by WWDT time-out reset or not.
|
||||
* | | |0 = WWDT time-out reset did not occur.
|
||||
* | | |1 = WWDT time-out reset occurred.
|
||||
* | | |Note: This bit is cleared by writing 1 to it.
|
||||
* @var WWDT_T::CNT
|
||||
* Offset: 0x0C WWDT Counter Value Register
|
||||
* ---------------------------------------------------------------------------------------------------
|
||||
* |Bits |Field |Descriptions
|
||||
* | :----: | :----: | :---- |
|
||||
* |[5:0] |CNTDAT |WWDT Counter Value
|
||||
* | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
|
||||
*/
|
||||
__O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */
|
||||
__IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */
|
||||
__IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */
|
||||
__I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */
|
||||
|
||||
} WWDT_T;
|
||||
|
||||
/**
|
||||
@addtogroup WWDT_CONST WWDT Bit Field Definition
|
||||
Constant Definitions for WWDT Controller
|
||||
@{ */
|
||||
|
||||
#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */
|
||||
#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */
|
||||
|
||||
#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */
|
||||
#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */
|
||||
|
||||
#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */
|
||||
#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */
|
||||
|
||||
#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */
|
||||
#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */
|
||||
|
||||
#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */
|
||||
#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */
|
||||
|
||||
#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */
|
||||
#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */
|
||||
|
||||
#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */
|
||||
#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */
|
||||
|
||||
#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */
|
||||
#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */
|
||||
|
||||
#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */
|
||||
#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */
|
||||
|
||||
/**@}*/ /* WWDT_CONST */
|
||||
/**@}*/ /* end of WWDT register group */
|
||||
/**@}*/ /* end of REGISTER group */
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
#endif /* __WWDT_REG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,130 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file system_M031Series.c
|
||||
* @version V2.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/07/19 1:44p $
|
||||
* @brief M031 Series System Setting Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
|
||||
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
|
||||
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||
const uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, __HSI, __LIRC, __HIRC, 0UL, 0UL, __HIRC};
|
||||
|
||||
|
||||
/**
|
||||
* @brief Update the Variable SystemCoreClock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to update the variable SystemCoreClock
|
||||
* and must be called whenever the core clock is changed.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t u32Freq, u32ClkSrc;
|
||||
uint32_t u32HclkDiv;
|
||||
|
||||
u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
|
||||
/* Update PLL Clock */
|
||||
PllClock = CLK_GetPLLClockFreq();
|
||||
|
||||
if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL)
|
||||
{
|
||||
/* Use the clock sources directly */
|
||||
u32Freq = gau32ClkSrcTbl[u32ClkSrc];
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Use PLL clock */
|
||||
u32Freq = PllClock;
|
||||
}
|
||||
|
||||
u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClock = u32Freq / u32HclkDiv;
|
||||
|
||||
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief System Initialization
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The necessary initialization of system. Global variables are forbidden here.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Unlock protected registers */
|
||||
SYS_UnlockReg();
|
||||
|
||||
/* Set HXTGain Level dependend on HXT Frequency */
|
||||
CLK->PWRCTL = CLK->PWRCTL & ~CLK_PWRCTL_HXTGAIN_Msk;
|
||||
if ((__HXT >= FREQ_4MHZ) && (__HXT < FREQ_8MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (1 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_8MHZ) && (__HXT < FREQ_12MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (2 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_12MHZ) && (__HXT < FREQ_16MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (3 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else if ((__HXT >= FREQ_16MHZ) && (__HXT < FREQ_24MHZ))
|
||||
{
|
||||
CLK->PWRCTL |= (4 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLK->PWRCTL |= (7 << CLK_PWRCTL_HXTGAIN_Pos);
|
||||
}
|
||||
|
||||
/* Lock protected registers */
|
||||
SYS_LockReg();
|
||||
}
|
||||
|
||||
#if USE_ASSERT
|
||||
|
||||
/**
|
||||
* @brief Assert Error Message
|
||||
*
|
||||
* @param[in] file the source file name
|
||||
* @param[in] line line number
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details The function prints the source file name and line number where
|
||||
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
|
||||
*/
|
||||
void AssertError(uint8_t * file, uint32_t line)
|
||||
{
|
||||
|
||||
printf("[%s] line %d : wrong parameters.\r\n", file, line);
|
||||
|
||||
/* Infinite loop */
|
||||
while(1) ;
|
||||
}
|
||||
#endif
|
||||
@@ -1,25 +0,0 @@
|
||||
import rtconfig
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
src = Split("""
|
||||
Nuvoton/M031/Source/system_M031Series.c
|
||||
""")
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
src = src + ['Nuvoton/M031/Source/GCC/startup_M031Series.S']
|
||||
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
src = src + ['Nuvoton/M031/Source/ARM/startup_M031Series.s']
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src = src + ['Nuvoton/M031/Source/IAR/startup_M031Series.s']
|
||||
|
||||
path = [cwd + '/Nuvoton/M031/Include',]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
|
||||
|
||||
Return('group')
|
||||
@@ -1,28 +0,0 @@
|
||||
# RT-Thread building script for component
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
libs = []
|
||||
src = Glob('*src/*.c') + Glob('src/*.cpp')
|
||||
cpppath = [cwd + '/inc']
|
||||
libpath = [cwd + '/lib']
|
||||
|
||||
if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
|
||||
if rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'):
|
||||
libs += ['libstddriver_keil']
|
||||
elif GetOption('target') == 'mdk4' and os.path.isfile('./lib/libstddriver_keil4.lib'):
|
||||
libs += ['libstddriver_keil4']
|
||||
elif rtconfig.PLATFORM in ['gcc'] and os.path.isfile('./lib/libstddriver_gcc.a'):
|
||||
libs += ['libstddriver_gcc']
|
||||
elif os.path.isfile('./lib/libstddriver_iar.a'):
|
||||
libs += ['libstddriver_iar']
|
||||
|
||||
if not libs:
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
|
||||
else:
|
||||
src = []
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,117 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file nu_crc.h
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 18/07/09 4:18p $
|
||||
* @brief M031 series CRC driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __NU_CRC_H__
|
||||
#define __NU_CRC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Driver CRC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CRC Polynomial Mode Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CCITT \hideinitializer */
|
||||
#define CRC_8 (1UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC8 \hideinitializer */
|
||||
#define CRC_16 (2UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC16 \hideinitializer */
|
||||
#define CRC_32 (3UL << CRC_CTL_CRCMODE_Pos) /*!<CRC Polynomial Mode - CRC32 \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Checksum, Write data Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_CHECKSUM_COM (CRC_CTL_CHKSFMT_Msk) /*!<CRC Checksum Complement \hideinitializer */
|
||||
#define CRC_CHECKSUM_RVS (CRC_CTL_CHKSREV_Msk) /*!<CRC Checksum Reverse \hideinitializer */
|
||||
#define CRC_WDATA_COM (CRC_CTL_DATFMT_Msk) /*!<CRC Write Data Complement \hideinitializer */
|
||||
#define CRC_WDATA_RVS (CRC_CTL_DATREV_Msk) /*!<CRC Write Data Reverse \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Write Data Length Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CRC_WDATA_8 (0UL << CRC_CTL_DATLEN_Pos) /*!<CRC Write Data length is 8-bit \hideinitializer */
|
||||
#define CRC_WDATA_16 (1UL << CRC_CTL_DATLEN_Pos) /*!<CRC Write Data length is 16-bit \hideinitializer */
|
||||
#define CRC_WDATA_32 (2UL << CRC_CTL_DATLEN_Pos) /*!<CRC Write Data length is 32-bit \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC Seed Value
|
||||
*
|
||||
* @param[in] u32Seed Seed value
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to set CRC seed value.
|
||||
*
|
||||
* @note User must to perform CRC_CHKSINIT(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
|
||||
* to CRC controller.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define CRC_SET_SEED(u32Seed) do{ CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0)
|
||||
|
||||
/**
|
||||
* @brief Get CRC Seed Value
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return CRC seed value
|
||||
*
|
||||
* @details This macro gets the current CRC seed value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define CRC_GET_SEED() (CRC->SEED)
|
||||
|
||||
/**
|
||||
* @brief CRC Write Data
|
||||
*
|
||||
* @param[in] u32Data Write data
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
|
||||
|
||||
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
|
||||
uint32_t CRC_GetChecksum(void);
|
||||
|
||||
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group CRC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,88 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file nu_hdiv.h
|
||||
* @version V1.00
|
||||
* $Revision: 1 $
|
||||
* $Date: 18/07/25 3:42p $
|
||||
* @brief M031 series Hardware Divider(HDIV) driver header file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __NU_HDIV_H__
|
||||
#define __NU_HDIV_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup HDIV_Driver HDIV Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup HDIV_EXPORTED_FUNCTIONS HDIV Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Division function to calculate (x/y)
|
||||
*
|
||||
* @param[in] x the dividend of the division
|
||||
* @param[in] y the divisor of the division
|
||||
*
|
||||
* @return The result of (x/y)
|
||||
*
|
||||
* @details This is a division function to calculate x/y
|
||||
*
|
||||
*/
|
||||
static __INLINE int32_t HDIV_Div(int32_t x, int16_t y)
|
||||
{
|
||||
uint32_t *p32;
|
||||
|
||||
p32 = (uint32_t *)HDIV_BASE;
|
||||
*p32++ = x;
|
||||
*p32++ = y;
|
||||
return *p32;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief To calculate the remainder of x/y, i.e., the result of x mod y.
|
||||
*
|
||||
* @param[in] x the dividend of the division
|
||||
* @param[in] y the divisor of the division
|
||||
*
|
||||
* @return The remainder of (x/y)
|
||||
*
|
||||
* @details This function is used to calculate the remainder of x/y.
|
||||
*/
|
||||
static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y)
|
||||
{
|
||||
uint32_t *p32;
|
||||
|
||||
p32 = (uint32_t *)HDIV_BASE;
|
||||
*p32++ = x;
|
||||
*p32++ = y;
|
||||
return p32[1];
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group HDIV_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group HDIV_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_HDIV_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,155 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file nu_wwdt.h
|
||||
* @version V3.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/06/07 9:48a $
|
||||
* @brief M031 series Window Watchdog Timet(WWDT) driver header file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __NU_WWDT_H__
|
||||
#define __NU_WWDT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT_Driver WWDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* WWDT Prescale Period Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */
|
||||
#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* WWDT Reload Counter Keyword Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */
|
||||
|
||||
/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear WWDT Reset System Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to clear WWDT time-out reset system flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Clear WWDT Compared Match Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to clear WWDT compared match interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Reset System Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 WWDT time-out reset system did not occur
|
||||
* @retval 1 WWDT time-out reset system occurred
|
||||
*
|
||||
* @details This macro is used to indicate system has been reset by WWDT time-out reset or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Compared Match Interrupt Flag
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @retval 0 WWDT compare match interrupt did not occur
|
||||
* @retval 1 WWDT compare match interrupt occurred
|
||||
*
|
||||
* @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Get WWDT Counter
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return WWDT Counter Value
|
||||
*
|
||||
* @details This macro reflects the current WWDT counter value.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_COUNTER() (WWDT->CNT)
|
||||
|
||||
/**
|
||||
* @brief Reload WWDT Counter
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This macro is used to reload the WWDT counter value to 0x3F.
|
||||
* @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
|
||||
* between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
|
||||
* WWDT reset signal will generate immediately to reset system.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
|
||||
|
||||
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
|
||||
|
||||
/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group WWDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__NU_WWDT_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,10 +0,0 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\libStdDriver.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,27 +0,0 @@
|
||||
/****************************************************************************
|
||||
* @file nutool_clkcfg.h
|
||||
* @version V1.05
|
||||
* @Date 2020/09/15-18:09:27
|
||||
* @brief NuMicro generated code file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef __NUTOOL_CLKCFG_H__
|
||||
#define __NUTOOL_CLKCFG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
#undef __HXT
|
||||
#define __HXT (32000000UL) /*!< High Speed External Crystal Clock Frequency */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /*__NUTOOL_CLKCFG_H__*/
|
||||
|
||||
/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
|
||||
@@ -1,82 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file acmp.c
|
||||
* @version V3.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 18/03/16 11:13a $
|
||||
* @brief M031 Series Analog Comparator(ACMP) Driver Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup ACMP_Driver ACMP Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the specified ACMP module
|
||||
*
|
||||
* @param[in] Acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum Comparator number.
|
||||
* @param[in] u32NegSrc Comparator negative input selection. Including:
|
||||
* - \ref ACMP_CTL_NEGSEL_PIN
|
||||
* - \ref ACMP_CTL_NEGSEL_CRV
|
||||
* - \ref ACMP_CTL_NEGSEL_VBG
|
||||
* @param[in] u32HysteresisEn The hysteresis function option. Including:
|
||||
* - \ref ACMP_CTL_HYSTERESIS_ENABLE
|
||||
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Configure hysteresis function, select the source of negative input and enable analog comparator.
|
||||
*/
|
||||
void ACMP_Open(ACMP_T *Acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
|
||||
{
|
||||
Acmp->CTL[u32ChNum] = (Acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSEN_Msk))) | (u32NegSrc | u32HysteresisEn | ACMP_CTL_ACMPEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close analog comparator
|
||||
*
|
||||
* @param[in] Acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum Comparator number.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
|
||||
*/
|
||||
void ACMP_Close(ACMP_T *Acmp, uint32_t u32ChNum)
|
||||
{
|
||||
Acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group ACMP_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,99 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file crc.c
|
||||
* @version V3.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 18/04/24 3:49p $
|
||||
* @brief M031 series Cyclic Redundancy Check(CRC) driver source file
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Driver CRC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC Open
|
||||
*
|
||||
* @param[in] u32Mode CRC operation polynomial mode. Valid values are:
|
||||
* - \ref CRC_CCITT
|
||||
* - \ref CRC_8
|
||||
* - \ref CRC_16
|
||||
* - \ref CRC_32
|
||||
* @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
|
||||
* - \ref CRC_CHECKSUM_COM
|
||||
* - \ref CRC_CHECKSUM_RVS
|
||||
* - \ref CRC_WDATA_COM
|
||||
* - \ref CRC_WDATA_RVS
|
||||
* @param[in] u32Seed Seed value.
|
||||
* @param[in] u32DataLen CPU Write Data Length. Valid values are:
|
||||
* - \ref CRC_CPU_WDATA_8
|
||||
* - \ref CRC_CPU_WDATA_16
|
||||
* - \ref CRC_CPU_WDATA_32
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
|
||||
* After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
|
||||
*/
|
||||
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
|
||||
{
|
||||
CRC->SEED = u32Seed;
|
||||
CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
|
||||
|
||||
/* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
|
||||
CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CRC Checksum
|
||||
*
|
||||
* @param[in] None
|
||||
*
|
||||
* @return Checksum Result
|
||||
*
|
||||
* @details This macro gets the CRC checksum result by current CRC polynomial mode.
|
||||
*/
|
||||
uint32_t CRC_GetChecksum(void)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
|
||||
{
|
||||
case CRC_CCITT:
|
||||
case CRC_16:
|
||||
ret = (CRC->CHECKSUM & 0xFFFFU);
|
||||
break;
|
||||
case CRC_32:
|
||||
ret = (CRC->CHECKSUM);
|
||||
break;
|
||||
case CRC_8:
|
||||
ret = (CRC->CHECKSUM & 0xFFU);
|
||||
break;
|
||||
default:
|
||||
ret = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group CRC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
@@ -1,182 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file ebi.c
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 18/08/20 11:48a $
|
||||
* @brief M031 series External Bus Interface(EBI) driver source file
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "NuMicro.h"
|
||||
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup EBI_Driver EBI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize EBI for specify Bank
|
||||
*
|
||||
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||
* - \ref EBI_BANK0
|
||||
* - \ref EBI_BANK1
|
||||
* @param[in] u32DataWidth Data bus width. Valid values are:
|
||||
* - \ref EBI_BUSWIDTH_8BIT
|
||||
* - \ref EBI_BUSWIDTH_16BIT
|
||||
* @param[in] u32TimingClass Default timing configuration. Valid values are:
|
||||
* - \ref EBI_TIMING_FASTEST
|
||||
* - \ref EBI_TIMING_VERYFAST
|
||||
* - \ref EBI_TIMING_FAST
|
||||
* - \ref EBI_TIMING_NORMAL
|
||||
* - \ref EBI_TIMING_SLOW
|
||||
* - \ref EBI_TIMING_VERYSLOW
|
||||
* - \ref EBI_TIMING_SLOWEST
|
||||
* @param[in] u32BusMode Set EBI bus operate mode. Valid values are:
|
||||
* - \ref EBI_OPMODE_NORMAL
|
||||
* - \ref EBI_OPMODE_CACCESS
|
||||
* @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
|
||||
* - \ref EBI_CS_ACTIVE_HIGH
|
||||
* - \ref EBI_CS_ACTIVE_LOW
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to open specify EBI bank with different bus width, timing setting and \n
|
||||
* active level of CS pin to access EBI device.
|
||||
* @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
|
||||
*/
|
||||
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
|
||||
{
|
||||
volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10));
|
||||
volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10));
|
||||
|
||||
if(u32DataWidth == EBI_BUSWIDTH_8BIT)
|
||||
*pu32EBICTL &= ~EBI_CTL_DW16_Msk;
|
||||
else
|
||||
*pu32EBICTL |= EBI_CTL_DW16_Msk;
|
||||
|
||||
*pu32EBICTL |= u32BusMode;
|
||||
|
||||
switch (u32TimingClass)
|
||||
{
|
||||
case EBI_TIMING_FASTEST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||
*pu32EBITCTL = 0x0U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_VERYFAST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x03003318U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_FAST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||
*pu32EBITCTL = 0x0U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_NORMAL:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x03003318U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_SLOW:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x07007738U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_VERYSLOW:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x07007738U;
|
||||
break;
|
||||
|
||||
case EBI_TIMING_SLOWEST:
|
||||
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||
(EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
|
||||
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||
*pu32EBITCTL = 0x07007738U;
|
||||
break;
|
||||
|
||||
default:
|
||||
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable EBI on specify Bank
|
||||
*
|
||||
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||
* - \ref EBI_BANK0
|
||||
* - \ref EBI_BANK1
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to close specify EBI function.
|
||||
*/
|
||||
void EBI_Close(uint32_t u32Bank)
|
||||
{
|
||||
volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10U));
|
||||
|
||||
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set EBI Bus Timing for specify Bank
|
||||
*
|
||||
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||
* - \ref EBI_BANK0
|
||||
* - \ref EBI_BANK1
|
||||
* @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
|
||||
* @param[in] u32MclkDiv Divider for MCLK. Valid values are:
|
||||
* - \ref EBI_MCLKDIV_1
|
||||
* - \ref EBI_MCLKDIV_2
|
||||
* - \ref EBI_MCLKDIV_4
|
||||
* - \ref EBI_MCLKDIV_8
|
||||
* - \ref EBI_MCLKDIV_16
|
||||
* - \ref EBI_MCLKDIV_32
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to configure specify EBI bus timing for access EBI device.
|
||||
*/
|
||||
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
|
||||
{
|
||||
volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&EBI->CTL0 + (u32Bank * 0x10U));
|
||||
volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&EBI->TCTL0 + (u32Bank * 0x10U));
|
||||
|
||||
*pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
|
||||
*pu32EBITCTL = u32TimingConfig;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group EBI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,108 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file gpio.c
|
||||
* @version V3.00
|
||||
* $Revision: 2 $
|
||||
* $Date: 18/03/28 5:52p $
|
||||
* @brief M031 Series General Purpose I/O (GPIO) Driver Source File
|
||||
*
|
||||
* @note
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "M031Series.h"
|
||||
|
||||
/** @addtogroup Standard_Driver Standard Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Driver GPIO Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set GPIO operation mode
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port.
|
||||
* It could be BIT0 ~ BIT15 for PA and PB.
|
||||
* It could be BIT0 ~ BIT7, and BIT14 for PC.
|
||||
* It could be BIT0 ~ BIT3, and BIT15 for PD.
|
||||
* It could be BIT0 ~ BIT6, BIT14, and BIT15 for PF.
|
||||
* @param[in] u32Mode Operation mode. It could be
|
||||
* - \ref GPIO_MODE_INPUT
|
||||
* - \ref GPIO_MODE_OUTPUT
|
||||
* - \ref GPIO_MODE_OPEN_DRAIN
|
||||
* - \ref GPIO_MODE_QUASI
|
||||
* @return None
|
||||
* @details This function is used to set specified GPIO operation mode.
|
||||
*/
|
||||
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for(i = 0; i < GPIO_PIN_MAX; i++)
|
||||
{
|
||||
if(u32PinMask & (1 << i))
|
||||
{
|
||||
port->MODE = (port->MODE & ~(GPIO_MODE_MODE0_Msk << (i << 1))) | (u32Mode << (i << 1));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable GPIO interrupt
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* It could be 0 ~ 15 for PA and PB.
|
||||
* It could be 0 ~ 7, and 14 for PC.
|
||||
* It could be 0 ~ 3, and 15 for PD.
|
||||
* It could be 0 ~ 6, 14, and 15 for PF.
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be
|
||||
* - \ref GPIO_INT_RISING
|
||||
* - \ref GPIO_INT_FALLING
|
||||
* - \ref GPIO_INT_BOTH_EDGE
|
||||
* - \ref GPIO_INT_HIGH
|
||||
* - \ref GPIO_INT_LOW
|
||||
* @return None
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
|
||||
{
|
||||
/* Configure interrupt mode of specified pin */
|
||||
port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
|
||||
|
||||
/* Enable interrupt function of specified pin */
|
||||
port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable GPIO interrupt
|
||||
* @param[in] port GPIO port. It could be PA, PB, PC, PD, or PF.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* It could be 0 ~ 15 for PA and PB.
|
||||
* It could be 0 ~ 7, and 14 for PC.
|
||||
* It could be 0 ~ 3, and 15 for PD.
|
||||
* It could be 0 ~ 6, 14, and 15 for PF.
|
||||
* @return None
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
|
||||
{
|
||||
/* Configure interrupt mode of specified pin */
|
||||
port->INTTYPE &= ~(1UL << u32Pin);
|
||||
|
||||
/* Disable interrupt function of specified pin */
|
||||
port->INTEN &= ~((0x00010001UL) << u32Pin);
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group GPIO_Driver */
|
||||
|
||||
/*@}*/ /* end of group Standard_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user