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!86 fix some bugs and update libraries

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Merge pull request !86 from 刘泓研/gitee_master
This commit is contained in:
bernard
2020-12-19 15:12:44 +08:00
committed by Gitee
parent 1276ec12af 2398376d45
commit c1fa39a821
269 changed files with 43125 additions and 38906 deletions
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108
bsp/essemi/es32f0334/.config
View File

@@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40002
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -115,18 +115,29 @@ CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
CONFIG_RT_USING_PM=y
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@@ -192,11 +203,15 @@ CONFIG_RT_USING_PIN=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
@@ -223,6 +238,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -235,8 +251,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
@@ -251,6 +269,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
#
# security packages
@@ -258,6 +285,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
@@ -274,6 +303,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
#
# tools packages
@@ -289,6 +319,12 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
#
# system packages
@@ -299,6 +335,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -307,6 +344,15 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_PPOOL is not set
#
# peripheral libraries and drivers
@@ -323,6 +369,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@@ -336,9 +386,27 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_LCD_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
#
# miscellaneous packages
@@ -373,8 +441,14 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
#
# Hardware Drivers Config
@@ -442,4 +516,18 @@ CONFIG_BSP_USING_UART1=y
#
# Offboard Peripheral Drivers
#
#
# Peripheral Drivers test example
#
# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set
# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set
# CONFIG_BSP_USING_EXAMPLE_I2C is not set
# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set
# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set
# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set
# CONFIG_BSP_USING_EXAMPLE_RTC is not set
# CONFIG_BSP_USING_EXAMPLE_SPI is not set
# CONFIG_BSP_USING_EXAMPLE_UART is not set
# CONFIG_BSP_USING_EXAMPLE_PM is not set
CONFIG_SOC_ES32F0334LT=y

18
bsp/essemi/es32f0334/README.md
View File

@@ -86,6 +86,22 @@ msh >
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
a）如果需要使用内核用例，先配置rt-thread内核，如图：
![kernel_config](figures/k_conf.jpg)
然后配置内核用例，如图：
![kernel_samples](figures/k_ex.jpg)
b）如果需要使用驱动用例：先使能驱动，如图：
![driver_config](figures/drv_conf.jpg)
然后配置驱动用例，如图：
![driver_sample](figures/drv_ex.jpg)
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
@@ -94,7 +110,7 @@ msh >
## 4. 联系人信息
- [wangyongquan](https://github.com/wangyq2018)
- [liuhongyan](https://gitee.com/liuhongyan98)
## 5. 参考

46
bsp/essemi/es32f0334/drivers/Kconfig
View File

@@ -127,4 +127,50 @@ menu "Hardware Drivers Config"
endmenu
menu "Peripheral Drivers test example"
config BSP_USING_EXAMPLE_ADC_VOL
bool "BSP_USING_EXAMPLE_ADC_VOL"
default n
config BSP_USING_EXAMPLE_HWTIMER
bool "BSP_USING_EXAMPLE_HWTIMER"
default n
config BSP_USING_EXAMPLE_I2C
bool "BSP_USING_EXAMPLE_I2C"
default n
config BSP_USING_EXAMPLE_LED_BLINK
bool "BSP_USING_EXAMPLE_LED_BLINK"
default y
config BSP_USING_EXAMPLE_PIN_BEEP
bool "BSP_USING_EXAMPLE_PIN_BEEP"
default y
config BSP_USING_EXAMPLE_PWM_LED
bool "BSP_USING_EXAMPLE_PWM_LED"
default n
config BSP_USING_EXAMPLE_RTC
bool "BSP_USING_EXAMPLE_RTC"
default n
config BSP_USING_EXAMPLE_SPI
bool "BSP_USING_EXAMPLE_SPI"
default n
config BSP_USING_EXAMPLE_UART
bool "BSP_USING_EXAMPLE_UART"
default y
config BSP_USING_EXAMPLE_PM
bool "BSP_USING_EXAMPLE_PM"
default n
endmenu
endmenu

42
bsp/essemi/es32f0334/drivers/SConscript
View File

@@ -2,6 +2,8 @@ from building import *
cwd = GetCurrentDir()
objs = []
# add the general drivers.
src = Split('''
board.c
@@ -50,5 +52,43 @@ if GetDepend(['BSP_USING_ADC']):
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
objs = objs + group
Return('group')
src = []
cwd = GetCurrentDir()
include_path = [cwd]
if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'):
src += ['bsp_driver_example/adc_vol_sample.c']
if GetDepend('BSP_USING_EXAMPLE_HWTIMER'):
src += ['bsp_driver_example/hwtimer_sample.c']
if GetDepend('BSP_USING_EXAMPLE_I2C'):
src += ['bsp_driver_example/i2c_sample.c']
if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'):
src += ['bsp_driver_example/led_blink_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'):
src += ['bsp_driver_example/pin_beep_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PWM_LED'):
src += ['bsp_driver_example/pwm_led_sample.c']
if GetDepend('BSP_USING_EXAMPLE_RTC'):
src += ['bsp_driver_example/rtc_sample.c']
if GetDepend('BSP_USING_EXAMPLE_UART'):
src += ['bsp_driver_example/uart_sample.c']
if GetDepend('BSP_USING_EXAMPLE_SPI'):
src += ['bsp_driver_example/spi_sample.c']
if GetDepend('BSP_USING_EXAMPLE_PM'):
src += ['bsp_driver_example/pm_sample.c']
group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path)
objs = objs + group
Return('objs')

52
bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore vendored Normal file
View File

@@ -0,0 +1,52 @@
# Prerequisites
*.d
# Object files
*.o
*.ko
*.obj
*.elf
# Linker output
*.ilk
*.map
*.exp
# Precompiled Headers
*.gch
*.pch
# Libraries
*.lib
*.a
*.la
*.lo
# Shared objects (inc. Windows DLLs)
*.dll
*.so
*.so.*
*.dylib
# Executables
*.exe
*.out
*.app
*.i*86
*.x86_64
*.hex
# Debug files
*.dSYM/
*.su
*.idb
*.pdb
# Kernel Module Compile Results
*.mod*
*.cmd
.tmp_versions/
modules.order
Module.symvers
Mkfile.old
dkms.conf

47
bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md Normal file
View File

@@ -0,0 +1,47 @@
# 外设驱动测试用例
## 1、介绍
这个软件包包含一些外设设备操作的例程。
### 1.1 例程说明
| 文件 | 说明 |
| ---------------- | ------------------------------- |
| adc_vol_sample.c | 使用 ADC 设备转换电压数据 |
| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 |
| hwtimer_sample.c | 使用 硬件定时器定时 |
| i2c_sample.c | 使用 i2c 设备进行读写 |
| pm.c | 反复进入不同程度的睡眠。 |
| led_blink_sample.c | 使用 pin 设备控制 LED 闪烁 |
| pin_beep_sample.c | 使用 pin 设备控制蜂鸣器 |
| pwm_led_sample.c | 使用 pwm 设备控制 LED 的亮度 |
| rtc_sample.c | 使用 rtc 设备设置年月日时分秒信息 |
| spi_sample.c | 使用 spi 设备进行读写 |
| uart_sample.c | 使用 serial 设备中断接收及轮询发送模式收发数据 |
### 1.2 依赖
依赖设备管理模块提供的设备驱动。
## 2、如何打开 外设驱动测试用例
使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下：
```
Hardware Driver Config --->
Peripheral Driver test example--->
```
## 3、使用 外设驱动测试用例
在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。
## 4、注意事项
暂无。
## 5、联系方式 & 感谢
* 维护：[misonyo](https://github.com/misonyo)
* 主页：https://github.com/RT-Thread-packages/peripheral-sample

57
bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c Normal file
View File

@@ -0,0 +1,57 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-29 misonyo first implementation.
*/
/*
* 程序清单： ADC 设备使用例程
* 例程导出了 adc_sample 命令到控制终端
* 命令调用格式：adc_sample
* 程序功能：通过 ADC 设备采样电压值并转换为数值。
* 示例代码参考电压为3.3V,转换位数为12位。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define ADC_DEV_NAME "adc0" /* ADC 设备名称 */
#define ADC_DEV_CHANNEL 5 /* PA1 ADC 通道 */
#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/
#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */
static int adc_vol_sample(int argc, char *argv[])
{
rt_adc_device_t adc_dev;
rt_uint32_t value, vol;
rt_err_t ret = RT_EOK;
/* 查找设备 */
adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
if (adc_dev == RT_NULL)
{
rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
return RT_ERROR;
}
/* 使能设备 */
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
/* 读取采样值 */
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d \n", value);
/* 转换为对应电压值 */
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
/* 关闭通道 */
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);

144
bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c Normal file
View File

@@ -0,0 +1,144 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-06-25 misonyo first implementation.
*/
/*
* 程序清单：这是一个 CAN 设备使用例程
* 例程导出了 can_sample 命令到控制终端
* 命令调用格式：can_sample can2
* 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备
* 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。
*/
#include <rtthread.h>
#include "rtdevice.h"
#define CAN_DEV_NAME "can2" /* CAN 设备名称 */
static struct rt_semaphore rx_sem; /* 用于接收消息的信号量 */
static rt_device_t can_dev; /* CAN 设备句柄 */
/* 接收数据回调函数 */
static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size)
{
/* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
rt_sem_release(&rx_sem);
return RT_EOK;
}
static void can_rx_thread(void *parameter)
{
int i;
struct rt_can_msg rxmsg = {0};
/* 设置接收回调函数 */
rt_device_set_rx_indicate(can_dev, can_rx_call);
#ifdef RT_CAN_USING_HDR
rt_err_t res;
struct rt_can_filter_item items[5] =
{
RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */
RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */
RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */
RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL), /* std,match ID:0x486，hdr为-1 */
{0x555, 0, 0, 0, 0x7ff, 7,} /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */
};
struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */
/* 设置硬件过滤表 */
res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg);
RT_ASSERT(res == RT_EOK);
#endif
while (1)
{
/* hdr值为-1，表示直接从uselist链表读取数据 */
rxmsg.hdr = -1;
/* 阻塞等待接收信号量 */
rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
/* 从CAN读取一帧数据 */
rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg));
/* 打印数据ID及内容 */
rt_kprintf("ID:%x ", rxmsg.id);
for (i = 0; i < 8; i++)
{
rt_kprintf("%2x ", rxmsg.data[i]);
}
rt_kprintf("\n");
}
}
int can_sample(int argc, char *argv[])
{
struct rt_can_msg msg = {0};
rt_err_t res;
rt_size_t size;
rt_thread_t thread;
char can_name[RT_NAME_MAX];
if (argc == 2)
{
rt_strncpy(can_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX);
}
can_dev = rt_device_find(can_name);
if (!can_dev)
{
rt_kprintf("find %s failed!\n", can_name);
return RT_ERROR;
}
/* 初始化CAN接收信号量 */
rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
/* 以中断接收及发送方式打开CAN设备 */
res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
RT_ASSERT(res == RT_EOK);
thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10);
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
rt_kprintf("create can_rx thread failed!\n");
}
msg.id = 0x78; /* ID为0x78 */
msg.ide = RT_CAN_STDID; /* 标准格式 */
msg.rtr = RT_CAN_DTR; /* 数据帧 */
msg.len = 8; /* 数据长度为8 */
/* 待发送的8字节数据 */
msg.data[0] = 0x00;
msg.data[1] = 0x11;
msg.data[2] = 0x22;
msg.data[3] = 0x33;
msg.data[4] = 0x44;
msg.data[5] = 0x55;
msg.data[6] = 0x66;
msg.data[7] = 0x77;
/* 发送一帧CAN数据 */
size = rt_device_write(can_dev, 0, &msg, sizeof(msg));
if (size == 0)
{
rt_kprintf("can dev write data failed!\n");
}
return res;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(can_sample, can device sample);

85
bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-30 misonyo first implementation.
*/
/*
* 程序清单：这是一个 hwtimer 设备使用例程
* 例程导出了 hwtimer_sample 命令到控制终端
* 命令调用格式：hwtimer_sample
* 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define HWTIMER_DEV_NAME "timer0" /* 定时器名称 */
/* 定时器超时回调函数 */
static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
{
rt_kprintf("tick is :%d !\n", rt_tick_get());
return 0;
}
static int hwtimer_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
rt_hwtimerval_t timeout_s; /* 定时器超时值 */
rt_device_t hw_dev = RT_NULL; /* 定时器设备句柄 */
rt_hwtimer_mode_t mode; /* 定时器模式 */
/* 查找定时器设备 */
hw_dev = rt_device_find(HWTIMER_DEV_NAME);
if (hw_dev == RT_NULL)
{
rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
return RT_ERROR;
}
/* 以读写方式打开设备 */
ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
if (ret != RT_EOK)
{
rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
return ret;
}
/* 设置超时回调函数 */
rt_device_set_rx_indicate(hw_dev, timeout_cb);
/* 设置模式为周期性定时器 */
mode = HWTIMER_MODE_PERIOD;
ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
if (ret != RT_EOK)
{
rt_kprintf("set mode failed! ret is :%d\n", ret);
return ret;
}
/* 设置定时器超时值为5s并启动定时器 */
timeout_s.sec = 5; /* 秒 */
timeout_s.usec = 0; /* 微秒 */
if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
{
rt_kprintf("set timeout value failed\n");
return RT_ERROR;
}
/* 延时3500ms */
rt_thread_mdelay(3500);
/* 读取定时器当前值 */
rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);

97
bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c Normal file
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/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-15 liuhy first implementation.
*/
/*
* 程序清单：这是一个 I2C 设备使用例程
* 例程导出了 i2c_io_sample 命令到控制终端
* 命令调用格式：i2c_io_sample
* 命令解释：使用默认的I2C总线设备
* 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define I2C_BUS_NAME "i2c1" /* I2C总线设备名称 */
#define SLAVE_ADDR 0x2D /* 从机地址 */
#define STR_LEN 16 /* 接收发送的数据长度 */
static void i2c_io_sample(int argc, char *argv[])
{
struct rt_i2c_bus_device *i2c_bus = RT_NULL; /* I2C总线设备句柄 */
struct rt_i2c_msg temp_msg; /* I2C消息 */
rt_uint8_t buffer[STR_LEN] = { 0U };
rt_uint32_t i,num_msg;
rt_size_t s_stat;
i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME); /* 通过名字获取I2C总线设备的句柄 */
if( i2c_bus == RT_NULL)
{
rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME);
return;
}
/*初始化消息*/
temp_msg.addr = SLAVE_ADDR; /* 从机地址 */
temp_msg.len = STR_LEN; /* 传输的数据长度 */
temp_msg.buf = buffer; /* 读写缓存器 */
num_msg = 1; /* 传输一条消息 */
temp_msg.flags = RT_I2C_RD; /* I2C读 */
s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输消息 */
rt_thread_mdelay(400);
if( s_stat == num_msg )
{
rt_kprintf("receive successful. \n receive messege : %s \n:",buffer);
for( i = 0 ; i < STR_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
}
else
{
rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer);
return;
}
for( i = 0 ; i < STR_LEN ; i++)
buffer[i]++;
temp_msg.flags = RT_I2C_WR; /* I2C写 */
s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg); /* 传输一条 */
rt_thread_mdelay(400);
if( s_stat == num_msg )
{
rt_kprintf(" send successful \n messege : %s \n:",buffer);
for( i = 0 ; i < STR_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
}
else
{
rt_kprintf("device s% send fail \n",I2C_BUS_NAME);
return;
}
return;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(i2c_io_sample, i2c io sample);

83
bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-09-25 misonyo first edition.
*/
/*
* 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程
* 例程导出了 led_sample 命令到控制终端
* 命令调用格式：led_sample
* 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。
* 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯
* 亮灭的效果。
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <stdlib.h>
/* PIN脚编号，查看驱动文件drv_gpio.c确定 */
#define LED_PIN_NUM 45 /*PA12*/
static int pin_num;
static void led_entry(void *parameter)
{
int count = 0;
/* 设置PIN脚模式为输出 */
rt_pin_mode(pin_num, PIN_MODE_OUTPUT);
while (1)
{
count++;
rt_kprintf("thread run count : %d\r\n", count);
/* 拉低PIN脚 */
rt_pin_write(pin_num, PIN_LOW);
rt_kprintf("led on!\r\n");
/* 延时1000ms */
rt_thread_mdelay(1000);
/* 拉高PIN脚 */
rt_pin_write(pin_num, PIN_HIGH);
rt_kprintf("led off!\r\n");
rt_thread_mdelay(1000);
}
}
static int led_sample(int argc, char *argv[])
{
rt_thread_t tid;
rt_err_t ret = RT_EOK;
/* 判断命令行参数是否给定了PIN脚编号 */
if (argc == 2)
{
pin_num = atoi(argv[1]);
}
else
{
pin_num = LED_PIN_NUM;
}
tid = rt_thread_create("led",
led_entry,
RT_NULL,
512,
RT_THREAD_PRIORITY_MAX / 3,
20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
ret = RT_ERROR;
}
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(led_sample, led sample);

67
bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-08-15 misonyo first implementation.
*/
/*
* 程序清单：这是一个 PIN 设备使用例程
* 例程导出了 pin_beep_sample 命令到控制终端
* 命令调用格式：pin_beep_sample
* 程序功能：通过按键控制蜂鸣器对应引脚的电平状态控制蜂鸣器
*/
#include <rtthread.h>
#include <rtdevice.h>
/* 引脚编号，通过查看驱动文件drv_gpio.c确定 */
#ifndef BEEP_PIN_NUM
#define BEEP_PIN_NUM 45 /* PA12 */
#endif
#ifndef KEY0_PIN_NUM
#define KEY0_PIN_NUM 18 /* PF0 */
#endif
#ifndef KEY1_PIN_NUM
#define KEY1_PIN_NUM 19 /* PF1 */
#endif
void beep_on(void *args)
{
rt_kprintf("turn on beep!\n");
rt_pin_write(BEEP_PIN_NUM, PIN_HIGH);
}
void beep_off(void *args)
{
rt_kprintf("turn off beep!\n");
rt_pin_write(BEEP_PIN_NUM, PIN_LOW);
}
static void pin_beep_sample(void)
{
/* 蜂鸣器引脚为输出模式 */
rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT);
/* 默认低电平 */
rt_pin_write(BEEP_PIN_NUM, PIN_LOW);
/* 按键0引脚为输入模式 */
rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP);
/* 绑定中断，下降沿模式，回调函数名为beep_on */
rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL);
/* 使能中断 */
rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE);
/* 按键1引脚为输入模式 */
rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP);
/* 绑定中断，下降沿模式，回调函数名为beep_off */
rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL);
/* 使能中断 */
rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE);
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(pin_beep_sample, pin beep sample);

182
bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c Normal file
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/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-15 liuhy first implementation.
*/
/*
* 程序清单：这是一个 pm睡眠唤醒的使用例程
* 例程导出了 pm_sample 命令到控制终端
* 命令调用格式：pm_sample
* 命令解释：进入不同的睡眠模式，然后用按键唤醒
* 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define PM_NAME "pm" /* 设备名称 */
#define WAKE_UP_PIN 18 /* 唤醒源 */
#define SLEEP_TIMES 12 /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */
struct pm_callback_t
{
volatile int in_fun_times; /*进入函数的次数*/
volatile char flag; /*标志*/
volatile int mode; /*需要打印的模式*/
};
volatile struct pm_callback_t g_pm_data;
/*进入睡眠前，睡眠唤醒后，都会进入。*/
/*函数打印睡眠相关的信息*/
void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data)
{
/*没有标志，不处理*/
if(!(g_pm_data.flag))
{
return;
}
/*标志不正常，清空标志*/
if((g_pm_data.flag) > 2)
{
(g_pm_data.flag) = 0;
return;
}
/*模式不匹配*/
if(g_pm_data.mode != mode )
{
return;
}
/*进入的事件*/
switch(event)
{
/*进入睡眠前*/
case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1;
rt_kprintf("\n\r##%d : ENTER ",g_pm_data.in_fun_times);
g_pm_data.in_fun_times++; /*进入睡眠次数+1*/
break;
/*睡眠唤醒后*/
case RT_PM_EXIT_SLEEP: g_pm_data.flag = 0; /*睡眠唤醒后*/
rt_kprintf("\n\rEXIT\n\r");
rt_pm_release(mode); /*释放休眠模式*/
return;
default: break;
};
/*当前的睡眠模式*/
switch(mode)
{
case PM_SLEEP_MODE_NONE: rt_kprintf("PM_SLEEP_MODE_NONE\n\r");
break;
case PM_SLEEP_MODE_IDLE: rt_kprintf("PM_SLEEP_MODE_IDLE\n\r");
break;
case PM_SLEEP_MODE_LIGHT: rt_kprintf("PM_SLEEP_MODE_LIGHT\n\r");
break;
case PM_SLEEP_MODE_DEEP: rt_kprintf("PM_SLEEP_MODE_DEEP\n\r");
break;
case PM_SLEEP_MODE_STANDBY: rt_kprintf("PM_SLEEP_MODE_STANDBY\n\r");
break;
case PM_SLEEP_MODE_SHUTDOWN: rt_kprintf("PM_SLEEP_MODE_SHUTDOWN\n\r");
break;
case PM_SLEEP_MODE_MAX: rt_kprintf("PM_SLEEP_MODE_MAX\n\r");
break;
default: break;
}
}
/* pm测试函数 */
static void pm_test(void *parameter)
{
int in_mode[7],i = 0;
g_pm_data.in_fun_times = 0;
g_pm_data.flag = 0;
in_mode[0] = PM_SLEEP_MODE_NONE;
in_mode[1] = PM_SLEEP_MODE_IDLE;
in_mode[2] = PM_SLEEP_MODE_LIGHT;
in_mode[3] = PM_SLEEP_MODE_DEEP;
in_mode[4] = PM_SLEEP_MODE_STANDBY;
in_mode[5] = PM_SLEEP_MODE_SHUTDOWN;
in_mode[6] = PM_SLEEP_MODE_MAX;
/*设置回调函数和私有数据*/
rt_pm_notify_set(sleep_in_out_callback,RT_NULL);
while(i < SLEEP_TIMES)
{
g_pm_data.mode = in_mode[i%6];
/*无休眠模式，不赋予标志*/
if(g_pm_data.mode != PM_SLEEP_MODE_NONE)
{
g_pm_data.flag = 2;
}
/*请求选择的休眠模式*/
rt_pm_request(in_mode[i%6]);
rt_thread_mdelay(500);
/*无休眠模式，不需要额外的等待*/
while(( g_pm_data.flag != 0 )&&(g_pm_data.mode != PM_SLEEP_MODE_NONE))
{
rt_thread_mdelay(500);
}
/*释放选择的休眠模式*/
rt_pm_release(in_mode[i%6]);
i++;
}
/*清除回调函数和私有数据*/
rt_pm_notify_set(RT_NULL,RT_NULL);
rt_kprintf("thread pm_test close\n\r");
}
/*按键唤醒的回调函数*/
void wake_by_pin(void *args)
{
}
static int pm_sample(int argc, char *argv[])
{
rt_thread_t thread;
/* 按键引脚为输入模式 */
rt_pin_mode(WAKE_UP_PIN, PIN_MODE_INPUT_PULLUP);
/* 绑定中断，下降沿模式，回调函数名为wake_by_pin */
rt_pin_attach_irq(WAKE_UP_PIN, PIN_IRQ_MODE_RISING, wake_by_pin, RT_NULL);
/* 使能中断 */
rt_pin_irq_enable(WAKE_UP_PIN, PIN_IRQ_ENABLE);
thread = rt_thread_create("pm_test", pm_test, RT_NULL, 1024, 25, 10);
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
rt_kprintf("create pm_test thread failed!\n\r");
}
return RT_EOK;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(pm_sample, pm sample);

72
bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-25 misonyo first implementation.
*/
/*
* 程序清单：这是一个 PWM 设备使用例程
* 例程导出了 pwm_led_sample 命令到控制终端
* 命令调用格式：pwm_led_sample
* 程序功能：通过 PWM 设备控制 LED 灯的亮度，可以看到LED不停的由暗变到亮，然后又从亮变到暗。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define LED_PIN_NUM 45 /* PA12 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */
#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */
#define PWM_DEV_CHANNEL 2 /* PA9 PWM通道 */
struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */
static int pwm_led_sample(int argc, char *argv[])
{
rt_uint32_t period, pulse, dir;
period = 500000; /* 周期为0.5ms，单位为纳秒ns */
dir = 1; /* PWM脉冲宽度值的增减方向 */
pulse = 0; /* PWM脉冲宽度值，单位为纳秒ns */
/* 查找设备 */
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
if (pwm_dev == RT_NULL)
{
rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
return RT_ERROR;
}
/* 设置PWM周期和脉冲宽度默认值 */
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
/* 使能设备 */
rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
while (1)
{
rt_thread_mdelay(50);
if (dir)
{
pulse += 5000; /* 从0值开始每次增加5000ns */
}
else
{
pulse -= 5000; /* 从最大值开始每次减少5000ns */
}
if (pulse >= period)
{
dir = 0;
}
if (0 == pulse)
{
dir = 1;
}
/* 设置PWM周期和脉冲宽度 */
rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
}
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(pwm_led_sample, pwm sample);

51
bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c Normal file
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-30 misonyo first implementation.
*/
/*
* 程序清单：这是一个 RTC 设备使用例程
* 例程导出了 rtc_sample 命令到控制终端
* 命令调用格式：rtc_sample
* 程序功能：设置RTC设备的日期和时间，延时一段时间后获取当前时间并打印显示。
*/
#include <rtthread.h>
#include <rtdevice.h>
static int rtc_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
time_t now;
/* 设置日期 */
ret = set_date(2018, 12, 3);
if (ret != RT_EOK)
{
rt_kprintf("set RTC date failed\n");
return ret;
}
/* 设置时间 */
ret = set_time(11, 15, 50);
if (ret != RT_EOK)
{
rt_kprintf("set RTC time failed\n");
return ret;
}
/* 延时3秒 */
rt_thread_mdelay(3000);
/* 获取时间 */
now = time(RT_NULL);
rt_kprintf("%s\n", ctime(&now));
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(rtc_sample, rtc sample);

152
bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c Normal file
View File

@@ -0,0 +1,152 @@
/*
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-15 liuhy first implementation.
*/
/*
* 程序清单：这是一个 SPI 设备使用例程
* 例程导出了 spi_io_sample 命令到控制终端
* 命令调用格式：spi_io_sample
* 程序功能：通过SPI设备先读取数据，然后每个字符加1后输出。
*/
#include <rtthread.h>
#include <rtdevice.h>
#define SPI_DEVICE_NAME "spi00"
#define BUF_LEN 16
static void spi_io_sample(int argc, char *argv[])
{
struct rt_spi_device * spi_dev; /* spi设备的句柄 */
struct rt_spi_configuration spi_config;
rt_uint8_t i,buffer[BUF_LEN] = { 0U };
rt_err_t s_stat;
rt_err_t result;
/* 查找 spi设备 获取spi设备句柄 */
spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME);
if (spi_dev == RT_NULL)
{
rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME);
return;
}
/* 清空配置结构体 */
rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration));
spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */
spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */
spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */
spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */
spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */
spi_config.mode |= RT_SPI_MSB; /* 高位在前 */
spi_config.data_width = 8; /* 数据长度：8 */
spi_config.max_hz = 2000000; /* 最快时钟频率 */
/* 配置SPI设备 */
s_stat = rt_spi_configure(spi_dev,&spi_config);
if(s_stat != RT_EOK)
{
rt_kprintf(" spi config fail !\n ");
return;
}
/* 获取总线 ，防止总线被多个线程同时使用 */
result = rt_spi_take_bus(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s take spi bus failed! \n", SPI_DEVICE_NAME);
return;
}
/* 选中片选 */
result = rt_spi_take(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s take spi cs failed! \n", SPI_DEVICE_NAME);
return;
}
/*接收一次数据*/
result = rt_spi_recv(spi_dev,buffer,BUF_LEN);
if(result != BUF_LEN)
{
rt_kprintf("receive fail. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
return;
}
rt_kprintf("receive successful. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
/* 将接收到的数据加1 */
for( i = 0 ; i < BUF_LEN ; i++)
buffer[i]++;
/*发送数据*/
result = rt_spi_send(spi_dev,buffer,BUF_LEN);
if(result != BUF_LEN)
{
rt_kprintf("send fail. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
return;
}
rt_kprintf("send successful. \n buffer is : %s \n:",buffer);
for( i = 0 ; i < BUF_LEN ; i++)
rt_kprintf(" %x",(unsigned int)buffer[i]);
rt_kprintf("\n");
/* 释放片选 */
result = rt_spi_release(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s release spi cs failed! \n", SPI_DEVICE_NAME);
return;
}
/* 释放总线 */
result = rt_spi_release_bus(spi_dev);
if (result != RT_EOK)
{
rt_kprintf(" %s release spi bus failed! \n", SPI_DEVICE_NAME);
return;
}
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(spi_io_sample, spi sample);

100
bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c Normal file
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@@ -0,0 +1,100 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-08-15 misonyo first implementation.
*/
/*
* 程序清单：这是一个 串口 设备使用例程
* 例程导出了 uart_sample 命令到控制终端
* 命令调用格式：uart_sample uart2
* 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备
* 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符
*/
#include <rtthread.h>
#define SAMPLE_UART_NAME "uart1" /* 串口设备名称 */
/* 用于接收消息的信号量 */
static struct rt_semaphore rx_sem;
static rt_device_t serial;
/* 接收数据回调函数 */
static rt_err_t uart_input(rt_device_t dev, rt_size_t size)
{
/* 串口接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
rt_sem_release(&rx_sem);
return RT_EOK;
}
static void serial_thread_entry(void *parameter)
{
char ch;
while (1)
{
/* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */
while (rt_device_read(serial, -1, &ch, 1) != 1)
{
/* 阻塞等待接收信号量，等到信号量后再次读取数据 */
rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
}
/* 读取到的数据通过串口错位输出 */
ch = ch + 1;
rt_device_write(serial, 0, &ch, 1);
}
}
static int uart_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
char uart_name[RT_NAME_MAX];
char str[] = "hello RT-Thread!\r\n";
if (argc == 2)
{
rt_strncpy(uart_name, argv[1], RT_NAME_MAX);
}
else
{
rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX);
}
/* 查找串口设备 */
serial = rt_device_find(uart_name);
if (!serial)
{
rt_kprintf("find %s failed!\n", uart_name);
return RT_ERROR;
}
/* 初始化信号量 */
rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
/* 以中断接收及轮询发送方式打开串口设备 */
rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
/* 设置接收回调函数 */
rt_device_set_rx_indicate(serial, uart_input);
/* 发送字符串 */
rt_device_write(serial, 0, str, (sizeof(str) - 1));
/* 创建 serial 线程 */
rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10);
/* 创建成功则启动线程 */
if (thread != RT_NULL)
{
rt_thread_startup(thread);
}
else
{
ret = RT_ERROR;
}
return ret;
}
/* 导出到 msh 命令列表中 */
MSH_CMD_EXPORT(uart_sample, uart device sample);

24
bsp/essemi/es32f0334/drivers/drv_adc.c
View File

@@ -146,9 +146,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c
RT_ASSERT(value != RT_NULL);
/* config adc channel */
nm_config.channel = es32f0_adc_get_channel(channel);
nm_config.rank = ADC_NCH_RANK_1;
nm_config.samp_time = ADC_SAMPLETIME_4;
nm_config.ch = es32f0_adc_get_channel(channel);
nm_config.idx = ADC_NCH_IDX_1;
nm_config.samp = ADC_SAMPLETIME_4;
ald_adc_normal_channel_config(_hadc, &nm_config);
ald_adc_normal_start(_hadc);
@@ -172,16 +172,16 @@ int rt_hw_adc_init(void)
/* adc function initialization */
_h_adc0.perh = ADC0;
_h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan_mode = DISABLE;
_h_adc0.init.cont_mode = DISABLE;
_h_adc0.init.disc_mode = ADC_ALL_DISABLE;
_h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
_h_adc0.init.conv_res = ADC_CONV_RES_10;
_h_adc0.init.clk_div = ADC_CKDIV_128;
_h_adc0.init.align = ADC_DATAALIGN_RIGHT;
_h_adc0.init.scan = DISABLE;
_h_adc0.init.cont = DISABLE;
_h_adc0.init.disc = ADC_ALL_DISABLE;
_h_adc0.init.disc_nr = ADC_DISC_NR_1;
_h_adc0.init.data_bit = ADC_CONV_BIT_12;
_h_adc0.init.div = ADC_CKDIV_128;
_h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
_h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
_h_adc0.init.pos_ref = ADC_POS_REF_VDD;
_h_adc0.init.n_ref = ADC_NEG_REF_VSS;
_h_adc0.init.p_ref = ADC_POS_REF_VDD;
ald_adc_init(&_h_adc0);
rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0);

3
bsp/essemi/es32f0334/drivers/drv_i2c.c
View File

@@ -7,6 +7,7 @@
* Date Author Notes
* 2019-03-19 wangyq the first version
* 2019-11-01 wangyq update libraries
* 2020-12-15 liuhy update libraries
*/
#include <rtthread.h>
@@ -29,7 +30,7 @@ static void _i2c_init(void)
/* Initialize I2C Pin */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.odos = GPIO_OPEN_DRAIN;
gpio_instruct.pupd = GPIO_PUSH_UP;
gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL;
gpio_instruct.flt = GPIO_FILTER_DISABLE;

21
bsp/essemi/es32f0334/drivers/drv_pm.c
View File

@@ -8,7 +8,7 @@
* 2019-04-08 wangyq the first version
* 2019-11-01 wangyq adapt to the new power management interface
*/
#include <rthw.h>
#include <board.h>
#include <rtdevice.h>
#include <drv_lptim.h>
@@ -24,6 +24,21 @@ static void uart_console_reconfig(void)
rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config);
}
static void delay(void)
{
long i;
rt_base_t level;
level = rt_hw_interrupt_disable();
i = 0;
do{
i++;
}
while (i < 10000);
rt_hw_interrupt_enable(level);
}
/**
* This function will put ES32F033x into sleep mode.
*
@@ -50,22 +65,26 @@ static void sleep(struct rt_pm *pm, uint8_t mode)
{
/* Enter SLEEP Mode, Main regulator is ON */
ald_pmu_stop1_enter();
delay();
}
break;
case PM_SLEEP_MODE_DEEP:
/* Enter STOP 2 mode */
ald_pmu_stop2_enter();
delay();
break;
case PM_SLEEP_MODE_STANDBY:
/* Enter STANDBY mode */
ald_pmu_stop2_enter();
delay();
break;
case PM_SLEEP_MODE_SHUTDOWN:
/* Enter SHUTDOWNN mode */
ald_pmu_stop2_enter();
delay();
break;
default:

240
bsp/essemi/es32f0334/drivers/drv_spi.c
View File

@@ -5,8 +5,9 @@
*
* Change Logs:
* Date Author Notes
* 2019-03-19 wangyq the first version
* 2019-01-24 wangyq the first version
* 2019-11-01 wangyq update libraries
* 2020-12-15 liuhy update libraries
*/
#include <rtthread.h>
@@ -146,45 +147,14 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
hspi = (spi_handle_t *)device->bus->parent.user_data;
cs = device->parent.user_data;
/* only send data */
if (message->recv_buf == RT_NULL)
if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL)
{
if (message->cs_take)
{
rt_pin_write(cs->pin, 0);
}
res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
}
/* only receive data */
if (message->send_buf == RT_NULL)
{
if (message->cs_take)
{
rt_pin_write(cs->pin, 0);
}
res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
}
/* send & receive */
else
if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
{
if (message->cs_take)
{
@@ -199,8 +169,56 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
if (res != RT_EOK)
return RT_ERROR;
}
else
{
/* only send data */
if (message->recv_buf == RT_NULL)
{
if (message->cs_take)
{
rt_pin_write(cs->pin, 0);
}
res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
}
/* only receive data */
if (message->send_buf == RT_NULL)
{
if (message->cs_take)
{
rt_pin_write(cs->pin, 0);
}
res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
}
if (res != RT_EOK)
return RT_ERROR;
}
}
}
else
{
if (message->cs_take)
{
rt_pin_write(cs->pin, 0);
}
if (message->cs_release)
{
rt_pin_write(cs->pin, 1);
}
return RT_EOK;
}
return message->length;
}
const struct rt_spi_ops es32f0_spi_ops =
@@ -209,62 +227,6 @@ const struct rt_spi_ops es32f0_spi_ops =
spixfer,
};
static struct rt_spi_bus _spi_bus0, _spi_bus1;
static spi_handle_t _spi0, _spi1;
int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
{
struct rt_spi_bus *spi_bus;
spi_handle_t *spi;
gpio_init_t gpio_instruct;
if (SPIx == SPI0)
{
_spi0.perh = SPI0;
spi_bus = &_spi_bus0;
spi = &_spi0;
/* SPI0 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB3->SPI0_SCK, PB5->SPI0_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
/* PB4->SPI0_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
}
else if (SPIx == SPI1)
{
_spi1.perh = SPI1;
spi_bus = &_spi_bus1;
spi = &_spi1;
/* SPI1 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB13->SPI1_SCK, PB15->SPI1_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
/* PB14->SPI1_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
}
else
{
return -1;
}
spi_bus->parent.user_data = spi;
return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops);
}
rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
{
@@ -279,16 +241,100 @@ rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c
return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
}
int rt_hw_spi_init(void)
{
int result = 0;
#ifdef BSP_USING_SPI0
result = es32f0_spi_register_bus(SPI0, "spi0");
static struct rt_spi_bus _spi_bus0;
static spi_handle_t _spi0;
#endif
#ifdef BSP_USING_SPI1
result = es32f0_spi_register_bus(SPI1, "spi1");
static struct rt_spi_bus _spi_bus1;
static spi_handle_t _spi1;
#endif
int rt_hw_spi_init(void)
{
int result = RT_EOK;
struct rt_spi_bus *spi_bus;
spi_handle_t *spi;
gpio_init_t gpio_instruct;
#ifdef BSP_USING_SPI0
_spi0.perh = SPI0;
spi_bus = &_spi_bus0;
spi = &_spi0;
rt_device_t spi_bus_dev0;
/* SPI0 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB3->SPI0_SCK, PB5->SPI0_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
/* PB4->SPI0_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
spi_bus->parent.user_data = spi;
result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops);
if (result != RT_EOK)
{
return result;
}
rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR);
/* SPI0_NSS = PA15 = PIN 50 */
result = es32f0_spi_device_attach(50, "spi0", "spi00");
if (result != RT_EOK)
{
return result;
}
#endif
#ifdef BSP_USING_SPI1
_spi1.perh = SPI1;
spi_bus = &_spi_bus1;
spi = &_spi1;
rt_device_t spi_bus_dev0;
/* SPI1 gpio init */
gpio_instruct.mode = GPIO_MODE_OUTPUT;
gpio_instruct.odos = GPIO_PUSH_PULL;
gpio_instruct.func = GPIO_FUNC_4;
gpio_instruct.type = GPIO_TYPE_CMOS;
gpio_instruct.flt = GPIO_FILTER_DISABLE;
/* PB13->SPI1_SCK, PB15->SPI1_MOSI */
ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
/* PB14->SPI1_MISO */
gpio_instruct.mode = GPIO_MODE_INPUT;
ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
spi_bus->parent.user_data = spi;
result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops);
if (result != RT_EOK)
{
return result;
}
rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR);
/* SPI1_NSS = PC00 = PIN 8 */
result = es32f0_spi_device_attach(8, "spi1", "spi10");
if (result != RT_EOK)
{
return result;
}
#endif
return result;

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bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h
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289
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h
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@@ -18,7 +18,7 @@
#define __ALD_ACMP_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -38,187 +38,171 @@ extern "C" {
/**
* @brief Acmp interrupt
*/
typedef enum
{
ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */
ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */
typedef enum {
ACMP_IT_EDGE = (1U << 0), /**< Edge interrupt bit */
ACMP_IT_WARMUP = (1U << 1), /**< Warm up interrupt bit */
} acmp_it_t;
/**
* @brief Acmp interrupt
*/
typedef enum
{
ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */
typedef enum {
ACMP_FLAG_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_FLAG_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_flag_t;
/**
* @brief Acmp interrupt flag
*/
typedef enum
{
ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */
typedef enum {
ACMP_STATUS_EDGE = (1U << 0), /**< Edge interrupt flag */
ACMP_STATUS_WARMUP = (1U << 1), /**< Warm up interrupt flag */
} acmp_status_t;
/**
* @brief Acmp positive input
*/
typedef enum
{
ACMP_POS_CH0 = 0, /**< Channel 0 as positive input */
ACMP_POS_CH1 = 1, /**< Channel 1 as positive input */
ACMP_POS_CH2 = 2, /**< Channel 2 as positive input */
ACMP_POS_CH3 = 3, /**< Channel 3 as positive input */
ACMP_POS_CH4 = 4, /**< Channel 4 as positive input */
ACMP_POS_CH5 = 5, /**< Channel 5 as positive input */
ACMP_POS_CH6 = 6, /**< Channel 6 as positive input */
ACMP_POS_CH7 = 7, /**< Channel 7 as positive input */
typedef enum {
ACMP_POS_CH0 = 0U, /**< Channel 0 as positive input */
ACMP_POS_CH1 = 1U, /**< Channel 1 as positive input */
ACMP_POS_CH2 = 2U, /**< Channel 2 as positive input */
ACMP_POS_CH3 = 3U, /**< Channel 3 as positive input */
ACMP_POS_CH4 = 4U, /**< Channel 4 as positive input */
ACMP_POS_CH5 = 5U, /**< Channel 5 as positive input */
ACMP_POS_CH6 = 6U, /**< Channel 6 as positive input */
ACMP_POS_CH7 = 7U, /**< Channel 7 as positive input */
} acmp_pos_input_t;
/**
* @brief Acmp negative input
*/
typedef enum
{
ACMP_NEG_CH0 = 0, /**< Channel 0 as negative input */
ACMP_NEG_CH1 = 1, /**< Channel 1 as negative input */
ACMP_NEG_CH2 = 2, /**< Channel 2 as negative input */
ACMP_NEG_CH3 = 3, /**< Channel 3 as negative input */
ACMP_NEG_CH4 = 4, /**< Channel 4 as negative input */
ACMP_NEG_CH5 = 5, /**< Channel 5 as negative input */
ACMP_NEG_CH6 = 6, /**< Channel 6 as negative input */
ACMP_NEG_CH7 = 7, /**< Channel 7 as negative input */
ACMP_NEG_1V25 = 8, /**< 1.25v as negative input */
ACMP_NEG_2V5 = 9, /**< 2.5v as negative input */
ACMP_NEG_VDD = 10, /**< VDD as negative input */
typedef enum {
ACMP_NEG_CH0 = 0U, /**< Channel 0 as negative input */
ACMP_NEG_CH1 = 1U, /**< Channel 1 as negative input */
ACMP_NEG_CH2 = 2U, /**< Channel 2 as negative input */
ACMP_NEG_CH3 = 3U, /**< Channel 3 as negative input */
ACMP_NEG_CH4 = 4U, /**< Channel 4 as negative input */
ACMP_NEG_CH5 = 5U, /**< Channel 5 as negative input */
ACMP_NEG_CH6 = 6U, /**< Channel 6 as negative input */
ACMP_NEG_CH7 = 7U, /**< Channel 7 as negative input */
ACMP_NEG_1V25 = 8U, /**< 1.25v as negative input */
ACMP_NEG_2V5 = 9U, /**< 2.5v as negative input */
ACMP_NEG_VDD = 10U, /**< VDD as negative input */
} acmp_neg_input_t;
/**
* @brief Acmp mode
*/
typedef enum
{
ACMP_ULTRA_LOW_POWER = 0, /**< Ultra low power mode */
ACMP_LOW_POWER = 1, /**< Low power mode */
ACMP_MIDDLE_POWER = 2, /**< Middle power mode */
ACMP_HIGH_POWER = 3, /**< High power mode */
typedef enum {
ACMP_ULTRA_LOW_POWER = 0U, /**< Ultra low power mode */
ACMP_LOW_POWER = 1U, /**< Low power mode */
ACMP_MIDDLE_POWER = 2U, /**< Middle power mode */
ACMP_HIGH_POWER = 3U, /**< High power mode */
} acmp_mode_t;
/**
* @brief Acmp warm-up time
*/
typedef enum
{
ACMP_4_PCLK = 0, /**< 4 hfperclk cycles */
ACMP_8_PCLK = 1, /**< 4 hfperclk cycles */
ACMP_16_PCLK = 2, /**< 4 hfperclk cycles */
ACMP_32_PCLK = 3, /**< 4 hfperclk cycles */
ACMP_64_PCLK = 4, /**< 4 hfperclk cycles */
ACMP_128_PCLK = 5, /**< 4 hfperclk cycles */
ACMP_256_PCLK = 6, /**< 4 hfperclk cycles */
ACMP_512_PCLK = 7, /**< 4 hfperclk cycles */
typedef enum {
ACMP_4_PCLK = 0U, /**< 4 hfperclk cycles */
ACMP_8_PCLK = 1U, /**< 4 hfperclk cycles */
ACMP_16_PCLK = 2U, /**< 4 hfperclk cycles */
ACMP_32_PCLK = 3U, /**< 4 hfperclk cycles */
ACMP_64_PCLK = 4U, /**< 4 hfperclk cycles */
ACMP_128_PCLK = 5U, /**< 4 hfperclk cycles */
ACMP_256_PCLK = 6U, /**< 4 hfperclk cycles */
ACMP_512_PCLK = 7U, /**< 4 hfperclk cycles */
} acmp_warm_time_t;
/**
* @brief Acmp hysteresis level
*/
typedef enum
{
ACMP_HYST_0 = 0, /**< No hysteresis */
ACMP_HYST_15 = 1, /**< 15mV hysteresis */
ACMP_HYST_22 = 2, /**< 22mV hysteresis */
ACMP_HYST_29 = 3, /**< 29mV hysteresis */
ACMP_HYST_36 = 4, /**< 36mV hysteresis */
ACMP_HYST_43 = 5, /**< 43mV hysteresis */
ACMP_HYST_50 = 6, /**< 50mV hysteresis */
ACMP_HYST_57 = 7, /**< 57mV hysteresis */
typedef enum {
ACMP_HYST_0 = 0U, /**< No hysteresis */
ACMP_HYST_15 = 1U, /**< 15mV hysteresis */
ACMP_HYST_22 = 2U, /**< 22mV hysteresis */
ACMP_HYST_29 = 3U, /**< 29mV hysteresis */
ACMP_HYST_36 = 4U, /**< 36mV hysteresis */
ACMP_HYST_43 = 5U, /**< 43mV hysteresis */
ACMP_HYST_50 = 6U, /**< 50mV hysteresis */
ACMP_HYST_57 = 7U, /**< 57mV hysteresis */
} acmp_hystsel_t;
/**
* @brief Acmp inactive state
*/
typedef enum
{
ACMP_INACTVAL_LOW = 0, /**< The inactive value is 0 */
ACMP_INACTVAL_HIGH = 1, /**< The inactive value is 1 */
typedef enum {
ACMP_INACTVAL_LOW = 0U, /**< The inactive value is 0 */
ACMP_INACTVAL_HIGH = 1U, /**< The inactive value is 1 */
} acmp_inactval_t;
/**
* @brief which edges set up interrupt
*/
typedef enum
{
ACMP_EDGE_NONE = 0, /**< Disable EDGE interrupt */
ACMP_EDGE_FALL = 1, /**< Falling edges set EDGE interrupt */
ACMP_EDGE_RISE = 2, /**< rise edges set EDGE interrupt */
ACMP_EDGE_ALL = 3, /**< Falling edges and rise edges set EDGE interrupt */
typedef enum {
ACMP_EDGE_NONE = 0U, /**< Disable EDGE interrupt */
ACMP_EDGE_FALL = 1U, /**< Falling edges set EDGE interrupt */
ACMP_EDGE_RISE = 2U, /**< rise edges set EDGE interrupt */
ACMP_EDGE_ALL = 3U, /**< Falling edges and rise edges set EDGE interrupt */
} acmp_edge_t;
/**
* @brief Acmp output function
*/
typedef enum
{
ACMP_OUT_DISABLE = 0, /**< Disable acmp output */
ACMP_OUT_ENABLE = 1, /**< Enable acmp output */
typedef enum {
ACMP_OUT_DISABLE = 0U, /**< Disable acmp output */
ACMP_OUT_ENABLE = 1U, /**< Enable acmp output */
} acmp_out_func_t;
/**
* @brief Acmp warm-up interrupt function
*/
typedef enum
{
ACMP_WARM_DISABLE = 0, /**< Disable acmp warm-up interrupt */
ACMP_WARM_ENABLE = 1, /**< Enable acmp warm-up interrupt */
typedef enum {
ACMP_WARM_DISABLE = 0U, /**< Disable acmp warm-up interrupt */
ACMP_WARM_ENABLE = 1U, /**< Enable acmp warm-up interrupt */
} acmp_warm_it_func;
/**
* @brief Acmp gpio output invert
*/
typedef enum
{
ACMP_GPIO_NO_INV = 0, /**< Acmp output to gpio is not inverted */
ACMP_GPIO_INV = 1, /**< Acmp output to gpio is inverted */
typedef enum {
ACMP_GPIO_NO_INV = 0U, /**< Acmp output to gpio is not inverted */
ACMP_GPIO_INV = 1U, /**< Acmp output to gpio is inverted */
} acmp_invert_t;
/**
* @brief Acmp output config structure definition
*/
typedef struct
{
acmp_out_func_t out_func; /**< Acmp output function */
acmp_invert_t gpio_inv; /**< If invert gpio output */
typedef struct {
acmp_out_func_t out_func; /**< Acmp output function */
acmp_invert_t gpio_inv; /**< If invert gpio output */
} acmp_output_config_t;
/**
* @brief Acmp init structure definition
*/
typedef struct
{
acmp_mode_t mode; /**< Acmp operation mode */
acmp_warm_time_t warm_time; /**< Acmp warm up time */
acmp_hystsel_t hystsel; /**< Acmp hysteresis level */
acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */
acmp_pos_input_t pos_port; /**< Acmp positive port select */
acmp_neg_input_t neg_port; /**< Acmp negative port select */
acmp_inactval_t inactval; /**< Acmp inavtive output value */
acmp_edge_t edge; /** Select edges to set interrupt flag */
uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */
typedef struct {
acmp_mode_t mode; /**< Acmp operation mode */
acmp_warm_time_t warm_time; /**< Acmp warm up time */
acmp_hystsel_t hystsel; /**< Acmp hysteresis level */
acmp_warm_it_func warm_func; /**< Acmp warm-up interrupt enable/disable */
acmp_pos_input_t pos_port; /**< Acmp positive port select */
acmp_neg_input_t neg_port; /**< Acmp negative port select */
acmp_inactval_t inactval; /**< Acmp inavtive output value */
acmp_edge_t edge; /** Select edges to set interrupt flag */
uint8_t vdd_level; /** Select scaling factor for CDD reference level, MAX is 63 */
} acmp_init_t;
/**
* @brief ACMP Handle Structure definition
*/
typedef struct acmp_handle_s
{
ACMP_TypeDef *perh; /**< Register base address */
acmp_init_t init; /**< ACMP required parameters */
lock_state_t lock; /**< Locking object */
typedef struct acmp_handle_s {
ACMP_TypeDef *perh; /**< Register base address */
acmp_init_t init; /**< ACMP required parameters */
lock_state_t lock; /**< Locking object */
void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */
void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */
void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp warm-up complete callback */
void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg); /**< Acmp edge trigger callback */
} acmp_handle_t;
/**
* @}
@@ -237,64 +221,64 @@ typedef struct acmp_handle_s
* @{
*/
#define IS_ACMP_TYPE(x) (((x) == ACMP0) || \
((x) == ACMP1))
((x) == ACMP1))
#define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \
((x) == ACMP_LOW_POWER) || \
((x) == ACMP_MIDDLE_POWER) || \
((x) == ACMP_HIGH_POWER))
((x) == ACMP_LOW_POWER) || \
((x) == ACMP_MIDDLE_POWER) || \
((x) == ACMP_HIGH_POWER))
#define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \
((x) == ACMP_IT_WARMUP))
((x) == ACMP_IT_WARMUP))
#define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \
((x) == ACMP_FLAG_WARMUP))
((x) == ACMP_FLAG_WARMUP))
#define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_EDGE) || \
((x) == ACMP_STATUS_WARMUP))
((x) == ACMP_STATUS_WARMUP))
#define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \
((x) == ACMP_POS_CH1) || \
((x) == ACMP_POS_CH2) || \
((x) == ACMP_POS_CH3) || \
((x) == ACMP_POS_CH4) || \
((x) == ACMP_POS_CH5) || \
((x) == ACMP_POS_CH6) || \
((x) == ACMP_POS_CH7))
((x) == ACMP_POS_CH1) || \
((x) == ACMP_POS_CH2) || \
((x) == ACMP_POS_CH3) || \
((x) == ACMP_POS_CH4) || \
((x) == ACMP_POS_CH5) || \
((x) == ACMP_POS_CH6) || \
((x) == ACMP_POS_CH7))
#define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \
((x) == ACMP_NEG_CH1) || \
((x) == ACMP_NEG_CH2) || \
((x) == ACMP_NEG_CH3) || \
((x) == ACMP_NEG_CH4) || \
((x) == ACMP_NEG_CH5) || \
((x) == ACMP_NEG_CH6) || \
((x) == ACMP_NEG_CH7) || \
((x) == ACMP_NEG_1V25) || \
((x) == ACMP_NEG_2V5) || \
((x) == ACMP_NEG_VDD))
((x) == ACMP_NEG_CH1) || \
((x) == ACMP_NEG_CH2) || \
((x) == ACMP_NEG_CH3) || \
((x) == ACMP_NEG_CH4) || \
((x) == ACMP_NEG_CH5) || \
((x) == ACMP_NEG_CH6) || \
((x) == ACMP_NEG_CH7) || \
((x) == ACMP_NEG_1V25) || \
((x) == ACMP_NEG_2V5) || \
((x) == ACMP_NEG_VDD))
#define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \
((x) == ACMP_8_PCLK) || \
((x) == ACMP_16_PCLK) || \
((x) == ACMP_32_PCLK) || \
((x) == ACMP_64_PCLK) || \
((x) == ACMP_128_PCLK) || \
((x) == ACMP_256_PCLK) || \
((x) == ACMP_512_PCLK))
((x) == ACMP_8_PCLK) || \
((x) == ACMP_16_PCLK) || \
((x) == ACMP_32_PCLK) || \
((x) == ACMP_64_PCLK) || \
((x) == ACMP_128_PCLK) || \
((x) == ACMP_256_PCLK) || \
((x) == ACMP_512_PCLK))
#define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \
((x) == ACMP_HYST_15) || \
((x) == ACMP_HYST_22) || \
((x) == ACMP_HYST_29) || \
((x) == ACMP_HYST_36) || \
((x) == ACMP_HYST_43) || \
((x) == ACMP_HYST_50) || \
((x) == ACMP_HYST_57))
((x) == ACMP_HYST_15) || \
((x) == ACMP_HYST_22) || \
((x) == ACMP_HYST_29) || \
((x) == ACMP_HYST_36) || \
((x) == ACMP_HYST_43) || \
((x) == ACMP_HYST_50) || \
((x) == ACMP_HYST_57))
#define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \
((x) == ACMP_INACTVAL_HIGH))
((x) == ACMP_INACTVAL_HIGH))
#define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \
((x) == ACMP_EDGE_FALL) || \
((x) == ACMP_EDGE_RISE) || \
((x) == ACMP_EDGE_ALL))
((x) == ACMP_EDGE_FALL) || \
((x) == ACMP_EDGE_RISE) || \
((x) == ACMP_EDGE_ALL))
#define IS_ACMP_OUT_FUNC_TYPE(x) (((x) == ACMP_OUT_DISABLE) || \
((x) == ACMP_OUT_ENABLE))
((x) == ACMP_OUT_ENABLE))
#define IS_ACMP_INVERT_TYPE(x) (((x) == ACMP_GPIO_NO_INV) || \
((x) == ACMP_GPIO_INV))
((x) == ACMP_GPIO_INV))
#define IS_ACMP_WARM_FUNC_TYPE(x) (((x) == ACMP_WARM_DISABLE) || \
((x) == ACMP_WARM_ENABLE))
((x) == ACMP_WARM_ENABLE))
/**
* @}
*/
@@ -348,8 +332,7 @@ uint8_t ald_acmp_out_result(acmp_handle_t *hperh);
* @}
*/
#ifdef __cplusplus
extern "C"
}
extern "C" }
#endif
#endif

586
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h
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135
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h
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@@ -35,44 +35,44 @@ extern "C" {
/** @defgroup BKPC_Public_Macros BKPC Public Macros
* @{
*/
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55))
#define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U))
#define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U))
#define BKPC_LRC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LRC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSM_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_ENABLE() \
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)
#define BKPC_LOSC_DISABLE() \
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)
/**
* @}
*/
@@ -83,37 +83,31 @@ extern "C" {
/**
* @brief BKPC ldo output select
*/
typedef enum
{
BKPC_LDO_OUTPUT_1_6 = 0x0, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4, /**< 1.5V */
typedef enum {
BKPC_LDO_OUTPUT_1_6 = 0x0U, /**< 1.6V */
BKPC_LDO_OUTPUT_1_3 = 0x1U, /**< 1.3V */
BKPC_LDO_OUTPUT_1_4 = 0x2U, /**< 1.4V */
BKPC_LDO_OUTPUT_1_5 = 0x4U, /**< 1.5V */
} bkpc_ldo_output_t;
/**
* @brief BKPC BOR voltage select
* @brief Standby wakeup port select
*/
typedef enum
{
BKPC_BOR_VOL_1_7 = 0x0, /**< 1.7V */
BKPC_BOR_VOL_2_0 = 0x1, /**< 2.0V */
BKPC_BOR_VOL_2_1 = 0x2, /**< 2.1V */
BKPC_BOR_VOL_2_2 = 0x3, /**< 2.2V */
BKPC_BOR_VOL_2_3 = 0x4, /**< 2.3V */
BKPC_BOR_VOL_2_4 = 0x5, /**< 2.4V */
BKPC_BOR_VOL_2_5 = 0x6, /**< 2.5V */
BKPC_BOR_VOL_2_6 = 0x7, /**< 2.6V */
BKPC_BOR_VOL_2_8 = 0x8, /**< 2.8V */
BKPC_BOR_VOL_3_0 = 0x9, /**< 3.0V */
BKPC_BOR_VOL_3_1 = 0xA, /**< 3.1V */
BKPC_BOR_VOL_3_3 = 0xB, /**< 3.3V */
BKPC_BOR_VOL_3_6 = 0xC, /**< 3.6V */
BKPC_BOR_VOL_3_7 = 0xD, /**< 3.7V */
BKPC_BOR_VOL_4_0 = 0xE, /**< 4.0V */
BKPC_BOR_VOL_4_3 = 0xF, /**< 4.3V */
} bkpc_bor_vol_t;
typedef enum {
PMU_STANDBY_PORT_SEL_PA0 = 0x0U, /**< Wakeup by PA0 */
PMU_STANDBY_PORT_SEL_PA1 = 0x1U, /**< Wakeup by PA1 */
PMU_STANDBY_PORT_SEL_PA2 = 0x2U, /**< Wakeup by PA2 */
PMU_STANDBY_PORT_SEL_PA3 = 0x3U, /**< Wakeup by PA3 */
PMU_STANDBY_PORT_SEL_NONE = 0xFU, /**< Wakeup by other source */
} bkpc_wakeup_port_t;
/**
* @brief Standby wakeup level
*/
typedef enum {
PMU_STANDBY_LEVEL_HIGH = 0x0U, /**< High level */
PMU_STANDBY_LEVEL_LOW = 0x1U, /**< Low level */
} bkpc_wakeup_level_t;
/**
* @}
*/
@@ -126,22 +120,13 @@ typedef enum
((x) == BKPC_LDO_OUTPUT_1_3) || \
((x) == BKPC_LDO_OUTPUT_1_4) || \
((x) == BKPC_LDO_OUTPUT_1_5))
#define IS_BKPC_BOR_VOL(x) (((x) == BKPC_BOR_VOL_1_7) || \
((x) == BKPC_BOR_VOL_2_0) || \
((x) == BKPC_BOR_VOL_2_1) || \
((x) == BKPC_BOR_VOL_2_2) || \
((x) == BKPC_BOR_VOL_2_3) || \
((x) == BKPC_BOR_VOL_2_4) || \
((x) == BKPC_BOR_VOL_2_5) || \
((x) == BKPC_BOR_VOL_2_6) || \
((x) == BKPC_BOR_VOL_2_8) || \
((x) == BKPC_BOR_VOL_3_0) || \
((x) == BKPC_BOR_VOL_3_1) || \
((x) == BKPC_BOR_VOL_3_3) || \
((x) == BKPC_BOR_VOL_3_6) || \
((x) == BKPC_BOR_VOL_3_7) || \
((x) == BKPC_BOR_VOL_4_0) || \
((x) == BKPC_BOR_VOL_4_3))
#define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \
((x) == PMU_STANDBY_PORT_SEL_PA1) || \
((x) == PMU_STANDBY_PORT_SEL_PA2) || \
((x) == PMU_STANDBY_PORT_SEL_PA3) || \
((x) == PMU_STANDBY_PORT_SEL_NONE))
#define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \
((x) == PMU_STANDBY_LEVEL_LOW))
#define IS_BKPC_RAM_IDX(x) ((x) < 32)
/**
* @}
@@ -154,8 +139,8 @@ typedef enum
* @{
*/
/* control functions */
extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
/**
* @}
*/

758
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h
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84
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h
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@@ -18,7 +18,7 @@
#define __ALD_CRC_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -39,75 +39,69 @@ extern "C" {
/**
* @brief CRC mode
*/
typedef enum
{
CRC_MODE_CCITT = 0, /**< Ccitt */
CRC_MODE_8 = 1, /**< Crc8 */
CRC_MODE_16 = 2, /**< Crc16 */
CRC_MODE_32 = 3, /**< Crc32 */
typedef enum {
CRC_MODE_CCITT = 0U, /**< Ccitt */
CRC_MODE_8 = 1U, /**< Crc8 */
CRC_MODE_16 = 2U, /**< Crc16 */
CRC_MODE_32 = 3U, /**< Crc32 */
} crc_mode_t;
/**
* @brief CRC input length
*/
typedef enum
{
CRC_LEN_AUTO = 0, /**< Auto */
CRC_DATASIZE_8 = 1, /**< Byte */
CRC_DATASIZE_16 = 2, /**< Half word */
CRC_DATASIZE_32 = 3, /**< Word */
typedef enum {
CRC_LEN_AUTO = 0U, /**< Auto */
CRC_DATASIZE_8 = 1U, /**< Byte */
CRC_DATASIZE_16 = 2U, /**< Half word */
CRC_DATASIZE_32 = 3U, /**< Word */
} crc_datasize_t;
/**
* @brief CRC whether write error or no
*/
typedef enum
{
CRC_WERR_NO = 0, /**< No error */
CRC_WERR_ERR = 1, /**< Error */
typedef enum {
CRC_WERR_NO = 0U, /**< No error */
CRC_WERR_ERR = 1U, /**< Error */
} crc_werr_t;
/**
* @brief CRC state structures definition
*/
typedef enum
{
CRC_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4, /**< Error */
typedef enum {
CRC_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
CRC_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
CRC_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
CRC_STATE_ERROR = 0x4U, /**< Error */
} crc_state_t;
/**
* @brief CRC init structure definition
*/
typedef struct
{
crc_mode_t mode; /**< CRC mode */
type_func_t data_rev; /**< CRC data reverse or no */
type_func_t data_inv; /**< CRC data inverse or no */
type_func_t chs_rev; /**< CRC check sum reverse or no */
type_func_t chs_inv; /**< CRC check sum inverse or no */
uint32_t seed; /**< CRC seed */
typedef struct {
crc_mode_t mode; /**< CRC mode */
type_func_t data_rev; /**< CRC data reverse or no */
type_func_t data_inv; /**< CRC data inverse or no */
type_func_t chs_rev; /**< CRC check sum reverse or no */
type_func_t chs_inv; /**< CRC check sum inverse or no */
uint32_t seed; /**< CRC seed */
} crc_init_t;
/**
* @brief CRC Handle Structure definition
*/
typedef struct crc_handle_s
{
CRC_TypeDef *perh; /**< Register base address */
crc_init_t init; /**< CRC required parameters */
uint8_t *cal_buf; /**< The pointer of preparing buffer */
uint32_t *cal_res; /**< The pointer of result */
typedef struct crc_handle_s {
CRC_TypeDef *perh; /**< Register base address */
crc_init_t init; /**< CRC required parameters */
uint8_t *cal_buf; /**< The pointer of preparing buffer */
uint32_t *cal_res; /**< The pointer of result */
#ifdef ALD_DMA
dma_handle_t hdma; /**< CRC DMA handle parameters */
dma_handle_t hdma; /**< CRC DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
crc_state_t state; /**< CRC operation state */
lock_state_t lock; /**< Locking object */
crc_state_t state; /**< CRC operation state */
void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */
void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */
void (*cal_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate completed callback */
void (*err_cplt_cbk)(struct crc_handle_s *arg); /**< Calculate error callback */
} crc_handle_t;
/**
* @}
@@ -131,9 +125,9 @@ typedef struct crc_handle_s
*/
#define IS_CRC(x) ((x) == CRC)
#define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \
((x) == CRC_MODE_8) || \
((x) == CRC_MODE_16) || \
((x) == CRC_MODE_32))
((x) == CRC_MODE_8) || \
((x) == CRC_MODE_16) || \
((x) == CRC_MODE_32))
/**
* @}
*/

121
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h
View File

@@ -18,7 +18,7 @@
#define __ALD_CRYPT_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -39,105 +39,96 @@ extern "C" {
/**
* @brief CRYPT encrypt or decrypt select
*/
typedef enum
{
CRYPT_DECRYPT = 0, /**< Decrypt */
CRYPT_ENCRYPT = 1, /**< Encrypt */
typedef enum {
CRYPT_DECRYPT = 0U, /**< Decrypt */
CRYPT_ENCRYPT = 1U, /**< Encrypt */
} crypt_encs_t;
/**
* @brief CRYPT mode select
*/
typedef enum
{
CRYPT_MODE_ECB = 0, /**< ECB */
CRYPT_MODE_CBC = 1, /**< CBC */
CRYPT_MODE_CTR = 2, /**< CTR */
typedef enum {
CRYPT_MODE_ECB = 0U, /**< ECB */
CRYPT_MODE_CBC = 1U, /**< CBC */
CRYPT_MODE_CTR = 2U, /**< CTR */
} crypt_mode_t;
/**
* @brief CRYPT data type
*/
typedef enum
{
CRYPT_DATA_CHANGE_NO = 0, /**< No exchange */
CRYPT_DATA_CHANGE_16 = 1, /**< 16bit exchange */
CRYPT_DATA_CHANGE_8 = 2, /**< 8bit exchange */
CRYPT_DATA_CHANGE_1 = 3, /**< 1bit exchange */
typedef enum {
CRYPT_DATA_CHANGE_NO = 0U, /**< No exchange */
CRYPT_DATA_CHANGE_16 = 1U, /**< 16bit exchange */
CRYPT_DATA_CHANGE_8 = 2U, /**< 8bit exchange */
CRYPT_DATA_CHANGE_1 = 3U, /**< 1bit exchange */
} crypt_datatype_t;
/**
* @brief CRYPT interrupt
*/
typedef enum
{
CRYPT_IT_IT = 0x80, /**< Interrupt */
typedef enum {
CRYPT_IT_IT = 0x80U, /**< Interrupt */
} crypt_it_t;
/**
* @brief CRYPT interrupt flag
*/
typedef enum
{
CRYPT_FLAG_AESIF = 0x1, /**< Aes flag */
CRYPT_FLAG_DONE = 0x100, /**< Complete flag */
typedef enum {
CRYPT_FLAG_AESIF = 0x1U, /**< Aes flag */
CRYPT_FLAG_DONE = 0x100U, /**< Complete flag */
} crypt_flag_t;
/**
* @brief CRYPT state structures definition
*/
typedef enum
{
CRYPT_STATE_RESET = 0x0, /**< Peripheral is not initialized */
CRYPT_STATE_READY = 0x1, /**< Peripheral Initialized and ready for use */
CRYPT_STATE_BUSY = 0x2, /**< An internal process is ongoing */
CRYPT_STATE_ERROR = 0x4, /**< Error */
typedef enum {
CRYPT_STATE_RESET = 0x0U, /**< Peripheral is not initialized */
CRYPT_STATE_READY = 0x1U, /**< Peripheral Initialized and ready for use */
CRYPT_STATE_BUSY = 0x2U, /**< An internal process is ongoing */
CRYPT_STATE_ERROR = 0x4U, /**< Error */
} crypt_state_t;
/**
* @brief CRYPT data type
*/
typedef enum
{
DATA_32_BIT = 0, /**< 32 bit data,don't swap */
DATA_16_BIT = 1, /**< 16 bit data,swap */
DATA_8_BIT = 2, /**< 8 bit data,swap */
DATA_1_BIT = 3, /**< 1 bit data, swap */
typedef enum {
DATA_32_BIT = 0U, /**< 32 bit data,don't swap */
DATA_16_BIT = 1U, /**< 16 bit data,swap */
DATA_8_BIT = 2U, /**< 8 bit data,swap */
DATA_1_BIT = 3U, /**< 1 bit data, swap */
} crypt_data_t;
/**
* @brief CRYPT init structure definition
*/
typedef struct
{
crypt_mode_t mode; /**< Crypt mode */
crypt_data_t type; /**< Data type select */
typedef struct {
crypt_mode_t mode; /**< Crypt mode */
crypt_data_t type; /**< Data type select */
} crypt_init_t;
/**
* @brief CRYPT Handle Structure definition
*/
typedef struct crypt_handle_s
{
CRYPT_TypeDef *perh; /**< Register base address */
crypt_init_t init; /**< CRYPT required parameters */
typedef struct crypt_handle_s {
CRYPT_TypeDef *perh; /**< Register base address */
crypt_init_t init; /**< CRYPT required parameters */
#ifdef ALD_DMA
dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */
dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */
dma_handle_t hdma_m2p; /**< CRYPT DMA handle parameters memory to crypt module */
dma_handle_t hdma_p2m; /**< CRYPT DMA handle parameters crypt module to memory */
#endif
uint8_t *plain_text; /**< Pointer to plain text */
uint8_t *cipher_text; /**< Pointer to cipher text */
uint32_t size; /**< The size of crypt data buf */
uint32_t count; /**< The count of crypt data buf */
uint32_t step; /**< The step of once crypt 4(aes) */
uint32_t dir; /**< ENCRYPT or DECRYPT */
uint32_t iv[4]; /**< The iv of crypt */
uint32_t key[4]; /**< The key of crypt */
lock_state_t lock; /**< Locking object */
crypt_state_t state; /**< CRYPT operation state */
uint8_t *plain_text; /**< Pointer to plain text */
uint8_t *cipher_text; /**< Pointer to cipher text */
uint32_t size; /**< The size of crypt data buf */
uint32_t count; /**< The count of crypt data buf */
uint32_t step; /**< The step of once crypt 4(aes) */
uint32_t dir; /**< ENCRYPT or DECRYPT */
uint32_t iv[4]; /**< The iv of crypt */
uint32_t key[4]; /**< The key of crypt */
lock_state_t lock; /**< Locking object */
crypt_state_t state; /**< CRYPT operation state */
void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */
void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */
void (*crypt_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt completed callback */
void (*err_cplt_cbk)(struct crypt_handle_s *arg); /**< Crypt error callback */
} crypt_handle_t;
/**
* @}
@@ -148,7 +139,7 @@ typedef struct crypt_handle_s
*/
#define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
#define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
@@ -156,7 +147,7 @@ typedef struct crypt_handle_s
#define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \
(handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
(handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
#define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data))
#define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO)
/**
@@ -168,13 +159,13 @@ typedef struct crypt_handle_s
*/
#define IS_CRYPT(x) ((x) == CRYPT)
#define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \
((x) == CRYPT_MODE_CBC) || \
((x) == CRYPT_MODE_CTR))
((x) == CRYPT_MODE_CBC) || \
((x) == CRYPT_MODE_CTR))
#define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT)
#define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \
((x) == CRYPT_FLAG_DONE))
((x) == CRYPT_FLAG_DONE))
#define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \
((x) == IV_4_LEN))
((x) == IV_4_LEN))
/**
* @}
*/
@@ -205,9 +196,9 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text,
ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
#ifdef ALD_DMA
ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text,
uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text,
uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
#endif
/**
* @}

86
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h
View File

@@ -18,7 +18,7 @@
#define __ALD_DBGC_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -41,34 +41,32 @@ extern "C" {
/**
* @brief Debug mode select
*/
typedef enum
{
DEBC_MODE_SLEEP = (1u << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1u << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1u << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1u << 3), /**< Standby mode */
typedef enum {
DEBC_MODE_SLEEP = (1U << 0), /**< Sleep mode */
DEBC_MODE_STOP1 = (1U << 1), /**< STOP1 mode */
DEBC_MODE_STOP2 = (1U << 2), /**< STOP2 mode */
DEBC_MODE_STANDBY = (1U << 3), /**< Standby mode */
} dbgc_mode_t;
/**
* @brief Debug peripheral select
*/
typedef enum
{
DEBC_PERH_TIMER0 = (1u << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1u << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1u << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1u << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1u << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1u << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1u << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1u << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1u << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1u << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1u << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1u << 0) | (1u << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1u << 8) | (1u << 16), /**< IWDT */
DEBC_PERH_WWDT = (1u << 9) | (1u << 16), /**< WWDT */
DEBC_PERH_RTC = (1u << 10) | (1u << 16), /**< RTC */
typedef enum {
DEBC_PERH_TIMER0 = (1U << 0), /**< AD16C4T0 */
DEBC_PERH_TIMER1 = (1U << 1), /**< BS16T0 */
DEBC_PERH_TIMER2 = (1U << 2), /**< GP16C2T0 */
DEBC_PERH_TIMER3 = (1U << 3), /**< GP16C2T1 */
DEBC_PERH_TIMER4 = (1U << 4), /**< BS16T1 */
DEBC_PERH_TIMER5 = (1U << 5), /**< BS16T2 */
DEBC_PERH_TIMER6 = (1U << 6), /**< GP16C4T0 */
DEBC_PERH_TIMER7 = (1U << 7), /**< BS16T3 */
DEBC_PERH_I2C0 = (1U << 8), /**< I2C0 SMBUS */
DEBC_PERH_I2C1 = (1U << 9), /**< I2C1 SMBUS */
DEBC_PERH_CAN = (1U << 12), /**< CAN */
DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16), /**< LPTIM0 */
DEBC_PERH_IWDT = (1U << 8) | (1U << 16), /**< IWDT */
DEBC_PERH_WWDT = (1U << 9) | (1U << 16), /**< WWDT */
DEBC_PERH_RTC = (1U << 10) | (1U << 16), /**< RTC */
} dbgc_perh_t;
/**
* @}
@@ -83,7 +81,7 @@ typedef enum
*/
__INLINE uint32_t ald_dbgc_get_rev_id(void)
{
return (DBGC->IDCODE >> 16);
return (DBGC->IDCODE >> 16);
}
/**
@@ -92,7 +90,7 @@ __INLINE uint32_t ald_dbgc_get_rev_id(void)
*/
__INLINE uint32_t ald_dbgc_get_core_id(void)
{
return (DBGC->IDCODE >> 12) & 0xF;
return (DBGC->IDCODE >> 12) & 0xF;
}
/**
@@ -101,7 +99,7 @@ __INLINE uint32_t ald_dbgc_get_core_id(void)
*/
__INLINE uint32_t ald_dbgc_get_device_id(void)
{
return DBGC->IDCODE & 0xFFF;
return DBGC->IDCODE & 0xFFF;
}
/**
@@ -112,10 +110,10 @@ __INLINE uint32_t ald_dbgc_get_device_id(void)
*/
__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
{
if (state)
SET_BIT(DBGC->CR, mode);
else
CLEAR_BIT(DBGC->CR, mode);
if (state)
SET_BIT(DBGC->CR, mode);
else
CLEAR_BIT(DBGC->CR, mode);
}
/**
@@ -126,20 +124,18 @@ __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
*/
__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
{
if ((perh >> 16) & 0x1)
{
if (state)
SET_BIT(DBGC->APB2FZ, perh);
else
CLEAR_BIT(DBGC->APB2FZ, perh);
}
else
{
if (state)
SET_BIT(DBGC->APB1FZ, perh);
else
CLEAR_BIT(DBGC->APB1FZ, perh);
}
if ((perh >> 16) & 0x1) {
if (state)
SET_BIT(DBGC->APB2FZ, perh);
else
CLEAR_BIT(DBGC->APB2FZ, perh);
}
else {
if (state)
SET_BIT(DBGC->APB1FZ, perh);
else
CLEAR_BIT(DBGC->APB1FZ, perh);
}
}
/**
* @}

434
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h
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File diff suppressed because it is too large Load Diff

48
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h
View File

@@ -36,21 +36,21 @@ extern "C" {
* @{
*/
#define FLASH_REG_UNLOCK() \
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \
} \
} while (0)
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246U); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357U); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9U); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8U); \
} \
} while (0)
#define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define FLASH_BASE_ADDR 0x00000000
#define FLASH_BASE_ADDR 0x00000000U
#define FLASH_PAGE_SIZE 1024UL
#define FLASH_WORD_SIZE 8UL
#define FLASH_TOTAL_SIZE 256UL
@@ -67,9 +67,9 @@ extern "C" {
#define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#ifdef USE_FLASH_FIFO
#define FLASH_FIFO 1
#define FLASH_FIFO 1
#else
#define FLASH_FIFO 0
#define FLASH_FIFO 0
#endif
/**
* @}
@@ -78,24 +78,22 @@ extern "C" {
/** @defgroup FLASH_Private_Types FLASH Private Types
* @{
*/
typedef enum
{
FLASH_CMD_AE = 0x000051AE, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5, /**< Data flash word program */
typedef enum {
FLASH_CMD_AE = 0x000051AEU, /**< Program area erase all */
FLASH_CMD_PE = 0x00005EA1U, /**< Page erase */
FLASH_CMD_WP = 0x00005DA2U, /**< Word program */
FLASH_CMD_DATAPE = 0x00005BA4U, /**< Data flash page page erase */
FLASH_CMD_DATAWP = 0x00005AA5U, /**< Data flash word program */
} flash_cmd_type;
typedef enum
{
OP_FLASH = 0, /**< Operate Pragram area */
OP_INFO = 1, /**< Operate info area */
typedef enum {
OP_FLASH = 0U, /**< Operate Pragram area */
OP_INFO = 1U, /**< Operate info area */
} op_cmd_type;
/**
* @}
*/
*/
/** @addtogroup Flash_Private_Functions
* @{
*/

157
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h
View File

@@ -18,7 +18,7 @@
#define __ALD_GPIO_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -52,7 +52,7 @@ extern "C" {
#define GPIO_PIN_13 (1U << 13)
#define GPIO_PIN_14 (1U << 14)
#define GPIO_PIN_15 (1U << 15)
#define GPIO_PIN_ALL (0xFFFF)
#define GPIO_PIN_ALL (0xFFFFU)
/**
* @}
*/
@@ -65,125 +65,114 @@ extern "C" {
/**
* @brief GPIO mode
*/
typedef enum
{
GPIO_MODE_CLOSE = 0x0, /**< Digital close Analog open */
GPIO_MODE_INPUT = 0x1, /**< Input */
GPIO_MODE_OUTPUT = 0x2, /**< Output */
typedef enum {
GPIO_MODE_CLOSE = 0x0U, /**< Digital close Analog open */
GPIO_MODE_INPUT = 0x1U, /**< Input */
GPIO_MODE_OUTPUT = 0x2U, /**< Output */
} gpio_mode_t;
/**
* @brief GPIO open-drain or push-pull
*/
typedef enum
{
GPIO_PUSH_PULL = 0x0, /**< Push-Pull */
GPIO_OPEN_DRAIN = 0x2, /**< Open-Drain */
GPIO_OPEN_SOURCE = 0x3, /**< Open-Source */
typedef enum {
GPIO_PUSH_PULL = 0x0U, /**< Push-Pull */
GPIO_OPEN_DRAIN = 0x2U, /**< Open-Drain. Can't output high level */
GPIO_OPEN_SOURCE = 0x3U, /**< Open-Source. Can't output low level */
} gpio_odos_t;
/**
* @brief GPIO push-up or push-down
*/
typedef enum
{
GPIO_FLOATING = 0x0,/**< Floating */
GPIO_PUSH_UP = 0x1,/**< Push-Up */
GPIO_PUSH_DOWN = 0x2,/**< Push-Down */
GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */
typedef enum {
GPIO_FLOATING = 0x0U, /**< Floating */
GPIO_PUSH_UP = 0x1U, /**< Push-Up */
GPIO_PUSH_DOWN = 0x2U, /**< Push-Down */
GPIO_PUSH_UP_DOWN = 0x3U, /**< Push-Up and Push-Down */
} gpio_push_t;
/**
* @brief GPIO output drive
*/
typedef enum
{
GPIO_OUT_DRIVE_NORMAL = 0x0, /**< Normal current flow */
GPIO_OUT_DRIVE_STRONG = 0x1, /**< Strong current flow */
typedef enum {
GPIO_OUT_DRIVE_NORMAL = 0x0U, /**< Normal current flow */
GPIO_OUT_DRIVE_STRONG = 0x1U, /**< Strong current flow */
} gpio_out_drive_t;
/**
* @brief GPIO filter
*/
typedef enum
{
GPIO_FILTER_DISABLE = 0x0, /**< Disable filter */
GPIO_FILTER_ENABLE = 0x1, /**< Enable filter */
typedef enum {
GPIO_FILTER_DISABLE = 0x0U, /**< Disable filter */
GPIO_FILTER_ENABLE = 0x1U, /**< Enable filter */
} gpio_filter_t;
/**
* @brief GPIO type
*/
typedef enum
{
GPIO_TYPE_CMOS = 0x0, /**< CMOS Type */
GPIO_TYPE_TTL = 0x1, /**< TTL Type */
typedef enum {
GPIO_TYPE_CMOS = 0x0U, /**< CMOS Type */
GPIO_TYPE_TTL = 0x1U, /**< TTL Type */
} gpio_type_t;
/**
* @brief GPIO functions
*/
typedef enum
{
GPIO_FUNC_0 = 0, /**< function #0 */
GPIO_FUNC_1 = 1, /**< function #1 */
GPIO_FUNC_2 = 2, /**< function #2 */
GPIO_FUNC_3 = 3, /**< function #3 */
GPIO_FUNC_4 = 4, /**< function #4 */
GPIO_FUNC_5 = 5, /**< function #5 */
GPIO_FUNC_6 = 6, /**< function #6 */
GPIO_FUNC_7 = 7, /**< function #7 */
typedef enum {
GPIO_FUNC_0 = 0U, /**< function #0 */
GPIO_FUNC_1 = 1U, /**< function #1 */
GPIO_FUNC_2 = 2U, /**< function #2 */
GPIO_FUNC_3 = 3U, /**< function #3 */
GPIO_FUNC_4 = 4U, /**< function #4 */
GPIO_FUNC_5 = 5U, /**< function #5 */
GPIO_FUNC_6 = 6U, /**< function #6 */
GPIO_FUNC_7 = 7U, /**< function #7 */
} gpio_func_t;
/**
* @brief GPIO Init Structure definition
*/
typedef struct
{
gpio_mode_t mode; /**< Specifies the operating mode for the selected pins.
typedef struct {
gpio_mode_t mode; /**< Specifies the operating mode for the selected pins.
This parameter can be any value of @ref gpio_mode_t */
gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins.
gpio_odos_t odos; /**< Specifies the Open-Drain or Push-Pull for the selected pins.
This parameter can be a value of @ref gpio_odos_t */
gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins.
gpio_push_t pupd; /**< Specifies the Pull-up or Pull-Down for the selected pins.
This parameter can be a value of @ref gpio_push_t */
gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins.
gpio_out_drive_t odrv; /**< Specifies the output driver for the selected pins.
This parameter can be a value of @ref gpio_out_drive_t */
gpio_filter_t flt; /**< Specifies the input filter for the selected pins.
gpio_filter_t flt; /**< Specifies the input filter for the selected pins.
This parameter can be a value of @ref gpio_filter_t */
gpio_type_t type; /**< Specifies the type for the selected pins.
gpio_type_t type; /**< Specifies the type for the selected pins.
This parameter can be a value of @ref gpio_type_t */
gpio_func_t func; /**< Specifies the function for the selected pins.
gpio_func_t func; /**< Specifies the function for the selected pins.
This parameter can be a value of @ref gpio_func_t */
} gpio_init_t;
/**
* @brief EXTI trigger style
*/
typedef enum
{
EXTI_TRIGGER_RISING_EDGE = 0, /**< Rising edge trigger */
EXTI_TRIGGER_TRAILING_EDGE = 1, /**< Trailing edge trigger */
EXTI_TRIGGER_BOTH_EDGE = 2, /**< Rising and trailing edge trigger */
typedef enum {
EXTI_TRIGGER_RISING_EDGE = 0U, /**< Rising edge trigger */
EXTI_TRIGGER_TRAILING_EDGE = 1U, /**< Trailing edge trigger */
EXTI_TRIGGER_BOTH_EDGE = 2U, /**< Rising and trailing edge trigger */
} exti_trigger_style_t;
/**
* @brief EXTI filter clock select
*/
typedef enum
{
EXTI_FILTER_CLOCK_10K = 0, /**< cks = 10KHz */
EXTI_FILTER_CLOCK_32K = 1, /**< cks = 32KHz */
typedef enum {
EXTI_FILTER_CLOCK_10K = 0U, /**< cks = 10KHz */
EXTI_FILTER_CLOCK_32K = 1U, /**< cks = 32KHz */
} exti_filter_clock_t;
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
type_func_t filter; /**< Enable filter. */
exti_filter_clock_t cks; /**< Filter clock select. */
uint8_t filter_time; /**< Filter duration */
typedef struct {
type_func_t filter; /**< Enable filter. */
exti_filter_clock_t cks; /**< Filter clock select. */
uint8_t filter_time; /**< Filter duration */
} exti_init_t;
/**
* @}
@@ -193,37 +182,37 @@ typedef struct
* @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define PIN_MASK 0xFFFF
#define UNLOCK_KEY 0x55AA
#define PIN_MASK 0xFFFFU
#define UNLOCK_KEY 0x55AAU
#define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
#define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \
(GPIOx == GPIOB) || \
(GPIOx == GPIOC) || \
(GPIOx == GPIOD) || \
(GPIOx == GPIOE) || \
(GPIOx == GPIOF) || \
(GPIOx == GPIOG) || \
(GPIOx == GPIOH))
(GPIOx == GPIOB) || \
(GPIOx == GPIOC) || \
(GPIOx == GPIOD) || \
(GPIOx == GPIOE) || \
(GPIOx == GPIOF) || \
(GPIOx == GPIOG) || \
(GPIOx == GPIOH))
#define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \
((x) == GPIO_MODE_INPUT) || \
((x) == GPIO_MODE_OUTPUT))
((x) == GPIO_MODE_INPUT) || \
((x) == GPIO_MODE_OUTPUT))
#define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \
((x) == GPIO_OPEN_DRAIN) || \
((x) == GPIO_OPEN_SOURCE))
((x) == GPIO_OPEN_DRAIN) || \
((x) == GPIO_OPEN_SOURCE))
#define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \
((x) == GPIO_PUSH_UP) || \
((x) == GPIO_PUSH_DOWN) || \
((x) == GPIO_PUSH_UP_DOWN))
((x) == GPIO_PUSH_UP) || \
((x) == GPIO_PUSH_DOWN) || \
((x) == GPIO_PUSH_UP_DOWN))
#define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_NORMAL) || \
((x) == GPIO_OUT_DRIVE_STRONG))
((x) == GPIO_OUT_DRIVE_STRONG))
#define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \
((x) == GPIO_FILTER_ENABLE))
((x) == GPIO_FILTER_ENABLE))
#define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \
((x) == GPIO_TYPE_CMOS))
((x) == GPIO_TYPE_CMOS))
#define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \
((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
((x) == EXTI_TRIGGER_BOTH_EDGE))
((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
((x) == EXTI_TRIGGER_BOTH_EDGE))
#define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \
((x) == EXTI_FILTER_CLOCK_32K))
#define IS_GPIO_FUNC(x) ((x) <= 7)

469
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h
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8
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h
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@@ -36,10 +36,10 @@ extern "C" {
* @defgroup IAP_Private_Macros IAP Private Macros
* @{
*/
#define IAP_WSP_ADDR 0x10000000
#define IAP_PE_ADDR 0x10000004
#define IAP_WP_ADDR 0x10000008
#define IAP_DWP_ADDR 0x1000000c
#define IAP_WSP_ADDR 0x10000000U
#define IAP_PE_ADDR 0x10000004U
#define IAP_WP_ADDR 0x10000008U
#define IAP_DWP_ADDR 0x1000000cU
/**
* @}
*/

497
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h
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260
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h
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@@ -19,7 +19,7 @@
#define __ALD_LPTIM_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -41,179 +41,163 @@ extern "C" {
/**
* @brief LPTIM clock select
*/
typedef enum
{
LPTIM_CKSEL_INTERNAL = 0, /**< Select internal clock */
LPTIM_CKSEL_EXTERNAL = 1, /**< Select external clock */
typedef enum {
LPTIM_CKSEL_INTERNAL = 0U, /**< Select internal clock */
LPTIM_CKSEL_EXTERNAL = 1U, /**< Select external clock */
} lptim_cksel_t;
/**
* @brief LPTIM clock pol
*/
typedef enum
{
LPTIM_CKPOL_RISING = 0, /**< using rising edge */
LPTIM_CKPOL_FALLING = 1, /**< using falling edge */
typedef enum {
LPTIM_CKPOL_RISING = 0U, /**< using rising edge */
LPTIM_CKPOL_FALLING = 1U, /**< using falling edge */
} lptim_ckpol_t;
/**
* @brief LPTIM clock fliter
*/
typedef enum
{
LPTIM_CKFLT_0 = 0, /**< not clock filter */
LPTIM_CKFLT_2 = 1, /**< 2 cycle filter */
LPTIM_CKFLT_4 = 2, /**< 4 cycle filter */
LPTIM_CKFLT_8 = 3, /**< 8 cycle filter */
typedef enum {
LPTIM_CKFLT_0 = 0U, /**< not clock filter */
LPTIM_CKFLT_2 = 1U, /**< 2 cycle filter */
LPTIM_CKFLT_4 = 2U, /**< 4 cycle filter */
LPTIM_CKFLT_8 = 3U, /**< 8 cycle filter */
} lptim_ckflt_t;
/**
* @brief LPTIM trigger fliter
*/
typedef enum
{
LPTIM_TRGFLT_0 = 0, /**< not clock filter */
LPTIM_TRGFLT_2 = 1, /**< 2 cycle filter */
LPTIM_TRGFLT_4 = 2, /**< 4 cycle filter */
LPTIM_TRGFLT_8 = 3, /**< 8 cycle filter */
typedef enum {
LPTIM_TRGFLT_0 = 0U, /**< not clock filter */
LPTIM_TRGFLT_2 = 1U, /**< 2 cycle filter */
LPTIM_TRGFLT_4 = 2U, /**< 4 cycle filter */
LPTIM_TRGFLT_8 = 3U, /**< 8 cycle filter */
} lptim_trgflt_t;
/**
* @brief LPTIM prescaler
*/
typedef enum
{
LPTIM_PRESC_1 = 0, /**< No prescaler is used */
LPTIM_PRESC_2 = 1, /**< Clock is divided by 2 */
LPTIM_PRESC_4 = 2, /**< Clock is divided by 4 */
LPTIM_PRESC_8 = 3, /**< Clock is divided by 8 */
LPTIM_PRESC_16 = 4, /**< Clock is divided by 16 */
LPTIM_PRESC_32 = 5, /**< Clock is divided by 32 */
LPTIM_PRESC_64 = 6, /**< Clock is divided by 64 */
LPTIM_PRESC_128 = 7, /**< Clock is divided by 128 */
typedef enum {
LPTIM_PRESC_1 = 0U, /**< No prescaler is used */
LPTIM_PRESC_2 = 1U, /**< Clock is divided by 2 */
LPTIM_PRESC_4 = 2U, /**< Clock is divided by 4 */
LPTIM_PRESC_8 = 3U, /**< Clock is divided by 8 */
LPTIM_PRESC_16 = 4U, /**< Clock is divided by 16 */
LPTIM_PRESC_32 = 5U, /**< Clock is divided by 32 */
LPTIM_PRESC_64 = 6U, /**< Clock is divided by 64 */
LPTIM_PRESC_128 = 7U, /**< Clock is divided by 128 */
} lptim_presc_t;
/**
* @brief LPTIM trig select
*/
typedef enum
{
LPTIM_TRIGSEL_EXT0 = 0, /**< Trigger select external channel 0 */
LPTIM_TRIGSEL_EXT1 = 1, /**< Trigger select external channel 1 */
LPTIM_TRIGSEL_EXT2 = 2, /**< Trigger select external channel 2 */
LPTIM_TRIGSEL_EXT3 = 3, /**< Trigger select external channel 3 */
LPTIM_TRIGSEL_EXT4 = 4, /**< Trigger select external channel 4 */
LPTIM_TRIGSEL_EXT5 = 5, /**< Trigger select external channel 5 */
LPTIM_TRIGSEL_EXT6 = 6, /**< Trigger select external channel 6 */
LPTIM_TRIGSEL_EXT7 = 7, /**< Trigger select external channel 7 */
typedef enum {
LPTIM_TRIGSEL_EXT0 = 0U, /**< Trigger select external channel 0 */
LPTIM_TRIGSEL_EXT1 = 1U, /**< Trigger select external channel 1 */
LPTIM_TRIGSEL_EXT2 = 2U, /**< Trigger select external channel 2 */
LPTIM_TRIGSEL_EXT3 = 3U, /**< Trigger select external channel 3 */
LPTIM_TRIGSEL_EXT4 = 4U, /**< Trigger select external channel 4 */
LPTIM_TRIGSEL_EXT5 = 5U, /**< Trigger select external channel 5 */
LPTIM_TRIGSEL_EXT6 = 6U, /**< Trigger select external channel 6 */
LPTIM_TRIGSEL_EXT7 = 7U, /**< Trigger select external channel 7 */
} lptim_trigsel_t;
/**
* @brief LPTIM start mode select
*/
typedef enum
{
LPTIM_MODE_SINGLE = 0, /**< Start single mode */
LPTIM_MODE_CONTINUOUS = 1, /**< Start continuous mode */
typedef enum {
LPTIM_MODE_SINGLE = 0U, /**< Start single mode */
LPTIM_MODE_CONTINUOUS = 1U, /**< Start continuous mode */
} lptim_mode_t;
/**
* @brief LPTIM trig en
*/
typedef enum
{
LPTIM_TRIGEN_SW = 0, /**< software trigger */
LPTIM_TRIGEN_RISING = 1, /**< rising edge trigger */
LPTIM_TRIGEN_FALLING = 2, /**< falling edge trigger */
LPTIM_TRIGEN_BOTH = 3, /**< rising and falling edge trigger */
typedef enum {
LPTIM_TRIGEN_SW = 0U, /**< software trigger */
LPTIM_TRIGEN_RISING = 1U, /**< rising edge trigger */
LPTIM_TRIGEN_FALLING = 2U, /**< falling edge trigger */
LPTIM_TRIGEN_BOTH = 3U, /**< rising and falling edge trigger */
} lptim_trigen_t;
/**
* @brief LPTIM wave
*/
typedef enum
{
LPTIM_WAVE_NONE = 0, /**< Output close */
LPTIM_WAVE_TOGGLE = 1, /**< Output toggle */
LPTIM_WAVE_PULSE = 2, /**< Output pulse */
LPTIM_WAVE_PWM = 3, /**< Output PWM */
typedef enum {
LPTIM_WAVE_NONE = 0U, /**< Output close */
LPTIM_WAVE_TOGGLE = 1U, /**< Output toggle */
LPTIM_WAVE_PULSE = 2U, /**< Output pulse */
LPTIM_WAVE_PWM = 3U, /**< Output PWM */
} lptim_wave_t;
/**
* @brief LPTIM interrupt
*/
typedef enum
{
LPTIM_IT_CMPMAT = 1, /**< Compare interrupt bit */
LPTIM_IT_ARRMAT = 2, /**< Update interrupt bit */
LPTIM_IT_EXTTRIG = 4, /**< external trigger interrupt bit */
typedef enum {
LPTIM_IT_CMPMAT = 1U, /**< Compare interrupt bit */
LPTIM_IT_ARRMAT = 2U, /**< Update interrupt bit */
LPTIM_IT_EXTTRIG = 4U, /**< external trigger interrupt bit */
} lptim_it_t;
/**
* @brief LPTIM Interrupt flag
*/
typedef enum
{
LPTIM_FLAG_CMPMAT = 1, /**< Compare interrupt flag */
LPTIM_FLAG_ARRMAT = 2, /**< Update interrupt flag */
LPTIM_FLAG_EXTTRIG = 4, /**< Update interrupt flag */
typedef enum {
LPTIM_FLAG_CMPMAT = 1U, /**< Compare interrupt flag */
LPTIM_FLAG_ARRMAT = 2U, /**< Update interrupt flag */
LPTIM_FLAG_EXTTRIG = 4U, /**< Update interrupt flag */
} lptim_flag_t;
/**
* @brief LPTIM state structures definition
*/
typedef enum
{
LPTIM_STATE_RESET = 0x00, /**< Peripheral not yet initialized or disabled */
LPTIM_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
LPTIM_STATE_BUSY = 0x02, /**< An internal process is ongoing */
LPTIM_STATE_TIMEOUT = 0x03, /**< Timeout state */
LPTIM_STATE_ERROR = 0x04, /**< Reception process is ongoing */
typedef enum {
LPTIM_STATE_RESET = 0x00U, /**< Peripheral not yet initialized or disabled */
LPTIM_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
LPTIM_STATE_BUSY = 0x02U, /**< An internal process is ongoing */
LPTIM_STATE_TIMEOUT = 0x03U, /**< Timeout state */
LPTIM_STATE_ERROR = 0x04U, /**< Reception process is ongoing */
} lptim_state_t;
/**
* @brief LPTIM Init Structure definition
*/
typedef struct
{
lptim_presc_t psc; /**< Specifies the prescaler value */
uint16_t arr; /**< Specifies the update value */
uint16_t cmp; /**< Specifies the compare value */
cmu_lp_perh_clock_sel_t clock; /**< Specifies the clock choose */
lptim_mode_t mode; /**< Specifies the start mode */
typedef struct {
lptim_presc_t psc; /**< Specifies the prescaler value */
uint16_t arr; /**< Specifies the update value */
uint16_t cmp; /**< Specifies the compare value */
cmu_lp_perh_clock_sel_t clock; /**< Specifies the clock choose */
lptim_mode_t mode; /**< Specifies the start mode */
} lptim_init_t;
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct
{
lptim_trigen_t mode; /**< Specifies the trigger mode */
lptim_trigsel_t sel; /**< Specifies the trigger source select */
typedef struct {
lptim_trigen_t mode; /**< Specifies the trigger mode */
lptim_trigsel_t sel; /**< Specifies the trigger source select */
} lptim_trigger_init_t;
/**
* @brief LPTIM trigger Structure definition
*/
typedef struct
{
lptim_cksel_t sel; /**< Specifies the clock select */
lptim_ckpol_t polarity; /**< Specifies the clock polarity */
typedef struct {
lptim_cksel_t sel; /**< Specifies the clock select */
lptim_ckpol_t polarity; /**< Specifies the clock polarity */
} lptim_clock_source_init_t;
/**
* @brief LPTIM Handle Structure definition
*/
typedef struct lptim_handle_s
{
LPTIM_TypeDef *perh; /**< Register base address */
lptim_init_t init; /**< LPTIM Time required parameters */
lock_state_t lock; /**< Locking object */
lptim_state_t state; /**< LPTIM operation state */
typedef struct lptim_handle_s {
LPTIM_TypeDef *perh; /**< Register base address */
lptim_init_t init; /**< LPTIM Time required parameters */
lock_state_t lock; /**< Locking object */
lptim_state_t state; /**< LPTIM operation state */
void (*trig_cbk)(struct lptim_handle_s *arg); /**< Trigger callback */
void (*update_cbk)(struct lptim_handle_s *arg); /**< Update callback */
void (*cmp_cbk)(struct lptim_handle_s *arg); /**< Compare callback */
void (*trig_cbk)(struct lptim_handle_s *arg); /**< Trigger callback */
void (*update_cbk)(struct lptim_handle_s *arg); /**< Update callback */
void (*cmp_cbk)(struct lptim_handle_s *arg); /**< Compare callback */
} lptim_handle_t;
/**
* @}
@@ -241,45 +225,45 @@ typedef struct lptim_handle_s
*/
#define IS_LPTIM(x) ((x) == LPTIM0)
#define IS_LPTIM_CKSEL(x) (((x) == LPTIM_CKSEL_INTERNAL) || \
((x) == LPTIM_CKSEL_EXTERNAL))
((x) == LPTIM_CKSEL_EXTERNAL))
#define IS_LPTIM_CKPOL(x) (((x) == LPTIM_CKPOL_RISING) || \
((x) == LPTIM_CKPOL_FALLING))
((x) == LPTIM_CKPOL_FALLING))
#define IS_LPTIM_MODE(x) (((x) == LPTIM_MODE_SINGLE) || \
((x) == LPTIM_MODE_CONTINUOUS))
((x) == LPTIM_MODE_CONTINUOUS))
#define IS_LPTIM_CKFLT(x) (((x) == LPTIM_CKFLT_0) || \
((x) == LPTIM_CKFLT_2) || \
((x) == LPTIM_CKFLT_4) || \
((x) == LPTIM_CKFLT_8))
((x) == LPTIM_CKFLT_2) || \
((x) == LPTIM_CKFLT_4) || \
((x) == LPTIM_CKFLT_8))
#define IS_LPTIM_TRGFLT(x) (((x) == LPTIM_TRGFLT_0) || \
((x) == LPTIM_TRGFLT_2) || \
((x) == LPTIM_TRGFLT_4) || \
((x) == LPTIM_TRGFLT_8))
((x) == LPTIM_TRGFLT_2) || \
((x) == LPTIM_TRGFLT_4) || \
((x) == LPTIM_TRGFLT_8))
#define IS_LPTIM_PRESC(x) (((x) == LPTIM_PRESC_1) || \
((x) == LPTIM_PRESC_2) || \
((x) == LPTIM_PRESC_4) || \
((x) == LPTIM_PRESC_8) || \
((x) == LPTIM_PRESC_16) || \
((x) == LPTIM_PRESC_32) || \
((x) == LPTIM_PRESC_64) || \
((x) == LPTIM_PRESC_128))
((x) == LPTIM_PRESC_2) || \
((x) == LPTIM_PRESC_4) || \
((x) == LPTIM_PRESC_8) || \
((x) == LPTIM_PRESC_16) || \
((x) == LPTIM_PRESC_32) || \
((x) == LPTIM_PRESC_64) || \
((x) == LPTIM_PRESC_128))
#define IS_LPTIM_TRIGSEL(x) (((x) == LPTIM_TRIGSEL_EXT0) || \
((x) == LPTIM_TRIGSEL_EXT1) || \
((x) == LPTIM_TRIGSEL_EXT2) || \
((x) == LPTIM_TRIGSEL_EXT3) || \
((x) == LPTIM_TRIGSEL_EXT4) || \
((x) == LPTIM_TRIGSEL_EXT5) || \
((x) == LPTIM_TRIGSEL_EXT6) || \
((x) == LPTIM_TRIGSEL_EXT7))
((x) == LPTIM_TRIGSEL_EXT1) || \
((x) == LPTIM_TRIGSEL_EXT2) || \
((x) == LPTIM_TRIGSEL_EXT3) || \
((x) == LPTIM_TRIGSEL_EXT4) || \
((x) == LPTIM_TRIGSEL_EXT5) || \
((x) == LPTIM_TRIGSEL_EXT6) || \
((x) == LPTIM_TRIGSEL_EXT7))
#define IS_LPTIM_TRIGEN(x) (((x) == LPTIM_TRIGEN_SW) || \
((x) == LPTIM_TRIGEN_RISING) || \
((x) == LPTIM_TRIGEN_FALLING) || \
((x) == LPTIM_TRIGEN_BOTH))
((x) == LPTIM_TRIGEN_RISING) || \
((x) == LPTIM_TRIGEN_FALLING) || \
((x) == LPTIM_TRIGEN_BOTH))
#define IS_LPTIM_IT(x) (((x) == LPTIM_IT_CMPMAT) || \
((x) == LPTIM_IT_ARRMAT) || \
((x) == LPTIM_IT_EXTTRIG))
((x) == LPTIM_IT_ARRMAT) || \
((x) == LPTIM_IT_EXTTRIG))
#define IS_LPTIM_FLAG(x) (((x) == LPTIM_FLAG_CMPMAT) || \
((x) == LPTIM_FLAG_ARRMAT) || \
((x) == LPTIM_FLAG_EXTTRIG))
((x) == LPTIM_FLAG_ARRMAT) || \
((x) == LPTIM_FLAG_EXTTRIG))
/**
* @}
*/
@@ -303,6 +287,18 @@ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt);
/** @addtogroup LPTIM_Public_Functions_Group2
* @{
*/
ald_status_t ald_lptim_base_init(lptim_handle_t *hperh);
void ald_lptim_base_start(lptim_handle_t *hperh);
void ald_lptim_base_stop(lptim_handle_t *hperh);
void ald_lptim_base_start_by_it(lptim_handle_t *hperh);
void ald_lptim_base_stop_by_it(lptim_handle_t *hperh);
/**
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group3
* @{
*/
ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh);
void ald_lptim_toggle_start(lptim_handle_t *hperh);
void ald_lptim_toggle_stop(lptim_handle_t *hperh);
@@ -312,7 +308,7 @@ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group3
/** @addtogroup LPTIM_Public_Functions_Group4
* @{
*/
ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh);
@@ -324,7 +320,7 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group4
/** @addtogroup LPTIM_Public_Functions_Group5
* @{
*/
ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh);
@@ -336,7 +332,7 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group5
/** @addtogroup LPTIM_Public_Functions_Group6
* @{
*/
void ald_lptim_irq_handler(lptim_handle_t *hperh);
@@ -348,7 +344,7 @@ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
* @}
*/
/** @addtogroup LPTIM_Public_Functions_Group6
/** @addtogroup LPTIM_Public_Functions_Group7
* @{
*/
lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh);

265
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h
View File

@@ -126,207 +126,192 @@ extern "C" {
/**
* @brief LPUART Word Length
*/
typedef enum
{
LPUART_WORD_LENGTH_5B = 0x0, /**< 5-bits */
LPUART_WORD_LENGTH_6B = 0x1, /**< 6-bits */
LPUART_WORD_LENGTH_7B = 0x2, /**< 7-bits */
LPUART_WORD_LENGTH_8B = 0x3, /**< 8-bits */
LPUART_WORD_LENGTH_9B = 0x4, /**< 9-bits */
typedef enum {
LPUART_WORD_LENGTH_5B = 0x0U, /**< 5-bits */
LPUART_WORD_LENGTH_6B = 0x1U, /**< 6-bits */
LPUART_WORD_LENGTH_7B = 0x2U, /**< 7-bits */
LPUART_WORD_LENGTH_8B = 0x3U, /**< 8-bits */
LPUART_WORD_LENGTH_9B = 0x4U, /**< 9-bits */
} lpuart_word_length_t;
/**
* @brief LPUART Stop Bits
*/
typedef enum
{
LPUART_STOP_BITS_1 = 0x0, /**< 1-bits */
LPUART_STOP_BITS_2 = 0x1, /**< 2-bits */
typedef enum {
LPUART_STOP_BITS_1 = 0x0U, /**< 1-bits */
LPUART_STOP_BITS_2 = 0x1U, /**< 2-bits */
} lpuart_stop_bits_t;
/**
* @brief LPUART Parity
*/
typedef enum
{
LPUART_PARITY_NONE = 0x0, /**< Not parity */
LPUART_PARITY_ODD = 0x1, /**< Odd parity */
LPUART_PARITY_EVEN = 0x3, /**< Even parity */
typedef enum {
LPUART_PARITY_NONE = 0x0U, /**< Not parity */
LPUART_PARITY_ODD = 0x1U, /**< Odd parity */
LPUART_PARITY_EVEN = 0x3U, /**< Even parity */
} lpuart_parity_t;
/**
* @brief LPUART Mode
*/
typedef enum
{
LPUART_MODE_UART = 0x0, /**< UART */
LPUART_MODE_IrDA = 0x2, /**< IrDA */
LPUART_MODE_RS485 = 0x3, /**< RS485 */
typedef enum {
LPUART_MODE_UART = 0x0U, /**< UART */
LPUART_MODE_IrDA = 0x2U, /**< IrDA */
LPUART_MODE_RS485 = 0x3U, /**< RS485 */
} lpuart_mode_t;
/**
* @brief LPUART Hardware Flow Control
*/
typedef enum
{
LPUART_HW_FLOW_CTL_NONE = 0x0, /**< None */
LPUART_HW_FLOW_CTL_RTS = 0x1, /**< RTS */
LPUART_HW_FLOW_CTL_CTS = 0x2, /**< CTS */
LPUART_HW_FLOW_CTL_RTS_CTS = 0x3, /**< RTS & CTS */
typedef enum {
LPUART_HW_FLOW_CTL_NONE = 0x0U, /**< None */
LPUART_HW_FLOW_CTL_RTS = 0x1U, /**< RTS */
LPUART_HW_FLOW_CTL_CTS = 0x2U, /**< CTS */
LPUART_HW_FLOW_CTL_RTS_CTS = 0x3U, /**< RTS & CTS */
} lpuart_hw_flow_ctl_t;
/**
* @brief ALD LPUART State
*/
typedef enum
{
LPUART_STATE_RESET = 0x00, /**< Peripheral is not initialized */
LPUART_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
LPUART_STATE_BUSY = 0x02, /**< an internal process is ongoing */
LPUART_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
LPUART_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
LPUART_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission Reception process is ongoing */
LPUART_STATE_TIMEOUT = 0x03, /**< Timeout state */
LPUART_STATE_ERROR = 0x04, /**< Error */
typedef enum {
LPUART_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
LPUART_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
LPUART_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
LPUART_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
LPUART_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
LPUART_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission Reception process is ongoing */
LPUART_STATE_TIMEOUT = 0x03U, /**< Timeout state */
LPUART_STATE_ERROR = 0x04U, /**< Error */
} lpuart_state_t;
/**
* @brief LPUART Error Codes
*/
typedef enum
{
LPUART_ERROR_NONE = ((uint32_t)0x00), /**< No error */
LPUART_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
LPUART_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
LPUART_ERROR_FE = ((uint32_t)0x04), /**< frame error */
LPUART_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
LPUART_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
typedef enum {
LPUART_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
LPUART_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
LPUART_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
LPUART_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
LPUART_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
LPUART_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} lpuart_error_t;
/**
* @brief LPUART Init structure definition
*/
typedef struct
{
uint32_t baud; /**< Specifies the lpuart communication baud rate */
lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
lpuart_parity_t parity; /**< Specifies the parity mode */
lpuart_mode_t mode; /**< Specifies uart mode */
lpuart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
cmu_lp_perh_clock_sel_t clock; /**< Specifies clock, only support LOSC and LRC */
typedef struct {
uint32_t baud; /**< Specifies the lpuart communication baud rate */
lpuart_word_length_t word_length; /**< Specifies the number of data bits transmitted or received in a frame */
lpuart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted */
lpuart_parity_t parity; /**< Specifies the parity mode */
lpuart_mode_t mode; /**< Specifies uart mode */
lpuart_hw_flow_ctl_t fctl; /**< Specifies wether the hardware flow control mode is enabled or disabled */
cmu_lp_perh_clock_sel_t clock; /**< Specifies clock, only support LOSC and LRC */
} lpuart_init_t;
/**
* @brief LPUART handle structure definition
*/
typedef struct lpuart_handle_s
{
LPUART_TypeDef *perh; /**< LPUART registers base address */
lpuart_init_t init; /**< LPUART communication parameters */
uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */
uint16_t tx_size; /**< LPUART Tx Transfer size */
uint16_t tx_count; /**< LPUART Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to LPUART Rx transfer Buffer */
uint16_t rx_size; /**< LPUART Rx Transfer size */
uint16_t rx_count; /**< LPUART Rx Transfer Counter */
typedef struct lpuart_handle_s {
LPUART_TypeDef *perh; /**< LPUART registers base address */
lpuart_init_t init; /**< LPUART communication parameters */
uint8_t *tx_buf; /**< Pointer to LPUART Tx transfer Buffer */
uint16_t tx_size; /**< LPUART Tx Transfer size */
uint16_t tx_count; /**< LPUART Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to LPUART Rx transfer Buffer */
uint16_t rx_size; /**< LPUART Rx Transfer size */
uint16_t rx_count; /**< LPUART Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< LPUART Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< LPUART Rx DMA Handle parameters */
dma_handle_t hdmatx; /**< LPUART Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< LPUART Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
lpuart_state_t state; /**< LPUART communication state */
lpuart_error_t err_code; /**< LPUART Error code */
lock_state_t lock; /**< Locking object */
lpuart_state_t state; /**< LPUART communication state */
lpuart_error_t err_code; /**< LPUART Error code */
void (*tx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct lpuart_handle_s *arg); /**< error callback */
void (*tx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct lpuart_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct lpuart_handle_s *arg); /**< error callback */
} lpuart_handle_t;
/**
* @brief LPUART RS485 Configure Structure definition
*/
typedef struct
{
type_func_t RS485_NMM; /**< Normal Point Mode */
type_func_t RS485_AAD; /**< Auto-Address Detect */
type_func_t RS485_AUD; /**< Auto-Direction Mode */
type_func_t RS485_ADD_DET; /**< Eable/Disable Address Detect */
uint8_t RS485_ADDCMP; /**< Address for compare */
typedef struct {
type_func_t RS485_NMM; /**< Normal Point Mode */
type_func_t RS485_AAD; /**< Auto-Address Detect */
type_func_t RS485_AUD; /**< Auto-Direction Mode */
type_func_t RS485_ADD_DET; /**< Eable/Disable Address Detect */
uint8_t RS485_ADDCMP; /**< Address for compare */
} lpuart_rs485_config_t;
/**
* @brief LPUART DMA Requests
*/
typedef enum
{
LPUART_DMA_REQ_TX = 0x0, /**< TX dma */
LPUART_DMA_REQ_RX = 0x1, /**< RX dma */
typedef enum {
LPUART_DMA_REQ_TX = 0x0U, /**< TX dma */
LPUART_DMA_REQ_RX = 0x1U, /**< RX dma */
} lpuart_dma_req_t;
/**
* @brief LPUART RXFIFO size
*/
typedef enum
{
LPUART_RXFIFO_1BYTE = 0x0, /**< 1-Byte */
LPUART_RXFIFO_4BYTE = 0x1, /**< 4-Bytes */
LPUART_RXFIFO_8BYTE = 0x2, /**< 8-Bytes */
LPUART_RXFIFO_14BYTE = 0x3, /**< 14-Bytes */
typedef enum {
LPUART_RXFIFO_1BYTE = 0x0U, /**< 1-Byte */
LPUART_RXFIFO_4BYTE = 0x1U, /**< 4-Bytes */
LPUART_RXFIFO_8BYTE = 0x2U, /**< 8-Bytes */
LPUART_RXFIFO_14BYTE = 0x3U, /**< 14-Bytes */
} lpuart_rxfifo_t;
/**
* @brief LPUART Interrupts Types
*/
typedef enum
{
LPUART_IT_RBR = (1U << 0), /**< RBR */
LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IT_RXTO = (1U << 3), /**< RXTO */
LPUART_IT_RXOV = (1U << 4), /**< RXOV */
LPUART_IT_TXOV = (1U << 5), /**< TXOV */
LPUART_IT_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IT_DATWK = (1U << 8), /**< DATWK */
LPUART_IT_PERR = (1U << 9), /**< PERR */
LPUART_IT_FERR = (1U << 10), /**< FERR */
LPUART_IT_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IT_ADET = (1U << 12), /**< ADET */
LPUART_IT_TC = (1U << 15), /**< TC */
typedef enum {
LPUART_IT_RBR = (1U << 0), /**< RBR */
LPUART_IT_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IT_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IT_RXTO = (1U << 3), /**< RXTO */
LPUART_IT_RXOV = (1U << 4), /**< RXOV */
LPUART_IT_TXOV = (1U << 5), /**< TXOV */
LPUART_IT_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IT_DATWK = (1U << 8), /**< DATWK */
LPUART_IT_PERR = (1U << 9), /**< PERR */
LPUART_IT_FERR = (1U << 10), /**< FERR */
LPUART_IT_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IT_ADET = (1U << 12), /**< ADET */
LPUART_IT_TC = (1U << 15), /**< TC */
} lpuart_it_t;
/**
* @brief LPUART Flags Types
*/
typedef enum
{
LPUART_IF_RBR = (1U << 0), /**< RBR */
LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IF_RXTO = (1U << 3), /**< RXTO */
LPUART_IF_RXOV = (1U << 4), /**< RXOV */
LPUART_IF_TXOV = (1U << 5), /**< TXOV */
LPUART_IF_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IF_DATWK = (1U << 8), /**< DATWK */
LPUART_IF_PERR = (1U << 9), /**< PERR */
LPUART_IF_FERR = (1U << 10), /**< FERR */
LPUART_IF_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IF_ADET = (1U << 12), /**< ADET */
LPUART_IF_TC = (1U << 15), /**< TC */
typedef enum {
LPUART_IF_RBR = (1U << 0), /**< RBR */
LPUART_IF_TBEMP = (1U << 1), /**< TBEMP */
LPUART_IF_CTSDET = (1U << 2), /**< CTSDET */
LPUART_IF_RXTO = (1U << 3), /**< RXTO */
LPUART_IF_RXOV = (1U << 4), /**< RXOV */
LPUART_IF_TXOV = (1U << 5), /**< TXOV */
LPUART_IF_CTSWK = (1U << 7), /**< CTSWK */
LPUART_IF_DATWK = (1U << 8), /**< DATWK */
LPUART_IF_PERR = (1U << 9), /**< PERR */
LPUART_IF_FERR = (1U << 10), /**< FERR */
LPUART_IF_BRKERR = (1U << 11), /**< BRKERR */
LPUART_IF_ADET = (1U << 12), /**< ADET */
LPUART_IF_TC = (1U << 15), /**< TC */
} lpuart_flag_t;
/**
* @brief LPUART Status Types
*/
typedef enum
{
LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */
LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */
LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */
LPUART_STAT_TXFULL = (1U << 15), /**< TX FIFO full */
LPUART_STAT_TXIDLE = (1U << 16), /**< TX idle */
LPUART_STAT_CTSSTAT = (1U << 17), /**< CTS status */
LPUART_STAT_RTSSTAT = (1U << 18), /**< RTS status */
typedef enum {
LPUART_STAT_RXEMP = (1U << 6), /**< RX FIFO empty */
LPUART_STAT_RXFULL = (1U << 7), /**< RX FIFO full */
LPUART_STAT_TXEMP = (1U << 14), /**< TX FIFO empty */
LPUART_STAT_TXFULL = (1U << 15), /**< TX FIFO full */
LPUART_STAT_TXIDLE = (1U << 16), /**< TX idle */
LPUART_STAT_CTSSTAT = (1U << 17), /**< CTS status */
LPUART_STAT_RTSSTAT = (1U << 18), /**< RTS status */
} lpuart_status_t;
/**
* @}
@@ -352,10 +337,10 @@ typedef enum
((x) == LPUART_MODE_IrDA) || \
((x) == LPUART_MODE_RS485))
#define IS_LPUART_HARDWARE_FLOW_CONTROL(x)\
(((x) == LPUART_HW_FLOW_CTL_NONE) || \
((x) == LPUART_HW_FLOW_CTL_RTS) || \
((x) == LPUART_HW_FLOW_CTL_CTS) || \
((x) == LPUART_HW_FLOW_CTL_RTS_CTS))
(((x) == LPUART_HW_FLOW_CTL_NONE) || \
((x) == LPUART_HW_FLOW_CTL_RTS) || \
((x) == LPUART_HW_FLOW_CTL_CTS) || \
((x) == LPUART_HW_FLOW_CTL_RTS_CTS))
#define IS_LPUART_DMAREQ(x) (((x) == LPUART_DMA_REQ_TX) || ((x) == LPUART_DMA_REQ_RX))
#define IS_LPUART_RXFIFO(x) (((x) == LPUART_RXFIFO_1BYTE) || \
((x) == LPUART_RXFIFO_4BYTE) || \
@@ -388,15 +373,15 @@ typedef enum
((x) == LPUART_IF_ADET) || \
((x) == LPUART_IF_TC))
#define IS_LPUART_STAT(x) (((x) == LPUART_STAT_RXEMP) || \
((x) == LPUART_STAT_RXFULL) || \
((x) == LPUART_STAT_TXEMP) || \
((x) == LPUART_STAT_TXFULL) || \
((x) == LPUART_STAT_TXIDLE) || \
((x) == LPUART_STAT_CTSSTAT) || \
((x) == LPUART_STAT_RTSSTAT))
((x) == LPUART_STAT_RXFULL) || \
((x) == LPUART_STAT_TXEMP) || \
((x) == LPUART_STAT_TXFULL) || \
((x) == LPUART_STAT_TXIDLE) || \
((x) == LPUART_STAT_CTSSTAT) || \
((x) == LPUART_STAT_RTSSTAT))
#define LPUART_STATE_TX_MASK (1 << 4)
#define LPUART_STATE_RX_MASK (1 << 5)
#define LPUART_STATE_TX_MASK (1U << 4)
#define LPUART_STATE_RX_MASK (1U << 5)
/**
* @}
*/

895
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h
View File

File diff suppressed because it is too large Load Diff

214
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h
View File

@@ -23,6 +23,7 @@ extern "C" {
#include "utils.h"
#include "ald_syscfg.h"
#include "ald_bkpc.h"
/** @addtogroup ES32FXXX_ALD
@@ -37,66 +38,66 @@ extern "C" {
* @{
*/
#define PMU_SRAM0_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM0_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE)); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_SRAM1_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_BXCAN_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_LPSTOP_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_LPSTOP_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_MTSTOP_ENABLE() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_MTSTOP_DISABLE() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
/**
@@ -110,57 +111,54 @@ extern "C" {
/**
* @brief Low power mode
*/
typedef enum
{
PMU_LP_STOP1 = 0x0, /**< Stop1 */
PMU_LP_STOP2 = 0x1, /**< Stop2 */
typedef enum {
PMU_LP_STOP1 = 0x0U, /**< Stop1 */
PMU_LP_STOP2 = 0x1U, /**< Stop2 */
PMU_LP_STANDBY = 0x2U, /**< Standby */
} pmu_lp_mode_t;
typedef enum
{
PMU_SR_WUF = (1U << 0),
typedef enum {
PMU_SR_WUF = (1U << 0),
PMU_SR_STANDBY = (1U << 1),
} pmu_status_t;
/**
* @brief LVD voltage select
*/
typedef enum
{
PMU_LVD_VOL_SEL_2_0 = 0x0, /**< 2.0V ~ 2.05V */
PMU_LVD_VOL_SEL_2_1 = 0x1, /**< 2.1V ~ 2.15V */
PMU_LVD_VOL_SEL_2_2 = 0x2, /**< 2.2V ~ 2.25V */
PMU_LVD_VOL_SEL_2_4 = 0x3, /**< 2.4V ~ 2.45V */
PMU_LVD_VOL_SEL_2_6 = 0x4, /**< 2.6V ~ 2.65V */
PMU_LVD_VOL_SEL_2_8 = 0x5, /**< 2.8V ~ 2.85V */
PMU_LVD_VOL_SEL_3_0 = 0x6, /**< 3.0V ~ 3.05V */
PMU_LVD_VOL_SEL_3_6 = 0x7, /**< 3.6V ~ 3.65V */
PMU_LVD_VOL_SEL_4_0 = 0x8, /**< 4.0V ~ 4.05V */
PMU_LVD_VOL_SEL_4_6 = 0x9, /**< 4.6V ~ 4.65V */
PMU_LVD_VOL_SEL_2_3 = 0xA, /**< 2.3V ~ 2.35V */
PMU_LVD_VOL_SEL_EXT = 0xF, /**< Select external input. It must be 1.2V */
typedef enum {
PMU_LVD_VOL_SEL_2_0 = 0x0U, /**< 2.0V ~ 2.05V */
PMU_LVD_VOL_SEL_2_1 = 0x1U, /**< 2.1V ~ 2.15V */
PMU_LVD_VOL_SEL_2_2 = 0x2U, /**< 2.2V ~ 2.25V */
PMU_LVD_VOL_SEL_2_4 = 0x3U, /**< 2.4V ~ 2.45V */
PMU_LVD_VOL_SEL_2_6 = 0x4U, /**< 2.6V ~ 2.65V */
PMU_LVD_VOL_SEL_2_8 = 0x5U, /**< 2.8V ~ 2.85V */
PMU_LVD_VOL_SEL_3_0 = 0x6U, /**< 3.0V ~ 3.05V */
PMU_LVD_VOL_SEL_3_6 = 0x7U, /**< 3.6V ~ 3.65V */
PMU_LVD_VOL_SEL_4_0 = 0x8U, /**< 4.0V ~ 4.05V */
PMU_LVD_VOL_SEL_4_6 = 0x9U, /**< 4.6V ~ 4.65V */
PMU_LVD_VOL_SEL_2_3 = 0xAU, /**< 2.3V ~ 2.35V */
PMU_LVD_VOL_SEL_EXT = 0xFU, /**< Select external input. It must be 1.2V */
} pmu_lvd_voltage_sel_t;
/**
* @brief LVD trigger mode
*/
typedef enum
{
PMU_LVD_TRIGGER_RISING_EDGE = 0x0, /**< Rising edge */
PMU_LVD_TRIGGER_FALLING_EDGE = 0x1, /**< Falling edge */
PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2, /**< High level */
PMU_LVD_TRIGGER_LOW_LEVEL = 0x3, /**< Low level */
PMU_LVD_TRIGGER_RISING_FALLING = 0x4, /**< Rising and falling edge */
typedef enum {
PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, /**< Rising edge */
PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, /**< Falling edge */
PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, /**< High level */
PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U, /**< Low level */
PMU_LVD_TRIGGER_RISING_FALLING = 0x4U, /**< Rising and falling edge */
} pmu_lvd_trigger_mode_t;
/**
* @brief LDO output voltage selest in low power mode
*/
typedef enum
{
PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0, /**< 1.5V */
PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1, /**< 1.4V */
PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2, /**< 1.3V */
PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4, /**< 1.2V */
typedef enum {
PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0U, /**< 1.5V */
PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1U, /**< 1.4V */
PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2U, /**< 1.3V */
PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4U, /**< 1.2V */
} pmu_ldo_lpmode_output_t;
/**
* @}
@@ -171,29 +169,30 @@ typedef enum
* @{
*/
#define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
((x) == PMU_LP_STOP2))
#define IS_PMU_STATUS(x) ((x) == PMU_SR_WUF)
((x) == PMU_LP_STOP2) || \
((x) == PMU_LP_STANDBY))
#define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || ((x) == PMU_SR_STANDBY))
#define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_0) || \
((x) == PMU_LVD_VOL_SEL_2_1) || \
((x) == PMU_LVD_VOL_SEL_2_2) || \
((x) == PMU_LVD_VOL_SEL_2_4) || \
((x) == PMU_LVD_VOL_SEL_2_6) || \
((x) == PMU_LVD_VOL_SEL_2_8) || \
((x) == PMU_LVD_VOL_SEL_3_0) || \
((x) == PMU_LVD_VOL_SEL_3_6) || \
((x) == PMU_LVD_VOL_SEL_4_0) || \
((x) == PMU_LVD_VOL_SEL_4_6) || \
((x) == PMU_LVD_VOL_SEL_2_3) || \
((x) == PMU_LVD_VOL_SEL_EXT))
((x) == PMU_LVD_VOL_SEL_2_1) || \
((x) == PMU_LVD_VOL_SEL_2_2) || \
((x) == PMU_LVD_VOL_SEL_2_4) || \
((x) == PMU_LVD_VOL_SEL_2_6) || \
((x) == PMU_LVD_VOL_SEL_2_8) || \
((x) == PMU_LVD_VOL_SEL_3_0) || \
((x) == PMU_LVD_VOL_SEL_3_6) || \
((x) == PMU_LVD_VOL_SEL_4_0) || \
((x) == PMU_LVD_VOL_SEL_4_6) || \
((x) == PMU_LVD_VOL_SEL_2_3) || \
((x) == PMU_LVD_VOL_SEL_EXT))
#define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
((x) == PMU_LVD_TRIGGER_RISING_FALLING))
((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
((x) == PMU_LVD_TRIGGER_RISING_FALLING))
#define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_1_5) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
/**
* @}
*/
@@ -207,17 +206,18 @@ typedef enum
/* Low power mode select */
__STATIC_INLINE__ void ald_pmu_sleep()
{
__WFI();
__WFI();
}
__STATIC_INLINE__ void ald_pmu_sleep_deep()
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__WFI();
}
void ald_pmu_stop1_enter(void);
void ald_pmu_stop2_enter(void);
void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
flag_status_t ald_pmu_get_status(pmu_status_t sr);
void ald_pmu_clear_status(pmu_status_t sr);

369
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h
View File

@@ -37,127 +37,128 @@ extern "C" {
/**
* @brief RMU BOR fliter
*/
typedef enum
{
RMU_BORFLT_1 = 0x1, /**< 1 cycle */
RMU_BORFLT_2 = 0x2, /**< 2 cycles */
RMU_BORFLT_3 = 0x3, /**< 3 cycles */
RMU_BORFLT_4 = 0x4, /**< 4 cycles */
RMU_BORFLT_5 = 0x5, /**< 5 cycles */
RMU_BORFLT_6 = 0x6, /**< 6 cycles */
RMU_BORFLT_7 = 0x7, /**< 7 cycles */
typedef enum {
RMU_BORFLT_1 = 0x1U, /**< 1 cycle */
RMU_BORFLT_2 = 0x2U, /**< 2 cycles */
RMU_BORFLT_3 = 0x3U, /**< 3 cycles */
RMU_BORFLT_4 = 0x4U, /**< 4 cycles */
RMU_BORFLT_5 = 0x5U, /**< 5 cycles */
RMU_BORFLT_6 = 0x6U, /**< 6 cycles */
RMU_BORFLT_7 = 0x7U, /**< 7 cycles */
} rmu_bor_filter_t;
/**
* @brief RMU BOR voltage
*/
typedef enum
{
RMU_VOL_1_7 = 0x0, /**< 1.7V */
RMU_VOL_2_0 = 0x1, /**< 2.0V */
RMU_VOL_2_1 = 0x2, /**< 2.1V */
RMU_VOL_2_2 = 0x3, /**< 2.2V */
RMU_VOL_2_3 = 0x4, /**< 2.3V */
RMU_VOL_2_4 = 0x5, /**< 2.4V */
RMU_VOL_2_5 = 0x6, /**< 2.5V */
RMU_VOL_2_6 = 0x7, /**< 2.6V */
RMU_VOL_2_8 = 0x8, /**< 2.8V */
RMU_VOL_3_0 = 0x9, /**< 3.0V */
RMU_VOL_3_1 = 0xA, /**< 3.1V */
RMU_VOL_3_3 = 0xB, /**< 3.3V */
RMU_VOL_3_6 = 0xC, /**< 3.6V */
RMU_VOL_3_7 = 0xD, /**< 3.7V */
RMU_VOL_4_0 = 0xE, /**< 4.0V */
RMU_VOL_4_3 = 0xF, /**< 4.3V */
typedef enum {
RMU_VOL_1_8 = 0x0U, /**< 1.8V */
RMU_VOL_2_0 = 0x1U, /**< 2.0V */
RMU_VOL_2_2 = 0x2U, /**< 2.2V */
RMU_VOL_2_4 = 0x3U, /**< 2.4V */
RMU_VOL_2_6 = 0x4U, /**< 2.6V */
RMU_VOL_2_8 = 0x5U, /**< 2.8V */
RMU_VOL_3_0 = 0x6U, /**< 3.0V */
RMU_VOL_3_2 = 0x7U, /**< 3.2V */
RMU_VOL_3_4 = 0x8U, /**< 3.4V */
RMU_VOL_3_6 = 0x9U, /**< 3.6V */
RMU_VOL_3_8 = 0xAU, /**< 3.8V */
RMU_VOL_4_0 = 0xBU, /**< 4.0V */
RMU_VOL_4_2 = 0xCU, /**< 4.2V */
RMU_VOL_4_4 = 0xDU, /**< 4.4V */
RMU_VOL_4_6 = 0xEU, /**< 4.6V */
RMU_VOL_4_8 = 0xFU, /**< 4.8V */
} rmu_bor_vol_t;
/**
* @brief RMU reset status
*/
typedef enum
{
RMU_RST_POR = (1U << 0), /**< POR */
RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */
RMU_RST_BOR = (1U << 2), /**< BOR */
RMU_RST_NMRST = (1U << 3), /**< NMRST */
RMU_RST_IWDT = (1U << 4), /**< IWDT */
RMU_RST_WWDT = (1U << 5), /**< WWDT */
RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */
RMU_RST_CHIP = (1U << 7), /**< CHIP */
RMU_RST_MCU = (1U << 8), /**< MCU */
RMU_RST_CPU = (1U << 9), /**< CPU */
RMU_RST_CFG = (1U << 10), /**< CFG */
RMU_RST_CFGERR = (1U << 16), /**< CFG Error */
typedef enum {
RMU_RST_POR = (1U << 0), /**< POR */
RMU_RST_WAKEUP = (1U << 1), /**< WAKEUP */
RMU_RST_BOR = (1U << 2), /**< BOR */
RMU_RST_NMRST = (1U << 3), /**< NMRST */
RMU_RST_IWDT = (1U << 4), /**< IWDT */
RMU_RST_WWDT = (1U << 5), /**< WWDT */
RMU_RST_LOCKUP = (1U << 6), /**< LOCKUP */
RMU_RST_CHIP = (1U << 7), /**< CHIP */
RMU_RST_MCU = (1U << 8), /**< MCU */
RMU_RST_CPU = (1U << 9), /**< CPU */
RMU_RST_CFG = (1U << 10), /**< CFG */
RMU_RST_CFGERR = (1U << 16), /**< CFG Error */
RMU_RST_ALL = (0xFFFFFU), /**< ALL */
} rmu_state_t;
/**
* @brief RMU periperal select bit
* @note ES32F065x:
* AD16C4T0--TIMER0
* GP16C4T0--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
*
* ES32F033x:
* ES32F093x:
* GP16C4T0--TIMER0
* GP16C4T1--TIMER6
* GP16C2T0--TIMER2
* GP16C2T1--TIMER3
* BS16T0----TIMER1
* BS16T1----TIMER4
* BS16T2----TIMER5
* BS16T3----TIMER7
* @verbatim
In this module, for the convenience of code maintenance,
TIMERx is used to indicate the sequence of the timer peripheral.
Different product series TIMERx represent different meanings:
1. For ES32F065x series:
TIMER0 ----> AD16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T0
TIMER7 ----> BS16T3
2. For ES32F033x/ES32F093x series:
TIMER0 ----> GP16C4T0
TIMER1 ----> BS16T0
TIMER2 ----> GP16C2T0
TIMER3 ----> GP16C2T1
TIMER4 ----> BS16T1
TIMER5 ----> BS16T2
TIMER6 ----> GP16C4T1
TIMER7 ----> BS16T3
@endverbatim
*/
typedef enum
{
RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */
RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */
RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */
RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */
RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */
RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */
RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */
RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */
RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */
RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */
RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */
RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */
RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */
RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */
RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */
RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */
RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */
RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */
RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */
RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */
RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */
RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */
RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */
RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */
RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */
RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */
RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */
RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */
RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */
RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */
RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */
RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */
RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */
RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */
RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */
RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */
RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */
RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */
RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */
RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */
RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */
RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */
RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */
typedef enum {
RMU_PERH_GPIO = (1U << 0), /**< AHB1: GPIO */
RMU_PERH_CRC = (1U << 1), /**< AHB1: CRC */
RMU_PERH_CALC = (1U << 2), /**< AHB1: CALC */
RMU_PERH_CRYPT = (1U << 3), /**< AHB1: CRYPT */
RMU_PERH_TRNG = (1U << 4), /**< AHB1: TRNG */
RMU_PERH_PIS = (1U << 5), /**< AHB1: PIS */
RMU_PERH_CHIP = (1U << 0) | (1U << 27), /**< AHB2: CHIP */
RMU_PERH_CPU = (1U << 1) | (1U << 27), /**< AHB2: CPU */
RMU_PERH_TIMER0 = (1U << 0) | (1U << 28), /**< APB1: TIMER0 */
RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), /**< APB1: TIMER1 */
RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), /**< APB1: TIMER2 */
RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), /**< APB1: TIMER3 */
RMU_PERH_TIMER4 = (1U << 4) | (1U << 28), /**< APB1: TIMER4 */
RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), /**< APB1: TIMER5 */
RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), /**< APB1: TIMER6 */
RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), /**< APB1: TIMER7 */
RMU_PERH_UART0 = (1U << 8) | (1U << 28), /**< APB1: UART0 */
RMU_PERH_UART1 = (1U << 9) | (1U << 28), /**< APB1: UART1 */
RMU_PERH_UART2 = (1U << 10) | (1U << 28), /**< APB1: UART2 */
RMU_PERH_UART3 = (1U << 11) | (1U << 28), /**< APB1: UART3 */
RMU_PERH_USART0 = (1U << 12) | (1U << 28), /**< APB1: EUART0 */
RMU_PERH_USART1 = (1U << 13) | (1U << 28), /**< APB1: EUART1 */
RMU_PERH_SPI0 = (1U << 16) | (1U << 28), /**< APB1: SPI0 */
RMU_PERH_SPI1 = (1U << 17) | (1U << 28), /**< APB1: SPI1 */
RMU_PERH_SPI2 = (1U << 18) | (1U << 28), /**< APB1: SPI2 */
RMU_PERH_I2C0 = (1U << 20) | (1U << 28), /**< APB1: I2C0 */
RMU_PERH_I2C1 = (1U << 21) | (1U << 28), /**< APB1: I2C1 */
RMU_PERH_CAN0 = (1U << 24) | (1U << 28), /**< APB1: CAN0 */
RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), /**< APB2: LPTIM0 */
RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), /**< APB2: LPUART */
RMU_PERH_ADC0 = (1U << 4) | (1U << 29), /**< APB2: ADC0 */
RMU_PERH_ADC1 = (1U << 5) | (1U << 29), /**< APB2: ADC1 */
RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), /**< APB2: ACMP0 */
RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), /**< APB2: ACMP1 */
RMU_PERH_OPAMP = (1U << 8) | (1U << 29), /**< APB2: OPAMP */
RMU_PERH_DAC0 = (1U << 9) | (1U << 29), /**< APB2: DAC0 */
RMU_PERH_WWDT = (1U << 12) | (1U << 29), /**< APB2: WWDT */
RMU_PERH_LCD = (1U << 13) | (1U << 29), /**< APB2: LCD */
RMU_PERH_IWDT = (1U << 14) | (1U << 29), /**< APB2: IWDT */
RMU_PERH_RTC = (1U << 15) | (1U << 29), /**< APB2: RTC */
RMU_PERH_TSENSE = (1U << 16) | (1U << 29), /**< APB2: TSENSE */
RMU_PERH_BKPC = (1U << 17) | (1U << 29), /**< APB2: BKPC */
RMU_PERH_BKPRAM = (1U << 18) | (1U << 29), /**< APB2: BKPRAM */
} rmu_peripheral_t;
/**
* @}
@@ -168,40 +169,41 @@ typedef enum
* @{
*/
#define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \
((x) == RMU_BORFLT_2) || \
((x) == RMU_BORFLT_3) || \
((x) == RMU_BORFLT_4) || \
((x) == RMU_BORFLT_5) || \
((x) == RMU_BORFLT_6) || \
((x) == RMU_BORFLT_7))
#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_7) || \
((x) == RMU_VOL_2_0) || \
((x) == RMU_VOL_2_1) || \
((x) == RMU_VOL_2_2) || \
((x) == RMU_VOL_2_3) || \
((x) == RMU_VOL_2_4) || \
((x) == RMU_VOL_2_5) || \
((x) == RMU_VOL_2_6) || \
((x) == RMU_VOL_2_8) || \
((x) == RMU_VOL_3_0) || \
((x) == RMU_VOL_3_1) || \
((x) == RMU_VOL_3_3) || \
((x) == RMU_VOL_3_6) || \
((x) == RMU_VOL_3_7) || \
((x) == RMU_VOL_4_0) || \
((x) == RMU_VOL_4_3))
((x) == RMU_BORFLT_2) || \
((x) == RMU_BORFLT_3) || \
((x) == RMU_BORFLT_4) || \
((x) == RMU_BORFLT_5) || \
((x) == RMU_BORFLT_6) || \
((x) == RMU_BORFLT_7))
#define IS_RMU_BORVOL(x) (((x) == RMU_VOL_1_8) || \
((x) == RMU_VOL_2_0) || \
((x) == RMU_VOL_2_2) || \
((x) == RMU_VOL_2_4) || \
((x) == RMU_VOL_2_6) || \
((x) == RMU_VOL_2_8) || \
((x) == RMU_VOL_3_0) || \
((x) == RMU_VOL_3_2) || \
((x) == RMU_VOL_3_4) || \
((x) == RMU_VOL_3_6) || \
((x) == RMU_VOL_3_8) || \
((x) == RMU_VOL_4_0) || \
((x) == RMU_VOL_4_2) || \
((x) == RMU_VOL_4_4) || \
((x) == RMU_VOL_4_6) || \
((x) == RMU_VOL_4_8))
#define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_CFGERR))
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_CFGERR) || \
((x) == RMU_RST_ALL))
#define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
@@ -212,50 +214,51 @@ typedef enum
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG))
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_ALL))
#define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \
((x) == RMU_PERH_CRC) || \
((x) == RMU_PERH_CALC) || \
((x) == RMU_PERH_CRYPT) || \
((x) == RMU_PERH_TRNG) || \
((x) == RMU_PERH_PIS) || \
((x) == RMU_PERH_CHIP) || \
((x) == RMU_PERH_CPU) || \
((x) == RMU_PERH_TIMER0) || \
((x) == RMU_PERH_TIMER1) || \
((x) == RMU_PERH_TIMER2) || \
((x) == RMU_PERH_TIMER3) || \
((x) == RMU_PERH_TIMER4) || \
((x) == RMU_PERH_TIMER5) || \
((x) == RMU_PERH_TIMER6) || \
((x) == RMU_PERH_TIMER7) || \
((x) == RMU_PERH_UART0) || \
((x) == RMU_PERH_UART1) || \
((x) == RMU_PERH_UART2) || \
((x) == RMU_PERH_UART3) || \
((x) == RMU_PERH_USART0) || \
((x) == RMU_PERH_USART1) || \
((x) == RMU_PERH_SPI0) || \
((x) == RMU_PERH_SPI1) || \
((x) == RMU_PERH_SPI2) || \
((x) == RMU_PERH_I2C0) || \
((x) == RMU_PERH_I2C1) || \
((x) == RMU_PERH_CAN0) || \
((x) == RMU_PERH_LPTIM0) || \
((x) == RMU_PERH_LPUART0) || \
((x) == RMU_PERH_ADC0) || \
((x) == RMU_PERH_ADC1) || \
((x) == RMU_PERH_ACMP0) || \
((x) == RMU_PERH_ACMP1) || \
((x) == RMU_PERH_OPAMP) || \
((x) == RMU_PERH_DAC0) || \
((x) == RMU_PERH_WWDT) || \
((x) == RMU_PERH_LCD) || \
((x) == RMU_PERH_IWDT) || \
((x) == RMU_PERH_RTC) || \
((x) == RMU_PERH_TSENSE) || \
((x) == RMU_PERH_BKPC) || \
((x) == RMU_PERH_BKPRAM))
((x) == RMU_PERH_CRC) || \
((x) == RMU_PERH_CALC) || \
((x) == RMU_PERH_CRYPT) || \
((x) == RMU_PERH_TRNG) || \
((x) == RMU_PERH_PIS) || \
((x) == RMU_PERH_CHIP) || \
((x) == RMU_PERH_CPU) || \
((x) == RMU_PERH_TIMER0) || \
((x) == RMU_PERH_TIMER1) || \
((x) == RMU_PERH_TIMER2) || \
((x) == RMU_PERH_TIMER3) || \
((x) == RMU_PERH_TIMER4) || \
((x) == RMU_PERH_TIMER5) || \
((x) == RMU_PERH_TIMER6) || \
((x) == RMU_PERH_TIMER7) || \
((x) == RMU_PERH_UART0) || \
((x) == RMU_PERH_UART1) || \
((x) == RMU_PERH_UART2) || \
((x) == RMU_PERH_UART3) || \
((x) == RMU_PERH_USART0) || \
((x) == RMU_PERH_USART1) || \
((x) == RMU_PERH_SPI0) || \
((x) == RMU_PERH_SPI1) || \
((x) == RMU_PERH_SPI2) || \
((x) == RMU_PERH_I2C0) || \
((x) == RMU_PERH_I2C1) || \
((x) == RMU_PERH_CAN0) || \
((x) == RMU_PERH_LPTIM0) || \
((x) == RMU_PERH_LPUART0) || \
((x) == RMU_PERH_ADC0) || \
((x) == RMU_PERH_ADC1) || \
((x) == RMU_PERH_ACMP0) || \
((x) == RMU_PERH_ACMP1) || \
((x) == RMU_PERH_OPAMP) || \
((x) == RMU_PERH_DAC0) || \
((x) == RMU_PERH_WWDT) || \
((x) == RMU_PERH_LCD) || \
((x) == RMU_PERH_IWDT) || \
((x) == RMU_PERH_RTC) || \
((x) == RMU_PERH_TSENSE) || \
((x) == RMU_PERH_BKPC) || \
((x) == RMU_PERH_BKPRAM))
/**
* @}
*/
@@ -264,7 +267,7 @@ typedef enum
* @{
*/
void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
flag_status_t ald_rmu_get_reset_status(rmu_state_t state);
uint32_t ald_rmu_get_reset_status(rmu_state_t state);
void ald_rmu_clear_reset_status(rmu_state_t state);
void ald_rmu_reset_periperal(rmu_peripheral_t perh);
/**

616
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h
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File diff suppressed because it is too large Load Diff

163
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h
View File

@@ -18,7 +18,7 @@
#define __ALD_SMARTCARD_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -41,52 +41,50 @@ extern "C" {
/**
* @brief SMARTCARD error codes
*/
typedef enum
{
SMARTCARD_ERROR_NONE = ((uint32_t)0x00), /**< No error */
SMARTCARD_ERROR_PE = ((uint32_t)0x01), /**< Parity error */
SMARTCARD_ERROR_NE = ((uint32_t)0x02), /**< Noise error */
SMARTCARD_ERROR_FE = ((uint32_t)0x04), /**< frame error */
SMARTCARD_ERROR_ORE = ((uint32_t)0x08), /**< Overrun error */
SMARTCARD_ERROR_DMA = ((uint32_t)0x10), /**< DMA transfer error */
typedef enum {
SMARTCARD_ERROR_NONE = ((uint32_t)0x00U), /**< No error */
SMARTCARD_ERROR_PE = ((uint32_t)0x01U), /**< Parity error */
SMARTCARD_ERROR_NE = ((uint32_t)0x02U), /**< Noise error */
SMARTCARD_ERROR_FE = ((uint32_t)0x04U), /**< frame error */
SMARTCARD_ERROR_ORE = ((uint32_t)0x08U), /**< Overrun error */
SMARTCARD_ERROR_DMA = ((uint32_t)0x10U), /**< DMA transfer error */
} smartcard_error_t;
/**
* @brief SMARTCARD Prescaler
*/
typedef enum
{
SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1), /**< SYSCLK divided by 2 */
SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2), /**< SYSCLK divided by 4 */
SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3), /**< SYSCLK divided by 6 */
SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4), /**< SYSCLK divided by 8 */
SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5), /**< SYSCLK divided by 10 */
SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6), /**< SYSCLK divided by 12 */
SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7), /**< SYSCLK divided by 14 */
SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8), /**< SYSCLK divided by 16 */
SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9), /**< SYSCLK divided by 18 */
SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA), /**< SYSCLK divided by 20 */
SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB), /**< SYSCLK divided by 22 */
SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC), /**< SYSCLK divided by 24 */
SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD), /**< SYSCLK divided by 26 */
SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE), /**< SYSCLK divided by 28 */
SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF), /**< SYSCLK divided by 30 */
SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10), /**< SYSCLK divided by 32 */
SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11), /**< SYSCLK divided by 34 */
SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12), /**< SYSCLK divided by 36 */
SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13), /**< SYSCLK divided by 38 */
SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14), /**< SYSCLK divided by 40 */
SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15), /**< SYSCLK divided by 42 */
SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16), /**< SYSCLK divided by 44 */
SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17), /**< SYSCLK divided by 46 */
SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18), /**< SYSCLK divided by 48 */
SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19), /**< SYSCLK divided by 50 */
SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A), /**< SYSCLK divided by 52 */
SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B), /**< SYSCLK divided by 54 */
SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C), /**< SYSCLK divided by 56 */
SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D), /**< SYSCLK divided by 58 */
SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E), /**< SYSCLK divided by 60 */
SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F), /**< SYSCLK divided by 62 */
typedef enum {
SMARTCARD_PRESCALER_SYSCLK_DIV2 = ((uint32_t)0x1U), /**< SYSCLK divided by 2 */
SMARTCARD_PRESCALER_SYSCLK_DIV4 = ((uint32_t)0x2U), /**< SYSCLK divided by 4 */
SMARTCARD_PRESCALER_SYSCLK_DIV6 = ((uint32_t)0x3U), /**< SYSCLK divided by 6 */
SMARTCARD_PRESCALER_SYSCLK_DIV8 = ((uint32_t)0x4U), /**< SYSCLK divided by 8 */
SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5U), /**< SYSCLK divided by 10 */
SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6U), /**< SYSCLK divided by 12 */
SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7U), /**< SYSCLK divided by 14 */
SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8U), /**< SYSCLK divided by 16 */
SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9U), /**< SYSCLK divided by 18 */
SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xAU), /**< SYSCLK divided by 20 */
SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xBU), /**< SYSCLK divided by 22 */
SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xCU), /**< SYSCLK divided by 24 */
SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xDU), /**< SYSCLK divided by 26 */
SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xEU), /**< SYSCLK divided by 28 */
SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xFU), /**< SYSCLK divided by 30 */
SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10U), /**< SYSCLK divided by 32 */
SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11U), /**< SYSCLK divided by 34 */
SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12U), /**< SYSCLK divided by 36 */
SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13U), /**< SYSCLK divided by 38 */
SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14U), /**< SYSCLK divided by 40 */
SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15U), /**< SYSCLK divided by 42 */
SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16U), /**< SYSCLK divided by 44 */
SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17U), /**< SYSCLK divided by 46 */
SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18U), /**< SYSCLK divided by 48 */
SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19U), /**< SYSCLK divided by 50 */
SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1AU), /**< SYSCLK divided by 52 */
SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1BU), /**< SYSCLK divided by 54 */
SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1CU), /**< SYSCLK divided by 56 */
SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1DU), /**< SYSCLK divided by 58 */
SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1EU), /**< SYSCLK divided by 60 */
SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1FU), /**< SYSCLK divided by 62 */
} smartcard_prescaler_t;
/**
@@ -100,69 +98,66 @@ typedef enum
/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct
{
uint32_t baud; /**< This member configures the SmartCard communication baud rate. */
usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */
usart_parity_t parity; /**< Specifies the parity mode.
typedef struct {
uint32_t baud; /**< This member configures the SmartCard communication baud rate. */
usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
usart_stop_bits_t stop_bits; /**< Specifies the number of stop bits transmitted. */
usart_parity_t parity; /**< Specifies the parity mode.
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits).*/
usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */
usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/
usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted
usart_mode_t mode; /**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
usart_cpol_t polarity; /**< Specifies the steady state of the serial clock. */
usart_cpha_t phase; /**< Specifies the clock transition on which the bit capture is made.*/
usart_last_bit_t last_bit; /**< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref usart_last_bit_t */
smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
to provide the smartcard clock. The value given in the register (5 significant bits)
is multiplied by 2 to give the division factor of the source clock frequency. */
uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */
uint32_t guard_time; /**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
type_func_t nack; /**< Specifies the SmartCard NACK Transmission state. */
} smartcard_init_t;
/**
* @brief ALD state structures definition
*/
typedef enum
{
SMARTCARD_STATE_RESET = 0x00, /**< Peripheral is not yet Initialized */
SMARTCARD_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SMARTCARD_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SMARTCARD_STATE_BUSY_TX = 0x11, /**< Data Transmission process is ongoing */
SMARTCARD_STATE_BUSY_RX = 0x21, /**< Data Reception process is ongoing */
SMARTCARD_STATE_BUSY_TX_RX = 0x31, /**< Data Transmission and Reception process is ongoing */
SMARTCARD_STATE_TIMEOUT = 0x03, /**< Timeout state */
SMARTCARD_STATE_ERROR = 0x04 /**< Error */
typedef enum {
SMARTCARD_STATE_RESET = 0x00U, /**< Peripheral is not yet Initialized */
SMARTCARD_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
SMARTCARD_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
SMARTCARD_STATE_BUSY_TX = 0x11U, /**< Data Transmission process is ongoing */
SMARTCARD_STATE_BUSY_RX = 0x21U, /**< Data Reception process is ongoing */
SMARTCARD_STATE_BUSY_TX_RX = 0x31U, /**< Data Transmission and Reception process is ongoing */
SMARTCARD_STATE_TIMEOUT = 0x03U, /**< Timeout state */
SMARTCARD_STATE_ERROR = 0x04U, /**< Error */
} smartcard_state_t;
/**
* @brief SMARTCARD handle structure definition
*/
typedef struct smartcard_handle_s
{
USART_TypeDef *perh; /**< USART registers base address */
smartcard_init_t init; /**< SmartCard communication parameters */
uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */
uint16_t tx_size; /**< SmartCard Tx Transfer size */
uint16_t tx_count; /**< SmartCard Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */
uint16_t rx_size; /**< SmartCard Rx Transfer size */
uint16_t rx_count; /**< SmartCard Rx Transfer Counter */
typedef struct smartcard_handle_s {
USART_TypeDef *perh; /**< USART registers base address */
smartcard_init_t init; /**< SmartCard communication parameters */
uint8_t *tx_buf; /**< Pointer to SmartCard Tx transfer Buffer */
uint16_t tx_size; /**< SmartCard Tx Transfer size */
uint16_t tx_count; /**< SmartCard Tx Transfer Counter */
uint8_t *rx_buf; /**< Pointer to SmartCard Rx transfer Buffer */
uint16_t rx_size; /**< SmartCard Rx Transfer size */
uint16_t rx_count; /**< SmartCard Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */
dma_handle_t hdmatx; /**< SmartCard Tx DMA Handle parameters */
dma_handle_t hdmarx; /**< SmartCard Rx DMA Handle parameters */
#endif
lock_state_t lock; /**< Locking object */
smartcard_state_t state; /**< SmartCard communication state */
uint32_t err_code; /**< SmartCard Error code */
lock_state_t lock; /**< Locking object */
smartcard_state_t state; /**< SmartCard communication state */
uint32_t err_code; /**< SmartCard Error code */
void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */
void (*tx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct smartcard_handle_s *arg); /**< Rx completed callback */
void (*error_cbk)(struct smartcard_handle_s *arg); /**< error callback */
} smartcard_handle_t;
/**
@@ -214,7 +209,7 @@ typedef struct smartcard_handle_s
*/
#define IS_SMARTCARD_PRESCALER(x) (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
/**
* @}
*/

263
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h
View File

@@ -18,7 +18,7 @@
#define __ALD_SPI_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -39,97 +39,88 @@ extern "C" {
/**
* @brief clock phase
*/
typedef enum
{
SPI_CPHA_FIRST = 0, /**< Transiting data in the first edge */
SPI_CPHA_SECOND = 1, /**< Transiting data in the seconde edge */
typedef enum {
SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */
SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */
} spi_cpha_t;
/**
* @brief clock polarity
*/
typedef enum
{
SPI_CPOL_LOW = 0, /**< Polarity hold low when spi-bus is idle */
SPI_CPOL_HIGH = 1, /**< Polarity hold high when spi-bus is idle */
typedef enum {
SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */
SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */
} spi_cpol_t;
/**
* @brief master selection
*/
typedef enum
{
SPI_MODE_SLAVER = 0, /**< Slave mode */
SPI_MODE_MASTER = 1, /**< Master mode */
typedef enum {
SPI_MODE_SLAVER = 0U, /**< Slave mode */
SPI_MODE_MASTER = 1U, /**< Master mode */
} spi_mode_t;
/**
* @brief baud rate control
*/
typedef enum
{
SPI_BAUD_2 = 0, /**< fpclk/2 */
SPI_BAUD_4 = 1, /**< fpclk/4 */
SPI_BAUD_8 = 2, /**< fpclk/8 */
SPI_BAUD_16 = 3, /**< fpclk/16 */
SPI_BAUD_32 = 4, /**< fpclk/32 */
SPI_BAUD_64 = 5, /**< fpclk/64 */
SPI_BAUD_128 = 6, /**< fpclk/128 */
SPI_BAUD_256 = 7, /**< fpclk/256 */
typedef enum {
SPI_BAUD_2 = 0U, /**< fpclk/2 */
SPI_BAUD_4 = 1U, /**< fpclk/4 */
SPI_BAUD_8 = 2U, /**< fpclk/8 */
SPI_BAUD_16 = 3U, /**< fpclk/16 */
SPI_BAUD_32 = 4U, /**< fpclk/32 */
SPI_BAUD_64 = 5U, /**< fpclk/64 */
SPI_BAUD_128 = 6U, /**< fpclk/128 */
SPI_BAUD_256 = 7U, /**< fpclk/256 */
} spi_baud_t;
/**
* @brief frame format
*/
typedef enum
{
SPI_FIRSTBIT_MSB = 0, /**< MSB transmitted first */
SPI_FIRSTBIT_LSB = 1, /**< LSB transmitted first */
typedef enum {
SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */
SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */
} spi_firstbit_t;
/**
* @brief data frame format
*/
typedef enum
{
SPI_DATA_SIZE_8 = 0, /**< 8-bit data frame format is selected for transmission/reception */
SPI_DATA_SIZE_16 = 1, /**< 16-bit data frame format is selected for transmission/reception */
typedef enum {
SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */
SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */
} spi_datasize_t;
/**
* @brief interrupt control
*/
typedef enum
{
SPI_IT_ERR = (1U << 5), /**< error interrupt */
SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */
SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */
typedef enum {
SPI_IT_ERR = (1U << 5), /**< error interrupt */
SPI_IT_RXBNE = (1U << 6), /**< rx buffer not empty interrupt */
SPI_IT_TXBE = (1U << 7), /**< tx buffer empty interrupt */
} spi_it_t;
/**
* @brief interrupt flag
*/
typedef enum
{
SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */
SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */
SPI_IF_CRCERR = (1U << 4), /**< crc error flag */
SPI_IF_MODF = (1U << 5), /**< mode fault */
SPI_IF_OVE = (1U << 6), /**< overrun flag */
SPI_IF_BUSY = (1U << 7), /**< busy flag */
typedef enum {
SPI_IF_RXBNE = (1U << 0), /**< receive buffer not empty */
SPI_IF_TXBE = (1U << 1), /**< transmit buffer empty */
SPI_IF_CRCERR = (1U << 4), /**< crc error flag */
SPI_IF_MODF = (1U << 5), /**< mode fault */
SPI_IF_OVE = (1U << 6), /**< overrun flag */
SPI_IF_BUSY = (1U << 7), /**< busy flag */
} spi_flag_t;
/**
* @brief SPI error status
*/
typedef enum
{
SPI_ERROR_NONE = 0, /**< none */
SPI_ERROR_MODF = 1, /**< mode fault */
SPI_ERROR_CRC = 2, /**< crc error */
SPI_ERROR_OVE = 4, /**< overrun error */
SPI_ERROR_DMA = 8, /**< dma error */
SPI_ERROR_FLAG = 0x10, /**< interrupt flag error */
typedef enum {
SPI_ERROR_NONE = 0U, /**< none */
SPI_ERROR_MODF = 1U, /**< mode fault */
SPI_ERROR_CRC = 2U, /**< crc error */
SPI_ERROR_OVE = 4U, /**< overrun error */
SPI_ERROR_DMA = 8U, /**< dma error */
SPI_ERROR_FLAG = 0x10U, /**< interrupt flag error */
} spi_error_t;
@@ -137,104 +128,97 @@ typedef enum
/**
* @brief SPI state structures definition
*/
typedef enum
{
SPI_STATE_RESET = 0x00, /**< Peripheral is not initialized */
SPI_STATE_READY = 0x01, /**< Peripheral Initialized and ready for use */
SPI_STATE_BUSY = 0x02, /**< an internal process is ongoing */
SPI_STATE_BUSY_TX = 0x11, /**< transmit is ongoing */
SPI_STATE_BUSY_RX = 0x21, /**< receive is ongoing */
SPI_STATE_BUSY_TX_RX = 0x31, /**< transmit and receive are ongoing */
SPI_STATE_TIMEOUT = 0x03, /**< Timeout state */
SPI_STATE_ERROR = 0x04, /**< Error */
typedef enum {
SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */
SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */
SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */
SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */
SPI_STATE_ERROR = 0x04U, /**< Error */
} spi_state_t;
/**
* @brief SPI status definition
*/
typedef enum
{
SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */
SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */
SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */
SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */
SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */
SPI_STATUS_BUSY = (1U << 7), /**< Busy status */
typedef enum {
SPI_STATUS_RXBNE = (1U << 0), /**< Receive not empty status */
SPI_STATUS_TXBE = (1U << 1), /**< Transmit empty status */
SPI_STATUS_CRCERR = (1U << 4), /**< CRC error status */
SPI_STATUS_MODEERR = (1U << 5), /**< Mode error status */
SPI_STATUS_OVERR = (1U << 6), /**< Overflow status */
SPI_STATUS_BUSY = (1U << 7), /**< Busy status */
} spi_status_t;
/**
* @brief SPI direction definition
*/
typedef enum
{
SPI_DIRECTION_2LINES = 0, /**< 2 lines */
SPI_DIRECTION_2LINES_RXONLY = 1, /**< 2 lines only rx */
SPI_DIRECTION_1LINE = 2, /**< 1 line */
SPI_DIRECTION_1LINE_RX = 3, /**< 1 line only rx */
typedef enum {
SPI_DIRECTION_2LINES = 0U, /**< 2 lines */
SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */
SPI_DIRECTION_1LINE = 2U, /**< 1 line */
SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */
} spi_direction_t;
/**
* @brief SPI dma request definition
*/
typedef enum
{
SPI_DMA_REQ_TX = 0, /**< TX dma request */
SPI_DMA_REQ_RX = 1, /**< RX dma request */
typedef enum {
SPI_DMA_REQ_TX = 0U, /**< TX dma request */
SPI_DMA_REQ_RX = 1U, /**< RX dma request */
} spi_dma_req_t;
/**
* @brief SPI TXE/RXNE status definition
*/
typedef enum
{
SPI_SR_TXBE = 0, /**< SR.TXE set */
SPI_SR_RXBNE = 1, /**< SR.RXNE set */
SPI_SR_TXBE_RXBNE = 2, /**< SR.TXE and SR.RXNE set */
typedef enum {
SPI_SR_TXBE = 0U, /**< SR.TXE set */
SPI_SR_RXBNE = 1U, /**< SR.RXNE set */
SPI_SR_TXBE_RXBNE = 2U, /**< SR.TXE and SR.RXNE set */
} spi_sr_status_t;
/**
* @brief SPI init structure definition
*/
typedef struct
{
spi_mode_t mode; /**< SPI mode */
spi_direction_t dir; /**< SPI direction */
spi_datasize_t data_size; /**< SPI data size */
spi_baud_t baud; /**< SPI baudrate prescaler */
spi_cpha_t phase; /**< SPI clock phase */
spi_cpol_t polarity; /**< SPI clock polarity */
spi_firstbit_t first_bit; /**< SPI first bit */
type_func_t ss_en; /**< SPI ssm enable or disable */
type_func_t crc_calc; /**< SPI crc calculation */
uint16_t crc_poly; /**< SPI crc polynomial */
typedef struct {
spi_mode_t mode; /**< SPI mode */
spi_direction_t dir; /**< SPI direction */
spi_datasize_t data_size; /**< SPI data size */
spi_baud_t baud; /**< SPI baudrate prescaler */
spi_cpha_t phase; /**< SPI clock phase */
spi_cpol_t polarity; /**< SPI clock polarity */
spi_firstbit_t first_bit; /**< SPI first bit */
type_func_t ss_en; /**< SPI ssm enable or disable */
type_func_t crc_calc; /**< SPI crc calculation */
uint16_t crc_poly; /**< SPI crc polynomial */
} spi_init_t;
/**
* @brief SPI handle structure definition
*/
typedef struct spi_handle_s
{
SPI_TypeDef *perh; /**< SPI registers base address */
spi_init_t init; /**< SPI communication parameters */
uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */
uint16_t tx_size; /**< SPI Tx transfer size */
uint16_t tx_count; /**< SPI Tx transfer counter */
uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */
uint16_t rx_size; /**< SPI Rx Transfer size */
uint16_t rx_count; /**< SPI Rx Transfer Counter */
typedef struct spi_handle_s {
SPI_TypeDef *perh; /**< SPI registers base address */
spi_init_t init; /**< SPI communication parameters */
uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */
uint16_t tx_size; /**< SPI Tx transfer size */
uint16_t tx_count; /**< SPI Tx transfer counter */
uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */
uint16_t rx_size; /**< SPI Rx Transfer size */
uint16_t rx_count; /**< SPI Rx Transfer Counter */
#ifdef ALD_DMA
dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */
dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */
dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */
dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */
#endif
lock_state_t lock; /**< Locking object */
spi_state_t state; /**< SPI communication state */
uint32_t err_code; /**< SPI error code */
lock_state_t lock; /**< Locking object */
spi_state_t state; /**< SPI communication state */
uint32_t err_code; /**< SPI error code */
void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */
void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */
void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */
void (*tx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx completed callback */
void (*rx_cplt_cbk)(struct spi_handle_s *arg); /**< Rx completed callback */
void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg); /**< Tx & Rx completed callback */
void (*err_cbk)(struct spi_handle_s *arg); /**< error callback */
} spi_handle_t;
/**
* @}
@@ -247,10 +231,10 @@ typedef struct spi_handle_s
#define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
#define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
#define SPI_CRC_RESET(x) \
do { \
CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
} while (0)
do { \
CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
} while (0)
#define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
@@ -268,9 +252,12 @@ typedef struct spi_handle_s
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
#define IS_SPI(x) (((x) == SPI0) || \
((x) == SPI1) || \
((x) == SPI2))
#if defined(ES32F065x) || defined(ES32F033x)
#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1))
#endif
#if defined(ES32F093x)
#define IS_SPI(x) (((x) == SPI0) || ((x) == SPI1) || ((x) == SPI2))
#endif
#define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \
((x) == SPI_CPHA_SECOND))
#define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \
@@ -286,20 +273,22 @@ typedef struct spi_handle_s
((x) == SPI_BAUD_128) || \
((x) == SPI_BAUD_256))
#define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \
((x) == SPI_DATA_SIZE_16))
((x) == SPI_DATA_SIZE_16))
#define IS_SPI_FIRSTBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \
((x) == SPI_FIRSTBIT_LSB))
#define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \
((x) == SPI_BID_TX))
((x) == SPI_BID_TX))
#define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \
((x) == SPI_BIDMODE_SOLE))
((x) == SPI_BIDMODE_SOLE))
#define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \
((x) == SPI_DIRECTION_2LINES_RXONLY) || \
((x) == SPI_DIRECTION_1LINE) || \
((x) == SPI_DIRECTION_1LINE_RX))
((x) == SPI_DIRECTION_2LINES_RXONLY) || \
((x) == SPI_DIRECTION_1LINE) || \
((x) == SPI_DIRECTION_1LINE_RX))
#define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \
((x) == SPI_DMA_REQ_RX))
((x) == SPI_DMA_REQ_RX))
#define IS_SPI_SR_STATUS(x) (((x) == SPI_SR_TXBE) || \
((x) == SPI_SR_RXBNE) || \
((x) == SPI_SR_TXBE_RXBNE))
((x) == SPI_SR_RXBNE) || \
((x) == SPI_SR_TXBE_RXBNE))
#define IS_SPI_IT(x) (((x) == SPI_IT_ERR) || \
((x) == SPI_IT_RXBNE) || \
((x) == SPI_IT_TXBE))
@@ -310,11 +299,11 @@ typedef struct spi_handle_s
((x) == SPI_IF_OVE) || \
((x) == SPI_IF_BUSY))
#define IS_SPI_STATUS(x) (((x) == SPI_STATUS_RXBNE) || \
((x) == SPI_STATUS_TXBE) || \
((x) == SPI_STATUS_CRCERR) || \
((x) == SPI_STATUS_MODEERR) || \
((x) == SPI_STATUS_OVERR) || \
((x) == SPI_STATUS_BUSY))
((x) == SPI_STATUS_TXBE) || \
((x) == SPI_STATUS_CRCERR) || \
((x) == SPI_STATUS_MODEERR) || \
((x) == SPI_STATUS_OVERR) || \
((x) == SPI_STATUS_BUSY))
/**
* @}
*/

64
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h
View File

@@ -18,7 +18,7 @@
#define __ALD_SYSCFG_H__
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#include "utils.h"
@@ -36,33 +36,33 @@ extern "C" {
/** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros
* @{
*/
#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0)
#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996)
#define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U)
#define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
#define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
#define BOOT_FROM_BOOT_ROM() \
do { \
SYSCFG_UNLOCK(); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define BOOT_FROM_BOOT_FLASH() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
#define BOOT_FROM_FLASH() \
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK); \
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK); \
SYSCFG_LOCK(); \
} while (0)
/**
* @}
*/
@@ -73,20 +73,18 @@ extern "C" {
*/
__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status)
{
SYSCFG_UNLOCK();
SYSCFG_UNLOCK();
if (status)
{
MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3F));
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}
else
{
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}
if (status) {
MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3FU));
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}
else {
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
}
SYSCFG_LOCK();
return;
SYSCFG_LOCK();
return;
}
/**
* @}

987
bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_timer.h
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