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[rpi4b] add new bsp for qemu-rpi4b

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This commit is contained in:
zhujiale
2024-10-28 15:57:45 +08:00
committed by Rbb666
parent 2b21b095f9
commit c1db34983d
31 changed files with 8821 additions and 0 deletions
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1541
bsp/raspberry-pi/raspi-dm2.0/.config Normal file
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bsp/raspberry-pi/raspi-dm2.0/Kconfig Normal file
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mainmenu "RT-Thread Project Configuration"
BSP_DIR := .
RTT_DIR := ../../..
PKGS_DIR := packages
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
config BCM2711_SOC
bool
select ARCH_ARMV8
select ARCH_ARM_MMU
select RT_USING_CACHE
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select ARCH_CPU_64BIT
default y
rsource "drivers/Kconfig"

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bsp/raspberry-pi/raspi-dm2.0/README.md Normal file
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# Raspberry PI 4-dm2.0BSP说明
## 1. 简介
树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
## 2. 编译说明
推荐使用[env工具](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)，可以在console下进入到`bsp\raspberry-pi\raspi4-64`目录中，运行以下命令：
```
scons
```
来编译这个板级支持包。如果编译正确无误，会产生 `rtthread.elf`, `rtthread.bin` 文件。
## 3. 支持情况
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
| UART | 支持 | pl011驱动 |
| GPIO | 尚未支持 | 等待dm2.0相关代码合入主线 |
| SPI | 尚未支持 | 等待gpio合入主线 |
| WATCHDOG | 尚未支持 | 等待gpio合入主线 |
| HDMI | 尚未支持 | 等待gpio合入主线 |
| SDIO | 支持 | 能够正常运行在qemu，但是qemu对于raspi目前只支持pio传输，后续需要硬件进行详细测试 |
| ETH | 尚未支持 | 等待gpio合入主线 |

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bsp/raspberry-pi/raspi-dm2.0/SConscript Normal file
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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

30
bsp/raspberry-pi/raspi-dm2.0/SConstruct Normal file
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import os
import sys
import rtconfig
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CPP = rtconfig.CPP, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# make a building
DoBuilding(TARGET, objs)

14
bsp/raspberry-pi/raspi-dm2.0/applications/SConscript Normal file
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

19
bsp/raspberry-pi/raspi-dm2.0/applications/main.c Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-16 bigmagic first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
int main(int argc, char** argv)
{
rt_kprintf("Hi, this is RT-Thread!!\n");
return 0;
}

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bsp/raspberry-pi/raspi-dm2.0/bcm2711-rpi-4-b.dtb Normal file
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bsp/raspberry-pi/raspi-dm2.0/drivers/Kconfig Normal file
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menu "Hardware Drivers Config"
config BSP_USING_PL011
bool "Enable pl011 for uart"
default n
config BSP_USING_SDHCI
bool "Enable sdhci driver"
select RT_USING_SDHCI
default y
rsource sdhci/Kconfig
endmenu

25
bsp/raspberry-pi/raspi-dm2.0/drivers/SConscript Normal file
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from building import *
cwd = GetCurrentDir()
src = ["board.c"]
CPPPATH = [cwd, str(Dir('#'))]
if GetDepend(['BSP_USING_PL011']):
src = src + ['drv_uart.c']
if GetDepend(['BSP_USING_SDHCI']):
src = src + ['drv_sd.c']
group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH)
# build for sub-directory
list = os.listdir(cwd)
objs = []
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
group = group + objs
Return('group')

32
bsp/raspberry-pi/raspi-dm2.0/drivers/board.c Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-28 zhujiale The first version
*/
#define DBG_TAG "board"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <rthw.h>
#include <rtthread.h>
#include <mm_aspace.h>
#include <setup.h>
#include "board.h"
#include "drv_uart.h"
#include "cp15.h"
#include "mmu.h"
#include <mm_page.h>
#ifdef RT_USING_SMART
#include <lwp_arch.h>
#endif
void rt_hw_board_init(void)
{
rt_hw_common_setup();
}

35
bsp/raspberry-pi/raspi-dm2.0/drivers/board.h Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-28 zhujiale The first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <stdint.h>
#include "mmu.h"
#include "ioremap.h"
extern int __bss_end;
#define HEAP_BEGIN ((void*)&__bss_end)
#ifdef RT_USING_SMART
#define HEAP_END ((size_t)KERNEL_VADDR_START + 32 * 1024 * 1024)
#define PAGE_START HEAP_END
#define PAGE_END ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
#else
#define KERNEL_VADDR_START 0x0
#define HEAP_END (KERNEL_VADDR_START + 32 * 1024 * 1024)
#define PAGE_START HEAP_END
#define PAGE_END ((size_t)PAGE_START + 128 * 1024 * 1024)
#endif
void rt_hw_board_init(void);
#endif

219
bsp/raspberry-pi/raspi-dm2.0/drivers/drv_sd.c Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-28 zhujiale The first version
*/
#include <sdhci.h>
#include <rtdevice.h>
#include "drv_sd.h"
#define DBG_TAG "SDHCI"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
struct sdhci_iproc_data {
const struct sdhci_pltfm_data *pdata;
rt_uint32_t caps;
rt_uint32_t caps1;
rt_uint32_t mmc_caps;
rt_bool_t missing_caps;
};
struct sdhci_iproc_host {
const struct sdhci_iproc_data *data;
rt_uint32_t shadow_cmd;
rt_uint32_t shadow_blk;
rt_bool_t is_cmd_shadowed;
rt_bool_t is_blk_shadowed;
};
static inline rt_uint32_t sdhci_iproc_readl(struct sdhci_host *host, int reg)
{
rt_uint32_t val = readl(host->ioaddr + reg);
return val;
}
static rt_uint16_t sdhci_iproc_readw(struct sdhci_host *host, int reg)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
rt_uint32_t val;
rt_uint16_t word;
if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed)
{
/* Get the saved transfer mode */
val = iproc_host->shadow_cmd;
} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
iproc_host->is_blk_shadowed)
{
/* Get the saved block info */
val = iproc_host->shadow_blk;
} else {
val = sdhci_iproc_readl(host, (reg & ~3));
}
word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
return word;
}
static rt_uint8_t sdhci_iproc_readb(struct sdhci_host *host, int reg)
{
rt_uint32_t val = sdhci_iproc_readl(host, (reg & ~3));
rt_uint8_t byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
return byte;
}
static inline void sdhci_iproc_writel(struct sdhci_host *host, rt_uint32_t val, int reg)
{
LOG_D("%s: writel [0x%02x] 0x%08x\n",
mmc_hostname(host->mmc), reg, val);
writel(val, host->ioaddr + reg);
if (host->clock <= 400000)
{
/* Round up to micro-second four SD clock delay */
if (host->clock)
rt_hw_us_delay((4 * 1000000 + host->clock - 1) / host->clock);
else
rt_hw_us_delay(10);
}
}
static void sdhci_iproc_writew(struct sdhci_host *host, rt_uint16_t val, int reg)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
rt_uint32_t word_shift = REG_OFFSET_IN_BITS(reg);
rt_uint32_t mask = 0xffff << word_shift;
rt_uint32_t oldval, newval;
if (reg == SDHCI_COMMAND)
{
/* Write the block now as we are issuing a command */
if (iproc_host->is_blk_shadowed)
{
sdhci_iproc_writel(host, iproc_host->shadow_blk,
SDHCI_BLOCK_SIZE);
iproc_host->is_blk_shadowed = false;
}
oldval = iproc_host->shadow_cmd;
iproc_host->is_cmd_shadowed = false;
} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
iproc_host->is_blk_shadowed)
{
/* Block size and count are stored in shadow reg */
oldval = iproc_host->shadow_blk;
} else {
/* Read reg, all other registers are not shadowed */
oldval = sdhci_iproc_readl(host, (reg & ~3));
}
newval = (oldval & ~mask) | (val << word_shift);
if (reg == SDHCI_TRANSFER_MODE)
{
/* Save the transfer mode until the command is issued */
iproc_host->shadow_cmd = newval;
iproc_host->is_cmd_shadowed = true;
} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT)
{
/* Save the block info until the command is issued */
iproc_host->shadow_blk = newval;
iproc_host->is_blk_shadowed = true;
} else {
/* Command or other regular 32-bit write */
sdhci_iproc_writel(host, newval, reg & ~3);
}
}
static void sdhci_iproc_writeb(struct sdhci_host *host, rt_uint8_t val, int reg)
{
rt_uint32_t oldval = sdhci_iproc_readl(host, (reg & ~3));
rt_uint32_t byte_shift = REG_OFFSET_IN_BITS(reg);
rt_uint32_t mask = 0xff << byte_shift;
rt_uint32_t newval = (oldval & ~mask) | (val << byte_shift);
sdhci_iproc_writel(host, newval, reg & ~3);
}
static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
.read_l = sdhci_iproc_readl,
.read_w = sdhci_iproc_readw,
.read_b = sdhci_iproc_readb,
.write_l = sdhci_iproc_writel,
.write_w = sdhci_iproc_writew,
.write_b = sdhci_iproc_writeb,
.set_clock = sdhci_set_clock,
.set_bus_width = sdhci_set_bus_width,
.reset = sdhci_reset,
.set_uhs_signaling = sdhci_set_uhs_signaling,
};
static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
.ops = &sdhci_iproc_bcm2711_ops,
};
static const struct sdhci_iproc_data bcm2711_data = {
.pdata = &sdhci_bcm2711_pltfm_data,
.mmc_caps = MMC_CAP_3_3V_DDR,
};
rt_err_t bcm2835_probe(struct rt_platform_device *pdev)
{
struct sdhci_iproc_host *iproc_host;
const struct sdhci_iproc_data *iproc_data = NULL;
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
int ret;
iproc_data = &bcm2711_data;
host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
pltfm_host = sdhci_priv(host);
iproc_host = sdhci_pltfm_priv(pltfm_host);
iproc_host->data = iproc_data;
ret = mmc_of_parse(host->mmc);
if (ret)
goto err;
sdhci_get_property(pdev);
host->mmc->caps |= iproc_host->data->mmc_caps;
ret = sdhci_add_host(host);
if (ret)
goto err;
return 0;
err:
return ret;
}
static const struct rt_ofw_node_id bcm2835_ofw_ids[] =
{
/* { .compatible = "brcm,bcm2711-emmc2"},*/
{ .compatible = "brcm,bcm2835-mmc"},
{ /* sentinel */ }
};
static struct rt_platform_driver bcm2835_driver =
{
.name = "bcm2835",
.ids = bcm2835_ofw_ids,
.probe = bcm2835_probe,
/* .remove = pl011_remove,*/
};
RT_PLATFORM_DRIVER_EXPORT(bcm2835_driver);

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bsp/raspberry-pi/raspi-dm2.0/drivers/drv_sd.h Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-10-28 zhujiale The first version
*/
#ifndef __DRV_SD_BCM2835_H_
#define __DRV_SD_BCM2835_H_
#include <drivers/dev_mmcsd_core.h>
#include <rtthread.h>
#include <drivers/mmcsd_cmd.h>
#include <drivers/mmcsd_host.h>
struct sdhci_bcm2835 {
struct sdhci_host *host;
struct rt_platform_device *pdev;
struct rt_mmcsd_req *mrq;
void *ioaddr;
rt_mutex_t mutex;
};
#define SDCMD 0x00 /* Command to SD card - 16 R/W */
#define SDARG 0x04 /* Argument to SD card - 32 R/W */
#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
#define SDHSTS 0x20 /* SD host status - 11 R/W */
#define SDVDD 0x30 /* SD card power control - 1 R/W */
#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
#define SDHCFG 0x38 /* Host configuration - 2 R/W */
#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
#define SDCMD_NEW_FLAG 0x8000
#define SDCMD_FAIL_FLAG 0x4000
#define SDCMD_BUSYWAIT 0x800
#define SDCMD_NO_RESPONSE 0x400
#define SDCMD_LONG_RESPONSE 0x200
#define SDCMD_WRITE_CMD 0x80
#define SDCMD_READ_CMD 0x40
#define SDCMD_CMD_MASK 0x3f
#define SDCDIV_MAX_CDIV 0x7ff
#define SDHSTS_BUSY_IRPT 0x400
#define SDHSTS_BLOCK_IRPT 0x200
#define SDHSTS_SDIO_IRPT 0x100
#define SDHSTS_REW_TIME_OUT 0x80
#define SDHSTS_CMD_TIME_OUT 0x40
#define SDHSTS_CRC16_ERROR 0x20
#define SDHSTS_CRC7_ERROR 0x10
#define SDHSTS_FIFO_ERROR 0x08
/* Reserved */
/* Reserved */
#define SDHSTS_DATA_FLAG 0x01
#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
SDHSTS_CRC16_ERROR | \
SDHSTS_REW_TIME_OUT | \
SDHSTS_FIFO_ERROR)
#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
SDHSTS_TRANSFER_ERROR_MASK)
#define SDHCFG_BUSY_IRPT_EN BIT(10)
#define SDHCFG_BLOCK_IRPT_EN BIT(8)
#define SDHCFG_SDIO_IRPT_EN BIT(5)
#define SDHCFG_DATA_IRPT_EN BIT(4)
#define SDHCFG_SLOW_CARD BIT(3)
#define SDHCFG_WIDE_EXT_BUS BIT(2)
#define SDHCFG_WIDE_INT_BUS BIT(1)
#define SDHCFG_REL_CMD_LINE BIT(0)
#define SDVDD_POWER_OFF 0
#define SDVDD_POWER_ON 1
#define SDEDM_FORCE_DATA_MODE BIT(19)
#define SDEDM_CLOCK_PULSE BIT(20)
#define SDEDM_BYPASS BIT(21)
#define SDEDM_WRITE_THRESHOLD_SHIFT 9
#define SDEDM_READ_THRESHOLD_SHIFT 14
#define SDEDM_THRESHOLD_MASK 0x1f
#define SDEDM_FSM_MASK 0xf
#define SDEDM_FSM_IDENTMODE 0x0
#define SDEDM_FSM_DATAMODE 0x1
#define SDEDM_FSM_READDATA 0x2
#define SDEDM_FSM_WRITEDATA 0x3
#define SDEDM_FSM_READWAIT 0x4
#define SDEDM_FSM_READCRC 0x5
#define SDEDM_FSM_WRITECRC 0x6
#define SDEDM_FSM_WRITEWAIT1 0x7
#define SDEDM_FSM_POWERDOWN 0x8
#define SDEDM_FSM_POWERUP 0x9
#define SDEDM_FSM_WRITESTART1 0xa
#define SDEDM_FSM_WRITESTART2 0xb
#define SDEDM_FSM_GENPULSES 0xc
#define SDEDM_FSM_WRITEWAIT2 0xd
#define SDEDM_FSM_STARTPOWDOWN 0xf
#define SDDATA_FIFO_WORDS 16
#define FIFO_READ_THRESHOLD 4
#define FIFO_WRITE_THRESHOLD 4
#define SDDATA_FIFO_PIO_BURST 8
#define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */
#endif

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bsp/raspberry-pi/raspi-dm2.0/drivers/drv_uart.c Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-05-05 Bernard The first version
* 2022-08-24 GuEe-GUI add OFW support
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <cpuport.h>
#include <ioremap.h>
#include <drivers/serial_dm.h>
#define PL011_OEIM RT_BIT(10) /* overrun error interrupt mask */
#define PL011_BEIM RT_BIT(9) /* break error interrupt mask */
#define PL011_PEIM RT_BIT(8) /* parity error interrupt mask */
#define PL011_FEIM RT_BIT(7) /* framing error interrupt mask */
#define PL011_RTIM RT_BIT(6) /* receive timeout interrupt mask */
#define PL011_TXIM RT_BIT(5) /* transmit interrupt mask */
#define PL011_RXIM RT_BIT(4) /* receive interrupt mask */
#define PL011_DSRMIM RT_BIT(3) /* DSR interrupt mask */
#define PL011_DCDMIM RT_BIT(2) /* DCD interrupt mask */
#define PL011_CTSMIM RT_BIT(1) /* CTS interrupt mask */
#define PL011_RIMIM RT_BIT(0) /* RI interrupt mask */
#define PL011_DR 0x000
#define PL011_FR 0x018
#define PL011_IBRD 0x024
#define PL011_FBRD 0x028
#define PL011_LCR 0x02c
#define PL011_CR 0x030
#define PL011_IMSC 0x038
#define PL011_RIS 0x03c
#define PL011_DMACR 0x048
#define PL011_LCRH_SPS (1 << 7)
#define PL011_LCRH_WLEN_8 (3 << 5)
#define PL011_LCRH_WLEN_7 (2 << 5)
#define PL011_LCRH_WLEN_6 (1 << 5)
#define PL011_LCRH_WLEN_5 (0 << 5)
#define PL011_LCRH_FEN (1 << 4)
#define PL011_LCRH_STP2 (1 << 3)
#define PL011_LCRH_EPS (1 << 2)
#define PL011_LCRH_PEN (1 << 1)
#define PL011_LCRH_BRK (1 << 0)
#define PL011_LCRH_WLEN(n) ((n - 5) << 5)
#define PL011_CR_CTSEN RT_BIT(15)
#define PL011_CR_RTSEN RT_BIT(14)
#define PL011_CR_RTS RT_BIT(11)
#define PL011_CR_DTR RT_BIT(10)
#define PL011_CR_RXE RT_BIT(9)
#define PL011_CR_TXE RT_BIT(8)
#define PL011_CR_LBE RT_BIT(7)
#define PL011_CR_SIRLP RT_BIT(2)
#define PL011_CR_SIREN RT_BIT(1)
#define PL011_CR_UARTEN RT_BIT(0)
struct pl011
{
struct rt_serial_device parent;
int irq;
void *base;
rt_ubase_t freq;
struct rt_clk *clk;
struct rt_clk *pclk;
struct rt_spinlock spinlock;
};
#define raw_to_pl011(raw) rt_container_of(raw, struct pl011, parent)
rt_inline rt_uint32_t pl011_read(struct pl011 *pl011, int offset)
{
return HWREG32(pl011->base + offset);
}
rt_inline void pl011_write(struct pl011 *pl011, int offset, rt_uint32_t value)
{
HWREG32(pl011->base + offset) = value;
}
static void pl011_isr(int irqno, void *param)
{
struct pl011 *pl011 = param;
/* Check irq */
if (pl011_read(pl011, PL011_RIS) & PL011_RXIM)
{
rt_base_t level = rt_spin_lock_irqsave(&pl011->spinlock);
rt_hw_serial_isr(&pl011->parent, RT_SERIAL_EVENT_RX_IND);
rt_spin_unlock_irqrestore(&pl011->spinlock, level);
}
}
static rt_err_t pl011_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
rt_ubase_t quot;
struct pl011 *pl011 = raw_to_pl011(serial);
/* Clear UART setting */
pl011_write(pl011, PL011_CR, 0);
/* Disable FIFO */
pl011_write(pl011, PL011_LCR, 0);
if (cfg->baud_rate > pl011->freq / 16)
{
quot = RT_DIV_ROUND_CLOSEST(pl011->freq * 8, cfg->baud_rate);
}
else
{
quot = RT_DIV_ROUND_CLOSEST(pl011->freq * 4, cfg->baud_rate);
}
pl011_write(pl011, PL011_IBRD, quot >> 6);
pl011_write(pl011, PL011_FBRD, quot & 0x3f);
/* FIFO */
pl011_write(pl011, PL011_LCR, PL011_LCRH_WLEN(cfg->data_bits));
/* Art enable, TX/RX enable */
pl011_write(pl011, PL011_CR, PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE);
return RT_EOK;
}
static rt_err_t pl011_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct pl011 *pl011 = raw_to_pl011(serial);
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* Disable rx irq */
pl011_write(pl011, PL011_IMSC, pl011_read(pl011, PL011_IMSC) & ~PL011_RXIM);
rt_hw_interrupt_mask(pl011->irq);
break;
case RT_DEVICE_CTRL_SET_INT:
/* Enable rx irq */
pl011_write(pl011, PL011_IMSC, pl011_read(pl011, PL011_IMSC) | PL011_RXIM);
rt_hw_interrupt_umask(pl011->irq);
break;
}
return RT_EOK;
}
static int pl011_uart_putc(struct rt_serial_device *serial, char c)
{
struct pl011 *pl011 = raw_to_pl011(serial);
while (pl011_read(pl011, PL011_FR) & PL011_TXIM)
{
rt_hw_cpu_relax();
}
pl011_write(pl011, PL011_DR, c);
return 1;
}
static int pl011_uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
struct pl011 *pl011 = raw_to_pl011(serial);
if (!(pl011_read(pl011, PL011_FR) & PL011_RXIM))
{
ch = pl011_read(pl011, PL011_DR);
}
return ch;
}
static const struct rt_uart_ops pl011_uart_ops =
{
.configure = pl011_uart_configure,
.control = pl011_uart_control,
.putc = pl011_uart_putc,
.getc = pl011_uart_getc,
};
static void pl011_early_kick(struct rt_fdt_earlycon *con, int why)
{
struct pl011 *pl011 = raw_to_pl011(con->data);
switch (why)
{
case FDT_EARLYCON_KICK_UPDATE:
pl011->base = rt_ioremap((void *)con->mmio, con->size);
break;
case FDT_EARLYCON_KICK_COMPLETED:
rt_iounmap(pl011->base);
break;
default:
break;
}
}
static rt_err_t pl011_early_setup(struct rt_fdt_earlycon *con, const char *options)
{
rt_err_t err = RT_EOK;
static struct pl011 pl011 = { };
if (options && !con->mmio)
{
char *arg;
con->mmio = RT_NULL;
/*
* The pl011 serial port must already be setup and configured in early.
* Options are not yet supported.
* pl011,<addr>
* pl011,mmio32,<addr>
*/
serial_for_each_args(arg, options)
{
if (!rt_strcmp(arg, "pl011") || !rt_strcmp(arg, "mmio32"))
{
continue;
}
if (!con->mmio)
{
con->mmio = (rt_ubase_t)serial_base_from_args(arg);
break;
}
}
}
if (!con->size)
{
con->size = 0x1000;
}
if (con->mmio)
{
pl011.base = rt_ioremap_early((void *)con->mmio, con->size);
}
if (pl011.base)
{
con->console_putc = (typeof(con->console_putc))&pl011_uart_putc;
con->console_kick = pl011_early_kick;
con->data = &pl011.parent;
pl011.parent.config = (typeof(pl011.parent.config))RT_SERIAL_CONFIG_DEFAULT;
}
else
{
err = -RT_ERROR;
}
return err;
}
RT_FDT_EARLYCON_EXPORT(pl011, "pl011", "arm,pl011", pl011_early_setup);
static void pl011_free(struct pl011 *pl011)
{
if (pl011->base)
{
rt_iounmap(pl011->base);
}
/* if (!rt_is_err_or_null(pl011->clk))*/
/* {*/
/* rt_clk_disable(pl011->clk);*/
/* rt_clk_put(pl011->clk);*/
/* }*/
/* if (!rt_is_err_or_null(pl011->pclk))*/
/* {*/
/* rt_clk_disable_unprepare(pl011->pclk);*/
/* rt_clk_put(pl011->pclk);*/
/* }*/
rt_free(pl011);
}
static rt_err_t pl011_probe(struct rt_platform_device *pdev)
{
rt_err_t err;
const char *name;
char isr_name[RT_NAME_MAX];
struct rt_device *dev = &pdev->parent;
struct pl011 *pl011 = rt_calloc(1, sizeof(*pl011));
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
if (!pl011)
{
return -RT_ENOMEM;
}
pl011->base = rt_dm_dev_iomap(dev, 0);
if (!pl011->base)
{
err = -RT_EIO;
goto _fail;
}
pl011->irq = rt_dm_dev_get_irq(dev, 0);
if (pl011->irq < 0)
{
err = pl011->irq;
goto _fail;
}
/* pl011->clk = rt_clk_get_by_index(dev, 0);*/
/* if (rt_is_err(pl011->clk))*/
/* {*/
/* err = rt_ptr_err(pl011->clk);*/
/* goto _fail;*/
/* }*/
/* pl011->pclk = rt_clk_get_by_name(dev, "apb_pclk");*/
/* if (rt_is_err(pl011->pclk))*/
/* {*/
/* err = rt_ptr_err(pl011->pclk);*/
/* goto _fail;*/
/* }*/
/* if ((err = rt_clk_prepare_enable(pl011->pclk)))*/
/* {*/
/* goto _fail;*/
/* }*/
rt_dm_dev_bind_fwdata(&pl011->parent.parent, dev->ofw_node, &pl011->parent);
/* rt_clk_enable(pl011->clk);*/
/* pl011->freq = rt_clk_get_rate(pl011->clk);*/
dev->user_data = pl011;
pl011->parent.ops = &pl011_uart_ops;
pl011->parent.config = config;
rt_spin_lock_init(&pl011->spinlock);
serial_dev_set_name(&pl011->parent);
name = rt_dm_dev_get_name(&pl011->parent.parent);
rt_hw_serial_register(&pl011->parent, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, pl011);
rt_snprintf(isr_name, RT_NAME_MAX, "%s-pl011", name);
rt_hw_interrupt_install(pl011->irq, pl011_isr, pl011, isr_name);
return RT_EOK;
_fail:
pl011_free(pl011);
return err;
}
static rt_err_t pl011_remove(struct rt_platform_device *pdev)
{
struct rt_device *dev = &pdev->parent;
struct pl011 *pl011 = dev->user_data;
rt_dm_dev_unbind_fwdata(dev, RT_NULL);
rt_hw_interrupt_mask(pl011->irq);
rt_pic_detach_irq(pl011->irq, pl011);
rt_device_unregister(&pl011->parent.parent);
pl011_free(pl011);
return RT_EOK;
}
static const struct rt_ofw_node_id pl011_ofw_ids[] =
{
{ .type = "ttyAMA", .compatible = "arm,pl011" },
{ .type = "ttyAMA", .compatible = "arm,pl011-axi" },
{ /* sentinel */ }
};
static struct rt_platform_driver pl011_driver =
{
.name = "serial-pl011",
.ids = pl011_ofw_ids,
.probe = pl011_probe,
.remove = pl011_remove,
};
static int pl011_drv_register(void)
{
rt_platform_driver_register(&pl011_driver);
return 0;
}
INIT_DRIVER_EARLY_EXPORT(pl011_drv_register);

108
bsp/raspberry-pi/raspi-dm2.0/drivers/drv_uart.h Normal file
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@@ -0,0 +1,108 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-16 bigmagic first version
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
/* register's bit*/
#define PL011_FR_RI (1 << 8)
#define PL011_FR_TXFE (1 << 7)
#define PL011_FR_RXFF (1 << 6)
#define PL011_FR_TXFF (1 << 5)
#define PL011_FR_RXFE (1 << 4)
#define PL011_FR_BUSY (1 << 3)
#define PL011_FR_DCD (1 << 2)
#define PL011_FR_DSR (1 << 1)
#define PL011_FR_CTS (1 << 0)
#define PL011_LCRH_SPS (1 << 7)
#define PL011_LCRH_WLEN_8 (3 << 5)
#define PL011_LCRH_WLEN_7 (2 << 5)
#define PL011_LCRH_WLEN_6 (1 << 5)
#define PL011_LCRH_WLEN_5 (0 << 5)
#define PL011_LCRH_FEN (1 << 4)
#define PL011_LCRH_STP2 (1 << 3)
#define PL011_LCRH_EPS (1 << 2)
#define PL011_LCRH_PEN (1 << 1)
#define PL011_LCRH_BRK (1 << 0)
#define PL011_CR_CTSEN (1 << 15)
#define PL011_CR_RTSEN (1 << 14)
#define PL011_CR_RTS (1 << 11)
#define PL011_CR_DTR (1 << 10)
#define PL011_CR_RXE (1 << 9)
#define PL011_CR_TXE (1 << 8)
#define PL011_CR_LBE (1 << 7)
#define PL011_CR_SIRLP (1 << 2)
#define PL011_CR_SIREN (1 << 1)
#define PL011_CR_UARTEN (1 << 0)
#define PL011_IMSC_TXIM (1 << 5)
#define PL011_IMSC_RXIM (1 << 4)
#define PL011_INTERRUPT_OVERRUN_ERROR (1 << 10)
#define PL011_INTERRUPT_BREAK_ERROR (1 << 9)
#define PL011_INTERRUPT_PARITY_ERROR (1 << 8)
#define PL011_INTERRUPT_FRAMING_ERROR (1 << 7)
#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
#define PL011_INTERRUPT_TRANSMIT (1 << 5)
#define PL011_INTERRUPT_RECEIVE (1 << 4)
#define PL011_INTERRUPT_nUARTCTS (1 << 1)
#define PL011_REG_DR(BASE) HWREG32(BASE + 0x00)
#define PL011_REG_RSRECR(BASE) HWREG32(BASE + 0x04)
#define PL011_REG_RESERVED0(BASE) HWREG32(BASE + 0x08)
#define PL011_REG_FR(BASE) HWREG32(BASE + 0x18)
#define PL011_REG_RESERVED1(BASE) HWREG32(BASE + 0x1C)
#define PL011_REG_ILPR(BASE) HWREG32(BASE + 0x20)
#define PL011_REG_IBRD(BASE) HWREG32(BASE + 0x24)
#define PL011_REG_FBRD(BASE) HWREG32(BASE + 0x28)
#define PL011_REG_LCRH(BASE) HWREG32(BASE + 0x2C)
#define PL011_REG_CR(BASE) HWREG32(BASE + 0x30)
#define PL011_REG_IFLS(BASE) HWREG32(BASE + 0x34)
#define PL011_REG_IMSC(BASE) HWREG32(BASE + 0x38)
#define PL011_REG_RIS(BASE) HWREG32(BASE + 0x3C)
#define PL011_REG_MIS(BASE) HWREG32(BASE + 0x40)
#define PL011_REG_ICR(BASE) HWREG32(BASE + 0x44)
#define PL011_REG_DMACR(BASE) HWREG32(BASE + 0x48)
#define PL011_REG_RESERVED2(BASE) HWREG32(BASE + 0x4C)
#define PL011_REG_ITCR(BASE) HWREG32(BASE + 0x80)
#define PL011_REG_ITIP(BASE) HWREG32(BASE + 0x84)
#define PL011_REG_ITOP(BASE) HWREG32(BASE + 0x88)
#define PL011_REG_TDR(BASE) HWREG32(BASE + 0x8C)
/*
* Auxiliary
*/
#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */
#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */
#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */
#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */
#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */
#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */
#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */
#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */
#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */
#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */
#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */
#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */
#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */
#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */
#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */
#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */
#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */
#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */
#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */
#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */
int rt_hw_uart_init(void);
void rt_hw_earlycon_ioremap_early(void);
#endif /* DRV_UART_H__ */

3
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/Kconfig Normal file
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@@ -0,0 +1,3 @@
menuconfig RT_USING_SDHCI
bool "Using sdhci for sd/mmc drivers"
default n

18
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/SConscript Normal file
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@@ -0,0 +1,18 @@
from building import *
group = []
if not GetDepend(['RT_USING_SDHCI']):
Return('group')
cwd = GetCurrentDir()
CPPPATH = [cwd + '/include']
src = []
src += Glob('*.c')
src += Glob('src/*.c')
src += Glob('sdhci-platform/*.c')
group = DefineGroup('sdhci-drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

74
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/include/sdhci-platform.h Normal file
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@@ -0,0 +1,74 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#ifndef _DRIVERS_MMC_SDHCI_PLTFM_H
#define _DRIVERS_MMC_SDHCI_PLTFM_H
#include <rtthread.h>
#include <drivers/core/dm.h>
#include <drivers/ofw.h>
#include <drivers/platform.h>
#include <drivers/clk.h>
#include "sdhci.h"
struct sdhci_pltfm_data
{
const struct sdhci_ops *ops;
unsigned int quirks;
unsigned int quirks2;
};
struct sdhci_pltfm_host
{
struct rt_clk *clk;
/* migrate from sdhci_of_host */
unsigned int clock;
rt_uint64_t xfer_mode_shadow;
unsigned long private[];
};
void sdhci_get_property(struct rt_platform_device *pdev);
static inline void sdhci_get_of_property(struct rt_platform_device *pdev)
{
return sdhci_get_property(pdev);
}
extern struct sdhci_host *sdhci_pltfm_init(struct rt_platform_device *pdev,
const struct sdhci_pltfm_data *pdata,
size_t priv_size);
extern void sdhci_pltfm_free(struct rt_platform_device *pdev);
extern int sdhci_pltfm_init_and_add_host(struct rt_platform_device *pdev,
const struct sdhci_pltfm_data *pdata,
size_t priv_size);
extern void sdhci_pltfm_remove(struct rt_platform_device *pdev);
extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)
{
return host->private;
}
extern const struct dev_pm_ops sdhci_pltfm_pmops;
static inline int sdhci_pltfm_suspend(struct rt_device *dev)
{
return 0;
}
static inline int sdhci_pltfm_resume(struct rt_device *dev)
{
return 0;
}
#endif

815
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/include/sdhci.h Normal file
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File diff suppressed because it is too large Load Diff

31
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/include/sdhci_dma.h Normal file
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@@ -0,0 +1,31 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#ifndef __SDHCI_DMA_H__
#define __SDHCI_DMA_H__
#include "ioremap.h"
#include <mm_aspace.h>
enum dma_data_direction
{
DMA_BIDIRECTIONAL = 0,
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
DMA_NONE = 3,
};
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL << (n)) - 1))
int dma_set_mask_and_coherent(struct rt_device *dev, rt_uint64_t mask);
unsigned long virt_to_phys(volatile void *address);
void *dma_alloc_coherent(struct rt_device *dev, size_t size,
rt_uint64_t *dma_handle);
void dma_free_coherent(struct rt_device *dev, size_t size,
void *cpu_addr, unsigned long dma_handle);
#endif

411
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/include/sdhci_host.h Normal file
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@@ -0,0 +1,411 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#ifndef __SDHCI_MMC_H__
#define __SDHCI_MMC_H__
#include <rtthread.h>
#include <drivers/mmcsd_cmd.h>
#include <drivers/dev_mmcsd_core.h>
#include <drivers/mmcsd_host.h>
#include "sdhci_dma.h"
#define mmc_dev(x) ((x)->parent)
#define MMC_SEND_TUNING_BLOCK_HS200 SEND_TUNING_BLOCK_HS200
#define MMC_SEND_TUNING_BLOCK SEND_TUNING_BLOCK
#define MMC_STOP_TRANSMISSION STOP_TRANSMISSION
#define MMC_BUS_TEST_R 14 /* adtc R1 */
#define MMC_WRITE_MULTIPLE_BLOCK WRITE_MULTIPLE_BLOCK
#define MMC_READ_MULTIPLE_BLOCK READ_MULTIPLE_BLOCK
#define MMC_TIMING_UHS_DDR50 MMCSD_TIMING_UHS_DDR50
#define MMC_TIMING_UHS_SDR50 MMCSD_TIMING_UHS_SDR50
#define MMC_TIMING_MMC_HS200 MMCSD_TIMING_MMC_HS200
#define MMC_TIMING_MMC_HS400 MMCSD_TIMING_MMC_HS400
#define MMC_TIMING_UHS_SDR104 MMCSD_TIMING_UHS_SDR104
#define MMC_TIMING_UHS_SDR25 MMCSD_TIMING_UHS_SDR25
#define MMC_TIMING_MMC_DDR52 MMCSD_TIMING_MMC_DDR52
#define MMC_TIMING_UHS_SDR12 MMCSD_TIMING_UHS_SDR12
#define MMC_TIMING_SD_HS MMCSD_TIMING_SD_HS
#define MMC_TIMING_MMC_HS MMCSD_TIMING_MMC_HS
#define MMC_POWER_OFF MMCSD_POWER_OFF
#define MMC_POWER_UP MMCSD_POWER_UP
#define MMC_POWER_ON MMCSD_POWER_ON
#define MMC_POWER_UNDEFINED 3
#define MMC_SET_DRIVER_TYPE_B 0
#define MMC_SET_DRIVER_TYPE_A 1
#define MMC_SET_DRIVER_TYPE_C 2
#define MMC_SET_DRIVER_TYPE_D 3
#define MMC_SIGNAL_VOLTAGE_330 0
#define MMC_SIGNAL_VOLTAGE_180 1
#define MMC_SIGNAL_VOLTAGE_120 2
#define MMC_RSP_PRESENT (1 << 16)
#define MMC_RSP_136 (1 << 17) /* 136 bit response */
#define MMC_RSP_CRC (1 << 18) /* expect valid crc */
#define MMC_RSP_BUSY (1 << 19) /* card may send busy */
#define MMC_RSP_OPCODE (1 << 20) /* response contains opcode */
/*
* These are the native response types, and correspond to valid bit
* patterns of the above flags. One additional valid pattern
* is all zeros, which means we don't expect a response.
*/
#define MMC_RSP_NONE (0)
#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
#define MMC_CMD_ADTC CMD_ADTC
#define MMC_BUS_WIDTH_8 MMCSD_BUS_WIDTH_8
#define MMC_BUS_WIDTH_4 MMCSD_BUS_WIDTH_4
#define MMC_BUS_WIDTH_1 MMCSD_BUS_WIDTH_1
#define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */
#define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */
enum mmc_blk_status
{
MMC_BLK_SUCCESS = 0,
MMC_BLK_PARTIAL,
MMC_BLK_CMD_ERR,
MMC_BLK_RETRY,
MMC_BLK_ABORT,
MMC_BLK_DATA_ERR,
MMC_BLK_ECC_ERR,
MMC_BLK_NOMEDIUM,
MMC_BLK_NEW_REQUEST,
};
/************************************************************************************************ */
#define MMC_NUM_CLK_PHASES (MMC_TIMING_MMC_HS400 + 1)
struct mmc_host;
struct mmc_host_ops
{
/*
* It is optional for the host to implement pre_req and post_req in
* order to support double buffering of requests (prepare one
* request while another request is active).
* pre_req() must always be followed by a post_req().
* To undo a call made to pre_req(), call post_req() with
* a nonzero err condition.
*/
void (*post_req)(struct mmc_host *host, struct rt_mmcsd_req *req,
int err);
void (*pre_req)(struct mmc_host *host, struct rt_mmcsd_req *req);
void (*request)(struct mmc_host *host, struct rt_mmcsd_req *req);
/*
* Avoid calling the next three functions too often or in a "fast
* path", since underlaying controller might implement them in an
* expensive and/or slow way. Also note that these functions might
* sleep, so don't call them in the atomic contexts!
*/
/*
* Notes to the set_ios callback:
* ios->clock might be 0. For some controllers, setting 0Hz
* as any other frequency works. However, some controllers
* explicitly need to disable the clock. Otherwise e.g. voltage
* switching might fail because the SDCLK is not really quiet.
*/
void (*set_ios)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
/*
* Return values for the get_ro callback should be:
* 0 for a read/write card
* 1 for a read-only card
* -ENOSYS when not supported (equal to NULL callback)
* or a negative errno value when something bad happened
*/
int (*get_ro)(struct mmc_host *host);
/*
* Return values for the get_cd callback should be:
* 0 for a absent card
* 1 for a present card
* -ENOSYS when not supported (equal to NULL callback)
* or a negative errno value when something bad happened
*/
int (*get_cd)(struct mmc_host *host);
void (*enable_sdio_irq)(struct mmc_host *host, int enable);
/* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */
void (*ack_sdio_irq)(struct mmc_host *host);
int (*start_signal_voltage_switch)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
/* Check if the card is pulling dat[0:3] low */
int (*card_busy)(struct mmc_host *host);
/* The tuning command opcode value is different for SD and eMMC cards */
int (*execute_tuning)(struct mmc_host *host, unsigned opcode);
/* Prepare HS400 target operating frequency depending host driver */
int (*prepare_hs400_tuning)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
/* Prepare switch to DDR during the HS400 init sequence */
int (*hs400_prepare_ddr)(struct mmc_host *host);
/* Prepare for switching from HS400 to HS200 */
void (*hs400_downgrade)(struct mmc_host *host);
/* Complete selection of HS400 */
void (*hs400_complete)(struct mmc_host *host);
/* Prepare enhanced strobe depending host driver */
void (*hs400_enhanced_strobe)(struct mmc_host *host,
struct rt_mmcsd_io_cfg *ios);
/* Reset the eMMC card via RST_n */
void (*hw_reset)(struct mmc_host *host);
void (*card_event)(struct mmc_host *host);
};
struct regulator;
struct mmc_pwrseq;
struct mmc_supply
{
struct regulator *vmmc; /* Card power supply */
struct regulator *vqmmc; /* Optional Vccq supply */
};
struct mmc_ctx
{
struct task_struct *task;
};
/* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
#define MMC_CAP2_HS200_1_8V_SDR MMCSD_SUP_HS200_1V8
#define MMC_CAP_4_BIT_DATA MMCSD_BUSWIDTH_4
#define MMC_CAP_8_BIT_DATA MMCSD_BUSWIDTH_8
#define MMC_CAP2_HS200 MMCSD_SUP_HS200
#define MMC_CAP_MMC_HIGHSPEED MMCSD_SUP_HIGHSPEED
#define MMC_CAP_SD_HIGHSPEED MMCSD_SUP_HIGHSPEED
#define MMC_CAP_1_8V_DDR MMCSD_SUP_DDR_1V8
#define MMC_CAP_3_3V_DDR MMCSD_SUP_DDR_3V3
#define MMC_CAP_1_2V_DDR MMCSD_SUP_DDR_1V2
#define MMC_CAP_NONREMOVABLE MMCSD_SUP_NONREMOVABLE
#define MMC_CAP_UHS_DDR50 0
#define MMC_CAP2_HS400 0
#define MMC_CAP_UHS_SDR50 0
#define MMC_CAP_UHS_SDR25 0
#define MMC_CAP_UHS_SDR12 0
#define MMC_CAP_UHS_SDR104 0
#define MMC_CAP_UHS 0
#define MMC_CAP2_HSX00_1_8V 0
#define MMC_CAP2_HS400_ES 0
#define MMC_CAP_NEEDS_POLL 0
#define MMC_CAP2_HSX00_1_2V 0
#define MMC_CAP2_HS400_1_8V 0
#define MMC_CAP_DRIVER_TYPE_D 0
#define MMC_CAP_DRIVER_TYPE_C 0
#define MMC_SET_DRIVER_TYPE_B 0
#define MMC_CAP_DRIVER_TYPE_A 0
#define MMC_CAP2_SDIO_IRQ_NOTHREAD 0
#define MMC_CAP_CMD23 0
#define MMC_CAP_SDIO_IRQ 0
#define MMC_CAP2_NO_SDIO (1 << 19)
#define MMC_CAP2_NO_SD (1 << 21)
#define MMC_CAP2_NO_MMC (1 << 22)
#define MMC_CAP2_CQE (1 << 23)
#define MMC_VDD_165_195 VDD_165_195
#define MMC_VDD_20_21 VDD_20_21
#define MMC_VDD_29_30 VDD_29_30
#define MMC_VDD_30_31 VDD_30_31
#define MMC_VDD_32_33 VDD_32_33
#define MMC_VDD_33_34 VDD_33_34
struct mmc_host
{
struct rt_mmcsd_host rthost;
struct rt_device *parent;
int index;
const struct mmc_host_ops *ops;
unsigned int f_min;
unsigned int f_max;
unsigned int f_init;
rt_uint32_t ocr_avail;
rt_uint32_t ocr_avail_sdio; /* SDIO-specific OCR */
rt_uint32_t ocr_avail_sd; /* SD-specific OCR */
rt_uint32_t ocr_avail_mmc; /* MMC-specific OCR */
struct wakeup_source *ws; /* Enable consume of uevents */
rt_uint32_t max_current_330;
rt_uint32_t max_current_300;
rt_uint32_t max_current_180;
rt_uint32_t caps; /* Host capabilities */
rt_uint32_t caps2; /* More host capabilities */
/* host specific block data */
unsigned int max_seg_size; /* see blk_queue_max_segment_size */
unsigned short max_segs; /* see blk_queue_max_segments */
unsigned short unused;
unsigned int max_req_size; /* maximum number of bytes in one req */
unsigned int max_blk_size; /* maximum size of one mmc block */
unsigned int max_blk_count; /* maximum number of blocks in one req */
unsigned int max_busy_timeout; /* max busy timeout in ms */
struct rt_mmcsd_io_cfg ios; /* current io bus settings */
unsigned int retune_period;
/* group bitfields together to minimize padding */
unsigned int use_spi_crc : 1;
unsigned int claimed : 1; /* host exclusively claimed */
unsigned int doing_init_tune : 1; /* initial tuning in progress */
unsigned int can_retune : 1; /* re-tuning can be used */
unsigned int doing_retune : 1; /* re-tuning in progress */
unsigned int retune_now : 1; /* do re-tuning at next req */
unsigned int retune_paused : 1; /* re-tuning is temporarily disabled */
unsigned int retune_crc_disable : 1; /* don't trigger retune upon crc */
unsigned int can_dma_map_merge : 1; /* merging can be used */
unsigned int vqmmc_enabled : 1; /* vqmmc regulator is enabled */
int need_retune; /* re-tuning is needed */
int hold_retune; /* hold off re-tuning */
rt_bool_t trigger_card_event; /* card_event necessary */
unsigned int sdio_irqs;
rt_bool_t sdio_irq_pending;
struct led_trigger *led; /* activity led */
struct mmc_supply supply;
/* Ongoing data transfer that allows commands during transfer */
struct rt_mmcsd_req *ongoing_mrq;
unsigned int actual_clock; /* Actual HC clock rate */
rt_uint32_t pm_caps;
unsigned long private[];
};
static inline int mmc_card_is_removable(struct mmc_host *host)
{
return !(host->caps & MMC_CAP_NONREMOVABLE);
}
struct device_node;
struct mmc_host *mmc_alloc_host(int extra, struct rt_device *);
int mmc_add_host(struct mmc_host *);
void mmc_remove_host(struct mmc_host *);
void mmc_free_host(struct mmc_host *);
int mmc_of_parse(struct mmc_host *host);
int mmc_of_parse_voltage(struct mmc_host *host, rt_uint32_t *mask);
static inline void *mmc_priv(struct mmc_host *host)
{
return (void *)host->private;
}
#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
#define mmc_dev(x) ((x)->parent)
#define mmc_classdev(x) (&(x)->class_dev)
#define mmc_hostname(x) (x->parent->parent.name)
void mmc_detect_change(struct mmc_host *, unsigned long delay);
void mmc_request_done(struct mmc_host *, struct rt_mmcsd_req *);
void mmc_command_done(struct mmc_host *host, struct rt_mmcsd_req *mrq);
void mmc_cqe_request_done(struct mmc_host *host, struct rt_mmcsd_req *mrq);
/*
* May be called from host driver's system/runtime suspend/resume callbacks,
* to know if SDIO IRQs has been claimed.
*/
static inline rt_bool_t sdio_irq_claimed(struct mmc_host *host)
{
return host->sdio_irqs > 0;
}
static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
struct regulator *supply,
unsigned short vdd_bit)
{
return 0;
}
int mmc_regulator_get_supply(struct mmc_host *mmc);
int mmc_regulator_enable_vqmmc(struct mmc_host *mmc);
void mmc_regulator_disable_vqmmc(struct mmc_host *mmc);
void mmc_retune_timer_stop(struct mmc_host *host);
static inline void mmc_retune_needed(struct mmc_host *host)
{
if (host->can_retune)
host->need_retune = 1;
}
static inline rt_bool_t mmc_can_retune(struct mmc_host *host)
{
return host->can_retune == 1;
}
static inline rt_bool_t mmc_doing_retune(struct mmc_host *host)
{
return host->doing_retune == 1;
}
static inline rt_bool_t mmc_doing_tune(struct mmc_host *host)
{
return host->doing_retune == 1 || host->doing_init_tune == 1;
}
static inline int mmc_get_dma_dir(struct rt_mmcsd_data *data)
{
return data->flags & DATA_DIR_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
}
static inline rt_bool_t mmc_op_multi(rt_uint32_t opcode)
{
return opcode == MMC_WRITE_MULTIPLE_BLOCK || opcode == MMC_READ_MULTIPLE_BLOCK;
}
static inline rt_bool_t mmc_op_tuning(rt_uint32_t opcode)
{
return opcode == MMC_SEND_TUNING_BLOCK || opcode == MMC_SEND_TUNING_BLOCK_HS200;
}
int mmc_gpio_get_cd(struct mmc_host *host);
void mmc_detect_change(struct mmc_host *host, unsigned long delay);
int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios);
rt_bool_t mmc_can_gpio_ro(struct mmc_host *host);
int mmc_gpio_get_ro(struct mmc_host *host);
int mmc_send_tuning(struct mmc_host *host, rt_uint32_t opcode, int *cmd_error);
int mmc_send_abort_tuning(struct mmc_host *host, rt_uint32_t opcode);
int mmc_of_parse(struct mmc_host *host);
#endif

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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#ifndef __SDHCI_MISC_H__
#define __SDHCI_MISC_H__
#include "sdhci_host.h"
#define __BF_FIELD_CHECK(...)
#define __bf_shf(x) (__builtin_ffsll(x) - 1)
#define FIELD_GET(_mask, _reg) \
({ \
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
(typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
})
#define FIELD_PREP(_mask, _val) \
({ \
__BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
})
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define min_t(type, x, y) (((type)x < (type)y) ? x : y)
#define max_t(type, x, y) (((type)x > (type)y) ? x : y)
#define min(x, y) ((x) < (y) ? (x) : (y))
#define from_timer(var, callback_timer, timer_fieldname) \
container_of(callback_timer, typeof(*var), timer_fieldname)
#define le32_to_cpu(x) (x)
#define le16_to_cpu(x) (x)
#define cpu_to_le16(x) (x)
#define cpu_to_le32(x) (x)
#define lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff))
#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16))
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define do_div(n, base) ({ \
uint32_t __base = (base); \
uint32_t __rem; \
__rem = ((uint64_t)(n)) % __base; \
(n) = ((uint64_t)(n)) / __base; \
__rem; \
})
#define fallthrough \
do { \
} while (0)
int regulator_is_supported_voltage(struct regulator *regulator,
int min_uV, int max_uV);
int regulator_enable(struct regulator *regulator);
rt_bool_t mmc_can_gpio_cd(struct mmc_host *host);
struct regulator
{
const char *supply_name;
};
int regulator_get_current_limit(struct regulator *regulator);
int regulator_enable(struct regulator *regulator);
void regulator_disable(struct regulator *regulator);
#endif

125
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/sdhci-platform/sdhci-platform.c Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#include "sdhci-platform.h"
static const struct sdhci_ops sdhci_pltfm_ops = {
.set_clock = sdhci_set_clock,
.set_bus_width = sdhci_set_bus_width,
.reset = sdhci_reset,
.set_uhs_signaling = sdhci_set_uhs_signaling,
};
void sdhci_get_property(struct rt_platform_device *pdev)
{
struct rt_device *dev = &pdev->parent;
struct sdhci_host *host = pdev->priv;
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
rt_uint32_t bus_width;
if (rt_dm_dev_prop_read_bool(dev, "sdhci,auto-cmd12"))
host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
if (rt_dm_dev_prop_read_bool(dev, "sdhci,1-bit-only") || (rt_dm_dev_prop_read_u32(dev, "bus-width", &bus_width) == 0 && bus_width == 1))
host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
if (rt_dm_dev_prop_read_bool(dev, "broken-cd"))
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
if (rt_dm_dev_prop_read_bool(dev, "no-1-8-v"))
host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
rt_dm_dev_prop_read_u32(dev, "clock-frequency", &pltfm_host->clock);
if (rt_dm_dev_prop_read_bool(dev, "keep-power-in-suspend"))
host->mmc->pm_caps |= MMC_PM_KEEP_POWER;
if (rt_dm_dev_prop_read_bool(dev, "wakeup-source") || rt_dm_dev_prop_read_bool(dev, "enable-sdio-wakeup")) /* legacy */
host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
}
struct sdhci_host *sdhci_pltfm_init(struct rt_platform_device *pdev,
const struct sdhci_pltfm_data *pdata,
size_t priv_size)
{
struct sdhci_host *host;
struct rt_device *dev = &pdev->parent;
void *ioaddr;
int irq;
ioaddr = rt_dm_dev_iomap(dev, 0);
if (!ioaddr)
{
return RT_NULL;
}
irq = rt_dm_dev_get_irq(dev, 0);
if (irq < 0)
{
return RT_NULL;
}
host = sdhci_alloc_host(dev, priv_size);
if (!host)
{
return RT_NULL;
}
host->irq = irq;
host->ioaddr = ioaddr;
host->hw_name = rt_dm_dev_get_name(dev);
if (pdata && pdata->ops)
host->ops = pdata->ops;
else
host->ops = &sdhci_pltfm_ops;
if (pdata)
{
host->quirks = pdata->quirks;
host->quirks2 = pdata->quirks2;
}
pdev->priv = host;
return host;
}
int sdhci_pltfm_init_and_add_host(struct rt_platform_device *pdev,
const struct sdhci_pltfm_data *pdata,
size_t priv_size)
{
struct sdhci_host *host;
int ret = 0;
host = sdhci_pltfm_init(pdev, pdata, priv_size);
if (!host)
return -RT_ERROR;
sdhci_get_property(pdev);
ret = sdhci_add_host(host);
if (ret)
sdhci_pltfm_free(pdev);
return ret;
}
void sdhci_pltfm_free(struct rt_platform_device *pdev)
{
struct sdhci_host *host = pdev->priv;
sdhci_free_host(host);
}
void sdhci_pltfm_remove(struct rt_platform_device *pdev)
{
struct sdhci_host *host = pdev->priv;
int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
sdhci_remove_host(host, dead);
sdhci_pltfm_free(pdev);
}

3606
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/sdhci.c Normal file
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303
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/src/fit-mmc.c Normal file
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/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#include <rtthread.h>
#include "sdhci.h"
#include <rtdbg.h>
#include <mmu.h>
#include <drivers/core/dm.h>
static void plat_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
struct mmc_host *mmc = (struct mmc_host *)host;
rt_uint32_t flags = req->cmd->flags;
switch (flags & RESP_MASK)
{
case RESP_NONE:
flags |= MMC_RSP_NONE;
break;
case RESP_R1:
flags |= MMC_RSP_R1;
break;
case RESP_R1B:
flags |= MMC_RSP_R1B;
break;
case RESP_R2:
flags |= MMC_RSP_R2;
break;
case RESP_R3:
flags |= MMC_RSP_R3;
break;
case RESP_R4:
flags |= MMC_RSP_R4;
break;
case RESP_R5:
flags |= MMC_RSP_R5;
break;
case RESP_R6:
flags |= MMC_RSP_R6;
break;
case RESP_R7:
flags |= MMC_RSP_R7;
break;
}
if (req->data)
{
if ((rt_uint64_t)rt_kmem_v2p(req->data->buf) > 0xffffffff)
{
void *dma_buffer = rt_malloc(ARCH_PAGE_SIZE);
void *req_buf = NULL;
if (req->data->blks * req->data->blksize > ARCH_PAGE_SIZE)
{
dma_buffer = rt_realloc(dma_buffer, req->data->blks * req->data->blksize);
}
if (req->data->flags & DATA_DIR_WRITE)
{
rt_memcpy(dma_buffer, req->data->buf, req->data->blks * req->data->blksize);
req->data->buf = dma_buffer;
}
else if (req->data->flags & DATA_DIR_READ)
{
req_buf = req->data->buf;
req->data->buf = dma_buffer;
}
req->cmd->flags |= flags;
mmc->ops->request(mmc, req);
rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER);
if (req->data->flags & DATA_DIR_READ)
{
rt_memcpy(req_buf, dma_buffer, req->data->blksize * req->data->blks);
req->data->buf = req_buf;
}
rt_free(dma_buffer);
rt_sem_release(&host->sem_ack);
}
else
{
req->cmd->flags |= flags;
mmc->ops->request(mmc, req);
}
}
else
{
req->cmd->flags |= flags;
mmc->ops->request(mmc, req);
}
}
static void plat_set_ioconfig(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *iocfg)
{
struct mmc_host *mmc = (struct mmc_host *)host;
LOG_D("clock:%d,width:%d,power:%d,vdd:%d,timing:%d\n",
iocfg->clock, iocfg->bus_width,
iocfg->power_mode, iocfg->vdd, iocfg->timing);
mmc->ops->set_ios(mmc, iocfg);
}
static rt_int32_t plat_get_card_status(struct rt_mmcsd_host *host)
{
struct mmc_host *mmc = (struct mmc_host *)host;
return mmc->ops->get_cd(mmc);
}
static rt_int32_t plat_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode)
{
struct mmc_host *mmc = (struct mmc_host *)host;
return mmc->ops->execute_tuning(mmc, opcode);
}
static void plat_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
{
struct mmc_host *mmc = (struct mmc_host *)host;
return mmc->ops->enable_sdio_irq(mmc, en);
}
static const struct rt_mmcsd_host_ops rt_mmcsd_ops = {
.request = plat_request,
.set_iocfg = plat_set_ioconfig,
.get_card_status = plat_get_card_status,
.enable_sdio_irq = plat_enable_sdio_irq,
.execute_tuning = plat_execute_tuning,
};
void mmc_request_done(struct mmc_host *host, struct rt_mmcsd_req *mrq)
{
mmcsd_req_complete(&host->rthost);
}
/*add host in rtt while sdhci complete*/
int mmc_add_host(struct mmc_host *mmc)
{
mmc->rthost.ops = &rt_mmcsd_ops;
mmc->rthost.flags = mmc->caps;
mmc->rthost.freq_max = mmc->f_max;
mmc->rthost.freq_min = 400000;
mmc->rthost.max_dma_segs = mmc->max_segs;
mmc->rthost.max_seg_size = mmc->max_seg_size;
mmc->rthost.max_blk_size = mmc->max_blk_size;
mmc->rthost.max_blk_count = mmc->max_blk_count;
mmc->rthost.valid_ocr = VDD_33_34 | VDD_32_33 | VDD_31_32 | VDD_30_31 | VDD_165_195 | VDD_20_21;
mmcsd_change(&mmc->rthost);
return 0;
}
struct mmc_host *mmc_alloc_host(int extra, struct rt_device *dev)
{
struct mmc_host *mmc;
mmc = rt_malloc(sizeof(*mmc) + extra);
if (mmc)
{
rt_memset(mmc, 0, sizeof(*mmc) + extra);
mmc->parent = dev;
mmcsd_host_init(&mmc->rthost);
}
return mmc;
}
void mmc_remove_host(struct mmc_host *host)
{
rt_free(host);
}
int mmc_abort_tuning(struct mmc_host *host, rt_uint32_t opcode)
{
return 0;
}
int mmc_gpio_get_cd(struct mmc_host *host)
{
return -ENOSYS;
}
void mmc_detect_change(struct mmc_host *host, unsigned long delay)
{
}
int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios)
{
return 0;
}
rt_bool_t mmc_can_gpio_ro(struct mmc_host *host)
{
return RT_FALSE;
}
int mmc_gpio_get_ro(struct mmc_host *host)
{
return 0;
}
int mmc_send_abort_tuning(struct mmc_host *host, rt_uint32_t opcode)
{
return 0;
}
int mmc_of_parse(struct mmc_host *host)
{
struct rt_device *dev = host->parent;
rt_uint32_t bus_width;
if (!dev || !dev->ofw_node)
return 0;
/* "bus-width" is translated to MMC_CAP_*_BIT_DATA flags */
if (rt_dm_dev_prop_read_u32(dev, "bus-width", &bus_width) < 0)
{
bus_width = 1;
}
switch (bus_width)
{
case 8:
host->caps |= MMC_CAP_8_BIT_DATA;
break; /* Hosts capable of 8-bit can also do 4 bits */
case 4:
host->caps |= MMC_CAP_4_BIT_DATA;
break;
case 1:
break;
default:
return -EINVAL;
}
/* f_max is obtained from the optional "max-frequency" property */
rt_dm_dev_prop_read_u32(dev, "max-frequency", &host->f_max);
if (rt_dm_dev_prop_read_bool(dev, "cap-mmc-highspeed"))
{
host->caps |= MMC_CAP_MMC_HIGHSPEED;
}
if (rt_dm_dev_prop_read_bool(dev, "mmc-hs200-1_8v"))
{
host->caps |= MMC_CAP2_HS200_1_8V_SDR;
}
if (rt_dm_dev_prop_read_bool(dev, "non-removable"))
{
host->caps |= MMC_CAP_NONREMOVABLE;
}
if (rt_dm_dev_prop_read_bool(dev, "no-sdio"))
{
host->caps2 |= MMC_CAP2_NO_SDIO;
}
if (rt_dm_dev_prop_read_bool(dev, "no-sd"))
{
host->caps2 |= MMC_CAP2_NO_SD;
}
if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-3_3v"))
{
host->caps |= MMC_CAP_3_3V_DDR;
}
if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-1_8v"))
{
host->caps |= MMC_CAP_1_8V_DDR;
}
if (rt_dm_dev_prop_read_bool(dev, "mmc-ddr-1_2v"))
{
host->caps |= MMC_CAP_1_2V_DDR;
}
return 0;
}
void mmc_free_host(struct mmc_host *host)
{
}
rt_bool_t mmc_can_gpio_cd(struct mmc_host *host)
{
return RT_FALSE;
}

44
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/src/sdhci_dma.c Normal file
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@@ -0,0 +1,44 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#include "sdhci.h"
#include <rtthread.h>
int dma_set_mask_and_coherent(struct rt_device *dev, rt_uint64_t mask)
{
return 0;
}
unsigned long virt_to_phys(volatile void *address)
{
return (unsigned long)((rt_uint64_t)address + PV_OFFSET);
}
void *dma_alloc_coherent(struct rt_device *dev, size_t size,
rt_uint64_t *dma_handle)
{
void *v;
v = rt_malloc_align(size, 2048);
rt_kprintf("v = %p \n", v);
if (v)
{
*dma_handle = virt_to_phys(v);
v = rt_ioremap((void *)*dma_handle, size);
rt_kprintf("v = %p *dma_handle = %p \n", v, *dma_handle);
}
return v;
}
void dma_free_coherent(struct rt_device *dev, size_t size,
void *cpu_addr, unsigned long dma_handle)
{
rt_free(cpu_addr);
}

37
bsp/raspberry-pi/raspi-dm2.0/drivers/sdhci/src/sdhci_voltage.c Normal file
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@@ -0,0 +1,37 @@
/*
* Copyright (c) 2006-2024 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-08-16 zhujiale first version
*/
#include "sdhci.h"
int mmc_regulator_get_supply(struct mmc_host *mmc)
{
mmc->supply.vmmc = -RT_NULL;
mmc->supply.vqmmc = -RT_NULL;
return 0;
}
int regulator_get_current_limit(struct regulator *regulator)
{
return 0;
}
int regulator_is_supported_voltage(struct regulator *regulator,
int min_uV, int max_uV)
{
return 0;
}
int regulator_enable(struct regulator *regulator)
{
return 0;
}
void regulator_disable(struct regulator *regulator)
{
}

9
bsp/raspberry-pi/raspi-dm2.0/qemu.sh Normal file
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@@ -0,0 +1,9 @@
if [ ! -f "sd.bin" ]; then
dd if=/dev/zero of=sd.bin bs=1024 count=65536
fi
qemu-system-aarch64 -M raspi4b -serial stdio \
-kernel rtthread.bin \
-drive if=sd,file=sd.bin \
-dtb bcm2711-rpi-4-b.dtb \
-append 'printk.time=0 earlycon=pl011,0xfe201000 console=ttyAMA0 root=ram0 rw'

575
bsp/raspberry-pi/raspi-dm2.0/rtconfig.h Normal file
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54
bsp/raspberry-pi/raspi-dm2.0/rtconfig.py Normal file
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import os
# toolchains options
ARCH ='aarch64'
CPU ='cortex-a'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CPP = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -march=armv8-a -mtune=cortex-a72 -fdiagnostics-color=always'
CPPFLAGS = ' -E -P -x assembler-with-cpp'
CFLAGS = DEVICE + ' -Wall -Wno-cpp -D_POSIX_SOURCE'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -ggdb'
AFLAGS += ' -ggdb'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'