Add bsp apollo2

bsp/apollo2/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/apollo2/SConstruct

@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread_apollo2.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/apollo2/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/apollo2/applications/application.c

@@ -0,0 +1,95 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+
+/**
+ * @addtogroup APOLLO2
+ */
+/*@{*/
+
+#include <rtthread.h>
+#include <stdint.h>
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+#include "hw_led.h"
+
+ALIGN(RT_ALIGN_SIZE)
+static rt_uint8_t led_stack[ 512 ];
+static struct rt_thread led_thread;
+
+static void led_thread_entry(void* parameter)
+{
+    unsigned int count=0;
+
+		rt_hw_led_init(0);
+		rt_hw_led_init(1);
+	
+    while (1)
+    {
+        /* led1 on */
+#ifndef RT_USING_FINSH
+        rt_kprintf("led on, count : %d\r\n",count);
+#endif
+        count++;
+        rt_hw_led_on(0);
+        rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
+
+        /* led1 off */
+#ifndef RT_USING_FINSH
+        rt_kprintf("led off\r\n");
+#endif
+        rt_hw_led_off(0);
+        rt_thread_delay( RT_TICK_PER_SECOND/2 );
+    }
+}
+
+void rt_init_thread_entry(void* parameter)
+{
+		#ifdef RT_USING_COMPONENTS_INIT
+		/* initialization RT-Thread Components */
+		rt_components_init();
+		#endif	
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t init_thread;
+
+    rt_err_t result;
+
+    /* init led thread */
+    result = rt_thread_init(&led_thread,
+                            "led",
+                            led_thread_entry,
+                            RT_NULL,
+                            (rt_uint8_t*)&led_stack[0],
+                            sizeof(led_stack),
+                            7,
+                            5);
+    if (result == RT_EOK)
+    {
+        rt_thread_startup(&led_thread);
+    }
+		
+    init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024,
+                            RT_THREAD_PRIORITY_MAX / 3, 20);
+    if (init_thread != RT_NULL)
+        rt_thread_startup(init_thread);
+
+    return 0;
+}
+
+/*@}*/

bsp/apollo2/applications/startup.c

@@ -0,0 +1,93 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2015, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-11     Haley        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+/**
+ * @addtogroup Apollo2
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define AM_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define AM_SRAM_BEGIN    (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define NRF_SRAM_BEGIN    (&__bss_end)
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init tick */
+    rt_system_tick_init();
+
+    /* init kernel object */
+    rt_system_object_init();
+
+    /* init timer system */
+    rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)AM_SRAM_BEGIN, (void*)AM_SRAM_END);
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    // rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/apollo2/board/Sconscript

@@ -0,0 +1,14 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/apollo2/board/board.c

@@ -0,0 +1,146 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        first implementation
+ */
+#include "board.h"
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "am_mcu_apollo.h"
+#include "hal/am_hal_clkgen.h"
+#include "hal/am_hal_cachectrl.h"
+#include "hw_uart.h"
+
+#define TICK_RATE_HZ  RT_TICK_PER_SECOND
+#define SYSTICK_CLOCK_HZ  ( 32768UL )
+#define WAKE_INTERVAL ( (uint32_t) ((SYSTICK_CLOCK_HZ / TICK_RATE_HZ)) )
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void am_stimer_cmpr0_isr(void)
+{
+    /* Check the timer interrupt status */
+    am_hal_stimer_int_clear(AM_HAL_STIMER_INT_COMPAREA);
+    am_hal_stimer_compare_delta_set(0, WAKE_INTERVAL);
+	
+    if (rt_thread_self() != RT_NULL)
+    {
+    	/* enter interrupt */
+    	rt_interrupt_enter();
+
+    	rt_tick_increase();
+
+    	/* leave interrupt */
+    	rt_interrupt_leave();
+    }
+}
+
+/**
+ * This is the SysTick Configure.
+ *
+ */
+void SysTick_Configuration(void)
+{
+		/* Set the main clk */
+    am_hal_clkgen_sysclk_select(AM_HAL_CLKGEN_SYSCLK_MAX);
+	
+    /* Enable compare A interrupt in STIMER */
+    am_hal_stimer_int_enable(AM_HAL_STIMER_INT_COMPAREA);
+
+    /* Enable the timer interrupt in the NVIC */
+    am_hal_interrupt_enable(AM_HAL_INTERRUPT_STIMER_CMPR0);
+
+    /* Configure the STIMER and run */
+    am_hal_stimer_config(AM_HAL_STIMER_CFG_CLEAR | AM_HAL_STIMER_CFG_FREEZE);
+    am_hal_stimer_compare_delta_set(0, WAKE_INTERVAL);
+    am_hal_stimer_config(AM_HAL_STIMER_XTAL_32KHZ |
+                         AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
+}
+
+/**
+ * This is the CacheCtrl Enable.
+ *
+ */
+void CacheCtrl_Enable(void)
+{
+    am_hal_cachectrl_enable(&am_hal_cachectrl_defaults);
+}
+
+/**
+ * This is the low power operation.
+ * This function enables several power-saving features of the MCU, and
+ * disables some of the less-frequently used peripherals. It also sets the
+ * system clock to 24 MHz.
+ */
+void am_low_power_init(void)
+{
+    /* Enable internal buck converters */
+    am_hal_pwrctrl_bucks_init();
+
+    /* Initialize for low power in the power control block */
+    am_hal_pwrctrl_low_power_init();
+
+    /* Turn off the voltage comparator as this is enabled on reset */
+    am_hal_vcomp_disable();
+
+    /* Run the RTC off the LFRC */
+    am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC);
+
+    /* Stop the XT and LFRC */
+    am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_XT);
+    // am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC);
+
+    /* Disable the RTC */
+    am_hal_rtc_osc_disable();
+}
+
+/**
+ * This is the deep power save.
+ *
+ */
+void deep_power_save(void)
+{
+		am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
+}
+
+/**
+ * This function will initial APOLLO2 board.
+ */
+void rt_hw_board_init(void)
+{
+		/* Set the clock frequency */
+    SysTick_Configuration();
+	
+		/* Set the default cache configuration */
+		CacheCtrl_Enable();
+
+    /* Configure the board for low power operation */
+    //am_low_power_init();
+	
+#ifdef RT_USING_IDLE_HOOK	
+    rt_thread_idle_sethook(deep_power_save);  
+#endif
+	
+#ifdef RT_USING_CONSOLE
+		rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/apollo2/board/board.h

@@ -0,0 +1,17 @@
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include <rtthread.h>
+
+// <o> Internal SRAM memory size[Kbytes] <8-256>
+//	<i>Default: 256
+#define AM_SRAM_SIZE         256
+#define AM_SRAM_END          (0x10000000 + AM_SRAM_SIZE * 1024)
+
+/* USART driver select. */
+#define RT_USING_UART0
+#define RT_USING_UART1
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */

bsp/apollo2/board/hw_led.c

@@ -0,0 +1,302 @@
+/*
+ * File      : hw_led.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+
+#include <rtthread.h>
+#include "am_mcu_apollo.h"
+#include "hw_led.h"
+
+#define AM_GPIO_LED0                46
+#define AM_GPIO_LED1                47
+#define AM_GPIO_LED2                48
+#define AM_GPIO_LED3                49
+
+#define AM_NUM_LEDS             4
+
+rt_hw_led_t am_psLEDs[AM_NUM_LEDS] =
+{
+    {AM_GPIO_LED0, AM_LED_ON_LOW | AM_LED_POL_DIRECT_DRIVE_M},
+    {AM_GPIO_LED1, AM_LED_ON_LOW | AM_LED_POL_DIRECT_DRIVE_M},
+    {AM_GPIO_LED2, AM_LED_ON_LOW | AM_LED_POL_DIRECT_DRIVE_M},
+    {AM_GPIO_LED3, AM_LED_ON_LOW | AM_LED_POL_DIRECT_DRIVE_M},
+};
+
+/**
+ * @brief Configures the necessary pins for an array of LEDs
+ *
+ * @param LEDNum is the LED number.
+ *
+ * This function configures a GPIO to drive an LED in a low-power way.
+ *
+ * @return None.
+ */
+void rt_hw_led_init(rt_uint32_t LEDNum)
+{
+		rt_hw_led_t *psLED = am_psLEDs + LEDNum;
+	
+    /* Handle Direct Drive Versus 3-State (with pull-up or no buffer) */
+    if ( AM_LED_POL_DIRECT_DRIVE_M & psLED->Polarity )
+    {
+        /* Configure the pin as a push-pull GPIO output */
+        am_hal_gpio_pin_config(psLED->GPIONumber, AM_HAL_GPIO_OUTPUT);
+
+        /* Enable the output driver, and set the output value to the LEDs "ON" state */
+        am_hal_gpio_out_enable_bit_set(psLED->GPIONumber);
+        am_hal_gpio_out_bit_replace(psLED->GPIONumber,
+                                    psLED->Polarity &
+                                    AM_LED_POL_DIRECT_DRIVE_M);
+    }
+    else
+    {
+        /* Configure the pin as a tri-state GPIO */
+        am_hal_gpio_pin_config(psLED->GPIONumber, AM_HAL_GPIO_3STATE);
+
+        /* Disable the output driver, and set the output value to the LEDs "ON" state */
+        am_hal_gpio_out_enable_bit_clear(psLED->GPIONumber);
+        am_hal_gpio_out_bit_replace(psLED->GPIONumber,
+                                    psLED->Polarity &
+                                    AM_LED_POL_DIRECT_DRIVE_M );
+    }
+}
+
+/**
+ * @brief Configures the necessary pins for an array of LEDs
+ *
+ * @param NumLEDs is the total number of LEDs in the array.
+ *
+ * This function configures the GPIOs for an array of LEDs.
+ *
+ * @return None.
+ */
+void rt_hw_led_array_init(rt_uint32_t NumLEDs)
+{
+    /* Loop through the list of LEDs, configuring each one individually */
+    for ( int i = 0; i < NumLEDs; i++ )
+    {
+        rt_hw_led_init(i);
+    }
+}
+
+/**
+ * @brief Disables an array of LEDs
+ *
+ * @param NumLEDs is the total number of LEDs in the array.
+ *
+ * This function disables the GPIOs for an array of LEDs.
+ *
+ * @return None.
+ */
+void rt_hw_led_array_disable(rt_uint32_t NumLEDs)
+{
+		rt_hw_led_t *psLEDs = am_psLEDs;
+	
+    /* Loop through the list of LEDs, configuring each one individually */
+    for ( int i = 0; i < NumLEDs; i++ )
+    {
+        am_hal_gpio_pin_config((psLEDs + i)->GPIONumber, AM_HAL_GPIO_DISABLE);
+    }
+}
+
+/**
+ * @brief Turns on the requested LED.
+ *
+ * @param LEDNum is the LED number for the light to turn on.
+ *
+ * This function turns on a single LED.
+ *
+ * @return None.
+ */
+void rt_hw_led_on(rt_uint32_t LEDNum)
+{
+		rt_hw_led_t *psLEDs = am_psLEDs;
+	
+    /* Handle Direct Drive Versus 3-State (with pull-up or no buffer) */
+    if ( AM_LED_POL_DIRECT_DRIVE_M & psLEDs[LEDNum].Polarity )
+    {
+        /* Set the output to the correct state for the LED */
+        am_hal_gpio_out_bit_replace(psLEDs[LEDNum].GPIONumber,
+                                    psLEDs[LEDNum].Polarity &
+                                    AM_LED_POL_POLARITY_M );
+    }
+    else
+    {
+        /* Turn on the output driver for the LED */
+        am_hal_gpio_out_enable_bit_set(psLEDs[LEDNum].GPIONumber);
+    }
+}
+
+/**
+ * @brief Turns off the requested LED.
+ *
+ * @param LEDNum is the LED number for the light to turn off.
+ *
+ * This function turns off a single LED.
+ *
+ * @return None.
+ */
+void rt_hw_led_off(rt_uint32_t LEDNum)
+{
+		rt_hw_led_t *psLEDs = am_psLEDs;
+
+    /* Handle Direct Drive Versus 3-State (with pull-up or no buffer) */
+    if ( AM_LED_POL_DIRECT_DRIVE_M & psLEDs[LEDNum].Polarity )
+    {
+        /* Set the output to the correct state for the LED */
+        am_hal_gpio_out_bit_replace(psLEDs[LEDNum].GPIONumber,
+                                    !(psLEDs[LEDNum].Polarity &
+                                      AM_LED_POL_POLARITY_M) );
+    }
+    else
+    {
+        /* Turn off the output driver for the LED */
+        am_hal_gpio_out_enable_bit_clear(psLEDs[LEDNum].GPIONumber);
+    }
+}
+
+/**
+ * @brief Toggles the requested LED.
+ *
+ * @param LEDNum is the LED number for the light to toggle.
+ *
+ * This function toggles a single LED.
+ *
+ * @return None.
+ */
+void rt_hw_led_toggle(rt_uint32_t LEDNum)
+{
+		rt_hw_led_t *psLEDs = am_psLEDs;
+
+    /* Handle Direct Drive Versus 3-State (with pull-up or no buffer) */
+    if ( AM_LED_POL_DIRECT_DRIVE_M & psLEDs[LEDNum].Polarity )
+    {
+        am_hal_gpio_out_bit_toggle(psLEDs[LEDNum].GPIONumber);
+    }
+    else
+    {
+        /* Check to see if the LED pin is enabled */
+        if ( am_hal_gpio_out_enable_bit_get(psLEDs[LEDNum].GPIONumber) )
+        {
+            /* If it was enabled, turn if off */
+            am_hal_gpio_out_enable_bit_clear(psLEDs[LEDNum].GPIONumber);
+        }
+        else
+        {
+            /* If it was not enabled, turn if on */
+            am_hal_gpio_out_enable_bit_set(psLEDs[LEDNum].GPIONumber);
+        }
+    }
+}
+
+/**
+ * @brief Gets the state of the requested LED.
+ *
+ * @param LEDNum is the LED to check.
+ *
+ * This function checks the state of a single LED.
+ *
+ * @return 1(true) if the LED is on.
+ */
+int rt_hw_led_get(rt_uint32_t LEDNum)
+{
+		rt_hw_led_t *psLEDs = am_psLEDs;
+
+    /* Handle Direct Drive Versus 3-State (with pull-up or no buffer) */
+    if ( AM_LED_POL_DIRECT_DRIVE_M & psLEDs[LEDNum].Polarity )
+    {
+        /* Mask to the GPIO bit position for this GPIO number */
+        uint64_t ui64Mask = 0x01l << psLEDs[LEDNum].GPIONumber;
+
+        /* Extract the state of this bit and return it */
+        return !!(am_hal_gpio_input_read() & ui64Mask);
+    }
+    else
+    {
+        return am_hal_gpio_out_enable_bit_get(
+                    psLEDs[LEDNum].GPIONumber);
+    }
+}
+
+/**
+ * @brief Display a binary value using LEDs.
+ *
+ * @param NumLEDs is the number of LEDs in the array.
+ * @param Value is the value to display on the LEDs.
+ *
+ * This function displays a value in binary across an array of LEDs.
+ *
+ * @return None.
+ */
+void rt_hw_led_array_out(rt_uint32_t NumLEDs, rt_uint32_t Value)
+{
+    for ( int i = 0; i < NumLEDs; i++ )
+    {
+        if ( Value & (1 << i) )
+        {
+            rt_hw_led_on(i);
+        }
+        else
+        {
+            rt_hw_led_off(i);
+        }
+    }
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static rt_uint8_t led_inited = 0;
+void led(rt_uint32_t led, rt_uint32_t value)
+{
+    /* init led configuration if it's not inited. */
+    if (!led_inited)
+    {
+//        rt_hw_led_init(0);
+//				rt_hw_led_init(1);
+        led_inited = 1;
+    }
+
+    if ( led == 0 )
+    {
+        /* set led status */
+        switch (value)
+        {
+        case 0:
+            rt_hw_led_off(0);
+            break;
+        case 1:
+            rt_hw_led_on(0);
+            break;
+        default:
+            break;
+        }
+    }
+
+    if ( led == 1 )
+    {
+        /* set led status */
+        switch (value)
+        {
+        case 0:
+            rt_hw_led_off(1);
+            break;
+        case 1:
+            rt_hw_led_on(1);
+            break;
+        default:
+            break;
+        }
+    }
+}
+FINSH_FUNCTION_EXPORT(led, set led[0 - 1] on[1] or off[0].)
+#endif
+
+/*@}*/

bsp/apollo2/board/hw_led.h

@@ -0,0 +1,60 @@
+/*
+ * File      : hw_led.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+ 
+#ifndef __HW_LED_H
+#define __HW_LED_H
+
+#include <rtthread.h>
+	
+/**
+ * @brief LED polarity macros
+ *
+ */
+#define AM_LED_POL_POLARITY_M       0x1
+#define AM_LED_ON_HIGH              0x1
+#define AM_LED_ON_LOW               0x0
+
+/**
+ * @brief LED direct drive indicator macro
+ *	Or this in with the polarity value to use the GPIO DATA register instead of
+ *	the GPIO DATA ENABLE register to directly drive an LED buffer.
+ */
+#define AM_LED_POL_DIRECT_DRIVE_M   0x2
+
+
+/**
+ * @brief Structure for keeping track of LEDs
+ *
+ */
+typedef struct
+{
+    rt_uint32_t GPIONumber;
+    rt_uint32_t Polarity;
+}
+rt_hw_led_t;
+
+/**
+ * @brief External function definitions
+ *
+ */
+void rt_hw_led_init(rt_uint32_t LEDNum);
+void rt_hw_led_array_init(rt_uint32_t NumLEDs);
+void rt_hw_led_array_disable(rt_uint32_t NumLEDs);
+void rt_hw_led_on(rt_uint32_t LEDNum);
+void rt_hw_led_off(rt_uint32_t LEDNum);
+void rt_hw_led_toggle(rt_uint32_t LEDNum);
+int rt_hw_led_get(rt_uint32_t LEDNum);
+void rt_hw_led_array_out(rt_uint32_t NumLEDs, rt_uint32_t Value);
+
+#endif // __HW_LED_H

bsp/apollo2/board/hw_uart.c

@@ -0,0 +1,413 @@
+/*
+ * File      : hw_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-15     Haley        the first version
+ */
+ 
+#include "am_mcu_apollo.h"
+#include "hw_uart.h"
+#include "board.h"
+#include <rtdevice.h>
+
+/* USART0 */
+#define AM_UART0_INST         0
+
+#define UART0_GPIO_RX         2
+#define UART0_GPIO_CFG_RX     AM_HAL_PIN_2_UART0RX
+#define UART0_GPIO_TX         1
+#define UART0_GPIO_CFG_TX     AM_HAL_PIN_1_UART0TX
+
+/* USART1 */
+#define AM_UART1_INST         1
+
+#define UART1_GPIO_RX         9
+#define UART1_GPIO_CFG_RX     AM_HAL_PIN_9_UART1RX
+#define UART1_GPIO_TX         8
+#define UART1_GPIO_CFG_TX     AM_HAL_PIN_8_UART1TX
+
+/* AM uart driver */
+struct am_uart
+{
+    uint32_t uart_device;
+		uint32_t uart_interrupt;
+};
+
+/**
+ * @brief UART configuration settings
+ *
+ */
+am_hal_uart_config_t g_sUartConfig =
+{
+    .ui32BaudRate = 115200,
+    .ui32DataBits = AM_HAL_UART_DATA_BITS_8,
+    .bTwoStopBits = false,
+    .ui32Parity   = AM_HAL_UART_PARITY_NONE,
+    .ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE,
+};
+
+/**
+ * @brief Enable the UART
+ *
+ * @param Uart driver
+ *
+ * This function is Enable the UART
+ *
+ * @return None.
+ */
+static void rt_hw_uart_enable(struct am_uart* uart)
+{
+    /* Enable the UART clock */
+    am_hal_uart_clock_enable(uart->uart_device);
+
+    /* Enable the UART */
+    am_hal_uart_enable(uart->uart_device);
+
+#if defined(RT_USING_UART0)	
+    /* Make sure the UART RX and TX pins are enabled */
+		am_hal_gpio_pin_config(UART0_GPIO_TX, UART0_GPIO_CFG_TX);
+		am_hal_gpio_pin_config(UART0_GPIO_RX, UART0_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART0 */	
+	
+#if defined(RT_USING_UART1)	
+    /* Make sure the UART RX and TX pins are enabled */
+		am_hal_gpio_pin_config(UART1_GPIO_TX, UART1_GPIO_CFG_TX);
+		am_hal_gpio_pin_config(UART1_GPIO_RX, UART1_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART1 */	
+}
+
+/**
+ * @brief Disable the UART
+ *
+ * @param Uart driver
+ *
+ * This function is Disable the UART
+ *
+ * @return None.
+ */
+static void rt_hw_uart_disable(struct am_uart* uart)
+{
+		/* Clear all interrupts before sleeping as having a pending UART interrupt burns power */
+		am_hal_uart_int_clear(uart->uart_device, 0xFFFFFFFF);
+
+		/* Disable the UART */
+		am_hal_uart_disable(uart->uart_device);
+	
+#if defined(RT_USING_UART0)	
+    /* Disable the UART pins */
+		am_hal_gpio_pin_config(UART0_GPIO_TX, AM_HAL_PIN_DISABLE);
+		am_hal_gpio_pin_config(UART0_GPIO_RX, AM_HAL_PIN_DISABLE);
+#endif /* RT_USING_UART0 */	
+	
+#if defined(RT_USING_UART1)	
+    /* Disable the UART pins */
+		am_hal_gpio_pin_config(UART1_GPIO_TX, AM_HAL_PIN_DISABLE);
+		am_hal_gpio_pin_config(UART1_GPIO_RX, AM_HAL_PIN_DISABLE);
+#endif /* RT_USING_UART1 */		
+	
+		/* Disable the UART clock */
+		am_hal_uart_clock_disable(uart->uart_device);
+}
+
+/**
+ * @brief UART-based string print function.
+ *
+ * @param Send buff
+ *
+ * This function is used for printing a string via the UART, which for some
+ * MCU devices may be multi-module.
+ *
+ * @return None.
+ */
+void rt_hw_uart_send_string(char *pcString)
+{
+    am_hal_uart_string_transmit_polled(AM_UART0_INST, pcString);
+	
+		/* Wait until busy bit clears to make sure UART fully transmitted last byte */
+		while ( am_hal_uart_flags_get(AM_UART0_INST) & AM_HAL_UART_FR_BUSY );
+}
+
+static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct am_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (struct am_uart *)serial->parent.user_data;	
+
+		RT_ASSERT(uart != RT_NULL);
+	
+		/* Get the configure */
+		g_sUartConfig.ui32BaudRate = cfg->baud_rate;
+		g_sUartConfig.ui32DataBits = cfg->data_bits;
+	
+    if (cfg->stop_bits == STOP_BITS_1)
+        g_sUartConfig.bTwoStopBits = false;
+    else if (cfg->stop_bits == STOP_BITS_2)
+        g_sUartConfig.bTwoStopBits = true;
+
+		g_sUartConfig.ui32Parity = cfg->parity;
+		g_sUartConfig.ui32FlowCtrl = AM_HAL_UART_PARITY_NONE;
+	
+    /* Configure the UART */
+    am_hal_uart_config(uart->uart_device, &g_sUartConfig);
+
+    /* Enable the UART */
+    am_hal_uart_enable(uart->uart_device);	
+	
+		return RT_EOK;
+}
+
+static rt_err_t am_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct am_uart* uart;
+    //rt_uint32_t ctrl_arg = (rt_uint32_t)(arg);
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct am_uart *)serial->parent.user_data;
+
+		RT_ASSERT(uart != RT_NULL);
+	
+    switch (cmd)
+    {
+        /* disable interrupt */
+				case RT_DEVICE_CTRL_CLR_INT:
+						rt_hw_uart_disable(uart);
+						break;
+						/* enable interrupt */
+				case RT_DEVICE_CTRL_SET_INT:
+						rt_hw_uart_enable(uart);
+						break;
+						/* UART config */
+				case RT_DEVICE_CTRL_CONFIG :
+						break;
+    }
+		
+		return RT_EOK;
+}
+
+static int am_putc(struct rt_serial_device *serial, char c)
+{
+    struct am_uart* uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct am_uart *)serial->parent.user_data;
+	
+		RT_ASSERT(uart != RT_NULL);
+	
+		am_hal_uart_char_transmit_polled(uart->uart_device, c);
+	
+		return 1;
+}
+	
+static int am_getc(struct rt_serial_device *serial)
+{
+		char c;
+		int ch;
+		struct am_uart* uart;
+	
+		RT_ASSERT(serial != RT_NULL);
+    uart = (struct am_uart *)serial->parent.user_data;
+
+		RT_ASSERT(uart != RT_NULL);
+	
+    ch = -1;
+    if (am_hal_uart_flags_get(uart->uart_device) & AM_HAL_UART_FR_RX_FULL)
+    {
+				am_hal_uart_char_receive_polled(uart->uart_device, &c);
+				ch = c & 0xff;
+    }
+		
+		return ch;
+}
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+		uint32_t status;
+	
+		RT_ASSERT(serial != RT_NULL);
+		struct am_uart *uart = (struct am_uart *) serial->parent.user_data;
+	
+		RT_ASSERT(uart != RT_NULL);
+
+    /* Read the interrupt status */
+    status = am_hal_uart_int_status_get(uart->uart_device, false);	
+	
+		//rt_kprintf("status is %d\r\n", status);
+	
+		/* Clear the UART interrupt */
+		am_hal_uart_int_clear(uart->uart_device, status);
+
+    if (status & (AM_HAL_UART_INT_RX_TMOUT))
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_TIMEOUT);
+    }
+
+    if (status & AM_HAL_UART_INT_RX)
+    {	
+				rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+		}
+
+		if (status & AM_HAL_UART_INT_TX)
+    {	
+				//rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+		}	
+}
+
+static const struct rt_uart_ops am_uart_ops =
+{
+    am_configure,
+    am_control,
+    am_putc,
+    am_getc,
+};
+
+#if defined(RT_USING_UART0)
+/* UART0 device driver structure */
+struct am_uart uart0 =
+{
+    AM_UART0_INST,
+		AM_HAL_INTERRUPT_UART0
+};
+static struct rt_serial_device serial0;
+
+void am_uart0_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial0);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+/* UART1 device driver structure */
+struct am_uart uart1 =
+{
+    AM_UART1_INST,
+		AM_HAL_INTERRUPT_UART1
+};
+static struct rt_serial_device serial1;
+
+void am_uart1_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+	
+    uart_isr(&serial1);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART1 */
+
+static void GPIO_Configuration(void)
+{
+#if defined(RT_USING_UART0)	
+    /* Make sure the UART RX and TX pins are enabled */
+		am_hal_gpio_pin_config(UART0_GPIO_TX, UART0_GPIO_CFG_TX);
+		am_hal_gpio_pin_config(UART0_GPIO_RX, UART0_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART0 */	
+	
+#if defined(RT_USING_UART1)	
+    /* Make sure the UART RX and TX pins are enabled */
+		am_hal_gpio_pin_config(UART1_GPIO_TX, UART1_GPIO_CFG_TX);
+		am_hal_gpio_pin_config(UART1_GPIO_RX, UART1_GPIO_CFG_RX | AM_HAL_GPIO_PULL12K);
+#endif /* RT_USING_UART1 */		
+}
+
+static void RCC_Configuration(struct am_uart* uart)
+{
+    /* Power on the selected UART */
+    am_hal_uart_pwrctrl_enable(uart->uart_device);
+
+    /* Start the UART interface, apply the desired configuration settings */
+    am_hal_uart_clock_enable(uart->uart_device);
+
+    /* Disable the UART before configuring it */
+    am_hal_uart_disable(uart->uart_device);		
+	
+    /* Configure the UART */
+    am_hal_uart_config(uart->uart_device, &g_sUartConfig);	
+	
+    /* Enable the UART */
+    am_hal_uart_enable(uart->uart_device);	
+
+    /* Enable the UART FIFO */
+    //am_hal_uart_fifo_config(uart->uart_device, AM_HAL_UART_TX_FIFO_1_2 | AM_HAL_UART_RX_FIFO_1_2);		
+}
+
+static void NVIC_Configuration(struct am_uart* uart)
+{
+		/* Enable interrupts */
+		am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX);
+	
+		/* Enable the uart interrupt in the NVIC */
+		am_hal_interrupt_enable(uart->uart_interrupt);
+		am_hal_uart_int_clear(uart->uart_device, 0xFFFFFFFF);
+}
+
+/**
+ * @brief Initialize the UART
+ *
+ * This function initialize the UART
+ *
+ * @return None.
+ */
+void rt_hw_uart_init(void)
+{
+    struct am_uart* uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;	
+
+    GPIO_Configuration();
+	
+#if defined(RT_USING_UART0)
+    uart = &uart0;
+    config.baud_rate = BAUD_RATE_115200;
+
+		RCC_Configuration(uart);	
+		NVIC_Configuration(uart);	
+	
+    serial0.ops    = &am_uart_ops;
+    serial0.config = config;	
+	
+    /* register UART1 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+                          RT_DEVICE_FLAG_INT_TX, uart);	
+#endif /* RT_USING_UART0 */
+
+#if defined(RT_USING_UART1)
+    uart = &uart1;
+    config.baud_rate = BAUD_RATE_115200;
+
+		RCC_Configuration(uart);	
+		NVIC_Configuration(uart);	    
+		
+    serial1.ops    = &am_uart_ops;
+    serial1.config = config;	
+	
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+                          RT_DEVICE_FLAG_INT_TX, uart);	
+#endif /* RT_USING_UART1 */
+}
+
+/*@}*/

bsp/apollo2/board/hw_uart.h

@@ -0,0 +1,23 @@
+/*
+ * File      : hw_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-14     Haley        the first version
+ */
+ 
+#ifndef __HW_UART_H_
+#define __HW_UART_H_
+
+#include <rtthread.h>
+
+void rt_hw_uart_init(void);
+void rt_hw_uart_send_string(char *pcString);
+
+#endif // __HW_UART_H_

bsp/apollo2/libraries/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/apollo2/libraries/drivers/SConscript

@@ -0,0 +1,29 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+hal/am_hal_clkgen.c
+hal/am_hal_debug.c
+hal/am_hal_cachectrl.c
+hal/am_hal_pwrctrl.c
+hal/am_hal_sysctrl.c
+hal/am_hal_stimer.c
+hal/am_hal_ctimer.c
+hal/am_hal_rtc.c
+hal/am_hal_interrupt.c
+hal/am_hal_queue.c
+hal/am_hal_vcomp.c
+hal/am_hal_flash.c
+hal/am_hal_gpio.c
+hal/am_hal_uart.c
+""")
+
+path = [cwd]
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/apollo2/libraries/drivers/am_mcu_apollo.h

@@ -0,0 +1,132 @@
+//*****************************************************************************
+//
+//! @file
+//!
+//! @brief Top Include for Apollo2 class devices.
+//!
+//! This file provides all the includes necessary for an apollo device.
+//!
+//! @addtogroup hal Hardware Abstraction Layer (HAL)
+//
+//! @defgroup apollo2hal HAL for Apollo2
+//! @ingroup hal
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_MCU_APOLLO_H
+#define AM_MCU_APOLLO_H
+
+//*****************************************************************************
+//
+// C99
+//
+//*****************************************************************************
+#include <stdarg.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#ifdef __IAR_SYSTEMS_ICC__
+#include "intrinsics.h"     // __CLZ() and other intrinsics
+#endif
+
+//*****************************************************************************
+//
+// Registers
+//
+//*****************************************************************************
+#include "regs/am_reg_base_addresses.h"
+
+#include "regs/am_reg_macros.h"
+
+#include "regs/am_reg_adc.h"
+#include "regs/am_reg_cachectrl.h"
+#include "regs/am_reg_clkgen.h"
+#include "regs/am_reg_ctimer.h"
+#include "regs/am_reg_gpio.h"
+#include "regs/am_reg_iomstr.h"
+#include "regs/am_reg_ioslave.h"
+#include "regs/am_reg_itm.h"
+#include "regs/am_reg_jedec.h"
+#include "regs/am_reg_mcuctrl.h"
+#include "regs/am_reg_nvic.h"
+#include "regs/am_reg_pdm.h"
+#include "regs/am_reg_pwrctrl.h"
+#include "regs/am_reg_rstgen.h"
+#include "regs/am_reg_rtc.h"
+#include "regs/am_reg_sysctrl.h"
+#include "regs/am_reg_systick.h"
+#include "regs/am_reg_tpiu.h"
+#include "regs/am_reg_uart.h"
+#include "regs/am_reg_vcomp.h"
+#include "regs/am_reg_wdt.h"
+
+//*****************************************************************************
+//
+// HAL
+//
+//*****************************************************************************
+#include "hal/am_hal_adc.h"
+#include "hal/am_hal_cachectrl.h"
+#include "hal/am_hal_clkgen.h"
+#include "hal/am_hal_ctimer.h"
+#include "hal/am_hal_debug.h"
+#include "hal/am_hal_flash.h"
+#include "hal/am_hal_global.h"
+#include "hal/am_hal_gpio.h"
+#include "hal/am_hal_i2c_bit_bang.h"
+#include "hal/am_hal_interrupt.h"
+#include "hal/am_hal_iom.h"
+#include "hal/am_hal_ios.h"
+#include "hal/am_hal_itm.h"
+#include "hal/am_hal_mcuctrl.h"
+#include "hal/am_hal_otp.h"
+#include "hal/am_hal_pdm.h"
+#include "hal/am_hal_pin.h"
+#include "hal/am_hal_pwrctrl.h"
+#include "hal/am_hal_queue.h"
+#include "hal/am_hal_reset.h"
+#include "hal/am_hal_rtc.h"
+#include "hal/am_hal_stimer.h"
+#include "hal/am_hal_sysctrl.h"
+#include "hal/am_hal_systick.h"
+#include "hal/am_hal_tpiu.h"
+#include "hal/am_hal_uart.h"
+#include "hal/am_hal_vcomp.h"
+#include "hal/am_hal_wdt.h"
+
+#endif // AM_MCU_APOLLO_H
+

bsp/apollo2/libraries/drivers/hal/am_hal_adc.h

@@ -0,0 +1,348 @@
+//*****************************************************************************
+//
+//  am_hal_adc.h
+//! @file
+//!
+//! @brief Functions for interfacing with the Analog to Digital Converter
+//!
+//! @addtogroup adc2 Analog-to-Digital Converter (ADC)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_ADC_H
+#define AM_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name Clock Selection
+//! @brief These macros may be used to set the ADC module's clock source.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_CLOCK_OFF                AM_REG_ADC_CFG_CLKSEL_OFF
+#define AM_HAL_ADC_CLOCK_HFRC               AM_REG_ADC_CFG_CLKSEL_HFRC
+#define AM_HAL_ADC_CLOCK_DIV2               AM_REG_ADC_CFG_CLKSEL_HFRC_DIV2
+//! @}
+
+//*****************************************************************************
+//
+//! @name Trigger Settings
+//! @brief ADC trigger setting macros.
+//!
+//! These macros alter the ADC's trigger source and trigger polarity. Note that
+//! the external trigger setting needs to be ORed with a POS or NEG option to
+//! define the desired trigger polarity.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_TRIGGER_SOFT             AM_REG_ADC_CFG_TRIGSEL_SWT
+#define AM_HAL_ADC_TRIGGER_VCOMP            AM_REG_ADC_CFG_TRIGSEL_VCOMP
+#define AM_HAL_ADC_TRIGGER_EXT0             AM_REG_ADC_CFG_TRIGSEL_EXT0
+#define AM_HAL_ADC_TRIGGER_EXT1             AM_REG_ADC_CFG_TRIGSEL_EXT1
+#define AM_HAL_ADC_TRIGGER_EXT2             AM_REG_ADC_CFG_TRIGSEL_EXT2
+#define AM_HAL_ADC_TRIGGER_EXT3             AM_REG_ADC_CFG_TRIGSEL_EXT3
+#define AM_HAL_ADC_TRIGGER_FALL             AM_REG_ADC_CFG_TRIGPOL_FALLING_EDGE
+#define AM_HAL_ADC_TRIGGER_RISE             AM_REG_ADC_CFG_TRIGPOL_RISING_EDGE
+//! @}
+
+//*****************************************************************************
+//
+//! @name Reference Settings
+//! @brief ADC reference voltage setting macros.
+//!
+//! These macros control the ADC reference voltage source.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_REF_EXT_2P0              AM_REG_ADC_CFG_REFSEL_EXT2P0
+#define AM_HAL_ADC_REF_EXT_1P5              AM_REG_ADC_CFG_REFSEL_EXT1P5
+#define AM_HAL_ADC_REF_INT_2P0              AM_REG_ADC_CFG_REFSEL_INT2P0
+#define AM_HAL_ADC_REF_INT_1P5              AM_REG_ADC_CFG_REFSEL_INT1P5
+//! @}
+
+//*****************************************************************************
+//
+//! @name Clock Mode
+//! @brief ADC clock mode settings
+//!
+//! These macros determine whether the ADC shuts down its clock between
+//! samples. Shutting down the clock will reduce power consumption, but
+//! increase latency. This setting is only valid for LPMODE 0. For other modes,
+//! it will be ignored.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_CK_LOW_POWER             AM_REG_ADC_CFG_CKMODE_LPCKMODE
+#define AM_HAL_ADC_CK_LOW_LATENCY           AM_REG_ADC_CFG_CKMODE_LLCKMODE
+//! @}
+
+//*****************************************************************************
+//
+//! @name Low Power Mode
+//! @brief ADC power conservation settings.
+//!
+//! These macros select the power state to enter between active scans. Each low
+//! power mode has its own set of timing constraints. Please see the datasheet
+//! for additional timing information on each power mode.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_LPMODE_0                 AM_REG_ADC_CFG_LPMODE_MODE0
+#define AM_HAL_ADC_LPMODE_1                 AM_REG_ADC_CFG_LPMODE_MODE1
+//! @}
+
+//*****************************************************************************
+//
+//! @name Repeat Mode
+//! @brief Enable repeating scan mode.
+//!
+//! Use this macro to enable repeating scans using timer 3.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_REPEAT                   AM_REG_ADC_CFG_RPTEN(1)
+#define AM_HAL_ADC_NO_REPEAT                AM_REG_ADC_CFG_RPTEN(0)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Slot configuration
+//! @brief Slot configuration macros
+//!
+//! These macros may be used to configure an individual ADC slot.
+//! @{
+//
+//*****************************************************************************
+
+// Set number of samples to average.
+#define AM_HAL_ADC_SLOT_AVG_1               AM_REG_ADC_SL0CFG_ADSEL0(0)
+#define AM_HAL_ADC_SLOT_AVG_2               AM_REG_ADC_SL0CFG_ADSEL0(1)
+#define AM_HAL_ADC_SLOT_AVG_4               AM_REG_ADC_SL0CFG_ADSEL0(2)
+#define AM_HAL_ADC_SLOT_AVG_8               AM_REG_ADC_SL0CFG_ADSEL0(3)
+#define AM_HAL_ADC_SLOT_AVG_16              AM_REG_ADC_SL0CFG_ADSEL0(4)
+#define AM_HAL_ADC_SLOT_AVG_32              AM_REG_ADC_SL0CFG_ADSEL0(5)
+#define AM_HAL_ADC_SLOT_AVG_64              AM_REG_ADC_SL0CFG_ADSEL0(6)
+#define AM_HAL_ADC_SLOT_AVG_128             AM_REG_ADC_SL0CFG_ADSEL0(7)
+
+// Set slot precision mode.
+#define AM_HAL_ADC_SLOT_14BIT               AM_REG_ADC_SL0CFG_PRMODE0_P14B
+#define AM_HAL_ADC_SLOT_12BIT               AM_REG_ADC_SL0CFG_PRMODE0_P14B
+#define AM_HAL_ADC_SLOT_10BIT               AM_REG_ADC_SL0CFG_PRMODE0_P14B
+#define AM_HAL_ADC_SLOT_8BIT                AM_REG_ADC_SL0CFG_PRMODE0_P14B
+
+// Select a channel by number.
+#define AM_HAL_ADC_SLOT_CHANNEL(n)          AM_REG_ADC_SL0CFG_CHSEL0(n)
+
+// Single-ended channels
+#define AM_HAL_ADC_SLOT_CHSEL_SE0           AM_REG_ADC_SL0CFG_CHSEL0_SE0
+#define AM_HAL_ADC_SLOT_CHSEL_SE1           AM_REG_ADC_SL0CFG_CHSEL0_SE1
+#define AM_HAL_ADC_SLOT_CHSEL_SE2           AM_REG_ADC_SL0CFG_CHSEL0_SE2
+#define AM_HAL_ADC_SLOT_CHSEL_SE3           AM_REG_ADC_SL0CFG_CHSEL0_SE3
+#define AM_HAL_ADC_SLOT_CHSEL_SE4           AM_REG_ADC_SL0CFG_CHSEL0_SE4
+#define AM_HAL_ADC_SLOT_CHSEL_SE5           AM_REG_ADC_SL0CFG_CHSEL0_SE5
+#define AM_HAL_ADC_SLOT_CHSEL_SE6           AM_REG_ADC_SL0CFG_CHSEL0_SE6
+#define AM_HAL_ADC_SLOT_CHSEL_SE7           AM_REG_ADC_SL0CFG_CHSEL0_SE7
+#define AM_HAL_ADC_SLOT_CHSEL_SE8           AM_REG_ADC_SL0CFG_CHSEL0_SE8
+#define AM_HAL_ADC_SLOT_CHSEL_SE9           AM_REG_ADC_SL0CFG_CHSEL0_SE9
+
+// Differential channels.
+#define AM_HAL_ADC_SLOT_CHSEL_DF0           AM_REG_ADC_SL0CFG_CHSEL0_DF0
+#define AM_HAL_ADC_SLOT_CHSEL_DF1           AM_REG_ADC_SL0CFG_CHSEL0_DF1
+
+// Miscellaneous other signals.
+#define AM_HAL_ADC_SLOT_CHSEL_TEMP          AM_REG_ADC_SL0CFG_CHSEL0_TEMP
+#define AM_HAL_ADC_SLOT_CHSEL_VSS           AM_REG_ADC_SL0CFG_CHSEL0_VSS
+#define AM_HAL_ADC_SLOT_CHSEL_VBATT         AM_REG_ADC_SL0CFG_CHSEL0_BATT
+
+// Window enable.
+#define AM_HAL_ADC_SLOT_WINDOW_EN           AM_REG_ADC_SL0CFG_WCEN0(1)
+
+// Enable the slot.
+#define AM_HAL_ADC_SLOT_ENABLE              AM_REG_ADC_SL0CFG_SLEN0(1)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to enable an individual ADC interrupt cause.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_INT_WCINC              AM_REG_ADC_INTEN_WCINC(1)
+#define AM_HAL_ADC_INT_WCEXC              AM_REG_ADC_INTEN_WCEXC(1)
+#define AM_HAL_ADC_INT_FIFOOVR2           AM_REG_ADC_INTEN_FIFOOVR2(1)
+#define AM_HAL_ADC_INT_FIFOOVR1           AM_REG_ADC_INTEN_FIFOOVR1(1)
+#define AM_HAL_ADC_INT_SCNCMP             AM_REG_ADC_INTEN_SCNCMP(1)
+#define AM_HAL_ADC_INT_CNVCMP             AM_REG_ADC_INTEN_CNVCMP(1)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Temperature Trim Value Locations
+//! @brief Temperature calibration cofficients are stored in readable space.
+//!
+//! These macros are used to access the temperature trim values in readable
+//! space.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_CALIB_TEMP_ADDR          (0x50023010)
+#define AM_HAL_ADC_CALIB_AMBIENT_ADDR       (0x50023014)
+#define AM_HAL_ADC_CALIB_ADC_OFFSET_ADDR    (0x50023018)
+
+//
+// Default coefficients (used when trims not provided):
+//  TEMP_DEFAULT    = Temperature in deg K (e.g. 299.5 - 273.15 = 26.35)
+//  AMBIENT_DEFAULT = Voltage measurement at default temperature.
+//  OFFSET_DEFAULT  = Default ADC offset at 1v.
+//
+#define AM_HAL_ADC_CALIB_TEMP_DEFAULT       (299.5F)
+#define AM_HAL_ADC_CALIB_AMBIENT_DEFAULT    (1.02809F)
+#define AM_HAL_ADC_CALIB_ADC_OFFSET_DEFAULT (-0.004281F)
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Configuration structure for the ADC.
+//
+//*****************************************************************************
+typedef struct
+{
+    //! Select the ADC Clock source using one of the clock source macros.
+    uint32_t ui32Clock;
+
+    //! Select the ADC trigger source using a trigger source macro.
+    uint32_t ui32TriggerConfig;
+
+    //! Use a macro to select the ADC reference voltage.
+    uint32_t ui32Reference;
+
+    //! Use a macro to decide whether to disable clocks between samples.
+    uint32_t ui32ClockMode;
+
+    //! Use a macro to select the ADC power mode.
+    uint32_t ui32PowerMode;
+
+    //! Select whether the ADC will re-trigger based on a signal from timer 3.
+    uint32_t ui32Repeat;
+}
+am_hal_adc_config_t;
+
+//*****************************************************************************
+//
+//! @brief ADC Fifo Read macros
+//!
+//! These are helper macros for interpreting FIFO data. Each ADC FIFO entry
+//! contains information about the slot number and the FIFO depth alongside the
+//! current sample. These macros perform the correct masking and shifting to
+//! read those values.
+//!
+//! The SAMPLE and FULL_SAMPLE options refer to the fractional part of averaged
+//! samples. If you are not using hardware averaging or don't need the
+//! fractional part of the ADC sample, you should just use
+//! AM_HAL_ADC_FIFO_SAMPLE.
+//!
+//! If you do need the fractional part, use AM_HAL_ADC_FIFO_FULL_SAMPLE. This
+//! macro will keep six bits of precision past the decimal point. Depending on
+//! the number of averaged samples, anywhere between 1 and 6 of these bits will
+//! be valid. Please consult the datasheet to find out how many bits of data
+//! are valid for your chosen averaging settings.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_ADC_FIFO_SAMPLE(value)                                         \
+    ((((value) & AM_REG_ADC_FIFO_DATA_M) >> AM_REG_ADC_FIFO_DATA_S) >> 6)
+
+#define AM_HAL_ADC_FIFO_FULL_SAMPLE(value)                                    \
+    (((value) & AM_REG_ADC_FIFO_DATA_M) >> AM_REG_ADC_FIFO_DATA_S )
+
+#define AM_HAL_ADC_FIFO_SLOT(value)                                           \
+    (((value) & AM_REG_ADC_FIFO_SLOTNUM_M) >> AM_REG_ADC_FIFO_SLOTNUM_S)
+
+#define AM_HAL_ADC_FIFO_COUNT(value)                                          \
+    (((value) & AM_REG_ADC_FIFO_COUNT_M) >> AM_REG_ADC_FIFO_COUNT_S)
+//! @}
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_adc_config(am_hal_adc_config_t *psConfig);
+extern void am_hal_adc_window_set(uint32_t ui32Upper, uint32_t ui32Lower);
+extern void am_hal_adc_slot_config(uint32_t ui32SlotNumber,
+                                   uint32_t ui32SlotConfig);
+
+extern uint32_t am_hal_adc_fifo_peek(void);
+extern uint32_t am_hal_adc_fifo_pop(void);
+
+extern void am_hal_adc_trigger(void);
+extern void am_hal_adc_enable(void);
+extern void am_hal_adc_disable(void);
+extern void am_hal_adc_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_adc_int_enable_get(void);
+extern void am_hal_adc_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_adc_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_adc_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_adc_int_status_get(bool bEnabledOnly);
+extern float am_hal_adc_volts_to_celsius(float fVoltage);
+extern void am_hal_adc_temp_trims_get(float * pfTemp, float * pfVoltage, float * pfOffsetV);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_ADC_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h

@@ -0,0 +1,211 @@
+//*****************************************************************************
+//
+//  am_hal_cachectrl.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the CACHE controller.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_CACHECTRL_H
+#define AM_HAL_CACHECTRL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Cache configuration structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Set to 1 to enable the cache.
+    //
+    uint8_t ui32EnableCache;
+
+    //
+    //! Set to 1 to enable the LRU cache replacement policy.
+    //! Set to 0 to enable the LRR (least recently used) replacement policy.
+    //! LEE minimizes writes to the TAG SRAM.
+    //
+    uint8_t ui32LRU;
+
+    //
+    //! Set to 3 to enable non-cachable region 1 and non-cachable region 0.
+    //! Set to 2 to enable non-cachable region 1.
+    //! Set to 1 to enable non-cachable region 0.
+    //! Set to 0 to make all regions cacheable.
+    //
+    uint8_t ui32EnableNCregions;
+
+    //
+    //! Set to:
+    //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 for direct-mapped,
+    //!     128-bit linesize, 256 entries (2 SRAMs active)
+    //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256 for two-way set associative,
+    //!     128-bit linesize, 256 entries (4 SRAMs active)
+    //! AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512 for two-way set associative,
+    //!     128-bit linesize, 512 entries (8 SRAMs active)
+    //
+    uint8_t ui32Config;
+
+    //
+    //! Set to 1 to enable serial cache mode.
+    //
+    uint8_t ui32SerialCacheMode;
+
+    //
+    //! Set to 3 to enable flash data caching and flash instruction caching.
+    //! Set to 2 to enable flash data caching.
+    //! Set to 1 to enable flash instruction caching.
+    //! Set to 0 to disable flash data caching and flash instruction caching.
+    //
+    uint8_t ui32FlashCachingEnables;
+
+    //
+    //! Set to 1 to enable clock gating of cache RAMs.
+    //
+    uint8_t ui32EnableCacheClockGating;
+
+    //
+    //! Set to 1 to enable light sleep of cache RAMs.
+    //
+    uint8_t ui32EnableLightSleep;
+
+    //
+    //! Set Data RAM delay value (0x0 - 0xF).
+    //
+    uint8_t ui32Dly;
+
+    //
+    //! Set SM Data RAM delay value (0x0 - 0xF).
+    //
+    uint8_t ui32SMDly;
+
+    //
+    //! Set to 1 to enable clock gating of the entire data array.
+    //
+    uint8_t ui32EnableDataClockGating;
+
+    //
+    //! Set to 1 to enable cache monitor statistics.
+    //
+    uint8_t ui32EnableCacheMonitoring;
+}
+am_hal_cachectrl_config_t;
+
+extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults;
+
+//*****************************************************************************
+//
+//! @name Cache enables
+//! @brief Configuration selection for the various cache enables.
+//!
+//! These macros may be used in conjunction with the
+//!  am_hal_cachectrl_cache_enable() function to enable various cache features.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CACHECTRL_CACHECFG_ENABLE                AM_REG_CACHECTRL_CACHECFG_ENABLE_M
+#define AM_HAL_CACHECTRL_CACHECFG_LRU_ENABLE            AM_REG_CACHECTRL_CACHECFG_LRU_M
+#define AM_HAL_CACHECTRL_CACHECFG_NC0_ENABLE            AM_REG_CACHECTRL_CACHECFG_ENABLE_NC0_M
+#define AM_HAL_CACHECTRL_CACHECFG_NC1_ENABLE            AM_REG_CACHECTRL_CACHECFG_ENABLE_NC1_M
+#define AM_HAL_CACHECTRL_CACHECFG_SERIAL_ENABLE         AM_REG_CACHECTRL_CACHECFG_SERIAL_M
+#define AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE         AM_REG_CACHECTRL_CACHECFG_ICACHE_ENABLE_M
+#define AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE         AM_REG_CACHECTRL_CACHECFG_DCACHE_ENABLE_M
+#define AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE  AM_REG_CACHECTRL_CACHECFG_CACHE_CLKGATE_M
+#define AM_HAL_CACHECTRL_CACHECFG_LS_ENABLE             AM_REG_CACHECTRL_CACHECFG_CACHE_LS_M
+#define AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE   AM_REG_CACHECTRL_CACHECFG_DATA_CLKGATE_M
+#define AM_HAL_CACHECTRL_CACHECFG_MONITOR_ENABLE        AM_REG_CACHECTRL_CACHECFG_ENABLE_MONITOR_M
+//! @}
+
+//*****************************************************************************
+//
+//! @name Cache Config
+//! @brief Configuration selection for the cache.
+//!
+//! These macros may be used in conjunction with the
+//!  am_hal_cachectrl_cache_config() function to select the cache type.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_DIRECT_256 AM_REG_CACHECTRL_CACHECFG_CONFIG_W1_128B_256E
+#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_256   AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_256E
+#define AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512   AM_REG_CACHECTRL_CACHECFG_CONFIG_W2_128B_512E
+//! @}
+
+//*****************************************************************************
+//
+// Default cache settings
+//
+//*****************************************************************************
+#define AM_HAL_CACHECTRL_DEFAULTS                                             \
+    (AM_HAL_CACHECTRL_CACHECFG_ICACHE_ENABLE |                                \
+     AM_HAL_CACHECTRL_CACHECFG_DCACHE_ENABLE |                                \
+     AM_HAL_CACHECTRL_CACHECFG_CACHE_CLKGATE_ENABLE |                         \
+     AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE |                          \
+     AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512)
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_cachectrl_enable(const am_hal_cachectrl_config_t *psConfig);
+extern void am_hal_cachectrl_disable(void);
+extern void am_hal_cachectrl_config_default(void);
+extern void am_hal_cachectrl_config(am_hal_cachectrl_config_t *psConfig);
+extern uint32_t am_hal_cachectrl_cache_enables(uint32_t u32EnableMask,
+                                               uint32_t u32DisableMask);
+extern void am_hal_cachectrl_cache_config(uint32_t ui32CacheConfig);
+extern void am_hal_cachectrl_invalidate_flash_cache(void);
+extern void am_hal_cachectrl_reset_statistics(void);
+extern uint32_t am_hal_cachectrl_sleep_mode_status(void);
+extern uint32_t am_hal_cachectrl_sleep_mode_enable(uint32_t ui32EnableMask,
+                                                   uint32_t ui32DisableMask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_CACHECTRL_H

bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c

@@ -0,0 +1,491 @@
+//*****************************************************************************
+//
+//  am_hal_clkgen.c
+//! @file
+//!
+//! @brief Functions for interfacing with the CLKGEN.
+//!
+//! @addtogroup clkgen2 Clock Generator (CLKGEN)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// CLKGEN HFADJ register
+//
+//*****************************************************************************
+#define AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT         0x5B8
+
+//*****************************************************************************
+//
+//! @brief Select the clock divisor for the main system clock.
+//!
+//! @param ui32ClockSetting - The divisor value for the system clock.
+//!
+//! This function can be used to select the frequency of the main system clock.
+//! The \e ui32ClockSetting parameter should be set to one of the following
+//! values:
+//!
+//!     AM_HAL_CLKGEN_SYSCLK_MAX
+//!     AM_HAL_CLKGEN_SYSCLK_48MHZ
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting)
+{
+    am_hal_debug_assert_msg(ui32ClockSetting == AM_HAL_CLKGEN_SYSCLK_48MHZ,
+        "am_hal_clkgen_sysclk_select(): invalid clock setting.");
+
+    //
+    // Unlock the clock control register.
+    //
+    AM_REG(CLKGEN, CLKKEY) = AM_REG_CLKGEN_CLKKEY_KEYVAL;
+
+    //
+    // Set the HFRC divisor to the user-selected value.
+    //
+    AM_REG(CLKGEN, CCTRL) = ui32ClockSetting;
+
+    //
+    // Lock the clock configuration registers.
+    //
+    AM_REG(CLKGEN, CLKKEY) = 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Get the current system clock frequency.
+//!
+//! This function can be used to determine the frequency of the main system
+//! clock. The return value is the system clock frequency measured in hertz.
+//!
+//! @return System clock frequency in Hz
+//
+//*****************************************************************************
+uint32_t
+am_hal_clkgen_sysclk_get(void)
+{
+    uint32_t ui32ClockSetting;
+
+    //
+    // Read the value of the clock divider.
+    //
+    ui32ClockSetting = AM_REG(CLKGEN, CCTRL) & AM_REG_CLKGEN_CCTRL_CORESEL_M;
+
+    switch ( ui32ClockSetting )
+    {
+        case AM_REG_CLKGEN_CCTRL_CORESEL_HFRC:
+            return 48000000;
+        case AM_REG_CLKGEN_CCTRL_CORESEL_HFRC_DIV2:
+            return 24000000;
+        default:
+            return 0xFFFFFFFF;
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Enable selected CLKGEN Interrupts.
+//!
+//! Use this function to enable the interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_clkgen.h
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Enable the interrupts.
+    //
+    AM_REG(CLKGEN, INTEN) |= ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Return enabled CLKGEN Interrupts.
+//!
+//! Use this function to get all enabled CLKGEN interrupts.
+//!
+//! @return enabled CLKGEN interrupts.
+//
+//*****************************************************************************
+uint32_t
+am_hal_clkgen_int_enable_get(void)
+{
+    //
+    // Return the enabled interrupts.
+    //
+    return AM_REG(CLKGEN, INTEN);
+}
+
+//*****************************************************************************
+//
+//! @brief Disable selected CLKGEN Interrupts.
+//!
+//! Use this function to disable the CLKGEN interrupts.
+//!
+//! @param ui32Interrupt - Use the macro bit fields provided in am_hal_clkgen.h
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Disable the interrupts.
+    //
+    AM_REG(CLKGEN, INTEN) &= ~ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Sets the interrupt status.
+//!
+//! @param ui32IntFlags interrupts to be enabled.
+//!
+//! This function sets the interrupts.
+//!
+//! Valid values for ui32IntFlags are:
+//!
+//!     AM_HAL_CLKGEN_INT_RTC_ALARM
+//!     AM_HAL_CLKGEN_INT_XT_FAIL
+//!     AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE
+//!     AM_HAL_CLKGEN_INT AUTOCAL_FAIL
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_set(uint32_t ui32Interrupt)
+{
+    //
+    // Set the interrupt status.
+    //
+    AM_REG(CLKGEN, INTSET) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the interrupt configuration.
+//!
+//! @param bEnabledOnly - return the status of only the enabled interrupts.
+//!
+//! This function gets the currently configured interrupts.
+//!
+//! @return the configured interrupts.
+//!
+//! Possible values for the return are:
+//!
+//!     AM_HAL_CLKGEN_INT_RTC_ALARM
+//!     AM_HAL_CLKGEN_INT_XT_FAIL
+//!     AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE
+//!     AM_HAL_CLKGEN_INT AUTOCAL_FAIL
+//
+//*****************************************************************************
+uint32_t
+am_hal_clkgen_int_status_get(bool bEnabledOnly)
+{
+    //
+    // Return the status.
+    //
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal = AM_REG(CLKGEN, INTSTAT);
+        u32RetVal &= AM_REG(CLKGEN, INTEN);
+        return u32RetVal;
+    }
+    else
+    {
+        return AM_REG(CLKGEN, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Clears the interrupts.
+//!
+//! @param ui32IntFlags interrupts to be cleared.
+//!
+//! This function clears the interrupts.
+//!
+//! Valid values for ui32IntFlags are:
+//!
+//!     AM_HAL_CLKGEN_INT_RTC_ALARM
+//!     AM_HAL_CLKGEN_INT_XT_FAIL
+//!     AM_HAL_CLKGEN_INT_AUTOCAL_COMPLETE
+//!     AM_HAL_CLKGEN_INT AUTOCAL_FAIL
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_int_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Clear the interrupts.
+    //
+    AM_REG(CLKGEN, INTCLR) = ui32Interrupt;
+}
+
+//*****************************************************************************
+//
+//! @brief Starts the desired oscillator(s) (OSC).
+//!
+//! @param ui32OscFlags oscillator(s) to start.
+//!
+//! This function starts the desired oscillator(s) (OSC).
+//!
+//! Valid values for ui32OscFlags are:
+//!
+//!     AM_HAL_CLKGEN_OSC_LFRC
+//!     AM_HAL_CLKGEN_OSC_XT
+//!
+//! @return 0 None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_osc_start(uint32_t ui32OscFlags)
+{
+    //
+    // Start the oscillator(s).
+    //
+    AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags;
+}
+
+//*****************************************************************************
+//
+//! @brief Stops the desired oscillator(s) (OSC).
+//!
+//! @param ui32OscFlags oscillator(s) to stop.
+//!
+//! This function stops the desired oscillator(s) (OSC).
+//!
+//! Valid values for ui32OscFlags are:
+//!
+//!     AM_HAL_CLKGEN_OSC_LFRC
+//!     AM_HAL_CLKGEN_OSC_XT
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_osc_stop(uint32_t ui32OscFlags)
+{
+    //
+    // Stop the oscillator(s).
+    //
+    AM_REG(CLKGEN, OCTRL) |= ui32OscFlags;
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the clock out signal.
+//!
+//! @param ui32Signal desired location for the clock out signal.
+//!
+//! This function enables the clock out signal. See am_hal_clkgen.h for
+//! available signals.
+//!
+//! e.g. AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC
+//!      AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4
+//!      AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_clkout_enable(uint32_t ui32Signal)
+{
+    //
+    // Enable the clock out on desired signal.
+    //
+    AM_REG(CLKGEN, CLKOUT) = AM_REG_CLKGEN_CLKOUT_CKEN_M | ui32Signal;
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the clock out signal.
+//!
+//! This function disables the clock out signal.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_clkout_disable(void)
+{
+    //
+    // Disable the clock out.
+    //
+    AM_REG(CLKGEN, CLKOUT) = 0;
+}
+
+//*****************************************************************************
+//
+//! @brief Enable UART system clock.
+//!
+//! This function enables or disables the UART system clock.
+//!
+//! @param ui32Module is 0 or 1 for Apollo2.
+//! @param ui32UartEn is one of the following.
+//!     AM_HAL_CLKGEN_UARTEN_DIS
+//!     AM_HAL_CLKGEN_UARTEN_EN
+//!     AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ
+//!     AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn)
+{
+    uint32_t ui32Mask;
+
+    if ( (ui32Module >= AM_REG_UART_NUM_MODULES)        ||
+         (ui32UartEn > AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV) )
+    {
+        return;
+    }
+
+    ui32UartEn <<= (ui32Module * AM_HAL_CLKGEN_UARTEN_UARTENn_S(ui32Module));
+    ui32Mask = ~(AM_HAL_CLKGEN_UARTEN_UARTENn_M(ui32Module));
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_BEGIN_ASM
+
+    //
+    // Set the UART clock
+    //
+    AM_REG(CLKGEN, UARTEN) &= ui32Mask;
+    AM_REG(CLKGEN, UARTEN) |= ui32UartEn;
+
+    //
+    // Begin critical section.
+    //
+    AM_CRITICAL_END_ASM
+}
+
+//*****************************************************************************
+//
+//! @brief Enables HFRC auto-adjustment at the specified interval.
+//!
+//! @param ui32Warmup - How long to give the HFRC to stabilize during each
+//! calibration attempt.
+//! @param ui32Frequency - How often the auto-adjustment should happen.
+//!
+//! This function enables HFRC auto-adjustment from an external crystal
+//! oscillator even when the crystal is not normally being used.
+//!
+//! ui32Warmup should be one of the following values:
+//!
+//!     AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC
+//!     AM_REG_CLKGEN_HFADJ_HFWARMUP_2SEC
+//!
+//! ui32Frequency should be one of the following values:
+//!
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_16SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_32SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_64SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_128SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_256SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_512SEC
+//!     AM_REG_CLKGEN_HFADJ_HFADJCK_1024SEC
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency)
+{
+    //
+    // Set the HFRC Auto-adjust register for the user's chosen settings. Assume
+    // that the HFRC should be calibrated to 48 MHz and that the crystal is
+    // running at 32.768 kHz.
+    //
+    AM_REG(CLKGEN, HFADJ) =
+         AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2                      |
+         ui32Warmup                                                         |
+         AM_REG_CLKGEN_HFADJ_HFXTADJ(AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT)   |
+         ui32Frequency                                                      |
+         AM_REG_CLKGEN_HFADJ_HFADJEN_EN;
+}
+
+//*****************************************************************************
+//
+//! @brief Disables HFRC auto-adjustment.
+//!
+//! This function disables HFRC auto-adjustment.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_clkgen_hfrc_adjust_disable(void)
+{
+    //
+    // Disable the clock out.
+    //
+    AM_REG(CLKGEN, HFADJ) =
+        AM_REG_CLKGEN_HFADJ_HFADJ_GAIN_Gain_of_1_in_2                       |
+        AM_REG_CLKGEN_HFADJ_HFWARMUP_1SEC                                   |
+        AM_REG_CLKGEN_HFADJ_HFXTADJ(AM_REG_CLKGEN_HFADJ_HFXTADJ_DEFAULT)    |
+        AM_REG_CLKGEN_HFADJ_HFADJCK_4SEC                                    |
+        AM_REG_CLKGEN_HFADJ_HFADJEN_DIS;
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h

@@ -0,0 +1,206 @@
+//*****************************************************************************
+//
+//  am_hal_clkgen.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the CLKGEN.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_CLKGEN_H
+#define AM_HAL_CLKGEN_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name System Clock max frequency
+//! @brief Defines the maximum clock frequency for this device.
+//!
+//! These macros provide a definition of the maximum clock frequency.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_FREQ_MAX_HZ       48000000
+#define AM_HAL_CLKGEN_FREQ_MAX_MHZ      (AM_HAL_CLKGEN_FREQ_MAX_HZ / 1000000)
+//! @}
+
+//*****************************************************************************
+//
+//! @name System Clock Selection
+//! @brief Divisor selection for the main system clock.
+//!
+//! These macros may be used along with the am_hal_clkgen_sysctl_select()
+//! function to select the frequency of the main system clock.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_SYSCLK_MAX        AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
+#define AM_HAL_CLKGEN_SYSCLK_48MHZ      AM_REG_CLKGEN_CCTRL_CORESEL_HFRC
+//! @}
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to set and clear interrupt bits.
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_INT_ALM           AM_REG_CLKGEN_INTEN_ALM_M
+#define AM_HAL_CLKGEN_INT_OF            AM_REG_CLKGEN_INTEN_OF_M
+#define AM_HAL_CLKGEN_INT_ACC           AM_REG_CLKGEN_INTEN_ACC_M
+#define AM_HAL_CLKGEN_INT_ACF           AM_REG_CLKGEN_INTEN_ACF_M
+//! @}
+
+//*****************************************************************************
+//
+//! @name OSC Start and Stop
+//! @brief OSC Start and Stop defines.
+//!
+//! OSC Start and Stop defines to be used with \e am_hal_clkgen_osc_x().
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_OSC_LFRC          AM_REG_CLKGEN_OCTRL_STOPRC_M
+#define AM_HAL_CLKGEN_OSC_XT            AM_REG_CLKGEN_OCTRL_STOPXT_M
+//! @}
+
+//*****************************************************************************
+//
+// OSC Start, Stop, Select defines
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC         AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV4      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV4
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8      AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV16     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV16
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV32     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_RTC_100Hz    AM_REG_CLKGEN_CLKOUT_CKSEL_RTC_100Hz
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV2M     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV2M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT           AM_REG_CLKGEN_CLKOUT_CKSEL_XT
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CG_100Hz     AM_REG_CLKGEN_CLKOUT_CKSEL_CG_100Hz
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC         AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4    AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV4
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8    AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV8
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32   AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64   AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV128
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV256
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLK     AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLK
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FLASH_CLK    AM_REG_CLKGEN_CLKOUT_CKSEL_FLASH_CLK
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2    AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32   AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512  AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV512
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K  AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV256    AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV256
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV8K     AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV8K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XT_DIV64K    AM_REG_CLKGEN_CLKOUT_CKSEL_XT_DIV64K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128 AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz    AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M  AM_REG_CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M   AM_REG_CLKGEN_CLKOUT_CKSEL_LFRC_DIV2M
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE       AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8  AM_REG_CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE   AM_REG_CLKGEN_CLKOUT_CKSEL_CORE_CLKNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE         AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16   AM_REG_CLKGEN_CLKOUT_CKSEL_XTNE_DIV16
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32 AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_FCLKNE       AM_REG_CLKGEN_CLKOUT_CKSEL_FCLKNE
+#define AM_HAL_CLKGEN_CLKOUT_CKSEL_LFRCNE       AM_REG_CLKGEN_CLKOUT_CKSEL_LFRCNE
+
+//*****************************************************************************
+//
+// UARTEN
+//
+//*****************************************************************************
+#define AM_HAL_CLKGEN_UARTEN_DIS          AM_REG_CLKGEN_UARTEN_UART0EN_DIS
+#define AM_HAL_CLKGEN_UARTEN_EN           AM_REG_CLKGEN_UARTEN_UART0EN_EN
+#define AM_HAL_CLKGEN_UARTEN_REDUCE_FREQ  AM_REG_CLKGEN_UARTEN_UART0EN_REDUCE_FREQ
+#define AM_HAL_CLKGEN_UARTEN_EN_POWER_SAV AM_REG_CLKGEN_UARTEN_UART0EN_EN_POWER_SAV
+
+#define AM_HAL_CLKGEN_UARTEN_UARTENn_S(module)                                  \
+        ((module) *                                                             \
+        (AM_REG_CLKGEN_UARTEN_UART1EN_S - AM_REG_CLKGEN_UARTEN_UART0EN_S))
+
+#define AM_HAL_CLKGEN_UARTEN_UARTENn_M(module)                                  \
+        (AM_REG_CLKGEN_UARTEN_UART0EN_M << AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
+
+//
+// UARTEN: entype is one of DIS, EN, REDUCE_FREQ, EN_POWER_SAV.
+//
+#define AM_HAL_CLKGEN_UARTEN_UARTENn(module, entype)                            \
+        (AM_REG_CLKGEN_UARTEN_UART0EN_##entype <<                               \
+         AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_clkgen_sysclk_select(uint32_t ui32ClockSetting);
+extern uint32_t am_hal_clkgen_sysclk_get(void);
+extern void am_hal_clkgen_osc_start(uint32_t ui32OscFlags);
+extern void am_hal_clkgen_osc_stop(uint32_t ui32OscFlags);
+extern void am_hal_clkgen_clkout_enable(uint32_t ui32Signal);
+extern void am_hal_clkgen_clkout_disable(void);
+extern void am_hal_clkgen_uarten_set(uint32_t ui32Module, uint32_t ui32UartEn);
+extern void am_hal_clkgen_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_clkgen_int_enable_get(void);
+extern void am_hal_clkgen_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_clkgen_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_clkgen_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_clkgen_int_status_get(bool bEnabledOnly);
+extern void am_hal_clkgen_hfrc_adjust_enable(uint32_t ui32Warmup, uint32_t ui32Frequency);
+extern void am_hal_clkgen_hfrc_adjust_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_CLKGEN_H

bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h

@@ -0,0 +1,278 @@
+//*****************************************************************************
+//
+//  am_hal_ctimer.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the CTIMER.
+//!
+//! @addtogroup ctimer2 Counter/Timer (CTIMER)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_CTIMER_H
+#define AM_HAL_CTIMER_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! Number of timers
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_TIMERS_NUM    4
+
+//*****************************************************************************
+//
+//! Timer offset value
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_TIMER_OFFSET  (AM_REG_CTIMER_TMR1_O - AM_REG_CTIMER_TMR0_O)
+
+//*****************************************************************************
+//
+//! @name Interrupt Status Bits
+//! @brief Interrupt Status Bits for enable/disble use
+//!
+//! These macros may be used to set and clear interrupt bits
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_INT_TIMERA0C0         AM_REG_CTIMER_INTEN_CTMRA0C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA0C1         AM_REG_CTIMER_INTEN_CTMRA0C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERA1C0         AM_REG_CTIMER_INTEN_CTMRA1C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA1C1         AM_REG_CTIMER_INTEN_CTMRA1C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERA2C0         AM_REG_CTIMER_INTEN_CTMRA2C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA2C1         AM_REG_CTIMER_INTEN_CTMRA2C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERA3C0         AM_REG_CTIMER_INTEN_CTMRA3C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERA3C1         AM_REG_CTIMER_INTEN_CTMRA3C1INT_M
+
+#define AM_HAL_CTIMER_INT_TIMERB0C0         AM_REG_CTIMER_INTEN_CTMRB0C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB0C1         AM_REG_CTIMER_INTEN_CTMRB0C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERB1C0         AM_REG_CTIMER_INTEN_CTMRB1C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB1C1         AM_REG_CTIMER_INTEN_CTMRB1C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERB2C0         AM_REG_CTIMER_INTEN_CTMRB2C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB2C1         AM_REG_CTIMER_INTEN_CTMRB2C1INT_M
+#define AM_HAL_CTIMER_INT_TIMERB3C0         AM_REG_CTIMER_INTEN_CTMRB3C0INT_M
+#define AM_HAL_CTIMER_INT_TIMERB3C1         AM_REG_CTIMER_INTEN_CTMRB3C1INT_M
+
+//
+// Deprecated, use the newer macros above.
+//
+#define AM_HAL_CTIMER_INT_TIMERA0           AM_HAL_CTIMER_INT_TIMERA0C0
+#define AM_HAL_CTIMER_INT_TIMERB0           AM_HAL_CTIMER_INT_TIMERB0C0
+#define AM_HAL_CTIMER_INT_TIMERA1           AM_HAL_CTIMER_INT_TIMERA1C0
+#define AM_HAL_CTIMER_INT_TIMERB1           AM_HAL_CTIMER_INT_TIMERB1C0
+#define AM_HAL_CTIMER_INT_TIMERA2           AM_HAL_CTIMER_INT_TIMERA2C0
+#define AM_HAL_CTIMER_INT_TIMERB2           AM_HAL_CTIMER_INT_TIMERB2C0
+#define AM_HAL_CTIMER_INT_TIMERA3           AM_HAL_CTIMER_INT_TIMERA3C0
+#define AM_HAL_CTIMER_INT_TIMERB3           AM_HAL_CTIMER_INT_TIMERB3C0
+//! @}
+
+//*****************************************************************************
+//
+//! @name Configuration options
+//! @brief Configuration options for \e am_hal_ctimer_config_t
+//!
+//! These options are to be used with the \e am_hal_ctimer_config_t structure
+//! used by \e am_hal_ctimer_config
+//!  @{
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_CLK_PIN               AM_REG_CTIMER_CTRL0_TMRA0CLK(0x0)
+#define AM_HAL_CTIMER_HFRC_12MHZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0x1)
+#define AM_HAL_CTIMER_HFRC_3MHZ             AM_REG_CTIMER_CTRL0_TMRA0CLK(0x2)
+#define AM_HAL_CTIMER_HFRC_187_5KHZ         AM_REG_CTIMER_CTRL0_TMRA0CLK(0x3)
+#define AM_HAL_CTIMER_HFRC_47KHZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0x4)
+#define AM_HAL_CTIMER_HFRC_12KHZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0x5)
+#define AM_HAL_CTIMER_XT_32_768KHZ          AM_REG_CTIMER_CTRL0_TMRA0CLK(0x6)
+#define AM_HAL_CTIMER_XT_16_384KHZ          AM_REG_CTIMER_CTRL0_TMRA0CLK(0x7)
+#define AM_HAL_CTIMER_XT_2_048KHZ           AM_REG_CTIMER_CTRL0_TMRA0CLK(0x8)
+#define AM_HAL_CTIMER_XT_256HZ              AM_REG_CTIMER_CTRL0_TMRA0CLK(0x9)
+#define AM_HAL_CTIMER_LFRC_512HZ            AM_REG_CTIMER_CTRL0_TMRA0CLK(0xA)
+#define AM_HAL_CTIMER_LFRC_32HZ             AM_REG_CTIMER_CTRL0_TMRA0CLK(0xB)
+#define AM_HAL_CTIMER_LFRC_1HZ              AM_REG_CTIMER_CTRL0_TMRA0CLK(0xC)
+#define AM_HAL_CTIMER_LFRC_1_16HZ           AM_REG_CTIMER_CTRL0_TMRA0CLK(0xD)
+#define AM_HAL_CTIMER_RTC_100HZ             AM_REG_CTIMER_CTRL0_TMRA0CLK(0xE)
+#define AM_HAL_CTIMER_HCLK                  AM_REG_CTIMER_CTRL0_TMRA0CLK(0xF)
+#define AM_HAL_CTIMER_BUCK                  AM_REG_CTIMER_CTRL0_TMRA0CLK(0x10)
+//! @}
+
+//*****************************************************************************
+//
+// Timer function macros.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_FN_ONCE               AM_REG_CTIMER_CTRL0_TMRA0FN(0)
+#define AM_HAL_CTIMER_FN_REPEAT             AM_REG_CTIMER_CTRL0_TMRA0FN(1)
+#define AM_HAL_CTIMER_FN_PWM_ONCE           AM_REG_CTIMER_CTRL0_TMRA0FN(2)
+#define AM_HAL_CTIMER_FN_PWM_REPEAT         AM_REG_CTIMER_CTRL0_TMRA0FN(3)
+#define AM_HAL_CTIMER_FN_CONTINUOUS         AM_REG_CTIMER_CTRL0_TMRA0FN(4)
+
+//*****************************************************************************
+//
+// Half-timer options.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_INT_ENABLE            AM_REG_CTIMER_CTRL0_TMRA0IE0_M
+#define AM_HAL_CTIMER_PIN_ENABLE            AM_REG_CTIMER_CTRL0_TMRA0PE_M
+#define AM_HAL_CTIMER_PIN_INVERT            AM_REG_CTIMER_CTRL0_TMRA0POL_M
+#define AM_HAL_CTIMER_CLEAR                 AM_REG_CTIMER_CTRL0_TMRA0CLR_M
+
+//*****************************************************************************
+//
+// Additional timer options.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_LINK                  AM_REG_CTIMER_CTRL0_CTLINK0_M
+#define AM_HAL_CTIMER_ADC_TRIG              AM_REG_CTIMER_CTRL3_ADCEN_M
+
+//*****************************************************************************
+//
+// Timer selection macros.
+//
+//*****************************************************************************
+#define AM_HAL_CTIMER_TIMERA                0x0000FFFF
+#define AM_HAL_CTIMER_TIMERB                0xFFFF0000
+#define AM_HAL_CTIMER_BOTH                  0xFFFFFFFF
+//! @}
+
+//*****************************************************************************
+//
+// Timer configuration structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Set to 1 to operate this timer as a 32-bit timer instead of two 16-bit
+    //! timers.
+    //
+    uint32_t ui32Link;
+
+    //
+    //! Configuration options for TIMERA
+    //
+    uint32_t ui32TimerAConfig;
+
+    //
+    //! Configuration options for TIMERB
+    //
+    uint32_t ui32TimerBConfig;
+
+}
+am_hal_ctimer_config_t;
+
+//*****************************************************************************
+//
+// Function pointer type for CTimer interrupt handlers.
+//
+//*****************************************************************************
+typedef void (*am_hal_ctimer_handler_t)(void);
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_ctimer_config(uint32_t ui32TimerNumber,
+                                 am_hal_ctimer_config_t *psConfig);
+
+extern void am_hal_ctimer_config_single(uint32_t ui32TimerNumber,
+                                        uint32_t ui32TimerSegment,
+                                        uint32_t ui32ConfigVal);
+
+extern void am_hal_ctimer_start(uint32_t ui32TimerNumber,
+                                uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_stop(uint32_t ui32TimerNumber,
+                               uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_clear(uint32_t ui32TimerNumber,
+                                uint32_t ui32TimerSegment);
+
+extern uint32_t am_hal_ctimer_read(uint32_t ui32TimerNumber,
+                                   uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_pin_enable(uint32_t ui32TimerNumber,
+                                     uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber,
+                                      uint32_t ui32TimerSegment);
+
+extern void am_hal_ctimer_pin_invert(uint32_t ui32TimerNumber,
+                                     uint32_t ui32TimerSegment,
+                                     bool bInvertOutput);
+
+extern void am_hal_ctimer_compare_set(uint32_t ui32TimerNumber,
+                                      uint32_t ui32TimerSegment,
+                                      uint32_t ui32CompareReg,
+                                      uint32_t ui32Value);
+
+extern void am_hal_ctimer_period_set(uint32_t ui32TimerNumber,
+                                     uint32_t ui32TimerSegment,
+                                     uint32_t ui32Period,
+                                     uint32_t ui32OnTime);
+
+extern void am_hal_ctimer_adc_trigger_enable(void);
+extern void am_hal_ctimer_adc_trigger_disable(void);
+extern void am_hal_ctimer_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ctimer_int_enable_get(void);
+extern void am_hal_ctimer_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_ctimer_int_set(uint32_t ui32Interrupt);
+extern void am_hal_ctimer_int_clear(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ctimer_int_status_get(bool bEnabledOnly);
+extern void am_hal_ctimer_int_register(uint32_t ui32Interrupt,
+                                       am_hal_ctimer_handler_t pfnHandler);
+extern void am_hal_ctimer_int_service(uint32_t ui32Status);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_CTIMER_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_debug.c

@@ -0,0 +1,81 @@
+//*****************************************************************************
+//
+//  am_hal_debug.c
+//! @file
+//!
+//! @brief Useful functions for debugging.
+//!
+//! These functions and macros were created to assist with debugging. They are
+//! intended to be as unintrusive as possible and designed to be removed from
+//! the compilation of a project when they are no longer needed.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Default implementation of a failed ASSERT statement.
+//!
+//! @param pcFile is the name of the source file where the error occurred.
+//! @param ui32Line is the line number where the error occurred.
+//! @param pcMessage is an optional message describing the failure.
+//!
+//! This function is called by am_hal_debug_assert() macro when the supplied
+//! condition is not true. The implementation here simply halts the application
+//! for further analysis. Individual applications may define their own
+//! implementations of am_hal_debug_error() to provide more detailed feedback
+//! about the failed am_hal_debug_assert() statement.
+//!
+//! @return
+//
+//*****************************************************************************
+#if defined (__IAR_SYSTEMS_ICC__)
+__weak void
+#else
+void __attribute__((weak))
+#endif
+am_hal_debug_error(const char *pcFile, uint32_t ui32Line, const char *pcMessage)
+{
+    //
+    // Halt for analysis.
+    //
+    while(1);
+}

bsp/apollo2/libraries/drivers/hal/am_hal_debug.h

@@ -0,0 +1,89 @@
+//*****************************************************************************
+//
+//  am_hal_debug.h
+//! @file
+//!
+//! @brief Useful macros for debugging.
+//!
+//! These functions and macros were created to assist with debugging. They are
+//! intended to be as unintrusive as possible and designed to be removed from
+//! the compilation of a project when they are no longer needed.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_DEBUG_H
+#define AM_HAL_DEBUG_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Debug assert macros.
+//
+//*****************************************************************************
+#ifndef AM_HAL_DEBUG_NO_ASSERT
+
+#define am_hal_debug_assert_msg(bCondition, pcMessage)                        \
+    if ( !(bCondition))  am_hal_debug_error(__FILE__, __LINE__, pcMessage)
+
+#define am_hal_debug_assert(bCondition)                                       \
+    if ( !(bCondition))  am_hal_debug_error(__FILE__, __LINE__, 0)
+
+#else
+
+#define am_hal_debug_assert_msg(bCondition, pcMessage)
+#define am_hal_debug_assert(bCondition)
+
+#endif // AM_DEBUG_ASSERT
+
+//*****************************************************************************
+//
+// External function prototypes.
+//
+//*****************************************************************************
+extern void am_hal_debug_error(const char *pcFile, uint32_t ui32Line,
+                               const char *pcMessage);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_DEBUG_H
+

bsp/apollo2/libraries/drivers/hal/am_hal_flash.h

@@ -0,0 +1,297 @@
+//*****************************************************************************
+//
+//  am_hal_flash.h
+//! @file
+//!
+//! @brief Functions for performing Flash operations.
+//!
+//! @addtogroup flash2 Flash
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_FLASH_H
+#define AM_HAL_FLASH_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+//*****************************************************************************
+//
+// Flash Program keys.
+//
+//*****************************************************************************
+#define AM_HAL_FLASH_PROGRAM_KEY            0x12344321
+#define AM_HAL_FLASH_RECOVERY_KEY           0xA35C9B6D
+#define AM_HAL_FLASH_INFO_KEY               0x12344321
+#define AM_HAL_FLASH_OTP_KEY                (AM_HAL_FLASH_INFO_KEY)
+
+//*****************************************************************************
+//
+// Some helpful flash values and macros.
+//
+//*****************************************************************************
+#define AM_HAL_FLASH_ADDR                   0x00000000
+#define AM_HAL_FLASH_PAGE_SIZE              ( 8 * 1024 )
+#define AM_HAL_FLASH_INFO_SIZE              AM_HAL_FLASH_PAGE_SIZE
+#define AM_HAL_FLASH_INSTANCE_SIZE          ( 512 * 1024 )
+#define AM_HAL_FLASH_INSTANCE_PAGES         ( AM_HAL_FLASH_INSTANCE_SIZE / AM_HAL_FLASH_PAGE_SIZE )
+#define AM_HAL_FLASH_TOTAL_SIZE             ( AM_HAL_FLASH_INSTANCE_SIZE * 2 )
+#define AM_HAL_FLASH_LARGEST_VALID_ADDR     ( AM_HAL_FLASH_ADDR + AM_HAL_FLASH_TOTAL_SIZE - 1 )
+
+//
+// Convert an absolute flash address to a instance
+//
+#define AM_HAL_FLASH_ADDR2INST(addr)        ( ( addr >> 19 ) & 1 )
+
+//
+// Convert an absolute flash address to a page number relative to the instance
+//
+#define AM_HAL_FLASH_ADDR2PAGE(addr)        ( ( addr >> 13 ) & 0x3F )
+
+//
+// Convert an absolute flash address to an absolute page number
+//
+#define AM_HAL_FLASH_ADDR2ABSPAGE(addr)     ( addr >> 13 )
+
+//
+// Given a number of microseconds, convert to a value representing the number of
+// cycles that will give that delay. This macro is basically taking into account
+// some of the call overhead.
+// e.g. To provide a 2us delay:
+//  am_hal_flash_delay( FLASH_CYCLES_US(2) );
+//
+#define FLASH_CYCLES_US(n)      ((n * (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3)) - 4)
+
+//
+// Backward compatibility
+//
+#define am_hal_flash_program_otp        am_hal_flash_program_info
+#define am_hal_flash_program_otp_sram   am_hal_flash_program_info_sram
+
+//*****************************************************************************
+//
+// Structure of function pointers to helper functions for invoking various
+// flash operations. The functions we are pointing to here are in the Apollo 2
+// integrated BOOTROM.
+//
+//*****************************************************************************
+typedef struct am_hal_flash_helper_struct
+{
+    //
+    // The basics.
+    //
+    int      (*flash_mass_erase)(uint32_t, uint32_t);
+    int      (*flash_page_erase)(uint32_t, uint32_t, uint32_t);
+    int      (*flash_program_main)(uint32_t,  uint32_t *,
+                                          uint32_t*, uint32_t);
+    int      (*flash_program_info)(uint32_t,   uint32_t,
+                                         uint32_t*,  uint32_t, uint32_t);
+
+    //
+    // Non-blocking variants, but be careful these are not interrupt safe so
+    // mask interrupts while these very long operations proceed.
+    //
+    int      (*flash_mass_erase_nb)(uint32_t, uint32_t);
+    int      (*flash_page_erase_nb)(uint32_t, uint32_t, uint32_t);
+    bool     (*flash_nb_operation_complete)(void);
+
+    //
+    // Essentially these are recovery options.
+    //
+    int      (*flash_erase_info)(uint32_t, uint32_t);
+    int      (*flash_erase_main_plus_info)(uint32_t, uint32_t);
+    int      (*flash_erase_main_plus_info_both_instances)(uint32_t);
+    void     (*flash_recovery)(uint32_t);
+
+    //
+    // Useful utilities.
+    //
+    uint32_t (*flash_util_read_word)(uint32_t*);
+    void     (*flash_util_write_word)(uint32_t*, uint32_t);
+    void     (*delay_cycles)(uint32_t);
+
+    //
+    // The following functions pointers will generally never be called from
+    // user programs. They are here primarily to document these entry points
+    // which are usable from a debugger or debugger script.
+    //
+    void     (*flash_program_main_sram)(void);
+    void     (*flash_program_info_sram)(void);
+    void     (*flash_erase_main_pages_sram)(void);
+    void     (*flash_mass_erase_sram)(void);
+    void     (*flash_erase_info_sram)(void);
+    void     (*flash_erase_main_plus_info_sram)(void);
+} g_am_hal_flash_t;
+extern g_am_hal_flash_t g_am_hal_flash;
+
+
+//*****************************************************************************
+//
+// Define some FLASH INFO SPACE values and macros.
+//
+//*****************************************************************************
+#define AM_HAL_FLASH_INFO_ADDR              0x50020000
+#define AM_HAL_FLASH_INFO_SECURITY_O        0x10
+#define AM_HAL_FLASH_INFO_WRITPROT_O        0x20
+#define AM_HAL_FLASH_INFO_COPYPROT_O        0x30
+
+#define AM_HAL_FLASH_INFO_SECURITY_ADDR     (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_SECURITY_O)
+#define AM_HAL_FLASH_INFO_WRITPROT_ADDR     (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_WRITPROT_O)
+#define AM_HAL_FLASH_INFO_COPYPROT_ADDR     (AM_HAL_FLASH_INFO_ADDR + AM_HAL_FLASH_INFO_COPYPROT_O)
+
+//
+// Define the customer info signature data (at AM_HAL_FLASH_INFO_ADDR).
+// These bits must exist in the customer info space in order for many of the
+// security and protection functions to work.
+//
+#define AM_HAL_FLASH_INFO_SIGNATURE0        0x48EAAD88
+#define AM_HAL_FLASH_INFO_SIGNATURE1        0xC9705737
+#define AM_HAL_FLASH_INFO_SIGNATURE2        0x0A6B8458
+#define AM_HAL_FLASH_INFO_SIGNATURE3        0xE41A9D74
+
+//
+// Define the customer security bits (at AM_HAL_FLASH_INFO_SECURITY_ADDR)
+//
+#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S       0
+#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S            1
+#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S           2
+#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S          3
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S         4
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S        8
+#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S     9
+
+#define AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_M       ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_DEBUGGERPROT_S))
+#define AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_M            ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SWOCTRL_S))
+#define AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_M           ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_SRAMWIPE_S))
+#define AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_M          ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_FLASHWIPE_S))
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_M         ((uint32_t)(0xF << AM_HAL_FLASH_INFO_SECURITY_ENINFOPRGM_S))
+#define AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_M        ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_ENINFOERASE_S))
+#define AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_M     ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S))
+#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP_M          ((uint32_t)(0x1 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S))
+#define AM_HAL_FLASH_INFO_SECURITY_DEEPSLEEP            ((uint32_t)(0x0 << AM_HAL_FLASH_INFO_SECURITY_BOOTLOADERSPIN_S))
+
+//
+// Protection chunk macros
+// AM_HAL_FLASH_INFO_CHUNK2ADDR: Convert a chunk number to an address
+// AM_HAL_FLASH_INFO_CHUNK2INST: Convert a chunk number to an instance number
+// AM_HAL_FLASH_INFO_ADDR2CHUNK: Convert an address to a chunk number
+//
+#define AM_HAL_FLASH_INFO_CHUNKSIZE         (16*1024)
+
+#define AM_HAL_FLASH_INFO_CHUNK2ADDR(n)     (AM_HAL_FLASH_ADDR + (n << 14))
+#define AM_HAL_FLASH_INFO_CHUNK2INST(n)     ((n >> 5) & 1
+#define AM_HAL_FLASH_INFO_ADDR2CHUNK(n)     ((n) >> 14)
+
+//*****************************************************************************
+//
+// Function prototypes for the helper functions
+//
+//*****************************************************************************
+extern int am_hal_flash_mass_erase(uint32_t ui32Value, uint32_t ui32FlashInst);
+extern int am_hal_flash_page_erase(uint32_t ui32Value, uint32_t ui32FlashInst,
+                                   uint32_t ui32PageNum);
+extern int am_hal_flash_program_main(uint32_t value, uint32_t *pSrc,
+                                     uint32_t *pDst, uint32_t  NumberOfWords);
+extern int am_hal_flash_program_info(uint32_t ui32Value, uint32_t ui32InfoInst,
+                                     uint32_t *pui32Src, uint32_t ui32Offset,
+                                     uint32_t ui32NumWords);
+
+//
+// Recovery type functions for Customer INFO space.
+//
+extern int      am_hal_flash_erase_info(uint32_t ui32ProgramKey,
+                                        uint32_t ui32Instance);
+extern int      am_hal_flash_erase_main_plus_info(uint32_t ui32ProgramKey,
+                                                  uint32_t ui32Instance);
+extern int      am_hal_flash_erase_main_plus_info_both_instances(
+                                                  uint32_t ui32ProgramKey);
+extern void     am_hal_flash_recovery(uint32_t ui32RecoveryKey);
+
+//
+// BOOTROM resident reader, writer and delay utility functions.
+//
+extern uint32_t am_hal_flash_load_ui32(uint32_t ui32Address);
+extern void     am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data);
+extern void     am_hal_flash_delay(uint32_t ui32Iterations);
+
+//
+// These functions update security/protection bits in the customer INFO blOCK.
+//
+extern bool     am_hal_flash_customer_info_signature_check(void);
+extern bool     am_hal_flash_info_signature_set(void);
+extern int32_t  am_hal_flash_info_erase_disable(void);
+extern bool     am_hal_flash_info_erase_disable_check(void);
+extern int32_t  am_hal_flash_info_program_disable(uint32_t ui32Mask);
+extern uint32_t am_hal_flash_info_program_disable_get(void);
+extern int32_t  am_hal_flash_wipe_flash_enable(void);
+extern bool     am_hal_flash_wipe_flash_enable_check(void);
+extern int32_t  am_hal_flash_wipe_sram_enable(void);
+extern bool     am_hal_flash_wipe_sram_enable_check(void);
+extern int32_t  am_hal_flash_swo_disable(void);
+extern bool     am_hal_flash_swo_disable_check(void);
+extern int32_t  am_hal_flash_debugger_disable(void);
+extern bool     am_hal_flash_debugger_disable_check(void);
+
+extern int32_t  am_hal_flash_copy_protect_set(uint32_t *pui32StartAddress,
+                                              uint32_t *pui32StopAddress);
+extern bool     am_hal_flash_copy_protect_check(uint32_t *pui32StartAddress,
+                                                uint32_t *pui32StopAddress);
+extern int32_t  am_hal_flash_write_protect_set(uint32_t *pui32StartAddress,
+                                               uint32_t *pui32StopAddress);
+extern bool     am_hal_flash_write_protect_check(uint32_t *pui32StartAddress,
+                                                 uint32_t *pui32StopAddress);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_FLASH_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_global.c

@@ -0,0 +1,59 @@
+//*****************************************************************************
+//
+//  am_hal_global.c
+//! @file
+//!
+//! @brief Locate global variables here.
+//!
+//! This module contains global variables that are used throughout the HAL.
+//!
+//! One use in particular is that it uses a global HAL flags variable that
+//! contains flags used in various parts of the HAL.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Global Variables
+//
+//*****************************************************************************
+uint32_t volatile g_ui32HALflags = 0x00000000;

bsp/apollo2/libraries/drivers/hal/am_hal_global.h

@@ -0,0 +1,114 @@
+//*****************************************************************************
+//
+//  am_hal_global.h
+//! @file
+//!
+//! @brief Locate all HAL global variables here.
+//!
+//! This module contains global variables that are used throughout the HAL,
+//! but not necessarily those designated as const (which typically end up in
+//! flash). Consolidating globals here will make it easier to manage them.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_GLOBAL_H
+#define AM_HAL_GLOBAL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Macro definitions
+//
+//*****************************************************************************
+
+//******************************************************************************
+//
+// Macros used to access the bit fields in the flags variable.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_BFR(flagnm)                                            \
+    ((g_ui32HALflags & AM_HAL_FLAGS_##flagnm##_M) >> AM_HAL_FLAGS_##flagnm##_S)
+
+#define AM_HAL_FLAGS_BFW(flagnm, value)                                     \
+    g_ui32HALflags = ((g_ui32HALflags & (~(AM_HAL_FLAGS_##flagnm##_M)))  |    \
+     ((value << AM_HAL_FLAGS_##flagnm##_S) & (AM_HAL_FLAGS_##flagnm##_M)) )
+
+//******************************************************************************
+//
+// ITMSKIPENABLEDISABLE - Set when the ITM is not to be disabled.  This is
+//                        typically needed by Keil debug.ini.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S         0
+#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M         (1 << AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S)
+#define AM_HAL_FLAGS_ITMSKIPENABLEDISABLE(n)        (((n) << AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_S) & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
+
+//******************************************************************************
+//
+// ITMBKPT - Breakpoint at the end of itm_enable(), which is needed by
+//           Keil debug.ini.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_ITMBKPT_S                      1
+#define AM_HAL_FLAGS_ITMBKPT_M                      (1 << AM_HAL_FLAGS_ITMBKPT_S)
+#define AM_HAL_FLAGS_ITMBKPT(n)                     (((n) << AM_HAL_FLAGS_ITMBKPT_S) & AM_HAL_FLAGS_ITMBKPT_M)
+
+//******************************************************************************
+//
+// Next available flag or bit field.
+//
+//******************************************************************************
+#define AM_HAL_FLAGS_NEXTBITFIELD_S                 2
+#define AM_HAL_FLAGS_NEXTBITFIELD_M                 (1 << AM_HAL_FLAGS_NEXTBITFIELD_S)
+#define AM_HAL_FLAGS_NEXTBITFIELD(n)                (((n) << AM_HAL_FLAGS_NEXTBITFIELD_S) & AM_HAL_FLAGS_NEXTBITFIELD_M)
+
+//*****************************************************************************
+//
+// Global Variables extern declarations.
+//
+//*****************************************************************************
+extern volatile uint32_t g_ui32HALflags;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_GLOBAL_H

bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h

@@ -0,0 +1,100 @@
+//*****************************************************************************
+//
+//  am_hal_i2c_bit_bang.h
+//! @file
+//!
+//! @brief I2C bit bang module.
+//!
+//! These functions implement the I2C bit bang utility
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_I2C_BIT_BANG_H
+#define AM_HAL_I2C_BIT_BANG_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Enumerated return constants
+//
+//*****************************************************************************
+typedef enum
+{
+    AM_HAL_I2C_BIT_BANG_SUCCESS = 0,
+    AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED,
+    AM_HAL_I2C_BIT_BANG_DATA_NAKED,
+    AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT,
+    AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT,
+}am_hal_i2c_bit_bang_enum_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
+                                     uint32_t sda_gpio_number);
+
+extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_send(uint8_t address,
+                                                    uint32_t number_of_bytes,
+                                                    uint8_t *pData,
+                                                    uint8_t ui8Offset,
+                                                    bool bUseOffset,
+                                                    bool bNoStop);
+
+extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_receive(uint8_t address,
+                                                    uint32_t number_of_bytes,
+                                                    uint8_t *pData,
+                                                    uint8_t ui8Offset,
+                                                    bool bUseOffset,
+                                                    bool bNoStop);
+#ifdef __cplusplus
+}
+#endif
+
+#endif //AM_HAL_I2C_BIT_BANG_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c

@@ -0,0 +1,407 @@
+//*****************************************************************************
+//
+//  am_hal_interrupt.c
+//! @file
+//!
+//! @brief Helper functions supporting interrupts and NVIC operation.
+//!
+//! These functions may be used for NVIC-level interrupt configuration.
+//!
+//! @addtogroup interrupt2 Interrupt (ARM NVIC support functions)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Enable an interrupt.
+//!
+//! @param ui32Interrupt The ISR number of the interrupt to be enabled.
+//!
+//! This function enables an interrupt signal to the NVIC based on the provided
+//! ISR number.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_interrupt_enable(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // enable it using the NVIC register.
+        //
+        AM_REG(NVIC, ISER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+    else
+    {
+        //
+        // If this is an ARM internal interrupt number, route it to the
+        // appropriate enable register.
+        //
+        switch(ui32Interrupt)
+        {
+            case AM_HAL_INTERRUPT_BUSFAULT:
+                AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 1);
+            break;
+
+            case AM_HAL_INTERRUPT_USAGEFAULT:
+                AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 1);
+            break;
+
+            case AM_HAL_INTERRUPT_MPUFAULT:
+                AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 1);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Disable an interrupt.
+//!
+//! @param ui32Interrupt The ISR number of the interrupt to be disabled.
+//!
+//! This function disables an interrupt signal to the NVIC based on the
+//! provided ISR number.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_interrupt_disable(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // disable it using the NVIC register.
+        //
+        AM_REG(NVIC, ICER0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+    else
+    {
+        //
+        // If this is an ARM internal interrupt number, route it to the
+        // appropriate enable register.
+        //
+        switch(ui32Interrupt)
+        {
+            case AM_HAL_INTERRUPT_BUSFAULT:
+                AM_BFW(SYSCTRL, SHCSR, BUSFAULTENA, 0);
+            break;
+
+            case AM_HAL_INTERRUPT_USAGEFAULT:
+                AM_BFW(SYSCTRL, SHCSR, USAGEFAULTENA, 0);
+            break;
+
+            case AM_HAL_INTERRUPT_MPUFAULT:
+                AM_BFW(SYSCTRL, SHCSR, MEMFAULTENA, 0);
+            break;
+        }
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Set the priority of an interrupt vector.
+//!
+//! @param ui32Interrupt is the ISR number of the interrupt to change.
+//! @param ui32Priority is the new ISR priority value.
+//!
+//! This function changes the priority value in the NVIC for the given
+//! interrupt vector number.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_interrupt_priority_set(uint32_t ui32Interrupt, uint32_t ui32Priority)
+{
+    volatile uint32_t *pui32PriorityReg;
+    volatile uint32_t ui32OldPriority;
+    uint32_t ui32Shift;
+
+    //
+    // Find the correct priority register.
+    //
+    pui32PriorityReg = (volatile uint32_t *) AM_REG_NVIC_IPR0_O;
+    pui32PriorityReg += ((ui32Interrupt - 16) >> 2);
+
+    //
+    // Find the correct shift value.
+    //
+    ui32Shift = (((ui32Interrupt - 16) & 0x3) * 8);
+
+    //
+    // Mask out the old priority.
+    //
+    ui32OldPriority = *pui32PriorityReg;
+    ui32OldPriority &= ~(0xFF << ui32Shift);
+
+    //
+    // OR in the new priority.
+    //
+    *pui32PriorityReg |= (ui32Priority << ui32Shift);
+}
+
+//*****************************************************************************
+//
+//! @brief Set a pending interrupt bit in the NVIC (Software Interrupt)
+//!
+//! @param ui32Interrupt is the ISR number of the interrupt to change.
+//!
+//! This function sets the specified bit in the Interrupt Set Pending (ISPR0)
+//! register. For future MCUs there may be more than one ISPR.
+//!
+//! @return None
+//
+//*****************************************************************************
+void am_hal_interrupt_pend_set(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see if the specified interrupt is valid for this MCU
+    //
+    if ( ui32Interrupt > 47 )
+    {
+        return;
+    }
+
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // disable it using the NVIC register.
+        //
+        AM_REG(NVIC, ISPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Clear a pending interrupt bit in the NVIC without servicing it
+//!
+//! @param ui32Interrupt is the ISR number of the interrupt to change.
+//!
+//! This function clears the specified bit in the Interrupt Clear Pending
+//! (ICPR0) register. For future MCUs there may be more than one ICPR. This
+//! function is useful immediately following a WFI before interrupts are
+//! re-enabled.
+//!
+//! @return None
+//
+//*****************************************************************************
+void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt)
+{
+    //
+    // Check to see if the specified interrupt is valid for this MCU
+    //
+    if ( ui32Interrupt > 47 )
+    {
+        return;
+    }
+
+    //
+    // Check to see what type of interrupt this is.
+    //
+    if ( ui32Interrupt > 15 )
+    {
+        //
+        // If this ISR number corresponds to a "normal" peripheral interrupt,
+        // disable it using the NVIC register.
+        //
+        AM_REG(NVIC, ICPR0) = 0x1 << ((ui32Interrupt - 16) & 0x1F);
+    }
+}
+
+//*****************************************************************************
+//
+//! @brief Globally enable interrupt service routines
+//!
+//! This function allows interrupt signals from the NVIC to trigger ISR entry
+//! in the CPU. This function must be called if interrupts are to be serviced
+//! in software.
+//!
+//! @return 1 if interrupts were previously disabled, 0 otherwise.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+uint32_t __attribute__((naked))
+am_hal_interrupt_master_enable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsie i");
+    __asm("    bx lr");
+}
+#elif defined(__ARMCC_VERSION)
+__asm uint32_t
+am_hal_interrupt_master_enable(void)
+{
+    mrs     r0, PRIMASK
+    cpsie   i
+    bx      lr
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless uint32_t
+am_hal_interrupt_master_enable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsie i");
+    __asm("    bx lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+//*****************************************************************************
+//
+//! @brief Globally disable interrupt service routines
+//!
+//! This function prevents interrupt signals from the NVIC from triggering ISR
+//! entry in the CPU. This will effectively stop incoming interrupt sources
+//! from triggering their corresponding ISRs.
+//!
+//! @note Any external interrupt signal that occurs while the master interrupt
+//! disable is active will still reach the "pending" state in the NVIC, but it
+//! will not be allowed to reach the "active" state or trigger the
+//! corresponding ISR. Instead, these interrupts are essentially "queued" until
+//! the next time the master interrupt enable instruction is executed. At that
+//! time, the interrupt handlers will be executed in order of decreasing
+//! priority.
+//!
+//! @return 1 if interrupts were previously disabled, 0 otherwise.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+uint32_t __attribute__((naked))
+am_hal_interrupt_master_disable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsid i");
+    __asm("    bx lr");
+}
+#elif defined(__ARMCC_VERSION)
+__asm uint32_t
+am_hal_interrupt_master_disable(void)
+{
+    mrs     r0, PRIMASK
+    cpsid   i
+    bx      lr
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless uint32_t
+am_hal_interrupt_master_disable(void)
+{
+    __asm("    mrs     r0, PRIMASK");
+    __asm("    cpsid i");
+    __asm("    bx lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+//*****************************************************************************
+//
+//! @brief Sets the master interrupt state based on the input.
+//!
+//! @param ui32InterruptState - Desired PRIMASK value.
+//!
+//! This function directly writes the PRIMASK register in the ARM core. A value
+//! of 1 will disable interrupts, while a value of zero will enable them.
+//!
+//! This function may be used along with am_hal_interrupt_master_disable() to
+//! implement a nesting critical section. To do this, call
+//! am_hal_interrupt_master_disable() to start the critical section, and save
+//! its return value. To complete the critical section, call
+//! am_hal_interrupt_master_set() using the saved return value as \e
+//! ui32InterruptState. This will safely restore PRIMASK to the value it
+//! contained just before the start of the critical section.
+//!
+//! @return None.
+//
+//*****************************************************************************
+#if defined(__GNUC_STDC_INLINE__)
+void __attribute__((naked))
+am_hal_interrupt_master_set(uint32_t ui32InterruptState)
+{
+    __asm("    msr     PRIMASK, r0");
+    __asm("    bx lr");
+}
+#elif defined(__ARMCC_VERSION)
+__asm void
+am_hal_interrupt_master_set(uint32_t ui32InterruptState)
+{
+    msr     PRIMASK, r0
+    bx      lr
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma diag_suppress = Pe940   // Suppress IAR compiler warning about missing
+                                // return statement on a non-void function
+__stackless void
+am_hal_interrupt_master_set(uint32_t ui32InterruptState)
+{
+    __asm("    msr     PRIMASK, r0");
+    __asm("    bx lr");
+}
+#pragma diag_default = Pe940    // Restore IAR compiler warning
+#endif
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h

@@ -0,0 +1,159 @@
+//*****************************************************************************
+//
+//  am_hal_interrupt.h
+//! @file
+//!
+//! @brief Helper functions supporting interrupts and NVIC operation.
+//!
+//! These functions may be used for NVIC-level interrupt configuration.
+//!
+//! @addtogroup interrupt2 Interrupt (ARM NVIC support functions)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_INTERRUPT_H
+#define AM_HAL_INTERRUPT_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+//*****************************************************************************
+//
+//! @name ISR number macros.
+//! @brief ISR macros.
+//!
+//! These macros are used for all ui32Interrupt arguments in this module.
+//! @{
+//
+//*****************************************************************************
+//
+// Hardware interrupts
+//
+#define AM_HAL_INTERRUPT_RESET              1
+#define AM_HAL_INTERRUPT_NMI                2
+#define AM_HAL_INTERRUPT_HARDFAULT          3
+#define AM_HAL_INTERRUPT_MPUFAULT           4
+#define AM_HAL_INTERRUPT_BUSFAULT           5
+#define AM_HAL_INTERRUPT_USAGEFAULT         6
+
+#define AM_HAL_INTERRUPT_SVCALL             11
+#define AM_HAL_INTERRUPT_DEBUGMON           12
+#define AM_HAL_INTERRUPT_PENDSV             14
+#define AM_HAL_INTERRUPT_SYSTICK            15
+
+//
+// Begin IRQs
+//
+#define AM_HAL_INTERRUPT_BROWNOUT           16
+#define AM_HAL_INTERRUPT_WATCHDOG           17
+#define AM_HAL_INTERRUPT_CLKGEN             18
+#define AM_HAL_INTERRUPT_VCOMP              19
+#define AM_HAL_INTERRUPT_IOSLAVE            20
+#define AM_HAL_INTERRUPT_IOSACC             21
+#define AM_HAL_INTERRUPT_IOMASTER0          22
+#define AM_HAL_INTERRUPT_IOMASTER1          23
+#define AM_HAL_INTERRUPT_IOMASTER2          24
+#define AM_HAL_INTERRUPT_IOMASTER3          25
+#define AM_HAL_INTERRUPT_IOMASTER4          26
+#define AM_HAL_INTERRUPT_IOMASTER5          27
+#define AM_HAL_INTERRUPT_GPIO               28
+#define AM_HAL_INTERRUPT_CTIMER             29
+#define AM_HAL_INTERRUPT_UART0              30
+#define AM_HAL_INTERRUPT_UART1              31
+#define AM_HAL_INTERRUPT_UART               (AM_HAL_INTERRUPT_UART0)
+#define AM_HAL_INTERRUPT_ADC                32
+#define AM_HAL_INTERRUPT_PDM                33
+#define AM_HAL_INTERRUPT_STIMER             34
+#define AM_HAL_INTERRUPT_STIMER_CMPR0       35
+#define AM_HAL_INTERRUPT_STIMER_CMPR1       36
+#define AM_HAL_INTERRUPT_STIMER_CMPR2       37
+#define AM_HAL_INTERRUPT_STIMER_CMPR3       38
+#define AM_HAL_INTERRUPT_STIMER_CMPR4       39
+#define AM_HAL_INTERRUPT_STIMER_CMPR5       40
+#define AM_HAL_INTERRUPT_STIMER_CMPR6       41
+#define AM_HAL_INTERRUPT_STIMER_CMPR7       42
+#define AM_HAL_INTERRUPT_FLASH              43
+
+#define AM_HAL_INTERRUPT_SOFTWARE0          44
+#define AM_HAL_INTERRUPT_SOFTWARE1          45
+#define AM_HAL_INTERRUPT_SOFTWARE2          46
+#define AM_HAL_INTERRUPT_SOFTWARE3          47
+//! @}
+
+//*****************************************************************************
+//
+//! @brief Interrupt priority
+//!
+//! This macro is made to be used with the \e am_hal_interrupt_priority_set()
+//! function. It converts a priority number to the format used by the ARM
+//! standard priority register, where only the top 3 bits are used.
+//!
+//! For example, AM_HAL_INTERRUPT_PRIORITY(1) yields a value of 0x20.
+//
+//*****************************************************************************
+#define AM_HAL_INTERRUPT_PRIORITY(n)        (((uint32_t)(n) & 0x7) << 5)
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_interrupt_enable(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_disable(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_pend_set(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt);
+extern void am_hal_interrupt_priority_set(uint32_t ui32Interrupt,
+                                          uint32_t ui32Priority);
+extern uint32_t am_hal_interrupt_master_disable(void);
+extern uint32_t am_hal_interrupt_master_enable(void);
+extern void am_hal_interrupt_master_set(uint32_t ui32InterruptState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_INTERRUPT_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_ios.h

@@ -0,0 +1,362 @@
+//*****************************************************************************
+//
+//  am_hal_ios.h
+//! @file
+//!
+//! @brief Functions for interfacing with the IO Slave module
+//!
+//! @addtogroup ios2 IO Slave (SPI/I2C)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_IOS_H
+#define AM_HAL_IOS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+//! @name Interface Configuration
+//! @brief Macro definitions for configuring the physical interface of the IO
+//! Slave
+//!
+//! These macros may be used with the am_hal_ios_config_t structure to set the
+//! physical parameters of the SPI/I2C slave module.
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_USE_SPI           AM_REG_IOSLAVE_CFG_IFCSEL_SPI
+#define AM_HAL_IOS_SPIMODE_0         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3
+#define AM_HAL_IOS_SPIMODE_1         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2
+#define AM_HAL_IOS_SPIMODE_2         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_1_2
+#define AM_HAL_IOS_SPIMODE_3         AM_REG_IOSLAVE_CFG_SPOL_SPI_MODES_0_3
+
+#define AM_HAL_IOS_USE_I2C           AM_REG_IOSLAVE_CFG_IFCSEL_I2C
+#define AM_HAL_IOS_I2C_ADDRESS(n)    AM_REG_IOSLAVE_CFG_I2CADDR(n)
+
+#define AM_HAL_IOS_LSB_FIRST         AM_REG_IOSLAVE_CFG_LSB(1)
+//! @}
+
+//*****************************************************************************
+//
+//! @name Register Access Interrupts
+//! @brief Macro definitions for register access interrupts.
+//!
+//! These macros may be used with any of the
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_ACCESS_INT_00     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 31)
+#define AM_HAL_IOS_ACCESS_INT_01     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 30)
+#define AM_HAL_IOS_ACCESS_INT_02     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 29)
+#define AM_HAL_IOS_ACCESS_INT_03     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 28)
+#define AM_HAL_IOS_ACCESS_INT_04     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 27)
+#define AM_HAL_IOS_ACCESS_INT_05     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 26)
+#define AM_HAL_IOS_ACCESS_INT_06     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 25)
+#define AM_HAL_IOS_ACCESS_INT_07     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 24)
+#define AM_HAL_IOS_ACCESS_INT_08     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 23)
+#define AM_HAL_IOS_ACCESS_INT_09     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 22)
+#define AM_HAL_IOS_ACCESS_INT_0A     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 21)
+#define AM_HAL_IOS_ACCESS_INT_0B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 20)
+#define AM_HAL_IOS_ACCESS_INT_0C     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 19)
+#define AM_HAL_IOS_ACCESS_INT_0D     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 18)
+#define AM_HAL_IOS_ACCESS_INT_0E     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 17)
+#define AM_HAL_IOS_ACCESS_INT_0F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 16)
+#define AM_HAL_IOS_ACCESS_INT_13     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 15)
+#define AM_HAL_IOS_ACCESS_INT_17     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 14)
+#define AM_HAL_IOS_ACCESS_INT_1B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 13)
+#define AM_HAL_IOS_ACCESS_INT_1F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 12)
+#define AM_HAL_IOS_ACCESS_INT_23     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 11)
+#define AM_HAL_IOS_ACCESS_INT_27     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 10)
+#define AM_HAL_IOS_ACCESS_INT_2B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 9)
+#define AM_HAL_IOS_ACCESS_INT_2F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 8)
+#define AM_HAL_IOS_ACCESS_INT_33     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 7)
+#define AM_HAL_IOS_ACCESS_INT_37     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 6)
+#define AM_HAL_IOS_ACCESS_INT_3B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 5)
+#define AM_HAL_IOS_ACCESS_INT_3F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 4)
+#define AM_HAL_IOS_ACCESS_INT_43     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 3)
+#define AM_HAL_IOS_ACCESS_INT_47     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 2)
+#define AM_HAL_IOS_ACCESS_INT_4B     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 1)
+#define AM_HAL_IOS_ACCESS_INT_4F     AM_REG_IOSLAVE_REGACCINTEN_REGACC((uint32_t)1 << 0)
+#define AM_HAL_IOS_ACCESS_INT_ALL    0xFFFFFFFF
+//! @}
+
+//*****************************************************************************
+//
+//! @name I/O Slave Interrupts
+//! @brief Macro definitions for I/O slave (IOS) interrupts.
+//!
+//! These macros may be used with any of the
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_INT_FSIZE            AM_REG_IOSLAVE_INTEN_FSIZE_M
+#define AM_HAL_IOS_INT_FOVFL            AM_REG_IOSLAVE_INTEN_FOVFL_M
+#define AM_HAL_IOS_INT_FUNDFL           AM_REG_IOSLAVE_INTEN_FUNDFL_M
+#define AM_HAL_IOS_INT_FRDERR           AM_REG_IOSLAVE_INTEN_FRDERR_M
+#define AM_HAL_IOS_INT_GENAD            AM_REG_IOSLAVE_INTEN_GENAD_M
+#define AM_HAL_IOS_INT_IOINTW           AM_REG_IOSLAVE_INTEN_IOINTW_M
+#define AM_HAL_IOS_INT_XCMPWR           AM_REG_IOSLAVE_INTEN_XCMPWR_M
+#define AM_HAL_IOS_INT_XCMPWF           AM_REG_IOSLAVE_INTEN_XCMPWF_M
+#define AM_HAL_IOS_INT_XCMPRR           AM_REG_IOSLAVE_INTEN_XCMPRR_M
+#define AM_HAL_IOS_INT_XCMPRF           AM_REG_IOSLAVE_INTEN_XCMPRF_M
+#define AM_HAL_IOS_INT_ALL              0xFFFFFFFF
+//! @}
+
+//*****************************************************************************
+//
+//! @name I/O Slave Interrupts triggers
+//! @brief Macro definitions for I/O slave (IOS) interrupts.
+//!
+//! These macros may be used with am_hal_ios_int_set and am_hal_ios_int_clear
+//!
+//! @{
+//
+//*****************************************************************************
+#define AM_HAL_IOS_IOINTCTL_INT0    (0x01)
+#define AM_HAL_IOS_IOINTCTL_INT1    (0x02)
+#define AM_HAL_IOS_IOINTCTL_INT2    (0x04)
+#define AM_HAL_IOS_IOINTCTL_INT3    (0x08)
+#define AM_HAL_IOS_IOINTCTL_INT4    (0x10)
+#define AM_HAL_IOS_IOINTCTL_INT5    (0x20)
+//! @}
+
+//*****************************************************************************
+//
+// External variable definitions
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @brief LRAM pointer
+//!
+//! Pointer to the base of the IO Slave LRAM.
+//
+//*****************************************************************************
+extern volatile uint8_t * const am_hal_ios_pui8LRAM;
+
+//*****************************************************************************
+//
+//! @brief Configuration structure for the IO slave module.
+//!
+//! This structure may be used along with the am_hal_ios_config() function to
+//! select key parameters of the IO Slave module. See the descriptions of each
+//! parameter within this structure for more information on what they control.
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Interface Selection
+    //!
+    //! This word selects the physical behavior of the IO Slave port. For SPI
+    //! mode, this word should be the logical OR of one or more of the
+    //! following:
+    //!
+    //!     AM_HAL_IOS_USE_SPI
+    //!     AM_HAL_IOS_SPIMODE_0
+    //!     AM_HAL_IOS_SPIMODE_1
+    //!     AM_HAL_IOS_SPIMODE_2
+    //!     AM_HAL_IOS_SPIMODE_3
+    //!
+    //! For I2C mode, use the logical OR of one or more of these values instead
+    //! (where n is the 7 or 10-bit I2C address to use):
+    //!
+    //!     AM_HAL_IOS_USE_I2C
+    //!     AM_HAL_IOS_I2C_ADDRESS(n)
+    //!
+    //! Also, in any mode, you may OR in this value to reverse the order of
+    //! incoming data bits.
+    //!
+    //!     AM_HAL_IOS_LSB_FIRST
+    //
+    uint32_t ui32InterfaceSelect;
+
+    //
+    //! Read-Only section
+    //!
+    //! The IO Slave LRAM is split into three main sections. The first section
+    //! is a "Direct Write" section, which may be accessed for reads or write
+    //! either directly through the Apollo CPU, or over the SPI/I2C bus. The
+    //! "Direct Write" section always begins at LRAM offset 0x0. At the end of
+    //! the normal "Direct Write" space, there is a "Read Only" space, which is
+    //! read/write accessible to the Apollo CPU, but read-only over the I2C/SPI
+    //! Bus. This word selects the base address of this "Read Only" space.
+    //!
+    //! This value may be set to any multiple of 8 between 0x0 and 0x78,
+    //! inclusive. For the configuration to be valid, \e ui32ROBase must also
+    //! be less than or equal to \e ui32FIFOBase
+    //!
+    //! @note The address given here is in units of BYTES. Since the location
+    //! of the "Read Only" space may only be set in 8-byte increments, this
+    //! value must be a multiple of 8.
+    //!
+    //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
+    //! will shift right by 8 internally.
+    //
+    uint32_t ui32ROBase;
+
+    //
+    //! FIFO section
+    //!
+    //! After the "Direct Access" and "Read Only" sections is a section of LRAM
+    //! allocated to a FIFO. This section is accessible by the Apollo CPU
+    //! through the FIFO control registers, and accessible on the SPI/I2C bus
+    //! through the 0x7F address. This word selects the base address of the
+    //! FIFO space. The FIFO will extend from the address specified here to the
+    //! address specified in \e ui32RAMBase.
+    //!
+    //! This value may be set to any multiple of 8 between 0x0 and 0x78,
+    //! inclusive. For the configuration to be valid, \e ui32FIFOBase must also
+    //! be greater than or equal to \e ui32ROBase.
+    //!
+    //! @note The address given here is in units of BYTES. Since the location
+    //! of the "FIFO" space may only be set in 8-byte increments, this value
+    //! must be a multiple of 8.
+    //!
+    //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
+    //! will shift right by 8 internally.
+    //
+    uint32_t ui32FIFOBase;
+
+    //
+    //! RAM section
+    //!
+    //! At the end of the IOS LRAM, the user may allocate a "RAM" space that
+    //! can only be accessed by the Apollo CPU. This space will not interact
+    //! with the SPI/I2C bus at all, and may be used as general-purpose memory.
+    //! Unlike normal SRAM, this section of LRAM will retain its state through
+    //! Deep Sleep, so it may be used as a data retention space for
+    //! ultra-low-power applications.
+    //!
+    //! This value may be set to any multiple of 8 between 0x0 and 0x100,
+    //! inclusive. For the configuration to be valid, \e ui32RAMBase must also
+    //! be greater than or equal to \e ui32FIFOBase.
+    //!
+    //! @note The address given here is in units of BYTES. Since the location
+    //! of the "FIFO" space may only be set in 8-byte increments, this value
+    //! must be a multiple of 8.
+    //!
+    //! For the avoidance of doubt this means 0x80 is 128 bytes. These functions
+    //! will shift right by 8 internally.
+    //
+    uint32_t ui32RAMBase;
+
+    //
+    //! FIFO threshold
+    //!
+    //! The IO Slave module will trigger an interrupt when the number of
+    //! entries in the FIFO drops below this number of bytes.
+    //
+    uint32_t ui32FIFOThreshold;
+
+    //
+    // Pointer to an SRAM
+    //
+    uint8_t *pui8SRAMBuffer;
+}
+am_hal_ios_config_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_ios_enable(uint32_t ui32Module);
+extern void am_hal_ios_disable(uint32_t ui32Module);
+
+// these interrupts drive the HOST side IOS interrupt pins
+extern void am_hal_ios_host_int_set(uint32_t ui32Interrupt);
+extern void am_hal_ios_host_int_clear(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_host_int_get(void);
+extern uint32_t am_hal_ios_host_int_enable_get(void);
+
+extern void am_hal_ios_lram_write(uint32_t ui32Offset, uint8_t ui8Value);
+extern uint8_t am_hal_ios_lram_read(uint32_t ui32Offset);
+
+// the following interrupts go back to the NVIC
+extern void am_hal_ios_config(am_hal_ios_config_t *psConfig);
+extern void am_hal_ios_access_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_access_int_enable_get(void);
+extern void am_hal_ios_access_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_ios_access_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_ios_access_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_access_int_status_get(bool bEnabledOnly);
+extern void am_hal_ios_int_enable(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_int_enable_get(void);
+extern void am_hal_ios_int_disable(uint32_t ui32Interrupt);
+extern void am_hal_ios_int_clear(uint32_t ui32Interrupt);
+extern void am_hal_ios_int_set(uint32_t ui32Interrupt);
+extern uint32_t am_hal_ios_int_status_get(bool bEnabledOnly);
+
+extern void am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes);
+extern uint32_t am_hal_ios_fifo_space_left(void);
+extern uint32_t am_hal_ios_fifo_space_used(void);
+extern void am_hal_ios_fifo_service(uint32_t ui32Status);
+// Returns the number of bytes actually written
+extern uint32_t am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes);
+extern void am_hal_ios_fifo_write_simple(uint8_t *pui8Data,
+                                         uint32_t ui32NumBytes);
+extern void am_hal_ios_fifo_ptr_set(uint32_t ui32Offset);
+extern void am_hal_ios_update_fifoctr(void);
+
+extern void am_hal_ios_read_poll_complete(void);
+extern void am_hal_ios_pwrctrl_enable(void);
+extern void am_hal_ios_pwrctrl_disable(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_IOS_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_itm.c

@@ -0,0 +1,453 @@
+//*****************************************************************************
+//
+//  am_hal_itm.c
+//! @file
+//!
+//! @brief Functions for operating the instrumentation trace macrocell
+//!
+//! @addtogroup itm2 Instrumentation Trace Macrocell (ITM)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+// Global Variables
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! @brief Delays for a desired amount of microseconds.
+//!
+//! @note - This function is based on the similar function in am_util_delay.c,
+//! please see that module for implementation details. It was necessary to
+//! duplicate it here to avoid having to update every example to include the
+//! am_util_delay.c module in its build.
+//!
+//! @returns None
+//
+//*****************************************************************************
+void
+am_hal_itm_delay_us(uint32_t ui32MicroSeconds)
+{
+    uint32_t ui32Iterations = ui32MicroSeconds *
+                              (am_hal_clkgen_sysclk_get() / 3000000);
+
+    //
+    // Call the BOOTROM cycle delay function
+    //
+    am_hal_flash_delay(ui32Iterations);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the ITM
+//!
+//! This function enables the ARM ITM by setting the TRCENA bit in the DEMCR
+//! register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_enable(void)
+{
+    if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
+    {
+        return;
+    }
+
+    //
+    // To be able to access ITM registers, set the Trace Enable bit
+    // in the Debug Exception and Monitor Control Register (DEMCR).
+    //
+    AM_REG(SYSCTRL, DEMCR) |= AM_REG_SYSCTRL_DEMCR_TRCENA(1);
+    while ( !(AM_REG(SYSCTRL, DEMCR) & AM_REG_SYSCTRL_DEMCR_TRCENA(1)) );
+
+    //
+    // Write the key to the ITM Lock Access register to unlock the ITM_TCR.
+    //
+    AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL;
+
+    //
+    // Set the enable bits in the ITM trace enable register, and the ITM
+    // control registers to enable trace data output.
+    //
+    AM_REGVAL(AM_REG_ITM_TPR_O) = 0x0000000f;
+    AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff;
+
+    //
+    // Write to the ITM control and status register (don't enable yet).
+    //
+    AM_REGVAL(AM_REG_ITM_TCR_O) =
+        AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15)      |
+        AM_WRITE_SM(AM_REG_ITM_TCR_TS_FREQ, 1)        |
+        AM_WRITE_SM(AM_REG_ITM_TCR_TS_PRESCALE, 1)    |
+        AM_WRITE_SM(AM_REG_ITM_TCR_SWV_ENABLE, 1)     |
+        AM_WRITE_SM(AM_REG_ITM_TCR_DWT_ENABLE, 0)     |
+        AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0)    |
+        AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0)      |
+        AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1);
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the ITM
+//!
+//! This function completely disables the ARM ITM by resetting the TRCENA bit
+//! in the DEMCR register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_disable(void)
+{
+
+    if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
+    {
+        return;
+    }
+
+    //
+    // Make sure the ITM_TCR is unlocked.
+    //
+    AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL;
+
+    //
+    // Make sure the ITM/TPIU is not busy.
+    //
+    while ( AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1) );
+
+    //
+    // Disable the ITM.
+    //
+    for (int ix = 0; ix < 100; ix++)
+    {
+        AM_REG(ITM, TCR) &= ~AM_REG_ITM_TCR_ITM_ENABLE(1);
+        while ( AM_REG(ITM, TCR) & (AM_REG_ITM_TCR_ITM_ENABLE(1) | AM_REG_ITM_TCR_BUSY(1)) );
+    }
+
+    //
+    // Reset the TRCENA bit in the DEMCR register, which should disable the ITM
+    // for operation.
+    //
+    AM_REG(SYSCTRL, DEMCR) &= ~AM_REG_SYSCTRL_DEMCR_TRCENA(1);
+
+    //
+    // Disable the TPIU clock source in MCU control.
+    //
+    AM_REG(MCUCTRL, TPIUCTRL) = AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz |
+                                AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS;
+}
+
+//*****************************************************************************
+//
+//! @brief Checks if itm is busy and provides a delay to flush the fifo
+//!
+//! This function disables the ARM ITM by resetting the TRCENA bit in the DEMCR
+//! register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_not_busy(void)
+{
+    //
+    // Make sure the ITM/TPIU is not busy.
+    //
+    while (AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1));
+
+    //
+    // wait for 50us for the data to flush out
+    //
+    am_hal_itm_delay_us(50);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables tracing on a given set of ITM ports
+//!
+//! @param ui8portNum - Set ports to be enabled
+//!
+//! Enables tracing on the ports referred to by \e ui8portNum by writing the
+//! associated bit in the Trace Privilege Register in the ITM. The value for
+//! ui8portNum should be the logical OR one or more of the following values:
+//!
+//! \e ITM_PRIVMASK_0_7 - enable ports 0 through 7
+//! \e ITM_PRIVMASK_8_15 - enable ports 8 through 15
+//! \e ITM_PRIVMASK_16_23 - enable ports 16 through 23
+//! \e ITM_PRIVMASK_24_31 - enable ports 24 through 31
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_trace_port_enable(uint8_t ui8portNum)
+{
+    AM_REGVAL(AM_REG_ITM_TPR_O) |= (0x00000001 << (ui8portNum>>3));
+}
+
+//*****************************************************************************
+//
+//! @brief Disable tracing on the given ITM stimulus port.
+//!
+//! @param ui8portNum
+//!
+//! Disables tracing on the ports referred to by \e ui8portNum by writing the
+//! associated bit in the Trace Privilege Register in the ITM. The value for
+//! ui8portNum should be the logical OR one or more of the following values:
+//!
+//! \e ITM_PRIVMASK_0_7 - disable ports 0 through 7
+//! \e ITM_PRIVMASK_8_15 - disable ports 8 through 15
+//! \e ITM_PRIVMASK_16_23 - disable ports 16 through 23
+//! \e ITM_PRIVMASK_24_31 - disable ports 24 through 31
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_trace_port_disable(uint8_t ui8portNum)
+{
+    AM_REGVAL(AM_REG_ITM_TPR_O) &= ~(0x00000001 << (ui8portNum >> 3));
+}
+
+//*****************************************************************************
+//
+//! @brief Poll the given ITM stimulus register until not busy.
+//!
+//! @param ui32StimReg - stimulus register
+//!
+//! @return true if not busy, false if busy (timed out or other error).
+//
+//*****************************************************************************
+bool
+am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg)
+{
+    uint32_t ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available, non-zero means ready.
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    return true;
+}
+
+//*****************************************************************************
+//
+//! @brief Writes a 32-bit value to the given ITM stimulus register.
+//!
+//! @param ui32StimReg - stimulus register
+//! @param ui32Value - value to be written.
+//!
+//! Write a word to the desired stimulus register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg, uint32_t ui32Value)
+{
+    uint32_t ui32StimAddr;
+
+    ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available, non-zero means ready
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    //
+    // Write the register.
+    //
+    AM_REGVAL(ui32StimAddr) = ui32Value;
+}
+
+//*****************************************************************************
+//
+//! @brief Writes a short to the given ITM stimulus register.
+//!
+//! @param ui32StimReg - stimulus register
+//! @param ui16Value - short to be written.
+//!
+//! Write a short to the desired stimulus register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg, uint16_t ui16Value)
+{
+    uint32_t ui32StimAddr;
+
+    ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available non-zero means ready
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    //
+    // Write the register.
+    //
+    *((volatile uint16_t *) ui32StimAddr) = ui16Value;
+}
+
+//*****************************************************************************
+//
+//! @brief Writes a byte to the given ITM stimulus register.
+//!
+//! @param ui32StimReg - stimulus register
+//! @param ui8Value - byte to be written.
+//!
+//! Write a byte to the desired stimulus register.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg, uint8_t ui8Value)
+{
+    uint32_t ui32StimAddr;
+
+    ui32StimAddr = (AM_REG_ITM_STIM0_O + (4 * ui32StimReg));
+
+    //
+    // Busy waiting until it is available (non-zero means ready)
+    //
+    while (!AM_REGVAL(ui32StimAddr));
+
+    //
+    // Write the register.
+    //
+    *((volatile uint8_t *) ui32StimAddr) = ui8Value;
+}
+
+//*****************************************************************************
+//
+//! @brief Sends a Sync Packet.
+//!
+//! Sends a sync packet. This can be useful for external software should it
+//! become out of sync with the ITM stream.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_sync_send(void)
+{
+    //
+    // Write the register.
+    //
+    am_hal_itm_stimulus_reg_word_write(AM_HAL_ITM_SYNC_REG,
+                                       AM_HAL_ITM_SYNC_VAL);
+}
+
+//*****************************************************************************
+//
+//! @brief Poll the print stimulus registers until not busy.
+//!
+//! @return true if not busy, false if busy (timed out or other error).
+//
+//*****************************************************************************
+bool
+am_hal_itm_print_not_busy(void)
+{
+    //
+    // Poll stimulus register allocated for printing.
+    //
+    am_hal_itm_stimulus_not_busy(0);
+
+
+    return true;
+}
+
+//*****************************************************************************
+//
+//! @brief Prints a char string out of the ITM.
+//!
+//! @param pcString pointer to the character sting
+//!
+//! This function prints a sting out of the ITM.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_itm_print(char *pcString)
+{
+    uint32_t ui32Length = 0;
+
+    //
+    // Determine the length of the string.
+    //
+    while (*(pcString + ui32Length))
+    {
+        ui32Length++;
+    }
+
+    //
+    // If there is no longer a word left, empty out the remaining characters.
+    //
+    while (ui32Length)
+    {
+            //
+            // Print string out the ITM.
+            //
+            am_hal_itm_stimulus_reg_byte_write(0, (uint8_t)*pcString++);
+
+            //
+            // Subtract from length.
+            //
+            ui32Length--;
+    }
+}
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_itm.h

@@ -0,0 +1,107 @@
+//*****************************************************************************
+//
+//  am_hal_itm.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the ARM ITM.
+//!
+//! @addtogroup itm2 Instrumentation Trace Macrocell (ITM)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_ITM_H
+#define AM_HAL_ITM_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Sync Packet Defines
+//
+//*****************************************************************************
+#define AM_HAL_ITM_SYNC_REG             23
+#define AM_HAL_ITM_SYNC_VAL             0xF8F8F8F8
+
+//*****************************************************************************
+//
+// PrintF Setup
+//
+//*****************************************************************************
+#define AM_HAL_ITM_PRINT_NUM_BYTES      1
+#define AM_HAL_ITM_PRINT_NUM_REGS       1
+extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS];
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_itm_delay_us(uint32_t ui32MicroSeconds);
+extern void am_hal_itm_enable(void);
+extern void am_hal_itm_disable(void);
+extern void am_hal_itm_not_busy(void);
+extern void am_hal_itm_sync_send(void);
+extern void am_hal_itm_trace_port_enable(uint8_t ui8portNum);
+extern void am_hal_itm_trace_port_disable(uint8_t ui8portNum);
+extern bool am_hal_itm_stimulus_not_busy(uint32_t ui32StimReg);
+extern void am_hal_itm_stimulus_reg_word_write(uint32_t ui32StimReg,
+                                                uint32_t ui32Value);
+extern void am_hal_itm_stimulus_reg_short_write(uint32_t ui32StimReg,
+                                                uint16_t ui16Value);
+extern void am_hal_itm_stimulus_reg_byte_write(uint32_t ui32StimReg,
+                                                uint8_t ui8Value);
+extern bool am_hal_itm_print_not_busy(void);
+extern void am_hal_itm_print(char *pcString);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_ITM_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c

@@ -0,0 +1,292 @@
+//*****************************************************************************
+//
+//  am_hal_mcuctrl.c
+//! @file
+//!
+//! @brief Functions for interfacing with the MCUCTRL.
+//!
+//! @addtogroup mcuctrl2 MCU Control (MCUCTRL)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+#define LDO_TRIM_REG_ADDR   (0x50023004)
+#define BUCK_TRIM_REG_ADDR  (0x50023000)
+
+//*****************************************************************************
+//
+// Global Variables.
+//
+//*****************************************************************************
+//
+// Define the flash sizes from CHIP_INFO.
+//
+const uint32_t g_am_hal_mcuctrl_flash_size[16] =
+{
+     16 * 1024,             /* 0x0 0x00004000   16 KB */
+     32 * 1024,             /* 0x1 0x00008000   32 KB */
+     64 * 1024,             /* 0x2 0x00010000   64 KB */
+    128 * 1024,             /* 0x3 0x00020000  128 KB */
+    256 * 1024,             /* 0x4 0x00040000  256 KB */
+    512 * 1024,             /* 0x5 0x00080000  512 KB */
+      1 * 1024 * 1024,      /* 0x6 0x00100000    1 MB */
+      2 * 1024 * 1024,      /* 0x7 0x00200000    2 MB */
+      4 * 1024 * 1024,      /* 0x8 0x00400000    4 MB */
+      8 * 1024 * 1024,      /* 0x9 0x00800000    8 MB */
+     16 * 1024 * 1024,      /* 0xA 0x01000000    16 MB */
+     32 * 1024 * 1024,      /* 0xB 0x02000000    32 MB */
+     64 * 1024 * 1024,      /* 0xC 0x04000000    64 MB */
+    128 * 1024 * 1024,      /* 0xD 0x08000000   128 MB */
+    256 * 1024 * 1024,      /* 0xE 0x10000000   256 MB */
+    512 * 1024 * 1024       /* 0xF 0x20000000   512 MB */
+};
+
+//
+// Define the SRAM sizes from CHIP_INFO.
+// For Apollo2, the SRAM sizes are defined exactly the same as the flash sizes.
+//
+#define g_am_hal_mcuctrl_sram_size  g_am_hal_mcuctrl_flash_size
+
+//*****************************************************************************
+//
+//! @brief Gets all relevant device information.
+//!
+//! @param psDevice is a pointer to a structure that will be used to store all
+//! device info.
+//!
+//! This function gets the device part number, chip IDs, and revision and
+//! stores them in the passed structure.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_device_info_get(am_hal_mcuctrl_device_t *psDevice)
+{
+    //
+    // Read the Part Number.
+    //
+    psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO);
+
+    //
+    // Read the Chip ID0.
+    //
+    psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0);
+
+    //
+    // Read the Chip ID1.
+    //
+    psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1);
+
+    //
+    // Read the Chip Revision.
+    //
+    psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV);
+
+    //
+    // Read the Part Number.
+    //
+    psDevice->ui32ChipPN = AM_REG(MCUCTRL, CHIP_INFO);
+
+    //
+    // Read the Chip ID0.
+    //
+    psDevice->ui32ChipID0 = AM_REG(MCUCTRL, CHIPID0);
+
+    //
+    // Read the Chip ID1.
+    //
+    psDevice->ui32ChipID1 = AM_REG(MCUCTRL, CHIPID1);
+
+    //
+    // Read the Chip Revision.
+    //
+    psDevice->ui32ChipRev = AM_REG(MCUCTRL, CHIPREV);
+
+    //
+    // Read the Chip VENDOR ID.
+    //
+    psDevice->ui32VendorID = AM_REG(MCUCTRL, VENDORID);
+
+    //
+    // Qualified from Part Number.
+    //
+    psDevice->ui32Qualified =
+            (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_QUAL_M) >>
+             AM_HAL_MCUCTRL_CHIP_INFO_QUAL_S;
+
+    //
+    // Flash size from Part Number.
+    //
+    psDevice->ui32FlashSize =
+        g_am_hal_mcuctrl_flash_size[
+            (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_M) >>
+            AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_S];
+
+    //
+    // SRAM size from Part Number.
+    //
+    psDevice->ui32SRAMSize =
+        g_am_hal_mcuctrl_flash_size[
+            (psDevice->ui32ChipPN & AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_M) >>
+            AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_S];
+
+    //
+    // Now, let's look at the JEDEC info.
+    // The full partnumber is 12 bits total, but is scattered across 2 registers.
+    // Bits [11:8] are 0xE.
+    // Bits [7:4] are 0xE for Apollo, 0xD for Apollo2.
+    // Bits [3:0] are defined differently for Apollo and Apollo2.
+    //   For Apollo, the low nibble is 0x0.
+    //   For Apollo2, the low nibble indicates flash and SRAM size.
+    //
+    psDevice->ui32JedecPN  = (AM_BFR(JEDEC, PID0, PNL8) << 0);
+    psDevice->ui32JedecPN |= (AM_BFR(JEDEC, PID1, PNH4) << 8);
+
+    //
+    // JEPID is the JEP-106 Manufacturer ID Code, which is assigned to Ambiq as
+    //  0x1B, with parity bit is 0x9B.  It is 8 bits located across 2 registers.
+    //
+    psDevice->ui32JedecJEPID  = (AM_BFR(JEDEC, PID1, JEPIDL) << 0);
+    psDevice->ui32JedecJEPID |= (AM_BFR(JEDEC, PID2, JEPIDH) << 4);
+
+    //
+    // CHIPREV is 8 bits located across 2 registers.
+    //
+    psDevice->ui32JedecCHIPREV  = (AM_BFR(JEDEC, PID2, CHIPREVH4) << 4);
+    psDevice->ui32JedecCHIPREV |= (AM_BFR(JEDEC, PID3, CHIPREVL4) << 0);
+
+    //
+    // Let's get the Coresight ID (32-bits across 4 registers)
+    // For Apollo and Apollo2, it's expected to be 0xB105100D.
+    //
+    psDevice->ui32JedecCID  = (AM_BFR(JEDEC, CID3, CID) << 24);
+    psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID2, CID) << 16);
+    psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID1, CID) <<  8);
+    psDevice->ui32JedecCID |= (AM_BFR(JEDEC, CID0, CID) <<  0);
+}
+
+//*****************************************************************************
+//
+//! @brief Enables the fault capture registers.
+//!
+//! This function enables the DCODEFAULTADDR and ICODEFAULTADDR registers.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_fault_capture_enable(void)
+{
+    //
+    // Enable the Fault Capture registers.
+    //
+    AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 1);
+}
+
+//*****************************************************************************
+//
+//! @brief Disables the fault capture registers.
+//!
+//! This function disables the DCODEFAULTADDR and ICODEFAULTADDR registers.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_fault_capture_disable(void)
+{
+    //
+    // Disable the Fault Capture registers.
+    //
+    AM_BFW(MCUCTRL, FAULTCAPTUREEN, ENABLE, 0);
+}
+
+//*****************************************************************************
+//
+//! @brief Gets the fault status and capture registers.
+//!
+//! @param psFault is a pointer to a structure that will be used to store all
+//! fault info.
+//!
+//! This function gets the status of the ICODE, DCODE, and SYS bus faults and
+//! the addresses associated with the fault.
+//!
+//! @return None
+//
+//*****************************************************************************
+void
+am_hal_mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault)
+{
+    uint32_t ui32FaultStat;
+
+    //
+    // Read the Fault Status Register.
+    //
+    ui32FaultStat = AM_REG(MCUCTRL, FAULTSTATUS);
+    psFault->bICODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_ICODE_M);
+    psFault->bDCODE = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_DCODE_M);
+    psFault->bSYS = (ui32FaultStat & AM_REG_MCUCTRL_FAULTSTATUS_SYS_M);
+
+    //
+    // Read the DCODE fault capture address register.
+    //
+    psFault->ui32DCODE = AM_REG(MCUCTRL, DCODEFAULTADDR);
+
+    //
+    // Read the ICODE fault capture address register.
+    //
+    psFault->ui32ICODE |= AM_REG(MCUCTRL, ICODEFAULTADDR);
+
+    //
+    // Read the ICODE fault capture address register.
+    //
+    psFault->ui32SYS |= AM_REG(MCUCTRL, SYSFAULTADDR);
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h

@@ -0,0 +1,212 @@
+//*****************************************************************************
+//
+//  am_hal_mcuctrl.h
+//! @file
+//!
+//! @brief Functions for accessing and configuring the MCUCTRL.
+//!
+//! @addtogroup mcuctrl2 MCU Control (MCUCTRL)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_MCUCTRL_H
+#define AM_HAL_MCUCTRL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//
+// Deprecate the am_hal_mcuctrl_bucks_enable() and disable() functions.
+// This functionality is now handled in pwrctrl.
+//
+#define am_hal_mcuctrl_bucks_enable     am_hal_pwrctrl_bucks_enable
+#define am_hal_mcuctrl_bucks_disable    am_hal_pwrctrl_bucks_disable
+
+
+//*****************************************************************************
+//
+// Define CHIP_INFO fields, which for Apollo2 are not defined in the register
+// definitions.
+//
+//*****************************************************************************
+#define AM_HAL_MCUCTRL_CHIP_INFO_CLASS_M        0xFF000000
+#define AM_HAL_MCUCTRL_CHIP_INFO_CLASS_S        24
+#define AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_M   0x00F00000
+#define AM_HAL_MCUCTRL_CHIP_INFO_FLASH_SIZE_S   20
+#define AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_M    0x000F0000
+#define AM_HAL_MCUCTRL_CHIP_INFO_SRAM_SIZE_S    16
+#define AM_HAL_MCUCTRL_CHIP_INFO_REV_M          0x0000FF00
+#define AM_HAL_MCUCTRL_CHIP_INFO_REV_S          8
+#define AM_HAL_MCUCTRL_CHIP_INFO_PKG_M          0x000000C0
+#define AM_HAL_MCUCTRL_CHIP_INFO_PKG_S          6
+#define AM_HAL_MCUCTRL_CHIP_INFO_PINS_M         0x00000038
+#define AM_HAL_MCUCTRL_CHIP_INFO_PINS_S         3
+#define AM_HAL_MCUCTRL_CHIP_INFO_TEMP_M         0x00000006
+#define AM_HAL_MCUCTRL_CHIP_INFO_TEMP_S         1
+#define AM_HAL_MCUCTRL_CHIP_INFO_QUAL_M         0x00000001
+#define AM_HAL_MCUCTRL_CHIP_INFO_QUAL_S         0
+
+//*****************************************************************************
+//
+// Apollo Number Decode.
+//
+//*****************************************************************************
+extern const uint32_t g_am_hal_mcuctrl_flash_size[];
+extern const uint32_t g_am_hal_mcuctrl_sram_size[];
+
+//*****************************************************************************
+//
+//! MCUCTRL device structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! Device part number. (BCD format)
+    //
+    uint32_t ui32ChipPN;
+
+    //
+    //! Unique Chip ID 0.
+    //
+    uint32_t ui32ChipID0;
+
+    //
+    //! Unique Chip ID 1.
+    //
+    uint32_t ui32ChipID1;
+
+    //
+    //! Chip Revision.
+    //
+    uint32_t ui32ChipRev;
+
+    //
+    //! Vendor ID.
+    //
+    uint32_t ui32VendorID;
+
+    //
+    //! Qualified chip.
+    //
+    uint32_t ui32Qualified;
+
+    //
+    //! Flash Size.
+    //
+    uint32_t ui32FlashSize;
+
+    //
+    //! SRAM Size.
+    //
+    uint32_t ui32SRAMSize;
+
+    //
+    // JEDEC chip info
+    //
+    uint32_t ui32JedecPN;
+    uint32_t ui32JedecJEPID;
+    uint32_t ui32JedecCHIPREV;
+    uint32_t ui32JedecCID;
+}
+am_hal_mcuctrl_device_t;
+
+//*****************************************************************************
+//
+//! MCUCTRL fault structure
+//
+//*****************************************************************************
+typedef struct
+{
+    //
+    //! ICODE bus fault occurred.
+    //
+    bool bICODE;
+
+    //
+    //! ICODE bus fault address.
+    //
+    uint32_t ui32ICODE;
+
+    //
+    //! DCODE bus fault occurred.
+    //
+    bool bDCODE;
+
+    //
+    //! DCODE bus fault address.
+    //
+    uint32_t ui32DCODE;
+
+    //
+    //! SYS bus fault occurred.
+    //
+    bool bSYS;
+
+    //
+    //! SYS bus fault address.
+    //
+    uint32_t ui32SYS;
+}
+am_hal_mcuctrl_fault_t;
+
+//*****************************************************************************
+//
+// External function definitions
+//
+//*****************************************************************************
+extern void am_hal_mcuctrl_device_info_get(am_hal_mcuctrl_device_t *psDevice);
+extern void am_hal_mcuctrl_fault_capture_enable(void);
+extern void am_hal_mcuctrl_fault_capture_disable(void);
+extern void am_hal_mcuctrl_fault_status(am_hal_mcuctrl_fault_t *psFault);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_MCUCTRL_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_otp.c

@@ -0,0 +1,173 @@
+//*****************************************************************************
+//
+//  am_hal_otp.c
+//! @file
+//!
+//! @brief Functions for handling the OTP interface.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#include "am_mcu_apollo.h"
+#include "am_hal_flash.h"
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Check if debugger is currently locked out.
+//
+// @param None.
+//
+// Determine if the debugger is already locked out.
+//
+// @return non-zero if debugger is currently locked out.
+//     Specifically:
+//     0 = debugger is not locked out.
+//     1 = debugger is locked out.
+//
+//*****************************************************************************
+int
+am_hal_otp_is_debugger_lockedout(void)
+{
+    return am_hal_flash_debugger_disable_check();
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Lock out debugger access.
+//
+// @param None.
+//
+// This function locks out access by a debugger.
+//
+// @return 0 if lockout was successful or if lockout was already enabled.
+//
+//*****************************************************************************
+int
+am_hal_otp_debugger_lockout(void)
+{
+    return am_hal_flash_debugger_disable();
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Lock out SRAM access.
+//
+// @param None.
+//
+// This function locks out access by a debugger to SRAM.
+//
+// @return 0 if lockout was successful or if lockout was already enabled.
+//         Low byte=0xff, byte 1 contains current value of lockout.
+//         Else, return value from HAL programming function.
+//
+//*****************************************************************************
+int
+am_hal_otp_sram_lockout(void)
+{
+    return am_hal_flash_wipe_sram_enable();
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Set copy (read) protection.
+//
+// @param @u32BegAddr The beginning address to be copy protected.
+//        @u32EndAddr The ending address to be copy protected.
+//
+// @note For Apollo, the u32BegAddr parameter should be on a 16KB boundary, and
+//       the u32EndAddr parameter should be on a (16KB-1) boundary. Otherwise
+//       both parameters will be truncated/expanded to do so.
+//       For example, if u32BegAddr=0x1000 and u32EndAddr=0xC200, the actual
+//       range that protected is: 0x0 - 0xFFFF.
+//
+// This function enables copy protection on a given flash address range.
+//
+// @return 0 if copy protection was successfully enabled.
+//
+//*****************************************************************************
+int
+am_hal_otp_set_copy_protection(uint32_t u32BegAddr, uint32_t u32EndAddr)
+{
+    return am_hal_flash_copy_protect_set((uint32_t*)u32BegAddr,
+                                         (uint32_t*)u32EndAddr);
+}
+
+//*****************************************************************************
+//
+//! THIS FUNCTION IS DEPRECATED!
+//! Use the respective HAL flash function instead.
+//!
+// @brief Set write protection.
+//
+// @param @u32BegAddr The beginning address to be write protected.
+//        @u32EndAddr The ending address to be write protected.
+//
+// @note For Apollo, the u32BegAddr parameter should be on a 16KB boundary, and
+//       the u32EndAddr parameter should be on a (16KB-1) boundary. Otherwise
+//       both parameters will be truncated/expanded to do so.
+//       For example, if u32BegAddr=0x1000 and u32EndAddr=0xC200, the actual
+//       range that protected is: 0x0 - 0xFFFF.
+//
+// This function enables write protection on a given flash address range.
+//
+// @return 0 if write protection was successfully enabled.
+//
+//*****************************************************************************
+int
+am_hal_otp_set_write_protection(uint32_t u32BegAddr, uint32_t u32EndAddr)
+{
+    return am_hal_flash_write_protect_set((uint32_t*)u32BegAddr,
+                                          (uint32_t*)u32EndAddr);
+}
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_otp.h

@@ -0,0 +1,108 @@
+//*****************************************************************************
+//
+//  am_hal_otp.h
+//! @file
+//!
+//! @brief Functions for handling the OTP interface.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+#ifndef AM_HAL_OTP_H
+#define AM_HAL_OTP_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Define some OTP values and macros.
+//
+//*****************************************************************************
+#define AM_HAL_OTP_SIG0             0x00
+#define AM_HAL_OTP_SIG1             0x04
+#define AM_HAL_OTP_SIG2             0x08
+#define AM_HAL_OTP_SIG3             0x0C
+
+#define AM_HAL_OTP_DBGR_O           0x10
+#define AM_HAL_OTP_WRITPROT0_O      0x20
+#define AM_HAL_OTP_WRITPROT1_O      0x24
+#define AM_HAL_OTP_COPYPROT0_O      0x30
+#define AM_HAL_OTP_COPYPROT1_O      0x34
+
+#define AM_HAL_OTP_ADDR             0x50020000
+#define AM_HAL_OTP_DBGRPROT_ADDR    (AM_HAL_OTP_ADDR + AM_HAL_OTP_DBGR_O)
+#define AM_HAL_OTP_WRITPROT_ADDR    (AM_HAL_OTP_ADDR + AM_HAL_OTP_WRITPROT0_O)
+#define AM_HAL_OTP_COPYPROT_ADDR    (AM_HAL_OTP_ADDR + AM_HAL_OTP_COPYPROT0_O)
+
+#define AM_HAL_OTP_CHUNKSIZE        (16*1024)
+
+//
+// Debugger port lockout macros.
+//
+#define AM_OTP_DBGR_LOCKOUT_S       (0)
+#define AM_OTP_DBGR_LOCKOUT_M       (0x1 << AM_OTP_DBGR_LOCKOUT_S)
+#define AM_OTP_STRM_LOCKOUT_S       (1)
+#define AM_OTP_STRM_LOCKOUT_M       (0x1 << AM_OTP_STRM_LOCKOUT_S)
+#define AM_OTP_SRAM_LOCKOUT_S       (2)
+#define AM_OTP_SRAM_LOCKOUT_M       (0x1 << AM_OTP_SRAM_LOCKOUT_S)
+
+//*****************************************************************************
+//
+// Function prototypes
+//
+//*****************************************************************************
+extern int am_hal_otp_is_debugger_lockedout(void);
+extern int am_hal_otp_debugger_lockout(void);
+extern int am_hal_otp_sram_lockout(void);
+extern int am_hal_otp_set_copy_protection(uint32_t u32BegAddr, uint32_t u32EndAddr);
+extern int am_hal_otp_set_write_protection(uint32_t u32BegAddr, uint32_t u32EndAddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // AM_HAL_OTP_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************
+

bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c

@@ -0,0 +1,158 @@
+//*****************************************************************************
+//
+//  am_hal_pdm.c
+//! @file
+//!
+//! @brief Functions for interfacing with Pulse Density Modulation (PDM).
+//!
+//! @addtogroup pdm2 DMEMS Microphon3 (PDM)
+//! @ingroup apollo2hal
+//! @{
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "am_mcu_apollo.h"
+
+//*****************************************************************************
+//
+//! @brief Configure the PDM module.
+//!
+//! This function reads the an \e am_hal_pdm_config_t structure and uses it to
+//! set up the PDM module.
+//!
+//! Please see the information on the am_hal_pdm_config_t configuration
+//! structure, found in am_hal_pdm.h, for more information on the parameters
+//! that may be set by this function.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pdm_config(am_hal_pdm_config_t *psConfig)
+{
+    //
+    // setup the PDM PCFG register
+    //
+    AM_REG(PDM, PCFG) = psConfig->ui32PDMConfigReg;
+
+    //
+    // setup the PDM VCFG register
+    //
+    AM_REG(PDM, VCFG) = psConfig->ui32VoiceConfigReg;
+
+    //
+    // setup the PDM FIFO Threshold register
+    //
+    AM_REG(PDM, FTHR) = psConfig->ui32FIFOThreshold;
+
+    //
+    // Flush the FIFO for good measure.
+    //
+    am_hal_pdm_fifo_flush();
+}
+
+//*****************************************************************************
+//
+//! @brief Enable the PDM module.
+//!
+//! This function enables the PDM module in the mode previously defined by
+//! am_hal_pdm_config().
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pdm_enable(void)
+{
+    AM_REG(PDM, PCFG) |=  AM_REG_PDM_PCFG_PDMCORE_EN;
+    AM_REG(PDM, VCFG) |=  ( AM_REG_PDM_VCFG_IOCLKEN_EN      |
+                            AM_REG_PDM_VCFG_PDMCLK_EN       |
+                            AM_REG_PDM_VCFG_RSTB_NORM );
+}
+
+//*****************************************************************************
+//
+//! @brief Disable the PDM module.
+//!
+//! This function disables the PDM module.
+//!
+//! @return None.
+//
+//*****************************************************************************
+void
+am_hal_pdm_disable(void)
+{
+    AM_REG(PDM, PCFG) &= ~ AM_REG_PDM_PCFG_PDMCORE_EN;
+    AM_REG(PDM, VCFG) &= ~ (  AM_REG_PDM_VCFG_IOCLKEN_EN    |
+                              AM_REG_PDM_VCFG_PDMCLK_EN     |
+                              AM_REG_PDM_VCFG_RSTB_NORM );
+}
+
+//*****************************************************************************
+//
+//! @brief Return the PDM Interrupt status.
+//!
+//! @param bEnabledOnly - return only the enabled interrupts.
+//!
+//! Use this function to get the PDM interrupt status.
+//!
+//! @return intrrupt status
+//
+//*****************************************************************************
+uint32_t
+am_hal_pdm_int_status_get(bool bEnabledOnly)
+{
+    if ( bEnabledOnly )
+    {
+        uint32_t u32RetVal = AM_REG(PDM, INTSTAT);
+        return u32RetVal & AM_REG(PDM, INTEN);
+    }
+    else
+    {
+        return AM_REG(PDM, INTSTAT);
+    }
+}
+
+//*****************************************************************************
+//
+//  End the doxygen group
+//! @}
+//
+//*****************************************************************************

bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h

@@ -0,0 +1,342 @@
+//*****************************************************************************
+//
+//  am_hal_pwrctrl.h
+//! @file
+//!
+//! @brief Functions for enabling and disabling power domains.
+//!
+//! @addtogroup pwrctrl2 Power Control
+//! @ingroup apollo2hal
+//! @{
+
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Copyright (c) 2017, Ambiq Micro
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+// 
+// 1. Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// 
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+// 
+// 3. Neither the name of the copyright holder nor the names of its
+// contributors may be used to endorse or promote products derived from this
+// software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
+//
+//*****************************************************************************
+
+#ifndef AM_HAL_PWRCTRL_H
+#define AM_HAL_PWRCTRL_H
+
+//*****************************************************************************
+//
+// Peripheral enable bits for am_hal_pwrctrl_periph_enable/disable()
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_ADC      AM_REG_PWRCTRL_DEVICEEN_ADC_EN
+#define AM_HAL_PWRCTRL_IOM0     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN
+#define AM_HAL_PWRCTRL_IOM1     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN
+#define AM_HAL_PWRCTRL_IOM2     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN
+#define AM_HAL_PWRCTRL_IOM3     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN
+#define AM_HAL_PWRCTRL_IOM4     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN
+#define AM_HAL_PWRCTRL_IOM5     AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN
+#define AM_HAL_PWRCTRL_IOS      AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN
+#define AM_HAL_PWRCTRL_PDM      AM_REG_PWRCTRL_DEVICEEN_PDM_EN
+#define AM_HAL_PWRCTRL_UART0    AM_REG_PWRCTRL_DEVICEEN_UART0_EN
+#define AM_HAL_PWRCTRL_UART1    AM_REG_PWRCTRL_DEVICEEN_UART1_EN
+
+//*****************************************************************************
+//
+// Macro to set the appropriate IOM peripheral when using
+//  am_hal_pwrctrl_periph_enable()/disable().
+// For Apollo2, the module argument must resolve to be a value from 0-5.
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_IOM(module)                      \
+    (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN << module)
+
+//*****************************************************************************
+//
+// Macro to set the appropriate UART peripheral when using
+//  am_hal_pwrctrl_periph_enable()/disable().
+// For Apollo2, the module argument must resolve to be a value from 0-1.
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_UART(module)                     \
+    (AM_REG_PWRCTRL_DEVICEEN_UART0_EN << module)
+
+
+//*****************************************************************************
+//
+// Memory enable values for am_hal_pwrctrl_memory_enable()
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_MEMEN_SRAM8K     AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM16K    AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM24K   (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K | \
+                                        AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM32K    AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM64K    AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM96K                    \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K    |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM128K   AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K
+#define AM_HAL_PWRCTRL_MEMEN_SRAM160K                   \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K   |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM192K                   \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K   |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4     |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM224K                   \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K   |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4     |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5     |   \
+             AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6)
+#define AM_HAL_PWRCTRL_MEMEN_SRAM256K   AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K
+
+#define AM_HAL_PWRCTRL_MEMEN_FLASH512K  AM_REG_PWRCTRL_MEMEN_FLASH0_EN
+#define AM_HAL_PWRCTRL_MEMEN_FLASH1M                \
+            (AM_REG_PWRCTRL_MEMEN_FLASH0_EN     |   \
+             AM_REG_PWRCTRL_MEMEN_FLASH1_EN)
+#define AM_HAL_PWRCTRL_MEMEN_CACHE                  \
+            (AM_REG_PWRCTRL_MEMEN_CACHEB0_EN    |   \
+             AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
+#define AM_HAL_PWRCTRL_MEMEN_CACHE_DIS              \
+            ~(AM_REG_PWRCTRL_MEMEN_CACHEB0_EN   |   \
+              AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
+
+//
+// Power up all available memory devices (this is the default power up state)
+//
+#define AM_HAL_PWRCTRL_MEMEN_ALL                    \
+            (AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL    |   \
+             AM_REG_PWRCTRL_MEMEN_FLASH0_EN     |   \
+             AM_REG_PWRCTRL_MEMEN_FLASH1_EN     |   \
+             AM_REG_PWRCTRL_MEMEN_CACHEB0_EN    |   \
+             AM_REG_PWRCTRL_MEMEN_CACHEB2_EN)
+
+//*****************************************************************************
+//
+// Peripheral power enable and disable delays
+// The delay counts are based on an internal clock that runs at half of
+// HFRC. Therefore, we need to double the delay cycles.
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_DEVICEEN_DELAYCYCLES     (22 * 2)
+#define AM_HAL_PWRCTRL_DEVICEDIS_DELAYCYCLES    (22 * 2)
+
+//
+// Use the following only when enabling after sleep (not during initialization).
+//
+#define AM_HAL_PWRCTRL_BUCKEN_DELAYCYCLES       (0 * 2)
+#define AM_HAL_PWRCTRL_BUCKDIS_DELAYCYCLES      (15 * 2)
+
+//*****************************************************************************
+//
+// Peripheral PWRONSTATUS groupings.
+//
+//*****************************************************************************
+//
+// Group DEVICEEN bits (per PWRONSTATUS groupings).
+//
+#define AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2                     \
+            (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN )
+
+#define AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5                     \
+            (AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN      |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN )
+
+#define AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS                   \
+            (AM_REG_PWRCTRL_DEVICEEN_UART0_EN           |   \
+             AM_REG_PWRCTRL_DEVICEEN_UART1_EN           |   \
+             AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN )
+
+#define AM_HAL_PWRCTRL_DEVICEEN_ADC             AM_REG_PWRCTRL_DEVICEEN_ADC_EN
+#define AM_HAL_PWRCTRL_DEVICEEN_PDM             AM_REG_PWRCTRL_DEVICEEN_PDM_EN
+
+//
+// Map PWRONSTATUS bits to peripheral groupings.
+//
+#define AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS    AM_REG_PWRCTRL_PWRONSTATUS_PDA_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5      AM_REG_PWRCTRL_PWRONSTATUS_PDC_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2      AM_REG_PWRCTRL_PWRONSTATUS_PDB_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_ADC          AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M
+#define AM_HAL_PWRCTRL_PWRONSTATUS_PDM          AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M
+
+#define POLL_PWRSTATUS(ui32Peripheral)                                  \
+    if ( 1 )                                                            \
+    {                                                                   \
+        uint32_t ui32PwrOnStat;                                         \
+        if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_0_2 )         \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_0_2;         \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOM_3_5 )    \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOM_3_5;         \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_IOS_UARTS )  \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_IOS_UARTS;       \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_ADC )        \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_ADC;             \
+        }                                                               \
+        else if ( ui32Peripheral & AM_HAL_PWRCTRL_DEVICEEN_PDM )        \
+        {                                                               \
+            ui32PwrOnStat = AM_HAL_PWRCTRL_PWRONSTATUS_PDM;             \
+        }                                                               \
+        else                                                            \
+        {                                                               \
+            ui32PwrOnStat = 0xFFFFFFFF;                                 \
+        }                                                               \
+                                                                        \
+        /* */                                                           \
+        /* Wait for the power control setting to take effect. */        \
+        /* */                                                           \
+        while ( !(AM_REG(PWRCTRL, PWRONSTATUS) & ui32PwrOnStat) );      \
+    }
+
+//*****************************************************************************
+//
+// Memory PWRONSTATUS enable values for am_hal_pwrctrl_memory_enable()
+//
+//*****************************************************************************
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_8K                  \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_16K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_24K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_32K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_64K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_96K                 \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_128K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_160K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_192K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_224K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K                \
+           (AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M   |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M  |   \
+            AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M)
+
+#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL                 \
+        AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K
+
+//*****************************************************************************
+//
+// Function prototypes
+//
+//*****************************************************************************
+extern void am_hal_pwrctrl_periph_enable(uint32_t ui32Peripheral);
+extern void am_hal_pwrctrl_periph_disable(uint32_t ui32Peripheral);
+extern bool am_hal_pwrctrl_memory_enable(uint32_t ui32MemEn);
+extern void am_hal_pwrctrl_bucks_init(void);
+extern void am_hal_pwrctrl_bucks_enable(void);
+extern void am_hal_pwrctrl_bucks_disable(void);
+extern void am_hal_pwrctrl_low_power_init(void);
+
+#endif // AM_HAL_PWRCTRL_H
+
+//*****************************************************************************
+//
+// End Doxygen group.
+//! @}
+//
+//*****************************************************************************