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[bsp][nxp] add mcxn947

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yandld
2024-01-29 18:18:15 +08:00
committed by Meco Man
parent b68957113c
commit bfa2f7ca57
253 changed files with 356814 additions and 0 deletions
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bsp/nxp/mcxn/Libraries/.ignore_format.yml
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# files format check exclude path, please follow the instructions below to modify;
dir_path:
- MCXN947
bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/cmsis_armclang.h
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bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/cmsis_armclang_ltm.h
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bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/cmsis_compiler.h
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/cmsis_gcc.h
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bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/cmsis_iccarm.h
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bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/cmsis_version.h
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/core_cm33.h
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bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/mpu_armv8.h
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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.3
* @date 03. February 2021
******************************************************************************/
/*
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif
bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/tz_context.h
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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H
bsp/nxp/mcxn/Libraries/CMSIS/LICENSE.txt
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bsp/nxp/mcxn/Libraries/Kconfig
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config SOC_MCX
bool
select ARCH_ARM_CORTEX_M33
select ARCH_ARM_CORTEX_FPU
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0.h
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c
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/*
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cache.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cache_cache64"
#endif
#if (FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0)
/*******************************************************************************
* Variables
******************************************************************************/
/* Array of CACHE64_CTRL peripheral base address. */
static CACHE64_CTRL_Type *const s_cache64ctrlBases[] = CACHE64_CTRL_BASE_PTRS;
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
/* Array of CACHE64_POLSEL peripheral base address. */
static CACHE64_POLSEL_Type *const s_cache64polselBases[] = CACHE64_POLSEL_BASE_PTRS;
#endif
/* Array of CACHE64 physical memory base address. */
static uint32_t const s_cache64PhymemBases[] = CACHE64_CTRL_PHYMEM_BASES;
/* Array of CACHE64 physical memory size. */
static uint32_t const s_cache64PhymemSizes[] = CACHE64_CTRL_PHYMEM_SIZES;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CACHE64_CLOCKS
/* Array of CACHE64_CTRL clock name. */
static const clock_ip_name_t s_cache64Clocks[] = CACHE64_CLOCKS;
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
/*!
* brief Returns an instance number given periphearl base address.
*
* param base The peripheral base address.
* return CACHE64_POLSEL instance number starting from 0.
*/
uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base)
{
uint32_t i;
for (i = 0; i < ARRAY_SIZE(s_cache64polselBases); i++)
{
if (base == s_cache64polselBases[i])
{
break;
}
}
assert(i < ARRAY_SIZE(s_cache64polselBases));
return i;
}
#endif
/*!
* brief Returns an instance number given physical memory address.
*
* param address The physical memory address.
* return CACHE64_CTRL instance number starting from 0.
*/
uint32_t CACHE64_GetInstanceByAddr(uint32_t address)
{
uint32_t i;
for (i = 0; i < ARRAY_SIZE(s_cache64ctrlBases); i++)
{
if ((address >= s_cache64PhymemBases[i]) &&
(address < (s_cache64PhymemBases[i] + s_cache64PhymemSizes[i] - 0x01U)))
{
break;
}
}
return i;
}
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
/*!
* @brief Initializes an CACHE64 instance with the user configuration structure.
*
* This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function
* to configure the configuration structure and get the default configuration.
*
* @param base CACHE64_POLSEL peripheral base address.
* @param config Pointer to a user-defined configuration structure.
* @retval kStatus_Success CACHE64 initialize succeed
*/
status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config)
{
volatile uint32_t *topReg = &base->REG0_TOP;
uint32_t i;
uint32_t polsel = 0;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CACHE64_CLOCKS
uint32_t instance = CACHE64_GetInstance(base);
/* Enable CACHE64 clock */
CLOCK_EnableClock(s_cache64Clocks[instance]);
#endif
#endif
for (i = 0; i < CACHE64_REGION_NUM - 1U; i++)
{
assert((config->boundaryAddr[i] & (CACHE64_REGION_ALIGNMENT - 1U)) == 0U);
((volatile uint32_t *)topReg)[i] = config->boundaryAddr[i] >= CACHE64_REGION_ALIGNMENT ?
config->boundaryAddr[i] - CACHE64_REGION_ALIGNMENT :
0U;
}
for (i = 0; i < CACHE64_REGION_NUM; i++)
{
polsel |= (((uint32_t)config->policy[i]) << (2U * i));
}
base->POLSEL = polsel;
return kStatus_Success;
}
/*!
* @brief Gets the default configuration structure.
*
* This function initializes the CACHE64 configuration structure to a default value. The default
* values are first region covers whole cacheable area, and policy set to write back.
*
* @param config Pointer to a configuration structure.
*/
void CACHE64_GetDefaultConfig(cache64_config_t *config)
{
(void)memset(config, 0, sizeof(cache64_config_t));
config->boundaryAddr[0] = s_cache64PhymemSizes[0];
config->policy[0] = kCACHE64_PolicyWriteBack;
}
#endif
/*!
* brief Enables the cache.
*
*/
void CACHE64_EnableCache(CACHE64_CTRL_Type *base)
{
/* if CACHE is not enabled */
if ((base->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U)
{
/* First, invalidate the entire cache. */
CACHE64_InvalidateCache(base);
/* Now enable the cache. */
base->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK;
}
}
/*!
* brief Disables the cache.
*
*/
void CACHE64_DisableCache(CACHE64_CTRL_Type *base)
{
/* if CACHE is enabled */
if ((base->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U)
{
/* First, push any modified contents. */
CACHE64_CleanCache(base);
/* Now disable the cache. */
base->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK;
}
}
/*!
* brief Invalidates the cache.
*
*/
void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
{
/* Invalidate all lines in both ways and initiate the cache command. */
base->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
/* Wait until the cache command completes. */
while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
{
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
base->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK);
}
/*!
* brief Invalidates cache by range.
*
* param address The physical address of cache.
* param size_byte size of the memory to be invalidated.
* note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
/* Set the invalidate by line command and use the physical address. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
{
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
}
/*!
* brief Cleans the cache.
*
*/
void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
{
/* Enable the to push all modified lines. */
base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
/* Wait until the cache command completes. */
while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
{
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK);
}
/*!
* brief Cleans cache by range.
*
* param address The physical address of cache.
* param size_byte size of the memory to be cleaned.
* note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
/* Set the push by line command. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
{
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
}
/*!
* brief Cleans and invalidates the cache.
*
*/
void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
{
/* Push and invalidate all. */
base->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK |
CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_GO_MASK;
/* Wait until the cache command completes. */
while ((base->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U)
{
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
base->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK |
CACHE64_CTRL_CCR_INVW1_MASK);
}
/*!
* brief Cleans and invalidate cache by range.
*
* param address The physical address of cache.
* param size_byte size of the memory to be Cleaned and Invalidated.
* note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
{
uint32_t endAddr = address + size_byte - 0x01U;
uint32_t pccReg = 0;
/* Align address to cache line size. */
uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
uint32_t instance = CACHE64_GetInstanceByAddr(address);
uint32_t endLim;
CACHE64_CTRL_Type *base;
if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
{
return;
}
base = s_cache64ctrlBases[instance];
endLim = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
endAddr = endAddr > endLim ? endLim : endAddr;
/* Set the push by line command. */
pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK;
base->CLCR = pccReg;
while (startAddr < endAddr)
{
/* Set the address and initiate the command. */
base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
/* Wait until the cache command completes. */
while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
{
}
startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
}
}
#if !(defined(FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF) && FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF)
/*!
* brief Enable the cache write buffer.
*
*/
void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable)
{
if (enable)
{
base->CCR |= CACHE64_CTRL_CCR_ENWRBUF_MASK;
}
else
{
base->CCR &= ~CACHE64_CTRL_CCR_ENWRBUF_MASK;
}
}
#endif
#endif /* FSL_FEATURE_SOC_CACHE64_CTRL_COUNT > 0 */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h
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/*
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_H_
#define _FSL_CACHE_H_
#include "fsl_common.h"
/*!
* @addtogroup cache64
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief cache driver version. */
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
/*@}*/
/*! @brief cache line size. */
#define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
/*! @brief cache region number. */
#define CACHE64_REGION_NUM (3U)
/*! @brief cache region alignment. */
#define CACHE64_REGION_ALIGNMENT (0x400U)
/*! @brief Level 2 cache controller way size. */
typedef enum _cache64_policy
{
kCACHE64_PolicyNonCacheable = 0, /*!< Non-cacheable */
kCACHE64_PolicyWriteThrough = 1, /*!< Write through */
kCACHE64_PolicyWriteBack = 2, /*!< Write back */
} cache64_policy_t;
/*! @brief CACHE64 configuration structure. */
typedef struct _cache64_config
{
/*!< The cache controller can divide whole memory into 3 regions.
* Boundary address is the FlexSPI internal address (start from 0) instead of system
* address (start from FlexSPI AMBA base) to split adjacent regions and must be 1KB
* aligned. The boundary address itself locates in upper region. */
uint32_t boundaryAddr[CACHE64_REGION_NUM - 1];
/*!< Cacheable policy for each region. */
cache64_policy_t policy[CACHE64_REGION_NUM];
} cache64_config_t;
#endif
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name cache control for cache64
*@{
*/
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
/*!
* @brief Returns an instance number given periphearl base address.
*
* @param base The peripheral base address.
* @return CACHE64_POLSEL instance number starting from 0.
*/
uint32_t CACHE64_GetInstance(CACHE64_POLSEL_Type *base);
#endif
/*!
* brief Returns an instance number given physical memory address.
*
* param address The physical memory address.
* @return CACHE64_CTRL instance number starting from 0.
*/
uint32_t CACHE64_GetInstanceByAddr(uint32_t address);
#if (defined(FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT) && (FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT > 0))
/*!
* @brief Initializes an CACHE64 instance with the user configuration structure.
*
* This function configures the CACHE64 module with user-defined settings. Call the CACHE64_GetDefaultConfig() function
* to configure the configuration structure and get the default configuration.
*
* @param base CACHE64_POLSEL peripheral base address.
* @param config Pointer to a user-defined configuration structure.
* @retval kStatus_Success CACHE64 initialize succeed
*/
status_t CACHE64_Init(CACHE64_POLSEL_Type *base, const cache64_config_t *config);
/*!
* @brief Gets the default configuration structure.
*
* This function initializes the CACHE64 configuration structure to a default value. The default
* values are first region covers whole cacheable area, and policy set to write back.
*
* @param config Pointer to a configuration structure.
*/
void CACHE64_GetDefaultConfig(cache64_config_t *config);
#endif
/*!
* @brief Enables the cache.
*
* @param base CACHE64_CTRL peripheral base address.
*
*/
void CACHE64_EnableCache(CACHE64_CTRL_Type *base);
/*!
* @brief Disables the cache.
*
* @param base CACHE64_CTRL peripheral base address.
*
*/
void CACHE64_DisableCache(CACHE64_CTRL_Type *base);
/*!
* @brief Invalidates the cache.
*
* @param base CACHE64_CTRL peripheral base address.
*
*/
void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base);
/*!
* @brief Invalidates cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be invalidated.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Cleans the cache.
*
* @param base CACHE64_CTRL peripheral base address.
*
*/
void CACHE64_CleanCache(CACHE64_CTRL_Type *base);
/*!
* @brief Cleans cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be cleaned.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte);
/*!
* @brief Cleans and invalidates the cache.
*
* @param base CACHE64_CTRL peripheral base address.
*
*/
void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base);
/*!
* @brief Cleans and invalidate cache by range.
*
* @param address The physical address of cache.
* @param size_byte size of the memory to be Cleaned and Invalidated.
* @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
* The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
* startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
#if !(defined(FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF) && FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF)
/*!
* @brief Enables/disables the write buffer.
*
* @param base CACHE64_CTRL peripheral base address.
* @param enable The enable or disable flag.
* true - enable the write buffer.
* false - disable the write buffer.
*/
void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
#endif
/*@}*/
/*!
* @name Unified Cache Control for all caches
*@{
*/
/*!
* @brief Invalidates instruction cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
CACHE64_InvalidateCacheByRange(address, size_byte);
}
/*!
* @brief Invalidates data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be invalidated.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
{
CACHE64_InvalidateCacheByRange(address, size_byte);
}
/*!
* @brief Clean data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be cleaned.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
{
CACHE64_CleanCacheByRange(address, size_byte);
}
/*!
* @brief Cleans and Invalidates data cache by range.
*
* @param address The physical address.
* @param size_byte size of the memory to be Cleaned and Invalidated.
* @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
* FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
* size if startAddr is not aligned. For the size_byte, application should make sure the
* alignment or make sure the right operation order if the size_byte is not aligned.
*/
static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
{
CACHE64_CleanInvalidateCacheByRange(address, size_byte);
}
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_CACHE_H_*/
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.c
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/*
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cache_lpcac.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cache_lpcac"
#endif
/*******************************************************************************
* Code
******************************************************************************/
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h
+184
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/*
* Copyright 2021-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CACHE_LPCAC_H_
#define _FSL_CACHE_LPCAC_H_
#include "fsl_common.h"
/*!
* @addtogroup cache_lpcac
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief cache driver version */
#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name cache control for the L1 low power cache controller
*@{
*/
/*!
* @brief Enables the processor code bus cache.
*
*/
static inline void L1CACHE_EnableCodeCache(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
}
/*!
* @brief Disables the processor code bus cache.
*
*/
static inline void L1CACHE_DisableCodeCache(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
}
/*!
* @brief Clears cache.
*
*/
static inline void L1CACHE_InvalidateCodeCache(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
}
/*!
* @brief Enables allocation.
*
*/
static inline void L1CACHE_EnableAllocation(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK;
}
/*!
* @brief Disables allocation.
*
*/
static inline void L1CACHE_DisableAllocation(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK;
}
/*!
* @brief Enables parity.
*
*/
static inline void L1CACHE_EnableParity(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK;
}
/*!
* @brief Disable parity.
*
*/
static inline void L1CACHE_DisableParity(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK;
}
#if defined(FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL) && FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL
/*!
* @brief Enables write through buffer.
*
*/
static inline void L1CACHE_EnableWriteBuffer(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK;
}
/*!
* @brief Disables write through buffer.
*
*/
static inline void L1CACHE_DisableWriteBuffer(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK;
}
/*!
* @brief Limits write through buffer.
*
*/
static inline void L1CACHE_LimitWriteBuffer(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK;
}
/*!
* @brief Unlimits write through buffer.
*
*/
static inline void L1CACHE_UnlimitParity(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK;
}
/*!
* @brief Enables parity error report.
*
*/
static inline void L1CACHE_EnableParityErrorReport(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK;
}
/*!
* @brief Disables parity error report.
*
*/
static inline void L1CACHE_DisableParityErrorReport(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK;
}
/*!
* @brief Enables XOM(eXecute-Only-Memory) control.
*
*/
static inline void L1CACHE_EnableXOMControl(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK;
}
/*!
* @brief Disables XOM(eXecute-Only-Memory) control.
*
*/
static inline void L1CACHE_DisableXOMControl(void)
{
SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK;
}
#endif
/*@}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_CACHE_LPCAC_H_*/
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c
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/*
* Copyright 2020-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cdog.h"
/*******************************************************************************
* Definitions
*******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cdog"
#endif
/* Reset CONTROL mask */
#define RESERVED_CTRL_MASK 0x800u
#if defined(CDOG_IRQS)
/* Array of IRQs */
static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
#endif /* CDOG_IRQS */
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
#if defined(CDOG)
/*!
* Weak implementation of CDOG IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG_DriverIRQHandler(void)
{
/* NVIC_DisableIRQ(CDOG_IRQn);
* CDOG_Stop(CDOG, s_start);
* CDOG->FLAGS = 0x0U;
* CDOG_Start(CDOG, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG_IRQn);
*/
}
#endif
#if defined(CDOG0)
/*!
* Weak implementation of CDOG0 IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG0_DriverIRQHandler(void)
{
/* NVIC_DisableIRQ(CDOG0_IRQn);
* CDOG_Stop(CDOG0, s_start);
* CDOG0->FLAGS = 0x0U;
* CDOG_Start(CDOG0, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG0_IRQn);
*/
}
#endif
#if defined(CDOG1)
/*!
* Weak implementation of CDOG1 IRQ, should be re-defined by user when using CDOG IRQ
*/
__WEAK void CDOG1_DriverIRQHandler(void)
{
/* NVIC_DisableIRQ(CDOG1_IRQn);
* CDOG_Stop(CDOG1, s_start);
* CDOG1->FLAGS = 0x0U;
* CDOG_Start(CDOG1, 0xFFFFFFU, s_start);
* NVIC_EnableIRQ(CDOG1_IRQn);
*/
}
#endif
/*!
* brief Sets the default configuration of CDOG
*
* This function initialize CDOG config structure to default values.
*
* param conf CDOG configuration structure
*/
void CDOG_GetDefaultConfig(cdog_config_t *conf)
{
/* Default configuration after reset */
conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */
conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */
conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */
conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */
conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */
conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */
conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */
conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */
return;
}
/*!
* brief Sets secure counter and instruction timer values
*
* This function sets value in RELOAD and START registers for instruction timer.
*
* param base CDOG peripheral base address
* param reload reload value
* param start start value
*/
void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)
{
base->RELOAD = reload;
base->START = start;
}
/*!
* brief Stops secure counter and instruction timer
*
* This function stops instruction timer and secure counter.
* This also change state of CDOG to IDLE.
*
* param base CDOG peripheral base address
* param stop expected value which will be compared with value of secure counter
*/
void CDOG_Stop(CDOG_Type *base, uint32_t stop)
{
base->STOP = stop;
}
/*!
* brief Sets secure counter and instruction timer values
*
* This function sets value in STOP, RELOAD and START registers
* for instruction timer and secure counter.
*
* param base CDOG peripheral base address
* param stop expected value which will be compared with value of secure counter
* param reload reload value for instruction timer
* param start start value for secure timer
*/
void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)
{
base->STOP = stop;
base->RELOAD = reload;
base->START = start;
}
/*!
* brief Add value to secure counter
*
* This function add specified value to secure counter.
*
* param base CDOG peripheral base address.
* param add Value to be added.
*/
void CDOG_Add(CDOG_Type *base, uint32_t add)
{
base->ADD = (secure_counter_t)add;
}
/*!
* brief Add 1 to secure counter
*
* This function add 1 to secure counter.
*
* param base CDOG peripheral base address.
* param add Value to be added.
*/
void CDOG_Add1(CDOG_Type *base)
{
base->ADD1 = (secure_counter_t)0x1U;
}
/*!
* brief Add 16 to secure counter
*
* This function add 16 to secure counter.
*
* param base CDOG peripheral base address.
* param add Value to be added.
*/
void CDOG_Add16(CDOG_Type *base)
{
base->ADD16 = (secure_counter_t)0x1U;
}
/*!
* brief Add 256 to secure counter
*
* This function add 256 to secure counter.
*
* param base CDOG peripheral base address.
* param add Value to be added.
*/
void CDOG_Add256(CDOG_Type *base)
{
base->ADD256 = (secure_counter_t)0x1U;
}
/*!
* brief Substract value to secure counter
*
* This function substract specified value to secure counter.
*
* param base CDOG peripheral base address.
* param sub Value to be substracted.
*/
void CDOG_Sub(CDOG_Type *base, uint32_t sub)
{
base->SUB = (secure_counter_t)sub;
}
/*!
* brief Substract 1 from secure counter
*
* This function substract specified 1 from secure counter.
*
* param base CDOG peripheral base address.
*/
void CDOG_Sub1(CDOG_Type *base)
{
base->SUB1 = (secure_counter_t)0x1U;
}
/*!
* brief Substract 16 from secure counter
*
* This function substract specified 16 from secure counter.
*
* param base CDOG peripheral base address.
*/
void CDOG_Sub16(CDOG_Type *base)
{
base->SUB16 = (secure_counter_t)0x1U;
}
/*!
* brief Substract 256 from secure counter
*
* This function substract specified 256 from secure counter.
*
* param base CDOG peripheral base address.
*/
void CDOG_Sub256(CDOG_Type *base)
{
base->SUB256 = (secure_counter_t)0x1U;
}
/*!
* brief Checks secure counter.
*
* This function compares stop value with secure counter value
* by writting to RELOAD refister.
*
* param base CDOG peripheral base address
* param check expected (stop) value.
*/
void CDOG_Check(CDOG_Type *base, uint32_t check)
{
base->RESTART = check;
}
/*!
* brief Set the CDOG persistent word.
*
* param base CDOG peripheral base address.
* param value The value to be written.
*/
void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)
{
base->PERSISTENT = value;
}
/*!
* brief Get the CDOG persistent word.
*
* param base CDOG peripheral base address.
* return The persistent word.
*/
uint32_t CDOG_ReadPersistent(CDOG_Type *base)
{
return base->PERSISTENT;
}
/*!
* brief Initialize CDOG
*
* This function initializes CDOG setting and enable all interrupts.
*
* param base CDOG peripheral base address
* param conf CDOG configuration structure
* return Status of the init operation
*/
status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
{
/* Ungate clock to CDOG engine and reset it */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CDOG_CLOCKS
CLOCK_EnableClock(kCLOCK_Cdog);
#endif /* CDOG_CLOCKS */
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn);
#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
if (base->CONTROL == 0x0U)
{
/* CDOG is not in IDLE mode, which may be cause after SW reset. */
/* Writing to CONTROL register will trigger fault. */
return kStatus_Fail;
}
/* Clear pending errors, otherwise the device will reset */
/* itself immediately after enable Code Watchdog */
if ((uint32_t)kCDOG_LockCtrl_Lock ==
((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT))
{
base->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) |
CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) |
CDOG_FLAGS_POR_FLAG(1U);
}
else
{
base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) |
CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) |
CDOG_FLAGS_POR_FLAG(0U);
}
base->CONTROL =
CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */
CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */
CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */
CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */
CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */
CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */
CDOG_CONTROL_DEBUG_HALT_CTRL(conf->debug_halt) | /* Halt CDOG timer during debug */
CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
#if defined(CDOG_IRQS)
/* Enable peripheral IRQs, if defined in array */
for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
{
NVIC_EnableIRQ(s_CdogIrqs[i]);
}
#endif /* CDOG_IRQS */
return kStatus_Success;
}
/*!
* brief Deinitialize CDOG
*
* This function stops CDOG secure counter.
*
* param base CDOG peripheral base address
*/
void CDOG_Deinit(CDOG_Type *base)
{
#if defined(CDOG_IRQS)
/* Enable peripheral IRQs, if defined in array */
for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
{
NVIC_DisableIRQ(s_CdogIrqs[i]);
}
#endif /* CDOG_IRQS */
#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn);
#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
#ifdef CDOG_CLOCKS
CLOCK_DisableClock(kCLOCK_Cdog);
#endif /* CDOG_CLOCKS */
#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h
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/*
* Copyright 2020-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CDOG_H_
#define _FSL_CDOG_H_
#include "fsl_common.h"
/*!
* @addtogroup CDOG
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Defines CDOG driver version 2.1.2.
*
* Change log:
* - Version 2.1.2
* - Support multiple IRQs
* - Fix default CONTROL values
* - Version 2.1.1
* - Remove bit CONTROL[CONTROL_CTRL]
* - Version 2.1.0
* - Rename CWT to CDOG
* - Version 2.0.2
* - Fix MISRA-2012 issues
* - Version 2.0.1
* - Fix doxygen issues
* - Version 2.0.0
* - initial version
*/
#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*@}*/
typedef struct
{
uint8_t lock : 2;
uint8_t timeout : 3;
uint8_t miscompare : 3;
uint8_t sequence : 3;
uint8_t state : 3;
uint8_t address : 3;
uint8_t reserved : 8;
uint8_t irq_pause : 2;
uint8_t debug_halt : 2;
} cdog_config_t;
enum __cdog_debug_Action_ctrl_enum
{
kCDOG_DebugHaltCtrl_Run = 0x1,
kCDOG_DebugHaltCtrl_Pause = 0x2,
};
enum __cdog_irq_pause_ctrl_enum
{
kCDOG_IrqPauseCtrl_Run = 0x1,
kCDOG_IrqPauseCtrl_Pause = 0x2,
};
enum __cdog_fault_ctrl_enum
{
kCDOG_FaultCtrl_EnableReset = 0x1U,
kCDOG_FaultCtrl_EnableInterrupt = 0x2U,
kCDOG_FaultCtrl_NoAction = 0x4U,
};
enum __code_lock_ctrl_enum
{
kCDOG_LockCtrl_Lock = 0x1,
kCDOG_LockCtrl_Unlock = 0x2,
};
typedef uint32_t secure_counter_t;
#define SC_ADD(add) \
do \
{ \
CDOG->ADD = (secure_counter_t)(add); \
} while (0)
#define SC_ADD1 \
do \
{ \
CDOG->ADD1 = (secure_counter_t)0x1U; \
} while (0)
#define SC_ADD16 \
do \
{ \
CDOG->ADD16 = (secure_counter_t)0x1U; \
} while (0)
#define SC_ADD256 \
do \
{ \
CDOG->ADD256 = (secure_counter_t)0x1U; \
} while (0)
#define SC_SUB(sub) \
do \
{ \
CDOG->SUB = (secure_counter_t)(sub); \
} while (0)
#define SC_SUB1 \
do \
{ \
CDOG->SUB1 = (secure_counter_t)0x1U; \
} while (0)
#define SC_SUB16 \
do \
{ \
CDOG->SUB16 = (secure_counter_t)0x1U; \
} while (0)
#define SC_SUB256 \
do \
{ \
CDOG->SUB256 = (secure_counter_t)0x1U; \
} while (0)
#define SC_CHECK(val) \
do \
{ \
CDOG->RESTART = (secure_counter_t)val; \
} while (0)
/*******************************************************************************
* API
*******************************************************************************/
#if defined(CDOG)
extern void CDOG_DriverIRQHandler(void);
#endif
#if defined(CDOG0)
extern void CDOG0_DriverIRQHandler(void);
#endif
#if defined(CDOG1)
extern void CDOG1_DriverIRQHandler(void);
#endif
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @name CDOG Functional Operation
* @{
*/
/*!
* @brief Initialize CDOG
*
* This function initializes CDOG block and setting.
*
* @param base CDOG peripheral base address
* @param conf CDOG configuration structure
* @return Status of the init operation
*/
status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf);
/*!
* @brief Deinitialize CDOG
*
* This function deinitializes CDOG secure counter.
*
* @param base CDOG peripheral base address
*/
void CDOG_Deinit(CDOG_Type *base);
/*!
* @brief Sets the default configuration of CDOG
*
* This function initialize CDOG config structure to default values.
*
* @param conf CDOG configuration structure
*/
void CDOG_GetDefaultConfig(cdog_config_t *conf);
/*!
* @brief Stops secure counter and instruction timer
*
* This function stops instruction timer and secure counter.
* This also change state od CDOG to IDLE.
*
* @param base CDOG peripheral base address
* @param stop expected value which will be compared with value of secure counter
*/
void CDOG_Stop(CDOG_Type *base, uint32_t stop);
/*!
* @brief Sets secure counter and instruction timer values
*
* This function sets value in RELOAD and START registers
* for instruction timer and secure counter
*
* @param base CDOG peripheral base address
* @param reload reload value
* @param start start value
*/
void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start);
/*!
* @brief Checks secure counter.
*
* This function compares stop value in handler with secure counter value
* by writting to RELOAD refister.
*
* @param base CDOG peripheral base address
* @param check expected (stop) value
*/
void CDOG_Check(CDOG_Type *base, uint32_t check);
/*!
* @brief Sets secure counter and instruction timer values
*
* This function sets value in STOP, RELOAD and START registers
* for instruction timer and secure counter.
*
* @param base CDOG peripheral base address
* @param stop expected value which will be compared with value of secure counter
* @param reload reload value for instruction timer
* @param start start value for secure timer
*/
void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start);
/*!
* @brief Add value to secure counter
*
* This function add specified value to secure counter.
*
* @param base CDOG peripheral base address.
* @param add Value to be added.
*/
void CDOG_Add(CDOG_Type *base, uint32_t add);
/*!
* @brief Add 1 to secure counter
*
* This function add 1 to secure counter.
*
* @param base CDOG peripheral base address.
*/
void CDOG_Add1(CDOG_Type *base);
/*!
* @brief Add 16 to secure counter
*
* This function add 16 to secure counter.
*
* @param base CDOG peripheral base address.
*/
void CDOG_Add16(CDOG_Type *base);
/*!
* @brief Add 256 to secure counter
*
* This function add 256 to secure counter.
*
* @param base CDOG peripheral base address.
*/
void CDOG_Add256(CDOG_Type *base);
/*!
* brief Substract value to secure counter
*
* This function substract specified value to secure counter.
*
* param base CDOG peripheral base address.
* param sub Value to be substracted.
*/
void CDOG_Sub(CDOG_Type *base, uint32_t sub);
/*!
* @brief Substract 1 from secure counter
*
* This function substract specified 1 from secure counter.
*
* @param base CDOG peripheral base address.
*/
void CDOG_Sub1(CDOG_Type *base);
/*!
* @brief Substract 16 from secure counter
*
* This function substract specified 16 from secure counter.
*
* @param base CDOG peripheral base address.
*/
void CDOG_Sub16(CDOG_Type *base);
/*!
* @brief Substract 256 from secure counter
*
* This function substract specified 256 from secure counter.
*
* @param base CDOG peripheral base address.
*/
void CDOG_Sub256(CDOG_Type *base);
/*!
* @brief Set the CDOG persistent word.
*
* @param base CDOG peripheral base address.
* @param value The value to be written.
*/
void CDOG_WritePersistent(CDOG_Type *base, uint32_t value);
/*!
* @brief Get the CDOG persistent word.
*
* @param base CDOG peripheral base address.
* @return The persistent word.
*/
uint32_t CDOG_ReadPersistent(CDOG_Type *base);
/*! @}*/
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/*! @}*/ /* end of group cdog */
#endif /* _FSL_CDOG_H_ */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.h
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c
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/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cmc.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.mcx_cmc"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
static uint32_t g_savedPrimask;
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief Sets clock mode.
*
* This function configs the amount of clock gating when the core asserts
* Sleeping due to WFI, WFE or SLEEPONEXIT.
*
* param base CMC peripheral base address.
* param mode System clock mode.
*/
void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode)
{
uint32_t reg;
reg = base->CKCTRL;
reg &= ~CMC_CKCTRL_CKMODE_MASK;
reg |= CMC_CKCTRL_CKMODE((mode));
base->CKCTRL = reg;
}
/*!
* brief Configures all power mode protection settings.
*
* This function configures the power mode protection settings for
* supported power modes. This should be done before setting the lowPower mode
* for each power doamin.
*
* The allowed lowpower modes are passed as bit map. For example, to allow
* Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode).
* To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes).
*
* param base CMC peripheral base address.
* param allowedModes Bitmaps of the allowed power modes.
*/
void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes)
{
uint32_t reg;
reg = base->PMPROT;
reg &= ~0xFUL;
reg |= allowedModes;
base->PMPROT = reg;
}
/*!
* brief Configure reset pin.
*
* This function configures reset pin. When enabled, the low power filter is enabled in both
* Active and Low power modes, the reset filter is only enabled in Active mode. When both filers
* are enabled, they operate in series.
*
* param base CMC peripheral base address.
* param config Pointer to the reset pin config structure.
*/
void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
{
assert(config != NULL);
uint32_t reg = base->RPC;
if (config->lowpowerFilterEnable)
{
reg |= CMC_RPC_LPFEN_MASK;
}
else
{
reg &= ~CMC_RPC_LPFEN_MASK;
}
if (config->resetFilterEnable)
{
reg |= (CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG(config->resetFilterWidth));
}
else
{
reg &= ~(CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG_MASK);
}
base->RPC = reg;
}
/*!
* brief Power off the selected system SRAM always.
*
* This function powers off the selected system SRAM always. The SRAM arrays should
* not be accessed while they are shut down. SRAM array contents are not retained
* if they are powered off.
*
* param base CMC peripheral base address.
* param mask Bitmap of the SRAM arrays to be powered off all modes.
*/
void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
{
uint32_t reg = base->SRAMDIS[0];
reg &= ~CMC_SRAMDIS_DIS_MASK;
reg |= CMC_SRAMDIS_DIS(mask);
base->SRAMDIS[0] = reg;
}
/*!
* brief Power off the selected system SRAm during low power mode only.
*
* This function powers off the selected system SRAM only during low power mode.
* SRAM array contents are not retained if they are power off.
*
* param base CMC peripheral base address.
* param mask Bitmap of the SRAM arrays to be power off during low power mode only.
*/
void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
{
uint32_t reg = base->SRAMRET[0];
reg &= ~CMC_SRAMRET_RET_MASK;
reg |= CMC_SRAMRET_RET(mask);
base->SRAMRET[0] = reg;
}
/*!
* brief Configs the low power mode of the on-chip flash memory.
*
* This function config the low power mode of the on-chip flash memory.
*
* param base CMC peripheral base address.
* param wake
* true - Flash will exit low power state during the flash memory accesses.
* false - No effect.
* param doze
* true - Flash is disabled while core is sleeping
* false - No effect.
* param disable
* true - Flash memory is placed in low power state.
* false - No effect.
*/
void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable)
{
uint32_t reg = 0UL;
reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) |
(doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)) |
(wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U));
base->FLASHCR = reg;
}
/*!
* brief Prepares to enter stop modes.
*
* This function should be called before entering low power modes.
*
*/
void CMC_PreEnterLowPowerMode(void)
{
g_savedPrimask = DisableGlobalIRQ();
__ISB();
}
/*!
* brief Recovers after wake up from stop modes.
*
* This function should be called after waking up from low power modes.
* This function should be used with CMC_PreEnterLowPowerMode()
*
*/
void CMC_PostExitLowPowerMode(void)
{
EnableGlobalIRQ(g_savedPrimask);
__ISB();
}
/*!
* brief Configs the entry into the same low power mode for each power domains.
*
* This function provides the feature to entry into the same low power mode for each power
* domains. Before invoking this function, please ensure the selected power mode have been allowed.
*
* param base CMC peripheral base address.
* param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details.
*
*/
void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode)
{
/* Note: unlock the CKCTRL register if this API will be reinvoked later. */
CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode);
CMC_SetGlobalPowerMode(base, lowPowerMode);
/* Before executing WFI instruction read back the last register to
* ensure all registers writes have completed. */
(void)base->GPMCTRL;
/* Set the core into DeepSleep mode. */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
__ISB();
}
/*!
* brief Configs the entry into different low power modes for each of the power domains.
*
* This function provides the feature to entry into different low power modes for
* each power domains. Before invoking this function please ensure the selected
* modes are allowed.
*
* param base CMC peripheral base address.
* param base config Pointer to the cmc_power_domain_config_t structure.
*/
void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config)
{
assert(config != NULL);
/* The WAKE domain must never be configured to a lower power mode compared with main power mode. */
assert(config->wake_domain <= config->main_domain);
if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode)
{
/* In This case the power domain doesn't need to be placed in low power state. */
/* Note: unlock the register if this API will be reinvoked later. */
CMC_SetClockMode(base, config->clock_mode);
CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode);
CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode);
/* Before executing WFI instruction read back the last register to
* ensure all registers writes have completed. */
(void)base->CKCTRL;
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
__ISB();
}
else
{
/* Note: unlock the register if this API will be reinvoked later. */
CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode);
CMC_SetMAINPowerMode(base, config->main_domain);
CMC_SetWAKEPowerMode(base, config->wake_domain);
/* Before execute WFI instruction read back the last register to
* ensure all registers writes have completed. */
if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain))
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
__ISB();
}
}
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.c
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#define SDK_MEM_MAGIC_NUMBER 12345U
typedef struct _mem_align_control_block
{
uint16_t identifier; /*!< Identifier for the memory control block. */
uint16_t offset; /*!< offset from aligned address to real address */
} mem_align_cb_t;
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.common"
#endif
#if !((defined(__DSC__) && defined(__CW__)))
void *SDK_Malloc(size_t size, size_t alignbytes)
{
mem_align_cb_t *p_cb = NULL;
uint32_t alignedsize;
/* Check overflow. */
alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
if (alignedsize < size)
{
return NULL;
}
if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
{
return NULL;
}
alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
union
{
void *pointer_value;
uintptr_t unsigned_value;
} p_align_addr, p_addr;
p_addr.pointer_value = malloc((size_t)alignedsize);
if (p_addr.pointer_value == NULL)
{
return NULL;
}
p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
return p_align_addr.pointer_value;
}
void SDK_Free(void *ptr)
{
union
{
void *pointer_value;
uintptr_t unsigned_value;
} p_free;
p_free.pointer_value = ptr;
mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
{
return;
}
p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
free(p_free.pointer_value);
}
#endif
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_COMMON_H_
#define _FSL_COMMON_H_
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
#include <stddef.h>
#endif
#include "fsl_device_registers.h"
/*!
* @addtogroup ksdk_common
* @{
*/
/*******************************************************************************
* Configurations
******************************************************************************/
/*! @brief Macro to use the default weak IRQ handler in drivers. */
#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Construct a status code value from a group and code number. */
#define MAKE_STATUS(group, code) ((((group)*100L) + (code)))
/*! @brief Construct the version number for drivers.
*
* The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M)
* and 16-bit platforms(such as DSC).
*
* @verbatim
| Unused || Major Version || Minor Version || Bug Fix |
31 25 24 17 16 9 8 0
@endverbatim
*/
#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
/*! @name Driver version */
/*@{*/
/*! @brief common driver version. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
/*@}*/
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
/*! @brief Status group numbers. */
enum _status_groups
{
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */
kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */
kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */
kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */
kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/
kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */
kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */
kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */
kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */
kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */
kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */
kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */
kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */
kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */
kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */
kStatusGroup_LED = 137, /*!< Group number for LED status codes. */
kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */
kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */
kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */
kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */
kStatusGroup_LIST = 142, /*!< Group number for List status codes. */
kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */
kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */
kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */
kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */
kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */
kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */
kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */
kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */
kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */
kStatusGroup_NETC = 165, /*!< Group number for NETC status codes. */
};
/*! \public
* @brief Generic status return codes.
*/
enum
{
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
kStatus_NoTransferInProgress =
MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */
kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
kStatus_NoData =
MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
/*!
* @name Min/max macros
* @{
*/
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
/* @} */
/*! @brief Computes the number of elements in an array. */
#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#endif
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
#if !defined(UINT16_MAX)
#define UINT16_MAX ((uint16_t)-1)
#endif
#if !defined(UINT32_MAX)
#define UINT32_MAX ((uint32_t)-1)
#endif
/* @} */
/*! @name Suppress fallthrough warning macro */
/* For switch case code block, if case section ends without "break;" statement, there wil be
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
case section which misses "break;"statement.
*/
/* @{ */
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
#else
#define SUPPRESS_FALL_THROUGH_WARNING()
#endif
/* @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
#if !((defined(__DSC__) && defined(__CW__)))
/*!
* @brief Allocate memory with given alignment and aligned size.
*
* This is provided to support the dynamically allocated memory
* used in cache-able region.
* @param size The length required to malloc.
* @param alignbytes The alignment size.
* @retval The allocated memory.
*/
void *SDK_Malloc(size_t size, size_t alignbytes);
/*!
* @brief Free memory.
*
* @param ptr The memory to be release.
*/
void SDK_Free(void *ptr);
#endif
/*!
* @brief Delay at least for some time.
* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
* if precise delay count was needed, please implement a new delay function with hardware timer.
*
* @param delayTime_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
#if defined(__cplusplus)
}
#endif
/*! @} */
#if (defined(__DSC__) && defined(__CW__))
#include "fsl_common_dsc.h"
#elif defined(__XCC__)
#include "fsl_common_dsp.h"
#else
#include "fsl_common_arm.h"
#endif
#endif /* _FSL_COMMON_H_ */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.common_arm"
#endif
#ifndef __GIC_PRIO_BITS
#if defined(ENABLE_RAM_VECTOR_TABLE)
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
#ifdef __VECTOR_TABLE
#undef __VECTOR_TABLE
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
irqMaskValue = DisableGlobalIRQ();
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
ret = __VECTOR_RAM[(int32_t)irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
return ret;
}
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#endif /* __GIC_PRIO_BITS. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*
* When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
* powerlib should be used instead of these functions.
*/
#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
/*
* When the SYSCON STARTER registers are discontinuous, these functions are
* implemented in fsl_power.c.
*/
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
void EnableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERSET[index] = 1UL << intNumber;
(void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
(void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
uint32_t index = 0;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
SYSCON->STARTERCLR[index] = 1UL << intNumber;
}
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#if defined(DWT)
/* Use WDT. */
void MSDK_EnableCpuCycleCounter(void)
{
/* Make sure the DWT trace fucntion is enabled. */
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
{
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
}
/* CYCCNT not supported on this device. */
assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk));
/* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */
if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL))
{
DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
}
}
uint32_t MSDK_GetCpuCycleCount(void)
{
return DWT->CYCCNT;
}
#endif /* defined(DWT) */
#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT))
/* Use software loop. */
#if defined(__CC_ARM) /* This macro is arm v5 specific */
/* clang-format off */
__ASM static void DelayLoop(uint32_t count)
{
loop
SUBS R0, R0, #1
CMP R0, #0
BNE loop
BX LR
}
#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
static void DelayLoop(uint32_t count)
{
__ASM volatile(" MOV X0, %0" : : "r"(count));
__ASM volatile(
"loop: \n"
" SUB X0, X0, #1 \n"
" CMP X0, #0 \n"
" BNE loop \n"
:
:
: "r0");
}
/* clang-format on */
#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
* use SUB and CMP here for compatibility */
static void DelayLoop(uint32_t count)
{
__ASM volatile(" MOV R0, %0" : : "r"(count));
__ASM volatile(
"loop: \n"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
" SUB R0, R0, #1 \n"
#else
" SUBS R0, R0, #1 \n"
#endif
" CMP R0, #0 \n"
" BNE loop \n"
:
:
: "r0");
}
#endif /* defined(__CC_ARM) */
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
/*!
* @brief Delay at least for some time.
* Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
* effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
* coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
* up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
*
* @param delayTime_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
{
uint64_t count;
if (delayTime_us > 0U)
{
count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
assert(count <= UINT32_MAX);
#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
MSDK_EnableCpuCycleCounter();
/* Calculate the count ticks. */
count += MSDK_GetCpuCycleCount();
if (count > UINT32_MAX)
{
count -= UINT32_MAX;
/* Wait for cyccnt overflow. */
while (count < MSDK_GetCpuCycleCount())
{
}
}
/* Wait for cyccnt reach count value. */
while (count > MSDK_GetCpuCycleCount())
{
}
#else
/* Divide value may be different in various environment to ensure delay is precise.
* Every loop count includes three instructions, due to Cortex-M7 sometimes executes
* two instructions in one period, through test here set divide 1.5. Other M cores use
* divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
* not matter because other instructions outside while loop is enough to fill the time.
*/
#if (__CORTEX_M == 7)
count = count / 3U * 2U;
#else
count = count / 4U;
#endif
DelayLoop((uint32_t)count);
#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
}
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017, 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_crc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.crc"
#endif
/*! @internal @brief Has data register with name CRC. */
#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG
#define DATA CRC
#define DATALL CRCLL
#endif
#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT
/* @brief Default user configuration structure for CRC-16-CCITT */
#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U
/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */
#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
/*< Default initial checksum */
#define CRC_DRIVER_DEFAULT_REFLECT_IN false
/*< Default is no transpose */
#define CRC_DRIVER_DEFAULT_REFLECT_OUT false
/*< Default is transpose bytes */
#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false
/*< Default is without complement of CRC data register read data */
#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16
/*< Default is 16-bit CRC protocol */
#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum
/*< Default is resutl type is final checksum */
#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
/*! @brief CRC type of transpose of read write data */
typedef enum _crc_transpose_type
{
kCrcTransposeNone = 0U, /*! No transpose */
kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */
kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */
kCrcTransposeBytes = 3U, /*! Transpose bytes */
} crc_transpose_type_t;
/*!
* @brief CRC module configuration.
*
* This structure holds the configuration for the CRC module.
*/
typedef struct _crc_module_config
{
uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n
Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
uint32_t seed; /*!< Starting checksum value */
crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */
crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */
bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */
} crc_module_config_t;
/*******************************************************************************
* Code
******************************************************************************/
/*!
* @brief Returns transpose type for CRC protocol reflect in parameter.
*
* This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter.
*
* @param enable True or false for the selected CRC protocol Reflect In (refin) parameter.
*/
static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable)
{
return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes);
}
/*!
* @brief Returns transpose type for CRC protocol reflect out parameter.
*
* This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter.
*
* @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter.
*/
static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable)
{
return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone);
}
/*!
* @brief Starts checksum computation.
*
* Configures the CRC module for the specified CRC protocol. @n
* Starts the checksum computation by writing the seed value
*
* @param base CRC peripheral address.
* @param config Pointer to protocol configuration structure.
*/
static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config)
{
uint32_t crcControl;
/* pre-compute value for CRC control registger based on user configuraton without WAS field */
crcControl = 0U | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) |
CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits);
/* make sure the control register is clear - WAS is deasserted, and protocol is set */
base->CTRL = crcControl;
/* write polynomial register */
base->GPOLY = config->polynomial;
/* write pre-computed control register value along with WAS to start checksum computation */
base->CTRL = crcControl | CRC_CTRL_WAS(true);
/* write seed (initial checksum) */
base->DATA = config->seed;
/* deassert WAS by writing pre-computed CRC control register value */
base->CTRL = crcControl;
}
/*!
* @brief Starts final checksum computation.
*
* Configures the CRC module for the specified CRC protocol. @n
* Starts final checksum computation by writing the seed value.
* @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum
* (output reflection and xor functions are applied).
*
* @param base CRC peripheral address.
* @param protocolConfig Pointer to protocol configuration structure.
*/
static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
{
crc_module_config_t moduleConfig;
/* convert protocol to CRC peripheral module configuration, prepare for final checksum */
moduleConfig.polynomial = protocolConfig->polynomial;
moduleConfig.seed = protocolConfig->seed;
moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut);
moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
moduleConfig.complementChecksum = protocolConfig->complementChecksum;
moduleConfig.crcBits = protocolConfig->crcBits;
CRC_ConfigureAndStart(base, &moduleConfig);
}
/*!
* @brief Starts intermediate checksum computation.
*
* Configures the CRC module for the specified CRC protocol. @n
* Starts intermediate checksum computation by writing the seed value.
* @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value).
*
* @param base CRC peripheral address.
* @param protocolConfig Pointer to protocol configuration structure.
*/
static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig)
{
crc_module_config_t moduleConfig;
/* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */
moduleConfig.polynomial = protocolConfig->polynomial;
moduleConfig.seed = protocolConfig->seed;
moduleConfig.readTranspose =
kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */
moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn);
moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */
moduleConfig.crcBits = protocolConfig->crcBits;
CRC_ConfigureAndStart(base, &moduleConfig);
}
/*!
* brief Enables and configures the CRC peripheral module.
*
* This function enables the clock gate in the SIM module for the CRC peripheral.
* It also configures the CRC module and starts a checksum computation by writing the seed.
*
* param base CRC peripheral address.
* param config CRC module configuration structure.
*/
void CRC_Init(CRC_Type *base, const crc_config_t *config)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* ungate clock */
CLOCK_EnableClock(kCLOCK_Crc0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* configure CRC module and write the seed */
if (config->crcResult == kCrcFinalChecksum)
{
CRC_SetProtocolConfig(base, config);
}
else
{
CRC_SetRawProtocolConfig(base, config);
}
}
/*!
* brief Loads default values to the CRC protocol configuration structure.
*
* Loads default values to the CRC protocol configuration structure. The default values are as follows.
* code
* config->polynomial = 0x1021;
* config->seed = 0xFFFF;
* config->reflectIn = false;
* config->reflectOut = false;
* config->complementChecksum = false;
* config->crcBits = kCrcBits16;
* config->crcResult = kCrcFinalChecksum;
* endcode
*
* param config CRC protocol configuration structure.
*/
void CRC_GetDefaultConfig(crc_config_t *config)
{
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
static const crc_config_t crc16ccit = {
CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED,
CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT,
CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS,
CRC_DRIVER_DEFAULT_CRC_RESULT,
};
*config = crc16ccit;
}
/*!
* brief Writes data to the CRC module.
*
* Writes input data buffer bytes to the CRC data register.
* The configured type of transpose is applied.
*
* param base CRC peripheral address.
* param data Input data stream, MSByte in data[0].
* param dataSize Size in bytes of the input data buffer.
*/
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
{
const uint32_t *data32;
/* 8-bit reads and writes till source address is aligned 4 bytes */
while ((0U != dataSize) && (0U != ((uint32_t)data & 3U)))
{
base->ACCESS8BIT.DATALL = *data;
data++;
dataSize--;
}
/* use 32-bit reads and writes as long as possible */
data32 = (const uint32_t *)(uint32_t)data;
while (dataSize >= sizeof(uint32_t))
{
base->DATA = *data32;
data32++;
dataSize -= sizeof(uint32_t);
}
data = (const uint8_t *)data32;
/* 8-bit reads and writes till end of data buffer */
while (dataSize != 0U)
{
base->ACCESS8BIT.DATALL = *data;
data++;
dataSize--;
}
}
/*!
* brief Reads the 32-bit checksum from the CRC module.
*
* Reads the CRC data register (either an intermediate or the final checksum).
* The configured type of transpose and complement is applied.
*
* param base CRC peripheral address.
* return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
*/
uint32_t CRC_Get32bitResult(CRC_Type *base)
{
return base->DATA;
}
/*!
* brief Reads a 16-bit checksum from the CRC module.
*
* Reads the CRC data register (either an intermediate or the final checksum).
* The configured type of transpose and complement is applied.
*
* param base CRC peripheral address.
* return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
*/
uint16_t CRC_Get16bitResult(CRC_Type *base)
{
uint32_t retval;
uint32_t totr; /* type of transpose read bitfield */
retval = base->DATA;
totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT;
/* check transpose type to get 16-bit out of 32-bit register */
if (totr >= 2U)
{
/* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */
retval &= 0xFFFF0000U;
retval = retval >> 16U;
}
else
{
/* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */
retval &= 0x0000FFFFU;
}
return (uint16_t)retval;
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h
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/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017, 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CRC_H_
#define _FSL_CRC_H_
#include "fsl_common.h"
/*!
* @addtogroup crc
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief CRC driver version. Version 2.0.3.
*
* Current version: 2.0.3
*
* Change log:
*
* - Version 2.0.3
* - Fix MISRA issues
*
* - Version 2.0.2
* - Fix MISRA issues
*
* - Version 2.0.1
* - move DATA and DATALL macro definition from header file to source file
*/
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
#endif
/*! @brief CRC bit width */
typedef enum _crc_bits
{
kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */
kCrcBits32 = 1U /*!< Generate 32-bit CRC code */
} crc_bits_t;
/*! @brief CRC result type */
typedef enum _crc_result
{
kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum.
Reflect out and final xor protocol features are applied. */
kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value).
Reflect out and final xor protocol feature are not applied.
Intermediate checksum can be used as a seed for CRC_Init()
to continue adding data to this checksum. */
} crc_result_t;
/*!
* @brief CRC protocol configuration.
*
* This structure holds the configuration for the CRC protocol.
*
*/
typedef struct _crc_config
{
uint32_t polynomial; /*!< CRC Polynomial, MSBit first.
Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
uint32_t seed; /*!< Starting checksum value */
bool reflectIn; /*!< Reflect bits on input. */
bool reflectOut; /*!< Reflect bits on output. */
bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */
crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or
CRC_Get32bitResult() */
} crc_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enables and configures the CRC peripheral module.
*
* This function enables the clock gate in the SIM module for the CRC peripheral.
* It also configures the CRC module and starts a checksum computation by writing the seed.
*
* @param base CRC peripheral address.
* @param config CRC module configuration structure.
*/
void CRC_Init(CRC_Type *base, const crc_config_t *config);
/*!
* @brief Disables the CRC peripheral module.
*
* This function disables the clock gate in the SIM module for the CRC peripheral.
*
* @param base CRC peripheral address.
*/
static inline void CRC_Deinit(CRC_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* gate clock */
CLOCK_DisableClock(kCLOCK_Crc0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief Loads default values to the CRC protocol configuration structure.
*
* Loads default values to the CRC protocol configuration structure. The default values are as follows.
* @code
* config->polynomial = 0x1021;
* config->seed = 0xFFFF;
* config->reflectIn = false;
* config->reflectOut = false;
* config->complementChecksum = false;
* config->crcBits = kCrcBits16;
* config->crcResult = kCrcFinalChecksum;
* @endcode
*
* @param config CRC protocol configuration structure.
*/
void CRC_GetDefaultConfig(crc_config_t *config);
/*!
* @brief Writes data to the CRC module.
*
* Writes input data buffer bytes to the CRC data register.
* The configured type of transpose is applied.
*
* @param base CRC peripheral address.
* @param data Input data stream, MSByte in data[0].
* @param dataSize Size in bytes of the input data buffer.
*/
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
/*!
* @brief Reads the 32-bit checksum from the CRC module.
*
* Reads the CRC data register (either an intermediate or the final checksum).
* The configured type of transpose and complement is applied.
*
* @param base CRC peripheral address.
* @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
*/
uint32_t CRC_Get32bitResult(CRC_Type *base);
/*!
* @brief Reads a 16-bit checksum from the CRC module.
*
* Reads the CRC data register (either an intermediate or the final checksum).
* The configured type of transpose and complement is applied.
*
* @param base CRC peripheral address.
* @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
*/
uint16_t CRC_Get16bitResult(CRC_Type *base);
#if defined(__cplusplus)
}
#endif
/*!
*@}
*/
#endif /* _FSL_CRC_H_ */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c
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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2019, 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_dac.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.dac_1"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for DAC module.
*
* @param base DAC peripheral base address
*/
static uint32_t DAC_GetInstance(LPDAC_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to DAC bases for each instance. */
static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to DAC clocks for each instance. */
static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t DAC_GetInstance(LPDAC_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++)
{
if (s_dacBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_dacBases));
return instance;
}
/*!
* brief Initialize the DAC module with common configuartion.
*
* The clock will be enabled in this function.
*
* param base DAC peripheral base address.
* param config Pointer to configuration structure.
*/
void DAC_Init(LPDAC_Type *base, const dac_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0U;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset the logic. */
DAC_SetReset(base, kDAC_ResetLogic);
DAC_ClearReset(base, kDAC_ResetLogic);
/* Reset the FIFO. */
DAC_SetReset(base, kDAC_ResetFIFO);
DAC_ClearReset(base, kDAC_ResetFIFO);
/* Configuration. */
if (kDAC_FIFOTriggerBySoftwareMode == config->fifoTriggerMode)
{
tmp32 |= LPDAC_GCR_TRGSEL_MASK; /* Software trigger. */
}
switch (config->fifoWorkMode)
{
case kDAC_FIFOWorkAsNormalMode: /* Normal FIFO. */
tmp32 |= LPDAC_GCR_FIFOEN_MASK;
break;
case kDAC_FIFOWorkAsSwingMode:
tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_SWMD_MASK; /* Enable swing mode. */
break;
#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
case kDAC_FIFOWorkAsPeriodTriggerMode:
tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK; /* Enable period trigger mode. */
/* Set trigger number and width. */
base->PCR =
LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth);
break;
case kDAC_FIFOWorkAsPeriodTriggerAndSwingMode:
tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK | LPDAC_GCR_SWMD_MASK;
/* Set trigger number and width. */
base->PCR =
LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth);
break;
#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
default: /* kDAC_FIFODisabled. */
break;
}
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG
if (config->enableExternalTriggerSource)
{
tmp32 |= LPDAC_GCR_RCV_TRG_MASK; /* Use trigger source from another DAC. */
}
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL
if (false == config->enableLowerLowPowerMode)
{
tmp32 |= LPDAC_GCR_BUF_SPD_CTRL_MASK; /* Enable low power. */
}
#else
if (config->enableLowPowerMode)
{
tmp32 |= LPDAC_GCR_LPEN_MASK; /* Enable low power. */
}
#endif /* LPDAC_GCR_BUF_SPD_CTRL_MASK */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN
tmp32 |= LPDAC_GCR_BUF_EN_MASK; /* Opamp is used as buffer. */
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC
/* Configure DAC sync cycles. */
tmp32 |= LPDAC_GCR_LATCH_CYC(config->syncTime);
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */
#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT
tmp32 |= (uint32_t)config->referenceCurrentSource;
#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */
/* Set reference voltage source. */
tmp32 |= LPDAC_GCR_DACRFS(config->referenceVoltageSource);
base->GCR = tmp32;
base->FCR = LPDAC_FCR_WML(config->fifoWatermarkLevel);
/* Now, the DAC is disabled. It needs to be enabled in application. */
}
/*!
* brief Get the default settings for initialization's configuration.
*
* This function initializes the user configuration structure to a default value. The default values are:
* code
* config->fifoWatermarkLevel = 0U;
* config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode;
* config->fifoWorkMode = kDAC_FIFODisabled;
* config->enableLowPowerMode = false;
* config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1;
* endcode
*
* param config Pointer to configuration structure.
* param
*/
void DAC_GetDefaultConfig(dac_config_t *config)
{
assert(config != NULL);
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->fifoWatermarkLevel = 0U;
config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode;
config->fifoWorkMode = kDAC_FIFODisabled;
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG
config->enableExternalTriggerSource = false;
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL
config->enableLowerLowPowerMode = true;
#else
config->enableLowPowerMode = false;
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */
#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
config->periodicTriggerNumber = 0UL;
config->periodicTriggerWidth = 0UL;
#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC
/* Configure DAC sync cycles. */
config->syncTime = 1U;
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */
#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT
config->referenceCurrentSource = kDAC_ReferenceCurrentSourcePtat;
#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */
config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1;
}
/*!
* brief De-initialize the DAC module.
*
* The clock will be disabled in this function.
*
* param base DAC peripheral base address.
* param
*/
void DAC_Deinit(LPDAC_Type *base)
{
/* Disable the module. */
DAC_Enable(base, false);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h
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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2020, 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DAC_H_
#define _FSL_DAC_H_
#include "fsl_common.h"
/*!
* @addtogroup dac
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief DAC driver version 2.1.1. */
#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*!
* @brief DAC reset control.
*/
enum
{
kDAC_ResetFIFO = LPDAC_RCR_FIFORST_MASK, /*!< Resets the FIFO pointers and flags. */
kDAC_ResetLogic = LPDAC_RCR_SWRST_MASK, /*!< Resets all DAC registers and internal logic. */
};
/*!
* @brief DAC interrupts.
*/
enum
{
kDAC_FIFOFullInterruptEnable = LPDAC_IER_FULL_IE_MASK, /*!< FIFO full interrupt enable. */
kDAC_FIFOEmptyInterruptEnable = LPDAC_IER_EMPTY_IE_MASK, /*!< FIFO empty interrupt enable. */
kDAC_FIFOWatermarkInterruptEnable = LPDAC_IER_WM_IE_MASK, /*!< FIFO watermark interrupt enable. */
kDAC_SwingBackInterruptEnable = LPDAC_IER_SWBK_IE_MASK, /*!< Swing back one cycle complete interrupt enable. */
kDAC_FIFOOverflowInterruptEnable = LPDAC_IER_OF_IE_MASK, /*!< FIFO overflow interrupt enable. */
kDAC_FIFOUnderflowInterruptEnable = LPDAC_IER_UF_IE_MASK, /*!< FIFO underflow interrupt enable. */
#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
kDAC_PeriodTriggerCompleteInterruptEnable =
LPDAC_IER_PTGCOCO_IE_MASK, /*!< Period trigger mode conversion complete interrupt enable */
#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
};
/*!
* @brief DAC DMA switchers.
*/
enum
{
kDAC_FIFOEmptyDMAEnable = LPDAC_DER_EMPTY_DMAEN_MASK, /*!< FIFO empty DMA enable. */
kDAC_FIFOWatermarkDMAEnable = LPDAC_DER_WM_DMAEN_MASK, /*!< FIFO watermark DMA enable. */
};
/*!
* @brief DAC status flags.
*/
enum
{
kDAC_FIFOUnderflowFlag = LPDAC_FSR_UF_MASK, /*!< This flag means that there is a new trigger after the buffer is
empty. The FIFO read pointer will not
increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1
to it. */
kDAC_FIFOOverflowFlag =
LPDAC_FSR_OF_MASK, /*!< This flag indicates that data is intended to write into FIFO after the
buffer is full. The writer pointer will
not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it.
*/
kDAC_FIFOSwingBackFlag = LPDAC_FSR_SWBK_MASK, /*!< This flag indicates that the DAC has completed one period of
conversion in swing back mode. It means
that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For
example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the
read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is
cleared by writing a 1 to it. */
kDAC_FIFOWatermarkFlag = LPDAC_FSR_WM_MASK, /*!< This field is set if the remaining data in FIFO is less than or
equal to the setting value of wartermark. By writing data into FIFO by DMA or CPU, this flag is
cleared automatically when the data in FIFO is more than the setting value of watermark. */
kDAC_FIFOEmptyFlag = LPDAC_FSR_EMPTY_MASK, /*!< FIFO empty flag. */
kDAC_FIFOFullFlag = LPDAC_FSR_FULL_MASK, /*!< FIFO full flag. */
#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
kDAC_PeriodTriggerCompleteFlag = LPDAC_FSR_PTGCOCO_MASK, /*!< Period trigger mode conversion complete flag. */
#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
};
/*!
* @brief DAC FIFO trigger mode.
*/
typedef enum _dac_fifo_trigger_mode
{
kDAC_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */
kDAC_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */
} dac_fifo_trigger_mode_t;
/*!
* @brief DAC FIFO work mode.
*/
typedef enum _dac_fifo_work_mode
{
kDAC_FIFODisabled = 0U, /*!< FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes
to buffer then goes to conversion. */
kDAC_FIFOWorkAsNormalMode = 1U, /*!< FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to
conversion. */
kDAC_FIFOWorkAsSwingMode = 2U, /*!< In swing mode, the read pointer swings between the writer pointer and zero. That
is, the trigger increases the read pointer till reach the writer pointer and
decreases the read pointer till zero, and so on. The FIFO empty/full/watermark
flag will not update during swing back mode. */
#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
kDAC_FIFOWorkAsPeriodTriggerMode =
3U, /*!< In periodic trigger mode, user only needs to send the first trigger. Then after every [PTG_PERIOD+1]
RCLK cycles, DAC will be automatically triggered by internal trigger. There will be [PTG_NUM] internal
triggers, thus in total [PTG_NUM+1] conversions including the first trigger sent by user. User can
terminate the current conversion queue by clearing the GCR[PTGEN] bit. Then, after the current conversion
is completed, the conversion is terminated and the PTGCOCO flag is set. If PCR[PTG_NUM] is set to zero,
there will be infinite triggers following the first hardware/software trigger, until the GCR[PTGEN] is
cleared by software. In any case, the conversion can be terminated by FIFORST/SWRST. */
kDAC_FIFOWorkAsPeriodTriggerAndSwingMode = 4U, /*!< Periodically trigger DAC and swing back. */
#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
} dac_fifo_work_mode_t;
/*!
* @brief DAC reference voltage source.
*/
typedef enum _dac_reference_voltage_source
{
#if defined(FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC) && (FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC == 3)
kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VDD_ANA as the reference voltage. */
kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREF_OUT as the reference voltage. */
kDAC_ReferenceVoltageSourceAlt3 = 2U, /*!< THe DAC selects VREFH as the reference voltage. */
#else
kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VREFH_INT as the reference voltage. */
kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREFH_EXT as the reference voltage. */
#endif /* FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC */
} dac_reference_voltage_source_t;
#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT
/*
* @brief DAC internal reference current source
*/
typedef enum _dac_reference_current_source
{
kDAC_ReferenceCurrentSourcePtat = LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK, /* Internal PTAT Current Reference selected */
kDAC_ReferenceCurrentSourceZtc = LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK, /* Internal ZTC Current Reference selected */
} dac_reference_current_source_t;
#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */
/*!
* @brief DAC configuration structure.
*/
typedef struct _dac_config
{
uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */
dac_fifo_trigger_mode_t fifoTriggerMode; /*!< Select the trigger mode for FIFO. */
dac_fifo_work_mode_t fifoWorkMode; /*!< Select the work mode for FIFO. */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN
bool enableOpampBuffer; /*!< Opamp is used as buffer. */
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG
bool enableExternalTriggerSource; /* DAC uses another DAC's hardware/software trigger as its trigger source. */
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL
bool enableLowerLowPowerMode; /*!< Enable the lower low power mode. */
#else
bool enableLowPowerMode; /*!< Enable the low power mode. */
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */
#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
uint32_t periodicTriggerNumber; /*!< There will be 'periodicTriggerNumber' internal triggers following the first
hardware/software trigger. So there will be 'periodicTriggerNumber + 1'
conversions in total. If set to zero, there will be infinite triggers following
the first hw/sw trigger, until the GCR[PTGEN] is cleared. */
uint32_t periodicTriggerWidth; /*!< Control the periodic trigger frequency. There will be 'periodicTriggerWidth + 1'
RCLK cycles between each periodic trigger. The periodic trigger frequency should
be configured to not larger than the analog conversion speed. */
#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC
uint32_t syncTime; /*!< RCLK cycles before data latch. accessible range is 0-15. It is used to configure the DAC
sync cycles which is helpful to reduce glitch on the output. The sync time is (LATCH_CYC+1)
RCLK cycles. User should configure this register according to the RCLK frequency. The
recommended sync time is at least 40ns.*/
#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */
#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT
dac_reference_current_source_t referenceCurrentSource; /*!< Select the internal reference current source. */
#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */
dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
} dac_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and de-initialization
* @{
*/
/*!
* @brief Initialize the DAC module with common configuartion.
*
* The clock will be enabled in this function.
*
* @param base DAC peripheral base address.
* @param config Pointer to configuration structure.
*/
void DAC_Init(LPDAC_Type *base, const dac_config_t *config);
/*!
* @brief Get the default settings for initialization's configuration.
*
* This function initializes the user configuration structure to a default value. The default values are:
* @code
* config->fifoWatermarkLevel = 0U;
* config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode;
* config->fifoWorkMode = kDAC_FIFODisabled;
* config->enableLowPowerMode = false;
* config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1;
* @endcode
*
* @param config Pointer to configuration structure.
*/
void DAC_GetDefaultConfig(dac_config_t *config);
/*!
* @brief De-initialize the DAC module.
*
* The clock will be disabled in this function.
*
* @param base DAC peripheral base address.
*/
void DAC_Deinit(LPDAC_Type *base);
/*!
* @brief Assert the reset control to part hardware.
*
* This function is to assert the reset control to part hardware. Responding part hardware would remain reset untill
* cleared by software.
*
* @param base DAC peripheral base address.
* @param mask The reset control mask, see to _dac_reset_control_t.
*/
static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask)
{
base->RCR |= mask;
}
/*!
* @brief Clear the reset control to part hardware.
*
* This function is to clear the reset control to part hardware. Responding part hardware would work after the reset
* control is cleared by software.
*
* @param base DAC peripheral base address.
* @param mask The reset control mask, see to _dac_reset_control_t.
*/
static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask)
{
base->RCR &= ~mask;
}
/*!
* @brief Enable the DAC hardware system or not.
*
* This function is to start the Programmable Reference Generator operation or not.
*
* @param base DAC peripheral base address.
* @param enable Assertion of indicated event.
*/
static inline void DAC_Enable(LPDAC_Type *base, bool enable)
{
if (enable)
{
base->GCR |= LPDAC_GCR_DACEN_MASK;
}
else
{
base->GCR &= ~LPDAC_GCR_DACEN_MASK;
}
}
/* @} */
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enable the interrupts.
*
* @param base DAC peripheral base address.
* @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable.
*/
static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask)
{
base->IER |= mask;
}
/*!
* @brief Disable the interrupts.
*
* @param base DAC peripheral base address.
* @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable.
*/
static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask)
{
base->IER &= ~mask;
}
/* @} */
/*!
* @name DMA control
* @{
*/
/*!
* @brief Enable the DMA switchers or not.
*
* @param base DAC peripheral base address.
* @param mask Mask value of indicated DMA requeset. See to _dac_dma_enable.
* @param enable Enable the DMA or not.
*/
static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable)
{
if (enable)
{
base->DER |= mask;
}
else
{
base->DER &= ~mask;
}
}
/* @} */
/*!
* @name Status flags
* @{
*/
/*!
* @brief Get status flags of DAC module.
*
* @param base DAC peripheral base address.
* @return Mask value of status flags. See to _dac_status_flags.
*/
static inline uint32_t DAC_GetStatusFlags(LPDAC_Type *base)
{
return base->FSR;
}
/*!
* @brief Clear status flags of DAC module.
*
* @param base DAC peripheral base address.
* @param flags Mask value of status flags to be cleared. See to _dac_status_flags.
*/
static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags)
{
base->FSR = flags;
}
/* @} */
/*!
* @name Functional feature
* @{
*/
/*!
* @brief Set data into the entry of FIFO buffer.
*
* @param base DAC peripheral base address.
* @param value Setting value into FIFO buffer.
*/
static inline void DAC_SetData(LPDAC_Type *base, uint32_t value)
{
base->DATA = LPDAC_DATA_DATA(value);
}
/*!
* @brief Get the value of the FIFO write pointer.
*
* @param base DAC peripheral base address.
* @return Current value of the FIFO write pointer.
*/
static inline uint32_t DAC_GetFIFOWritePointer(LPDAC_Type *base)
{
return (LPDAC_FPR_FIFO_WPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_WPT_SHIFT;
}
/*!
* @brief Get the value of the FIFO read pointer.
*
* @param base DAC peripheral base address.
* @return Current value of the FIFO read pointer.
*/
static inline uint32_t DAC_GetFIFOReadPointer(LPDAC_Type *base)
{
return (LPDAC_FPR_FIFO_RPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_RPT_SHIFT;
}
/*!
* @brief Do software trigger to FIFO when in software mode.
*
* @param base DAC peripheral base address.
*/
static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
{
base->TCR = LPDAC_TCR_SWTRG_MASK;
}
/* @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_DAC12_H_ */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.c
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/*!
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_dac14.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.dac14"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for DAC14 module.
*
* @param base DAC14 peripheral base address
*/
static uint32_t DAC14_GetInstance(HPDAC_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to DAC14 bases for each instance. */
static HPDAC_Type *const s_dac14Bases[] = HPDAC_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to DAC14 clocks for each instance. */
static const clock_ip_name_t s_dac14Clocks[] = HPDAC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t DAC14_GetInstance(HPDAC_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_dac14Bases); instance++)
{
if (s_dac14Bases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_dac14Bases));
return instance;
}
/*!
* brief Initialize the DAC14 module with common configuartion.
*
* The clock will be enabled in this function.
*
* param base DAC14 peripheral base address.
* param config Pointer to configuration structure.
*/
void DAC14_Init(HPDAC_Type *base, const dac14_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0U;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(s_dac14Clocks[DAC14_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Software reset and FIFO reset. */
DAC14_DoSoftwareReset(base);
DAC14_DoFIFOReset(base);
/* Opamp is used as buffer. */
if (config->enableOpampBuffer)
{
tmp32 |= HPDAC_GCR_BUF_EN_MASK;
}
/*Enable the DAC system.*/
if (config->enableDAC)
{
tmp32 |= HPDAC_GCR_DACEN_MASK;
}
if (config->WorkMode != kDAC14_BufferWorkMode)
{
/*Use software trigger source.*/
if (kDAC14_SoftwareTriggerSource == config->TriggerSource)
{
tmp32 |= HPDAC_GCR_TRGSEL_MASK;
}
if (config->WorkMode != kDAC14_SwingBackWorkMode)
{
if (config->WorkMode != kDAC14_PeriodTriggerAndSwingBackWorkMode)
{
/*Configurtion FIFO watermarklevel.*/
base->FCR = HPDAC_FCR_WML(config->fifoWatermarkLevel);
if (config->WorkMode == kDAC14_PeriodTriggerWorkMode)
{
tmp32 |= HPDAC_GCR_FIFOEN_MASK | HPDAC_GCR_PTGEN_MASK; /* Enable period trigger mode. */
/* Set trigger number and width. */
base->PCR = HPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) |
HPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth);
}
else
{
tmp32 |= HPDAC_GCR_FIFOEN_MASK; /* Enable FIFO mode.*/
}
}
else
{
/* Enable period trigger mode and swing back mode. */
tmp32 |= HPDAC_GCR_FIFOEN_MASK | HPDAC_GCR_PTGEN_MASK | HPDAC_GCR_SWMD_MASK;
/* Set trigger number and width. */
base->PCR = HPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) |
HPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth);
}
}
else
{
tmp32 |= HPDAC_GCR_FIFOEN_MASK | HPDAC_GCR_SWMD_MASK; /* Enable swing mode. */
}
}
base->GCR = tmp32;
}
/*!
* brief Get the default settings for initialization's configuration.
*
* This function initializes the user configuration structure to a default value. The default values are:
* code
config->fifoWatermarkLevel = 0U;
config->TriggerSource = kDAC14_HardwareTriggerSource;
config->WorkMode = kDAC14_BufferWorkMode;
config->enableOpampBuffer = false;
config->enableADC = false;
config->periodicTriggerNumber = 0U;
config->periodicTriggerWidth = 0U;
* endcode
*
* param config Pointer to configuration structure.
*/
void DAC14_GetDefaultConfig(dac14_config_t *config)
{
assert(config != NULL);
/* Initializes the configure structure to zero. */
(void)memset(config, 0, sizeof(*config));
config->fifoWatermarkLevel = 0U;
config->TriggerSource = kDAC14_HardwareTriggerSource;
config->WorkMode = kDAC14_BufferWorkMode;
config->enableOpampBuffer = false;
config->enableDAC = false;
config->periodicTriggerNumber = 0U;
config->periodicTriggerWidth = 0U;
}
/*!
* brief De-initialize the DAC14 module.
*
* The clock will be disabled in this function.
*
* param base DAC14 peripheral base address.
*/
void DAC14_Deinit(HPDAC_Type *base)
{
/* Disable the module. */
DAC14_Enable(base, false);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(s_dac14Clocks[DAC14_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h
+419
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/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_DAC14_H_
#define _FSL_DAC14_H_
#include "fsl_common.h"
/*!
* @addtogroup dac14
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief DAC14 driver version 2.0.0. */
#define FSL_DAC14_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*!
* @brief DAC14 interrupts enumeration.
*/
enum _dac14_interrupt_enable
{
kDAC14_PeriodTriggerCompleteInterruptEnable = HPDAC_IER_PTGCOCO_IE_MASK, /*!< Period trigger mode conversion complete interrupt enable */
kDAC14_FIFOUnderflowInterruptEnable = HPDAC_IER_UF_IE_MASK, /*!< FIFO underflow interrupt enable. */
kDAC14_FIFOOverflowInterruptEnable = HPDAC_IER_OF_IE_MASK, /*!< FIFO overflow interrupt enable. */
kDAC14_SwingBackInterruptEnable = HPDAC_IER_SWBK_IE_MASK, /*!< Swing back one cycle complete interrupt enable. */
kDAC14_FIFOWatermarkInterruptEnable = HPDAC_IER_WM_IE_MASK, /*!< FIFO watermark interrupt enable. */
kDAC14_FIFOEmptyInterruptEnable = HPDAC_IER_EMPTY_IE_MASK, /*!< FIFO empty interrupt enable. */
kDAC14_FIFOFullInterruptEnable = HPDAC_IER_FULL_IE_MASK, /*!< FIFO full interrupt enable. */
};
/*!
* @brief DAC14 DMA switchers.
*/
enum _dac14_dma_enable
{
kDAC14_FIFOWatermarkDMAEnable = HPDAC_DER_WM_DMAEN_MASK, /*!< FIFO watermark DMA enable. */
kDAC14_FIFOEmptyDMAEnable = HPDAC_DER_EMPTY_DMAEN_MASK, /*!< FIFO empty DMA enable. */
};
/*!
* @brief DAC14 status flags.
*/
enum _dac14_status_flags
{
kDAC14_PeriodTriggerCompleteFlag = HPDAC_FSR_PTGCOCO_MASK, /*!< Period trigger mode conversion complete flag. */
kDAC14_FIFOUnderflowFlag = HPDAC_FSR_UF_MASK, /*!< This flag means that there is a new trigger after the buffer is empty. The FIFO read pointer will not increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1
to it. */
kDAC14_FIFOOverflowFlag = HPDAC_FSR_OF_MASK, /*!< This flag indicates that data is intended to write into FIFO after the buffer is full. The writer pointer will
not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it.
*/
kDAC14_SwingBackCompleteFlag = HPDAC_FSR_SWBK_MASK, /*!< This flag indicates that the DAC has completed one period of conversion in swing back mode. It means that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For
example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the
read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is
cleared by writing a 1 to it. */
kDAC14_FIFOWaterMarkFlag = HPDAC_FSR_WM_MASK, /*!< This field is set if the remaining data in FIFO is less than or
equal to the setting value of wartermark. By writing data into FIFO by DMA or CPU, this flag is
cleared automatically when the data in FIFO is more than the setting value of watermark. */
kDAC14_FIFOEmptyFlag = HPDAC_FSR_EMPTY_MASK, /*!< FIFO empty flag, when CPU or DMA writes data to FIFO, this bit will automatically clear.*/
kDAC14_FIFOFullFlag = HPDAC_FSR_FULL_MASK, /*!< FIFO full flag, when software trigger and hardware trigger read FIFO automatically clears this flag.*/
};
/*!
* @brief DAC14 trigger source, include software and hardware.
*/
typedef enum _dac14_trigger_source
{
kDAC14_HardwareTriggerSource = 0U, /*!< Trigger source selection hardware . */
kDAC14_SoftwareTriggerSource = 1U, /*!< Trigger source selection software . */
} dac14_trigger_source_t;
/*!
* @brief DAC14 work mode.
*/
typedef enum _dac14_work_mode
{
kDAC14_BufferWorkMode = 0U, /*!< FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes
to buffer then goes to conversion. */
kDAC14_FIFOWorkMode = 1U, /*!< FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to
conversion. */
kDAC14_SwingBackWorkMode = 2U, /*!< In swing mode, the read pointer swings between the writer pointer and zero. That
is, the trigger increases the read pointer till reach the writer pointer and
decreases the read pointer till zero, and so on. The FIFO empty/full/watermark
flag will not update during swing back mode. */
kDAC14_PeriodTriggerWorkMode = 3U, /*!< In periodic trigger mode, user only needs to send the first trigger. Then after every [PTG_PERIOD+1]
RCLK cycles, DAC will be automatically triggered by internal trigger. There will be [PTG_NUM] internal
triggers, thus in total [PTG_NUM+1] conversions including the first trigger sent by user. User can
terminate the current conversion queue by clearing the GCR[PTGEN] bit. Then, after the current conversion
is completed, the conversion is terminated and the PTGCOCO flag is set. If PCR[PTG_NUM] is set to zero,
there will be infinite triggers following the first hardware/software trigger, until the GCR[PTGEN] is
cleared by software. In any case, the conversion can be terminated by FIFORST/SWRST. */
kDAC14_PeriodTriggerAndSwingBackWorkMode = 4U, /*!< Periodically trigger DAC and swing back. */
} dac14_work_mode_t;
/*!
* @brief DAC14 configuration structure.
*/
typedef struct _dac14_config
{
uint16_t periodicTriggerNumber; /*!< There will be 'periodicTriggerNumber' internal triggers following the first
hardware/software trigger. So there will be 'periodicTriggerNumber + 1'
conversions in total. If set to zero, there will be infinite triggers following
the first hw/sw trigger, until the GCR[PTGEN] is cleared. */
uint16_t periodicTriggerWidth; /*!< Control the periodic trigger frequency. There will be 'periodicTriggerWidth + 1'
RCLK cycles between each periodic trigger. The periodic trigger frequency should
be configured to not larger than the analog conversion speed. */
uint8_t fifoWatermarkLevel :5; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */
bool enableOpampBuffer :1; /*!< Opamp is used as buffer.*/
bool enableDAC :1; /*!< Enable the DAC system.*/
dac14_work_mode_t WorkMode; /*!< Select DAC work mode.*/
dac14_trigger_source_t TriggerSource; /*!< Select DAC trigger source. */
} dac14_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization And De-initialization
* @{
*/
/*!
* @brief Initialize the DAC14 module with common configuartion.
*
* The clock will be enabled in this function.
*
* @param base DAC14 peripheral base address.
* @param config Pointer to configuration structure.
*/
void DAC14_Init(HPDAC_Type *base, const dac14_config_t *config);
/*!
* @brief Get the default settings for initialization's configuration.
*
* This function initializes the user configuration structure to a default value. The default values are:
* @code
config->fifoWatermarkLevel = 0U;
config->TriggerSource = kDAC14_HardwareTriggerSource;
config->WorkMode = kDAC14_BufferWorkMode;
config->enableOpampBuffer = false;
config->enableADC = false;
config->periodicTriggerNumber = 0U;
config->periodicTriggerWidth = 0U;
* @endcode
*
* @param config Pointer to configuration structure.
*/
void DAC14_GetDefaultConfig(dac14_config_t *config);
/*!
* @brief De-initialize the DAC14 module.
*
* The clock will be disabled in this function.
*
* @param base DAC14 peripheral base address.
*/
void DAC14_Deinit(HPDAC_Type *base);
/*!
* @brief Do software reset .
*
* This function is resets all DAC registers and internal logic.
*
* @param base DAC14 peripheral base address.
*/
static inline void DAC14_DoSoftwareReset(HPDAC_Type *base)
{
base->RCR |= HPDAC_RCR_SWRST_MASK;
base->RCR &= ~HPDAC_RCR_SWRST_MASK;
}
/*!
* @brief Do FIFO reset.
*
* This function is resets the FIFO pointers and flags in FIFO Status.
*
* @param base DAC14 peripheral base address.
*/
static inline void DAC14_DoFIFOReset(HPDAC_Type *base)
{
base->RCR |= HPDAC_RCR_FIFORST_MASK;
base->RCR &= ~HPDAC_RCR_FIFORST_MASK;
}
/*!
* @brief Abort DAC14 period trigger conversion sequence.
*
* This function is write 0 to PTGEN to terminate the current conversion sequence.
*
* @param base DAC14 peripheral base address.
*/
static inline void DAC14_AbortPeriodTriggerConvSequence(HPDAC_Type *base)
{
base->GCR &= ~HPDAC_GCR_PTGEN_MASK;
}
/* @} */
/*!
* @name DAC Control Interface
* @{
*/
/*!
* @brief Enable the DAC14 system.
*
* @param base DAC14 peripheral base address.
* @param enable true to enable and false to disable.
*/
static inline void DAC14_Enable(HPDAC_Type *base, bool enable)
{
if (enable)
{
base->GCR |= HPDAC_GCR_DACEN_MASK;
}
else
{
base->GCR &= ~HPDAC_GCR_DACEN_MASK;
}
}
/* @} */
/*!
* @name Swing Back Mode Control Interface
* @{
*/
/*!
* @brief Enable swing back mode.
*
* @param base DAC14 peripheral base address.
* @param enable true to enable and false to disable.
*/
static inline void DAC14_EnableSwingBackMode(HPDAC_Type *base, bool enable)
{
if (enable)
{
base->GCR |= HPDAC_GCR_SWMD_MASK;
}
else
{
base->GCR &= ~HPDAC_GCR_SWMD_MASK;
}
}
/* @} */
/*!
* @name FIFO Mode Control Interface
* @{
*/
/*!
* @brief Enable FIFO mode.
*
* @param base DAC14 peripheral base address.
* @param enable true to enable and false to disable.
*/
static inline void DAC14_EnableFIFOMode(HPDAC_Type *base, bool enable)
{
if (enable)
{
base->GCR |= HPDAC_GCR_FIFOEN_MASK;
}
else
{
base->GCR &= ~HPDAC_GCR_FIFOEN_MASK;
}
}
/* @} */
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enable the interrupts.
*
* @param base DAC14 peripheral base address.
* @param mask Mask value of indicated interrupt events, please see @ref _dac14_interrupt_enable for details.
*/
static inline void DAC14_EnableInterrupts(HPDAC_Type *base, uint32_t mask)
{
base->IER |= mask;
}
/*!
* @brief Disable the interrupts.
*
* @param base DAC14 peripheral base address.
* @param mask Mask value of indicated interrupt events, please see @ref _dac14_interrupt_enable for details.
*/
static inline void DAC14_DisableInterrupts(HPDAC_Type *base, uint32_t mask)
{
base->IER &= ~mask;
}
/* @} */
/*!
* @name DMA Control Interface
* @{
*/
/*!
* @brief Enable the DMA switchers or not.
*
* @param base DAC14 peripheral base address.
* @param mask Mask value of indicated DMA requeset, please see @ref _dac14_dma_enable for details.
* @param enable true to enable and false to disable.
*/
static inline void DAC14_EnableDMA(HPDAC_Type *base, uint32_t mask, bool enable)
{
if (enable)
{
base->DER |= mask;
}
else
{
base->DER &= ~mask;
}
}
/* @} */
/*!
* @name Status
* @{
*/
/*!
* @brief Get status flags of DAC14 module.
*
* @param base DAC14 peripheral base address.
* @return Current DAC status flags.
*/
static inline uint32_t DAC14_GetStatusFlags(HPDAC_Type *base)
{
return base->FSR;
}
/*!
* @brief Clear status flags of DAC14 module.
*
* @param base DAC14 peripheral base address.
* @param flags Mask value of status flags to be cleared, please see @ref _dac14_status_flags for details.
*/
static inline void DAC14_ClearStatusFlags(HPDAC_Type *base, uint32_t flags)
{
base->FSR = flags;
}
/* @} */
/*!
* @name Functional Feature
* @{
*/
/*!
* @brief Set data into the entry of FIFO buffer.
*
* @param base DAC14 peripheral base address.
* @param value Setting value into FIFO buffer.
*/
static inline void DAC14_SetData(HPDAC_Type *base, uint32_t value)
{
base->DATA = HPDAC_DATA_DATA(value);
}
/*!
* @brief Get the value of the FIFO write pointer.
*
* @param base DAC14 peripheral base address.
* @return Current value of the FIFO write pointer.
*/
static inline uint32_t DAC14_GetFIFOWritePointer(HPDAC_Type *base)
{
return (HPDAC_FPR_FIFO_WPT_MASK & base->FPR) >> HPDAC_FPR_FIFO_WPT_SHIFT;
}
/*!
* @brief Get the value of the FIFO read pointer.
*
* @param base DAC14 peripheral base address.
* @return Current value of the FIFO read pointer.
*/
static inline uint32_t DAC14_GetFIFOReadPointer(HPDAC_Type *base)
{
return (HPDAC_FPR_FIFO_RPT_MASK & base->FPR) >> HPDAC_FPR_FIFO_RPT_SHIFT;
}
/*!
* @brief Do software trigger.
*
* @param base DAC14 peripheral base address.
*/
static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base)
{
base->TCR = HPDAC_TCR_SWTRG_MASK;
}
/* @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_DAC14_H_ */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.c
+1972
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File diff suppressed because it is too large Load Diff
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma.h
+1484
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File diff suppressed because it is too large Load Diff
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h
+220
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@@ -0,0 +1,220 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EDMA_CORE_H_
#define _FSL_EDMA_CORE_H_
#include "fsl_edma_soc.h"
/*!
* @addtogroup edma_core
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4
#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK
#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK
#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK
#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK
#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK
#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK
#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK
#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT
#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK
#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK
#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK
#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK
#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK
#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK
#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK
#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK
#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK
#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x)
#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X)
#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x)
#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x)
#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x)
#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x)
#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x)
#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x)
#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x)
#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK
#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT
#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK
#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT
#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK
#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT
#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x)
#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \
(!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4))
#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK
#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK
#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK
#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK
#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK
#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK
#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK
#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT
#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK
#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK
#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK
#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK
#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK
#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK
#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK
#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK
#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x)
#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X)
#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x)
#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x)
#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x)
#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x)
#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x)
#define DMA_CH_MUX_SOURCE(x) DMA_CH_MUX_SRC(x)
#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \
(!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3))
#define DMA_CSR_INTMAJOR_MASK DMA4_CSR_INTMAJOR_MASK
#define DMA_CSR_INTHALF_MASK DMA4_CSR_INTHALF_MASK
#define DMA_CSR_DREQ_MASK DMA4_CSR_DREQ_MASK
#define DMA_CSR_ESG_MASK DMA4_CSR_ESG_MASK
#define DMA_CSR_START_MASK DMA4_CSR_START_MASK
#define DMA_CITER_ELINKNO_CITER_MASK DMA4_CITER_ELINKNO_CITER_MASK
#define DMA_BITER_ELINKNO_BITER_MASK DMA4_BITER_ELINKNO_BITER_MASK
#define DMA_CITER_ELINKNO_CITER_SHIFT DMA4_CITER_ELINKNO_CITER_SHIFT
#define DMA_CITER_ELINKYES_CITER_MASK DMA4_CITER_ELINKYES_CITER_MASK
#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT
#define DMA_ATTR_SMOD_MASK DMA4_ATTR_SMOD_MASK
#define DMA_ATTR_DMOD_MASK DMA4_ATTR_DMOD_MASK
#define DMA_CITER_ELINKNO_ELINK_MASK DMA4_CITER_ELINKNO_ELINK_MASK
#define DMA_CSR_MAJORELINK_MASK DMA4_CSR_MAJORELINK_MASK
#define DMA_BITER_ELINKYES_ELINK_MASK DMA4_BITER_ELINKYES_ELINK_MASK
#define DMA_CITER_ELINKYES_ELINK_MASK DMA4_CITER_ELINKYES_ELINK_MASK
#define DMA_CSR_MAJORLINKCH_MASK DMA4_CSR_MAJORLINKCH_MASK
#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK
#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK
#define DMA_ATTR_DMOD(x) DMA4_ATTR_DMOD(x)
#define DMA_ATTR_SMOD(X) DMA4_ATTR_SMOD(X)
#define DMA_BITER_ELINKYES_LINKCH(x) DMA4_BITER_ELINKYES_LINKCH(x)
#define DMA_CITER_ELINKYES_LINKCH(x) DMA4_CITER_ELINKYES_LINKCH(x)
#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA4_NBYTES_MLOFFYES_MLOFF(x)
#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA4_NBYTES_MLOFFYES_DMLOE(x)
#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA4_NBYTES_MLOFFYES_SMLOE(x)
#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA4_NBYTES_MLOFFNO_NBYTES(x)
#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA4_NBYTES_MLOFFYES_NBYTES(x)
#define DMA_ATTR_DSIZE(x) DMA4_ATTR_DSIZE(x)
#define DMA_ATTR_SSIZE(x) DMA4_ATTR_SSIZE(x)
#define DMA_CSR_DREQ(x) DMA4_CSR_DREQ(x)
#define DMA_CSR_MAJORLINKCH(x) DMA4_CSR_MAJORLINKCH(x)
#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x)
#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x)
#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK
#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT
#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK
#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT
#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK
#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT
#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x)
#define DMA_CH_CSR_DONE_MASK DMA4_CH_CSR_DONE_MASK
#define DMA_CH_CSR_ERQ_MASK DMA4_CH_CSR_ERQ_MASK
#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
/*! intentional empty */
#endif
/*!@brief edma core channel struture definition */
typedef struct _edma_core_mp
{
__IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
__IO uint32_t MP_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
} edma_core_mp_t;
/*!@brief edma core channel struture definition */
typedef struct _edma_core_channel
{
__IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
__IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
__IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
__IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
__IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
__IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
__IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
} edma_core_channel_t;
/*!@brief edma core TCD struture definition */
typedef struct _edma_core_tcd
{
__IO uint32_t SADDR; /*!< SADDR register, used to save source address */
__IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */
__IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */
__IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */
__IO uint32_t SLAST; /*!< SLAST register */
__IO uint32_t DADDR; /*!< DADDR register, used for destination address */
__IO uint16_t DOFF; /*!< DOFF register, used for destination offset */
__IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
__IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
__IO uint16_t CSR; /*!< CSR register, for TCD control status */
__IO uint16_t BITER; /*!< BITER register, begin minor loop count. */
} edma_core_tcd_t;
/*!@brief EDMA typedef */
typedef edma_core_channel_t EDMA_ChannelType;
typedef edma_core_tcd_t EDMA_TCDType;
typedef void EDMA_Type;
/*!@brief EDMA base address convert macro */
#define EDMA_BASE(base)
#define EDMA_CHANNEL_BASE(base, channel) \
((edma_core_channel_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base)))
#define EDMA_TCD_BASE(base, channel) \
((edma_core_tcd_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U))
#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)base))
/*******************************************************************************
* API
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/*!
* @}
*/
#endif /* _FSL_EDMA_CORE_H_ */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.c
+377
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@@ -0,0 +1,377 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_edma_soc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.edma_soc"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
extern void EDMA_0_CH0_DriverIRQHandler(void);
extern void EDMA_0_CH1_DriverIRQHandler(void);
extern void EDMA_0_CH2_DriverIRQHandler(void);
extern void EDMA_0_CH3_DriverIRQHandler(void);
extern void EDMA_0_CH4_DriverIRQHandler(void);
extern void EDMA_0_CH5_DriverIRQHandler(void);
extern void EDMA_0_CH6_DriverIRQHandler(void);
extern void EDMA_0_CH7_DriverIRQHandler(void);
extern void EDMA_0_CH8_DriverIRQHandler(void);
extern void EDMA_0_CH9_DriverIRQHandler(void);
extern void EDMA_0_CH10_DriverIRQHandler(void);
extern void EDMA_0_CH11_DriverIRQHandler(void);
extern void EDMA_0_CH12_DriverIRQHandler(void);
extern void EDMA_0_CH13_DriverIRQHandler(void);
extern void EDMA_0_CH14_DriverIRQHandler(void);
extern void EDMA_0_CH15_DriverIRQHandler(void);
extern void EDMA_1_CH0_DriverIRQHandler(void);
extern void EDMA_1_CH1_DriverIRQHandler(void);
extern void EDMA_1_CH2_DriverIRQHandler(void);
extern void EDMA_1_CH3_DriverIRQHandler(void);
extern void EDMA_1_CH4_DriverIRQHandler(void);
extern void EDMA_1_CH5_DriverIRQHandler(void);
extern void EDMA_1_CH6_DriverIRQHandler(void);
extern void EDMA_1_CH7_DriverIRQHandler(void);
extern void EDMA_1_CH8_DriverIRQHandler(void);
extern void EDMA_1_CH9_DriverIRQHandler(void);
extern void EDMA_1_CH10_DriverIRQHandler(void);
extern void EDMA_1_CH11_DriverIRQHandler(void);
extern void EDMA_1_CH12_DriverIRQHandler(void);
extern void EDMA_1_CH13_DriverIRQHandler(void);
extern void EDMA_1_CH14_DriverIRQHandler(void);
extern void EDMA_1_CH15_DriverIRQHandler(void);
extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel);
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief DMA instance 0, channel 0 IRQ handler.
*
*/
void EDMA_0_CH0_DriverIRQHandler(void)
{
/* Instance 0 channel 0 */
EDMA_DriverIRQHandler(0U, 0U);
}
/*!
* brief DMA instance 0, channel 1 IRQ handler.
*
*/
void EDMA_0_CH1_DriverIRQHandler(void)
{
/* Instance 0 channel 1 */
EDMA_DriverIRQHandler(0U, 1U);
}
/*!
* brief DMA instance 0, channel 2 IRQ handler.
*
*/
void EDMA_0_CH2_DriverIRQHandler(void)
{
/* Instance 0 channel 2 */
EDMA_DriverIRQHandler(0U, 2U);
}
/*!
* brief DMA instance 0, channel 3 IRQ handler.
*
*/
void EDMA_0_CH3_DriverIRQHandler(void)
{
/* Instance 0 channel 3 */
EDMA_DriverIRQHandler(0U, 3U);
}
/*!
* brief DMA instance 0, channel 4 IRQ handler.
*
*/
void EDMA_0_CH4_DriverIRQHandler(void)
{
/* Instance 0 channel 4 */
EDMA_DriverIRQHandler(0U, 4U);
}
/*!
* brief DMA instance 0, channel 5 IRQ handler.
*
*/
void EDMA_0_CH5_DriverIRQHandler(void)
{
/* Instance 0 channel 5 */
EDMA_DriverIRQHandler(0U, 5U);
}
/*!
* brief DMA instance 0, channel 6 IRQ handler.
*
*/
void EDMA_0_CH6_DriverIRQHandler(void)
{
/* Instance 0 channel 6 */
EDMA_DriverIRQHandler(0U, 6U);
}
/*!
* brief DMA instance 0, channel 7 IRQ handler.
*
*/
void EDMA_0_CH7_DriverIRQHandler(void)
{
/* Instance 0 channel 7 */
EDMA_DriverIRQHandler(0U, 7U);
}
/*!
* brief DMA instance 0, channel 8 IRQ handler.
*
*/
void EDMA_0_CH8_DriverIRQHandler(void)
{
/* Instance 0 channel 8 */
EDMA_DriverIRQHandler(0U, 8U);
}
/*!
* brief DMA instance 0, channel 9 IRQ handler.
*
*/
void EDMA_0_CH9_DriverIRQHandler(void)
{
/* Instance 0 channel 9 */
EDMA_DriverIRQHandler(0U, 9U);
}
/*!
* brief DMA instance 0, channel 10 IRQ handler.
*
*/
void EDMA_0_CH10_DriverIRQHandler(void)
{
/* Instance 0 channel 10 */
EDMA_DriverIRQHandler(0U, 10U);
}
/*!
* brief DMA instance 0, channel 11 IRQ handler.
*
*/
void EDMA_0_CH11_DriverIRQHandler(void)
{
/* Instance 0 channel 11 */
EDMA_DriverIRQHandler(0U, 11U);
}
/*!
* brief DMA instance 0, channel 12 IRQ handler.
*
*/
void EDMA_0_CH12_DriverIRQHandler(void)
{
/* Instance 0 channel 12 */
EDMA_DriverIRQHandler(0U, 12U);
}
/*!
* brief DMA instance 0, channel 13 IRQ handler.
*
*/
void EDMA_0_CH13_DriverIRQHandler(void)
{
/* Instance 0 channel 13 */
EDMA_DriverIRQHandler(0U, 13U);
}
/*!
* brief DMA instance 0, channel 14 IRQ handler.
*
*/
void EDMA_0_CH14_DriverIRQHandler(void)
{
/* Instance 0 channel 14 */
EDMA_DriverIRQHandler(0U, 14U);
}
/*!
* brief DMA instance 0, channel 15 IRQ handler.
*
*/
void EDMA_0_CH15_DriverIRQHandler(void)
{
/* Instance 0 channel 15 */
EDMA_DriverIRQHandler(0U, 15U);
}
/*!
* brief DMA instance 1, channel 0 IRQ handler.
*
*/
void EDMA_1_CH0_DriverIRQHandler(void)
{
/* Instance 1 channel 0 */
EDMA_DriverIRQHandler(1U, 0U);
}
/*!
* brief DMA instance 1, channel 1 IRQ handler.
*
*/
void EDMA_1_CH1_DriverIRQHandler(void)
{
/* Instance 1 channel 1 */
EDMA_DriverIRQHandler(1U, 1U);
}
/*!
* brief DMA instance 1, channel 2 IRQ handler.
*
*/
void EDMA_1_CH2_DriverIRQHandler(void)
{
/* Instance 1 channel 2 */
EDMA_DriverIRQHandler(1U, 2U);
}
/*!
* brief DMA instance 1, channel 3 IRQ handler.
*
*/
void EDMA_1_CH3_DriverIRQHandler(void)
{
/* Instance 1 channel 3 */
EDMA_DriverIRQHandler(1U, 3U);
}
/*!
* brief DMA instance 1, channel 4 IRQ handler.
*
*/
void EDMA_1_CH4_DriverIRQHandler(void)
{
/* Instance 1 channel 4 */
EDMA_DriverIRQHandler(1U, 4U);
}
/*!
* brief DMA instance 1, channel 5 IRQ handler.
*
*/
void EDMA_1_CH5_DriverIRQHandler(void)
{
/* Instance 1 channel 5 */
EDMA_DriverIRQHandler(1U, 5U);
}
/*!
* brief DMA instance 1, channel 6 IRQ handler.
*
*/
void EDMA_1_CH6_DriverIRQHandler(void)
{
/* Instance 1 channel 6 */
EDMA_DriverIRQHandler(1U, 6U);
}
/*!
* brief DMA instance 1, channel 7 IRQ handler.
*
*/
void EDMA_1_CH7_DriverIRQHandler(void)
{
/* Instance 1 channel 7 */
EDMA_DriverIRQHandler(1U, 7U);
}
/*!
* brief DMA instance 1, channel 8 IRQ handler.
*
*/
void EDMA_1_CH8_DriverIRQHandler(void)
{
/* Instance 1 channel 8 */
EDMA_DriverIRQHandler(1U, 8U);
}
/*!
* brief DMA instance 1, channel 9 IRQ handler.
*
*/
void EDMA_1_CH9_DriverIRQHandler(void)
{
/* Instance 1 channel 9 */
EDMA_DriverIRQHandler(1U, 9U);
}
/*!
* brief DMA instance 1, channel 10 IRQ handler.
*
*/
void EDMA_1_CH10_DriverIRQHandler(void)
{
/* Instance 1 channel 10 */
EDMA_DriverIRQHandler(1U, 10U);
}
/*!
* brief DMA instance 1, channel 11 IRQ handler.
*
*/
void EDMA_1_CH11_DriverIRQHandler(void)
{
/* Instance 1 channel 11 */
EDMA_DriverIRQHandler(1U, 11U);
}
/*!
* brief DMA instance 1, channel 12 IRQ handler.
*
*/
void EDMA_1_CH12_DriverIRQHandler(void)
{
/* Instance 1 channel 12 */
EDMA_DriverIRQHandler(1U, 12U);
}
/*!
* brief DMA instance 1, channel 13 IRQ handler.
*
*/
void EDMA_1_CH13_DriverIRQHandler(void)
{
/* Instance 1 channel 13 */
EDMA_DriverIRQHandler(1U, 13U);
}
/*!
* brief DMA instance 1, channel 14 IRQ handler.
*
*/
void EDMA_1_CH14_DriverIRQHandler(void)
{
/* Instance 1 channel 14 */
EDMA_DriverIRQHandler(1U, 14U);
}
/*!
* brief DMA instance 1, channel 15 IRQ handler.
*
*/
void EDMA_1_CH15_DriverIRQHandler(void)
{
/* Instance 1 channel 15 */
EDMA_DriverIRQHandler(1U, 15U);
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h
+213
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@@ -0,0 +1,213 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EDMA_SOC_H_
#define _FSL_EDMA_SOC_H_
#include "fsl_common.h"
/*!
* @addtogroup edma_soc
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Driver version 1.0.0. */
#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
/*@}*/
/*!@brief DMA IP version */
#define FSL_EDMA_SOC_IP_DMA3 (1)
#define FSL_EDMA_SOC_IP_DMA4 (0)
/*!@brief DMA base table */
#define EDMA_BASE_PTRS \
{ \
DMA0, DMA1 \
}
#define EDMA_CHN_IRQS \
{ \
{EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, \
EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, \
EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn}, \
{ \
EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, \
EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, EDMA_1_CH8_IRQn, EDMA_1_CH9_IRQn, EDMA_1_CH10_IRQn, \
EDMA_1_CH11_IRQn, EDMA_1_CH12_IRQn, EDMA_1_CH13_IRQn, EDMA_1_CH14_IRQn, EDMA_1_CH15_IRQn \
} \
}
/*!@brief dma request source */
typedef enum _dma_request_source
{
kDmaRequestDisabled = 0U, /**< DSisabled*/
kDmaRequestMuxFlexSpi0Rx = 1 | 0x100U, /**< FlexSPI0 Receive event */
kDmaRequestMuxFlexSpi0Tx = 2 | 0x100U, /**< FlexSPI0 Transmit event */
kDmaRequestMuxPinInt0 = 3 | 0x100U, /**< PinInt0 */
kDmaRequestMuxPinInt1 = 4 | 0x100U, /**< PinInt1 */
kDmaRequestMuxPinInt2 = 5 | 0x100U, /**< PinInt2 */
kDmaRequestMuxPinInt3 = 6 | 0x100U, /**< PinInt3 */
kDmaRequestMuxCtimer0M0 = 7 | 0x100U, /**< Ctimer0_M0 */
kDmaRequestMuxCtimer0M1 = 8 | 0x100U, /**< Ctimer0_M1 */
kDmaRequestMuxCtimer1M0 = 9 | 0x100U, /**< Ctimer1_M0 */
kDmaRequestMuxCtimer1M1 = 10 | 0x100U, /**< Ctimer1_M1 */
kDmaRequestMuxCtimer2M0 = 11 | 0x100U, /**< Ctimer2_M0 */
kDmaRequestMuxCtimer2M1 = 12 | 0x100U, /**< Ctimer2_M1 */
kDmaRequestMuxCtimer3M0 = 13 | 0x100U, /**< Ctimer3_M0 */
kDmaRequestMuxCtimer3M1 = 14 | 0x100U, /**< Ctimer3_M1 */
kDmaRequestMuxCtimer4M0 = 15 | 0x100U, /**< Ctimer4_M0 */
kDmaRequestMuxCtimer5M1 = 16 | 0x100U, /**< Ctimer4_M1 */
kDmaRequestMuxWuu0 = 17 | 0x100U, /**< Wake up event */
kDmaRequestMuxMicfil0FifoRequest = 18 | 0x100U, /**< MICFIL0 FIFO_request */
kDmaRequestMuxSct0Dma0 = 19 | 0x100U, /**< SCT0 DMA0 */
kDmaRequestMuxSct0Dma1 = 20 | 0x100U, /**< SCT0 DMA1 */
kDmaRequestMuxAdc0FifoARequest = 21 | 0x100U, /**< ADC0 FIFO A request */
kDmaRequestMuxAdc0FifoBRequest = 22 | 0x100U, /**< ADC0 FIFO B request */
kDmaRequestMuxAdc1FifoARequest = 23 | 0x100U, /**< ADC1 FIFO A request */
kDmaRequestMuxAdc1FifoBRequest = 24 | 0x100U, /**< ADC1 FIFO B request */
kDmaRequestMuxDac0FifoRequest = 25 | 0x100U, /**< DAC0 FIFO_request */
kDmaRequestMuxDac1FifoRequest = 26 | 0x100U, /**< DAC1 FIFO_request */
kDmaRequestMuxHpDac0FifoRequest = 27 | 0x100U, /**< HP DAC0 FIFO_request */
kDmaRequestMuxHsCmp0DmaRequest = 28 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxHsCmp1DmaRequest = 29 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxHsCmp2DmaRequest = 30 | 0x100U, /**< HS CMP0 DMA_request */
kDmaRequestMuxEvtg0Out0A = 31 | 0x100U, /**< EVTG0 OUT0A */
kDmaRequestMuxEvtg0Out0B = 32 | 0x100U, /**< EVTG0 OUT0B */
kDmaRequestMuxEvtg0Out1A = 33 | 0x100U, /**< EVTG0 OUT1A */
kDmaRequestMuxEvtg0Out1B = 34 | 0x100U, /**< EVTG0 OUT1B */
kDmaRequestMuxEvtg0Out2A = 35 | 0x100U, /**< EVTG0 OUT2A */
kDmaRequestMuxEvtg0Out2B = 36 | 0x100U, /**< EVTG0 OUT2B */
kDmaRequestMuxEvtg0Out3A = 37 | 0x100U, /**< EVTG0 OUT3A */
kDmaRequestMuxEvtg0Out3B = 38 | 0x100U, /**< EVTG0 OUT3B */
kDmaRequestMuxFlexPwm0ReqCapt0 = 39 | 0x100U, /**< FlexPWM0 Req_capt0 */
kDmaRequestMuxFlexPwm0ReqCapt1 = 40 | 0x100U, /**< FlexPWM0 Req_capt1 */
kDmaRequestMuxFlexPwm0ReqCapt2 = 41 | 0x100U, /**< FlexPWM0 Req_capt2 */
kDmaRequestMuxFlexPwm0ReqCapt3 = 42 | 0x100U, /**< FlexPWM0 Req_capt3 */
kDmaRequestMuxFlexPwm0ReqVal0 = 43 | 0x100U, /**< FlexPWM0 Req_val0 */
kDmaRequestMuxFlexPwm0ReqVal1 = 44 | 0x100U, /**< FlexPWM0 Req_val1 */
kDmaRequestMuxFlexPwm0ReqVal2 = 45 | 0x100U, /**< FlexPWM0 Req_val2 */
kDmaRequestMuxFlexPwm0ReqVal3 = 46 | 0x100U, /**< FlexPWM0 Req_val3 */
kDmaRequestMuxFlexPwm1ReqCapt0 = 47 | 0x100U, /**< FlexPWM1 Req_capt0 */
kDmaRequestMuxFlexPwm1ReqCapt1 = 48 | 0x100U, /**< FlexPWM1 Req_capt1 */
kDmaRequestMuxFlexPwm1ReqCapt2 = 49 | 0x100U, /**< FlexPWM1 Req_capt2 */
kDmaRequestMuxFlexPwm1ReqCapt3 = 50 | 0x100U, /**< FlexPWM1 Req_capt3 */
kDmaRequestMuxFlexPwm1ReqVal0 = 51 | 0x100U, /**< FlexPWM1 Req_val0 */
kDmaRequestMuxFlexPwm1ReqVal1 = 52 | 0x100U, /**< FlexPWM1 Req_val1 */
kDmaRequestMuxFlexPwm1ReqVal2 = 53 | 0x100U, /**< FlexPWM1 Req_val2 */
kDmaRequestMuxFlexPwm1ReqVal3 = 54 | 0x100U, /**< FlexPWM1 Req_val3 */
kDmaRequestMuxItrc0TmprOut0 = 55 | 0x100U, /**< ITRC0 TMPR_OUT0 */
kDmaRequestMuxItrc0TmprOut1 = 56 | 0x100U, /**< ITRC0 TMPR_OUT1 */
kDmaRequestMuxLptmr0 = 57 | 0x100U, /**< LPTMR0 Counter match event */
kDmaRequestMuxLptmr1 = 58 | 0x100U, /**< LPTMR1 Counter match event */
kDmaRequestMuxFlexCan0DmaRequest = 59 | 0x100U, /**< FlexCAN0 DMA request */
kDmaRequestMuxFlexCan1DmaRequest = 60 | 0x100U, /**< FlexCAN1 DMA request */
kDmaRequestMuxFlexIO0ShiftRegister0Request = 61 | 0x100U, /**< FlexIO0 Shift Register 0 request */
kDmaRequestMuxFlexIO0ShiftRegister1Request = 62 | 0x100U, /**< FlexIO0 Shift Register 1 request */
kDmaRequestMuxFlexIO0ShiftRegister2Request = 63 | 0x100U, /**< FlexIO0 Shift Register 2 request */
kDmaRequestMuxFlexIO0ShiftRegister3Request = 64 | 0x100U, /**< FlexIO0 Shift Register 3 request */
kDmaRequestMuxFlexIO0ShiftRegister4Request = 65 | 0x100U, /**< FlexIO0 Shift Register 4 request */
kDmaRequestMuxFlexIO0ShiftRegister5Request = 66 | 0x100U, /**< FlexIO0 Shift Register 5 request */
kDmaRequestMuxFlexIO0ShiftRegister6Request = 67 | 0x100U, /**< FlexIO0 Shift Register 6 request */
kDmaRequestMuxFlexIO0ShiftRegister7Request = 68 | 0x100U, /**< FlexIO0 Shift Register 7 request */
kDmaRequestMuxLpFlexcomm0Rx = 69 | 0x100U, /**< LP_FLEXCOMM0 Receive request */
kDmaRequestMuxLpFlexcomm0Tx = 70 | 0x100U, /**< LP_FLEXCOMM0 Transmit request */
kDmaRequestMuxLpFlexcomm1Rx = 71 | 0x100U, /**< LP_FLEXCOMM1 Receive request */
kDmaRequestMuxLpFlexcomm1Tx = 72 | 0x100U, /**< LP_FLEXCOMM1 Transmit request */
kDmaRequestMuxLpFlexcomm2Rx = 73 | 0x100U, /**< LP_FLEXCOMM2 Receive request */
kDmaRequestMuxLpFlexcomm2Tx = 74 | 0x100U, /**< LP_FLEXCOMM2 Transmit request */
kDmaRequestMuxLpFlexcomm3Rx = 75 | 0x100U, /**< LP_FLEXCOMM3 Receive request */
kDmaRequestMuxLpFlexcomm3Tx = 76 | 0x100U, /**< LP_FLEXCOMM3 Transmit request */
kDmaRequestMuxLpFlexcomm4Rx = 77 | 0x100U, /**< LP_FLEXCOMM4 Receive request */
kDmaRequestMuxLpFlexcomm4Tx = 78 | 0x100U, /**< LP_FLEXCOMM4 Transmit request */
kDmaRequestMuxLpFlexcomm5Rx = 79 | 0x100U, /**< LP_FLEXCOMM5 Receive request */
kDmaRequestMuxLpFlexcomm5Tx = 80 | 0x100U, /**< LP_FLEXCOMM5 Transmit request */
kDmaRequestMuxLpFlexcomm6Rx = 81 | 0x100U, /**< LP_FLEXCOMM6 Receive request */
kDmaRequestMuxLpFlexcomm6Tx = 82 | 0x100U, /**< LP_FLEXCOMM6 Transmit request */
kDmaRequestMuxLpFlexcomm7Rx = 83 | 0x100U, /**< LP_FLEXCOMM7 Receive request */
kDmaRequestMuxLpFlexcomm7Tx = 84 | 0x100U, /**< LP_FLEXCOMM7 Transmit request */
kDmaRequestMuxLpFlexcomm8Rx = 85 | 0x100U, /**< LP_FLEXCOMM8 Receive request */
kDmaRequestMuxLpFlexcomm8Tx = 86 | 0x100U, /**< LP_FLEXCOMM8 Transmit request */
kDmaRequestMuxLpFlexcomm9Rx = 87 | 0x100U, /**< LP_FLEXCOMM9 Receive request */
kDmaRequestMuxLpFlexcomm9Tx = 88 | 0x100U, /**< LP_FLEXCOMM9 Transmit request */
kDmaRequestMuxESpi0Ch0 = 89 | 0x100U, /**< eSPI0 channel 0 */
kDmaRequestMuxESpi0Ch1 = 90 | 0x100U, /**< eSPI0 channel 1 */
kDmaRequestMuxEmvSim0Rx = 91 | 0x100U, /**< EMVSIM0 Receive request */
kDmaRequestMuxEmvSim0Tx = 92 | 0x100U, /**< EMVSIM0 Transmit request */
kDmaRequestMuxEmvSim1Rx = 93 | 0x100U, /**< EMVSIM1 Receive request */
kDmaRequestMuxEmvSim1Tx = 94 | 0x100U, /**< EMVSIM1 Transmit request */
kDmaRequestMuxI3c0Rx = 95 | 0x100U, /**< I3C0 Receive request */
kDmaRequestMuxI3c0Tx = 96 | 0x100U, /**< I3C0 Transmit request */
kDmaRequestMuxI3c1Rx = 97 | 0x100U, /**< I3C0 Receive request */
kDmaRequestMuxI3c1Tx = 98 | 0x100U, /**< I3C0 Transmit request */
kDmaRequestMuxSai0Rx = 99 | 0x100U, /**< SAI0 Receive request */
kDmaRequestMuxSai0Tx = 100 | 0x100U, /**< SAI0 Receive request */
kDmaRequestMuxSai1Rx = 101 | 0x100U, /**< SAI1 Receive request */
kDmaRequestMuxSai1Tx = 102 | 0x100U, /**< SAI1 Receive request */
kDmaRequestMuxSinc0IpdReqSincAlt0 = 103 | 0x100U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */
kDmaRequestMuxSinc0IpdReqSincAlt1 = 104 | 0x100U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */
kDmaRequestMuxSinc0IpdReqSincAlt2 = 105 | 0x100U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */
kDmaRequestMuxSinc0IpdReqSincAlt3 = 106 | 0x100U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */
kDmaRequestMuxSinc0IpdReqSincAlt4 = 107 | 0x100U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */
kDmaRequestMuxGpio0PinEventRequest0 = 108 | 0x100U, /**< GPIO0 Pin event request 0 */
kDmaRequestMuxGpio0PinEventRequest1 = 109 | 0x100U, /**< GPIO0 Pin event request 1 */
kDmaRequestMuxGpio1PinEventRequest0 = 110 | 0x100U, /**< GPIO1 Pin event request 0 */
kDmaRequestMuxGpio1PinEventRequest1 = 111 | 0x100U, /**< GPIO1 Pin event request 1 */
kDmaRequestMuxGpio2PinEventRequest0 = 112 | 0x100U, /**< GPIO2 Pin event request 0 */
kDmaRequestMuxGpio2PinEventRequest1 = 113 | 0x100U, /**< GPIO2 Pin event request 1 */
kDmaRequestMuxGpio3PinEventRequest0 = 114 | 0x100U, /**< GPIO3 Pin event request 0 */
kDmaRequestMuxGpio3PinEventRequest1 = 115 | 0x100U, /**< GPIO3 Pin event request 1 */
kDmaRequestMuxGpio4PinEventRequest0 = 116 | 0x100U, /**< GPIO4 Pin event request 0 */
kDmaRequestMuxGpio4PinEventRequest1 = 117 | 0x100U, /**< GPIO4 Pin event request 1 */
kDmaRequestMuxGpio5PinEventRequest0 = 118 | 0x100U, /**< GPIO5 Pin event request 0 */
kDmaRequestMuxGpio5PinEventRequest1 = 119 | 0x100U, /**< GPIO5 Pin event request 1 */
kDmaRequestMuxTsi0EndOfScan = 120 | 0x100U, /**< TSI0 End of Scan */
kDmaRequestMuxTsi0OutOfRange = 121 | 0x100U, /**< TSI0 Out of Range */
} dma_request_source_t;
/*!< Verify dma base and request source */
#define EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source) ((source)&0x100U)
#define FSL_FEATURE_EDMA_MODULE_CHANNEL(base) (16U)
#define FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL (16)
#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
#define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE (0)
#define FSL_FEATURE_EDMA_MODULE_COUNT (2)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE (0)
#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_MATTR(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SIGN_EXTENSION(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SWAP(base) (0U)
#define FSL_FEATURE_EDMA_MODULE_SUPPORT_INSTR(base) (0U)
/*!@brief EDMA base address convert macro */
#define EDMA_CHANNEL_OFFSET 0x1000U
#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)
/*******************************************************************************
* API
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/*!
* @}
*/
#endif /* _FSL_EDMA_SOC_H_ */
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c
+282
View File
@@ -0,0 +1,282 @@
/*
* Copyright 2022 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_eim.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.eim"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to EIM bases for each instance. */
static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to EIM clocks for each instance. */
static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t EIM_GetInstance(EIM_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_eimBases); instance++)
{
if (s_eimBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_eimBases));
return instance;
}
/*!
* brief EIM module initialization function.
*
* param base EIM base address.
*/
void EIM_Init(EIM_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate EIM clock. */
CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
base->EIMCR = 0x00U;
base->EICHEN = 0x00U;
}
/*!
* brief Deinitializes the EIM.
*
*/
void EIM_Deinit(EIM_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate EIM clock. */
CLOCK_DisableClock(s_eimClocks[EIM_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
{
switch (channel)
{
case kEIM_MemoryChannelRAMX:
base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMA:
base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMB:
base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMC:
base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMD:
base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAME:
base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelRAMF:
base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelLPCACRAM:
base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask);
break;
case kEIM_MemoryChannelPKCRAM:
base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask);
break;
default:
assert(NULL);
break;
}
}
uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
{
uint8_t mask = 0x00U;
switch (channel)
{
case kEIM_MemoryChannelRAMX:
mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMA:
mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMB:
mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMC:
mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMD:
mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAME:
mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelRAMF:
mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelLPCACRAM:
mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT);
break;
case kEIM_MemoryChannelPKCRAM:
mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >>
EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT);
break;
default:
assert(NULL);
break;
}
return mask;
}
void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
{
switch (channel)
{
case kEIM_MemoryChannelRAMX:
base->EICHD0_WORD1 = mask;
break;
case kEIM_MemoryChannelRAMA:
base->EICHD1_WORD1 = mask;
break;
case kEIM_MemoryChannelRAMB:
base->EICHD2_WORD1 = mask;
break;
case kEIM_MemoryChannelRAMC:
base->EICHD3_WORD1 = mask;
break;
case kEIM_MemoryChannelRAMD:
base->EICHD4_WORD1 = mask;
break;
case kEIM_MemoryChannelRAME:
base->EICHD5_WORD1 = mask;
break;
case kEIM_MemoryChannelRAMF:
base->EICHD6_WORD1 = mask;
break;
case kEIM_MemoryChannelLPCACRAM:
base->EICHD7_WORD1 = mask;
break;
case kEIM_MemoryChannelPKCRAM:
base->EICHD8_WORD1 = mask;
break;
default:
assert(NULL);
break;
}
}
uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel)
{
uint32_t mask = 0x00U;
switch (channel)
{
case kEIM_MemoryChannelRAMX:
mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMA:
mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMB:
mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMC:
mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMD:
mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAME:
mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelRAMF:
mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelLPCACRAM:
mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT;
break;
case kEIM_MemoryChannelPKCRAM:
mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT;
break;
default:
assert(NULL);
break;
}
return mask;
}
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h
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/*
* Copyright 2022 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_EIM_H_
#define _FSL_EIM_H_
#include "fsl_common.h"
/*!
* @addtogroup eim
* @{
*/
/******************************************************************************
* Definitions.
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Driver version. */
#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
/*@}*/
/*******************************************************************************
* APIs
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief EIM module initialization function.
*
* @param base EIM base address.
*/
void EIM_Init(EIM_Type *base);
/*!
* @brief De-initializes the EIM.
*
*/
void EIM_Deinit(EIM_Type *base);
/* @} */
/*!
* @name functional
* @{
*/
/*!
* @brief EIM module enable global error injection.
*
* @param base EIM base address.
* @param mask The interrupts to enable.
*/
static inline void EIM_EnableGlobalErrorInjection(EIM_Type *base, bool enable)
{
if (enable)
{
base->EIMCR = EIM_EIMCR_GEIEN_MASK;
}
else
{
base->EIMCR = ~EIM_EIMCR_GEIEN_MASK;
}
}
/*!
* @brief EIM module enable error injection for memory channel n, this function enables the corresponding error
* injection channel. The Global Error Injection Enable function must also be called to enable error injection.
*
* @param base EIM base address.
* @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
*/
static inline void EIM_EnableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
{
base->EICHEN |= mask;
}
/*!
* @brief EIM module disable error injection for memory channel n.
*
* @param base EIM base address.
* @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
*/
static inline void EIM_DisableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
{
base->EICHEN &= ~mask;
}
/*!
* @brief EIM module inject checkbit error for memory channel n, an attempt to invert more than 2 bits in one operation
* might result in undefined behavior.
*
* @param base EIM base address.
* @param channel memory channel.
* @param mask The interrupts to enable.
*/
void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
/*!
* @brief EIM module get checkbit mask for memory channel n.
*
* @param base EIM base address.
* @param channel memory channel.
* @retval return checkbit mask.
*/
uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel);
/*!
* @brief EIM module inject databit error for memory channel n, an attempt to invert more than 2 bits in one operation
* might result in undefined behavior.
*
* @param base EIM base address.
* @param channel memory channel.
* @param mask The interrupts to enable.
*/
void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
/*!
* @brief EIM module get databit mask for memory channel n.
*
* @param base EIM base address.
* @param channel memory channel.
* @retval return checkbit mask.
*/
uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel);
/*! @}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif
bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.c
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.h
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bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c
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