[bsp][nxp] add mcxn947

bsp/nxp/mcxn/Libraries/.ignore_format.yml

@@ -0,0 +1,4 @@
+# files format check exclude path, please follow the instructions below to modify;
+
+dir_path:
+- MCXN947

bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.4
+ * @date     23. July 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/nxp/mcxn/Libraries/CMSIS/Core/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+
+#include <stdint.h>
+
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+
+#endif  // TZ_CONTEXT_H

bsp/nxp/mcxn/Libraries/Kconfig

@@ -0,0 +1,4 @@
+config SOC_MCX
+    bool
+    select ARCH_ARM_CORTEX_M33
+    select ARCH_ARM_CORTEX_FPU

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.c

@@ -0,0 +1,20 @@
+/*
+ * Copyright 2021-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cache_lpcac.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cache_lpcac"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h

@@ -0,0 +1,184 @@
+/*
+ * Copyright 2021-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_CACHE_LPCAC_H_
+#define _FSL_CACHE_LPCAC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cache_lpcac
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief cache driver version */
+#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name cache control for the L1 low power cache controller
+ *@{
+ */
+
+/*!
+ * @brief Enables the processor code bus cache.
+ *
+ */
+static inline void L1CACHE_EnableCodeCache(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
+}
+
+/*!
+ * @brief Disables the processor code bus cache.
+ *
+ */
+static inline void L1CACHE_DisableCodeCache(void)
+{
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
+}
+
+/*!
+ * @brief  Clears cache.
+ *
+ */
+static inline void L1CACHE_InvalidateCodeCache(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
+}
+
+/*!
+ * @brief Enables allocation.
+ *
+ */
+static inline void L1CACHE_EnableAllocation(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK;
+}
+
+/*!
+ * @brief Disables allocation.
+ *
+ */
+static inline void L1CACHE_DisableAllocation(void)
+{
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK;
+}
+
+/*!
+ * @brief Enables parity.
+ *
+ */
+static inline void L1CACHE_EnableParity(void)
+{
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK;
+}
+
+/*!
+ * @brief Disable parity.
+ *
+ */
+static inline void L1CACHE_DisableParity(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK;
+}
+
+#if defined(FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL) && FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL
+/*!
+ * @brief Enables write through buffer.
+ *
+ */
+static inline void L1CACHE_EnableWriteBuffer(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK;
+}
+
+/*!
+ * @brief Disables write through buffer.
+ *
+ */
+static inline void L1CACHE_DisableWriteBuffer(void)
+{
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK;
+}
+
+/*!
+ * @brief Limits write through buffer.
+ *
+ */
+static inline void L1CACHE_LimitWriteBuffer(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK;
+}
+
+/*!
+ * @brief Unlimits write through buffer.
+ *
+ */
+static inline void L1CACHE_UnlimitParity(void)
+{
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK;
+}
+
+/*!
+ * @brief Enables parity error report.
+ *
+ */
+static inline void L1CACHE_EnableParityErrorReport(void)
+{
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK;
+}
+
+/*!
+ * @brief Disables parity error report.
+ *
+ */
+static inline void L1CACHE_DisableParityErrorReport(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK;
+}
+
+/*!
+ * @brief Enables XOM(eXecute-Only-Memory) control.
+ *
+ */
+static inline void L1CACHE_EnableXOMControl(void)
+{
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK;
+}
+
+/*!
+ * @brief Disables XOM(eXecute-Only-Memory) control.
+ *
+ */
+static inline void L1CACHE_DisableXOMControl(void)
+{
+    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK;
+}
+#endif
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_CACHE_LPCAC_H_*/

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#if !((defined(__DSC__) && defined(__CW__)))
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize;
+
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
+    {
+        return NULL;
+    }
+
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+    {
+        return NULL;
+    }
+
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc((size_t)alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
+}
+#endif

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CRC driver version. Version 2.0.3.
+ *
+ * Current version: 2.0.3
+ *
+ * Change log:
+ *
+ * - Version 2.0.3
+ *   - Fix MISRA issues
+ *
+ * - Version 2.0.2
+ *   - Fix MISRA issues
+ *
+ * - Version 2.0.1
+ *   - move DATA and DATALL macro definition from header file to source file
+ */
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
+/*@}*/
+
+#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
+/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
+#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1
+#endif
+
+/*! @brief CRC bit width */
+typedef enum _crc_bits
+{
+    kCrcBits16 = 0U, /*!< Generate 16-bit CRC code  */
+    kCrcBits32 = 1U  /*!< Generate 32-bit CRC code  */
+} crc_bits_t;
+
+/*! @brief CRC result type */
+typedef enum _crc_result
+{
+    kCrcFinalChecksum = 0U,       /*!< CRC data register read value is the final checksum.
+                                      Reflect out and final xor protocol features are applied. */
+    kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value).
+                                      Reflect out and final xor protocol feature are not applied.
+                                      Intermediate checksum can be used as a seed for CRC_Init()
+                                      to continue adding data to this checksum. */
+} crc_result_t;
+
+/*!
+ * @brief CRC protocol configuration.
+ *
+ * This structure holds the configuration for the CRC protocol.
+ *
+ */
+typedef struct _crc_config
+{
+    uint32_t polynomial;     /*!< CRC Polynomial, MSBit first.
+                                  Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */
+    uint32_t seed;           /*!< Starting checksum value */
+    bool reflectIn;          /*!< Reflect bits on input. */
+    bool reflectOut;         /*!< Reflect bits on output. */
+    bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */
+    crc_bits_t crcBits;      /*!< Selects 16- or 32- bit CRC protocol. */
+    crc_result_t crcResult;  /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or
+                                CRC_Get32bitResult() */
+} crc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enables and configures the CRC peripheral module.
+ *
+ * This function enables the clock gate in the SIM module for the CRC peripheral.
+ * It also configures the CRC module and starts a checksum computation by writing the seed.
+ *
+ * @param base CRC peripheral address.
+ * @param config CRC module configuration structure.
+ */
+void CRC_Init(CRC_Type *base, const crc_config_t *config);
+
+/*!
+ * @brief Disables the CRC peripheral module.
+ *
+ * This function disables the clock gate in the SIM module for the CRC peripheral.
+ *
+ * @param base CRC peripheral address.
+ */
+static inline void CRC_Deinit(CRC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* gate clock */
+    CLOCK_DisableClock(kCLOCK_Crc0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief Loads default values to the CRC protocol configuration structure.
+ *
+ * Loads default values to the CRC protocol configuration structure. The default values are as follows.
+ * @code
+ *   config->polynomial = 0x1021;
+ *   config->seed = 0xFFFF;
+ *   config->reflectIn = false;
+ *   config->reflectOut = false;
+ *   config->complementChecksum = false;
+ *   config->crcBits = kCrcBits16;
+ *   config->crcResult = kCrcFinalChecksum;
+ * @endcode
+ *
+ * @param config CRC protocol configuration structure.
+ */
+void CRC_GetDefaultConfig(crc_config_t *config);
+
+/*!
+ * @brief Writes data to the CRC module.
+ *
+ * Writes input data buffer bytes to the CRC data register.
+ * The configured type of transpose is applied.
+ *
+ * @param base CRC peripheral address.
+ * @param data Input data stream, MSByte in data[0].
+ * @param dataSize Size in bytes of the input data buffer.
+ */
+void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
+
+/*!
+ * @brief Reads the 32-bit checksum from the CRC module.
+ *
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
+ *
+ * @param base CRC peripheral address.
+ * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations.
+ */
+uint32_t CRC_Get32bitResult(CRC_Type *base);
+
+/*!
+ * @brief Reads a 16-bit checksum from the CRC module.
+ *
+ * Reads the CRC data register (either an intermediate or the final checksum).
+ * The configured type of transpose and complement is applied.
+ *
+ * @param base CRC peripheral address.
+ * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations.
+ */
+uint16_t CRC_Get16bitResult(CRC_Type *base);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_CRC_H_ */

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.c

@@ -0,0 +1,182 @@
+/*!
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dac14.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dac14"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for DAC14 module.
+ *
+ * @param base DAC14 peripheral base address
+ */
+static uint32_t DAC14_GetInstance(HPDAC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to DAC14 bases for each instance. */
+static HPDAC_Type *const s_dac14Bases[] = HPDAC_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to DAC14 clocks for each instance. */
+static const clock_ip_name_t s_dac14Clocks[] = HPDAC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t DAC14_GetInstance(HPDAC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_dac14Bases); instance++)
+    {
+        if (s_dac14Bases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_dac14Bases));
+
+    return instance;
+}
+
+/*!
+ * brief Initialize the DAC14 module with common configuartion.
+ *
+ * The clock will be enabled in this function.
+ *
+ * param base DAC14 peripheral base address.
+ * param config Pointer to configuration structure.
+ */
+void DAC14_Init(HPDAC_Type *base, const dac14_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32 = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(s_dac14Clocks[DAC14_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    /* Software reset and FIFO reset. */
+    DAC14_DoSoftwareReset(base);
+    DAC14_DoFIFOReset(base);
+
+    /* Opamp is used as buffer. */
+    if (config->enableOpampBuffer)
+    {
+        tmp32 |= HPDAC_GCR_BUF_EN_MASK;
+    }
+    /*Enable the DAC system.*/
+    if (config->enableDAC)
+    {
+        tmp32 |= HPDAC_GCR_DACEN_MASK;
+    }
+
+    if (config->WorkMode != kDAC14_BufferWorkMode)
+    {
+        /*Use software trigger source.*/
+        if (kDAC14_SoftwareTriggerSource == config->TriggerSource)
+        {
+            tmp32 |= HPDAC_GCR_TRGSEL_MASK;
+        }
+
+        if (config->WorkMode != kDAC14_SwingBackWorkMode)
+        {
+            if (config->WorkMode != kDAC14_PeriodTriggerAndSwingBackWorkMode)
+            {
+                /*Configurtion FIFO watermarklevel.*/
+                base->FCR = HPDAC_FCR_WML(config->fifoWatermarkLevel);
+
+                if (config->WorkMode == kDAC14_PeriodTriggerWorkMode)
+                {
+                    tmp32 |= HPDAC_GCR_FIFOEN_MASK | HPDAC_GCR_PTGEN_MASK; /* Enable period trigger mode. */
+                    /* Set trigger number and width. */
+                    base->PCR = HPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) |
+                                HPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth);
+                }
+                else
+                {
+                    tmp32 |= HPDAC_GCR_FIFOEN_MASK; /* Enable FIFO mode.*/
+                }
+            }
+            else
+            {
+                /* Enable period trigger mode and swing back mode. */
+                tmp32 |= HPDAC_GCR_FIFOEN_MASK | HPDAC_GCR_PTGEN_MASK | HPDAC_GCR_SWMD_MASK;
+                /* Set trigger number and width. */
+                base->PCR = HPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) |
+                            HPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth);
+            }
+        }
+        else
+        {
+            tmp32 |= HPDAC_GCR_FIFOEN_MASK | HPDAC_GCR_SWMD_MASK; /* Enable swing mode. */
+        }
+    }
+    base->GCR = tmp32;
+}
+
+/*!
+ * brief Get the default settings for initialization's configuration.
+ *
+ * This function initializes the user configuration structure to a default value. The default values are:
+ * code
+    config->fifoWatermarkLevel = 0U;
+    config->TriggerSource    = kDAC14_HardwareTriggerSource;
+    config->WorkMode       = kDAC14_BufferWorkMode;
+    config->enableOpampBuffer  = false;
+    config->enableADC  = false;
+    config->periodicTriggerNumber = 0U;
+    config->periodicTriggerWidth  = 0U;
+ * endcode
+ *
+ * param config Pointer to configuration structure.
+ */
+void DAC14_GetDefaultConfig(dac14_config_t *config)
+{
+    assert(config != NULL);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->fifoWatermarkLevel    = 0U;
+    config->TriggerSource         = kDAC14_HardwareTriggerSource;
+    config->WorkMode              = kDAC14_BufferWorkMode;
+    config->enableOpampBuffer     = false;
+    config->enableDAC             = false;
+    config->periodicTriggerNumber = 0U;
+    config->periodicTriggerWidth  = 0U;
+}
+/*!
+ * brief De-initialize the DAC14 module.
+ *
+ * The clock will be disabled in this function.
+ *
+ * param base DAC14 peripheral base address.
+ */
+void DAC14_Deinit(HPDAC_Type *base)
+{
+    /* Disable the module. */
+    DAC14_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_dac14Clocks[DAC14_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_EIM_H_
+#define _FSL_EIM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup eim
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version. */
+#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
+/*@}*/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief EIM module initialization function.
+ *
+ * @param base EIM base address.
+ */
+void EIM_Init(EIM_Type *base);
+
+/*!
+ * @brief De-initializes the EIM.
+ *
+ */
+void EIM_Deinit(EIM_Type *base);
+
+/* @} */
+
+/*!
+ * @name functional
+ * @{
+ */
+
+/*!
+ * @brief EIM module enable global error injection.
+ *
+ * @param base EIM base address.
+ * @param mask The interrupts to enable.
+ */
+static inline void EIM_EnableGlobalErrorInjection(EIM_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->EIMCR = EIM_EIMCR_GEIEN_MASK;
+    }
+    else
+    {
+        base->EIMCR = ~EIM_EIMCR_GEIEN_MASK;
+    }
+}
+
+/*!
+ * @brief EIM module enable error injection for memory channel n, this function enables the corresponding error
+ * injection channel. The Global Error Injection Enable function must also be called to enable error injection.
+ *
+ * @param base EIM base address.
+ * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
+ */
+static inline void EIM_EnableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
+{
+    base->EICHEN |= mask;
+}
+
+/*!
+ * @brief EIM module disable error injection for memory channel n.
+ *
+ * @param base EIM base address.
+ * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration.
+ */
+static inline void EIM_DisableErrorInjectionChannels(EIM_Type *base, uint32_t mask)
+{
+    base->EICHEN &= ~mask;
+}
+
+/*!
+ * @brief EIM module inject checkbit error for memory channel n, an attempt to invert more than 2 bits in one operation
+ * might result in undefined behavior.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @param mask The interrupts to enable.
+ */
+void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
+
+/*!
+ * @brief EIM module get checkbit mask for memory channel n.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @retval return checkbit mask.
+ */
+uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel);
+
+/*!
+ * @brief EIM module inject databit error for memory channel n, an attempt to invert more than 2 bits in one operation
+ * might result in undefined behavior.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @param mask The interrupts to enable.
+ */
+void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask);
+
+/*!
+ * @brief EIM module get databit mask for memory channel n.
+ *
+ * @param base EIM base address.
+ * @param channel memory channel.
+ * @retval return checkbit mask.
+ */
+uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.c

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017, 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_ewm.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.ewm"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Initializes the EWM peripheral.
+ *
+ * This function is used to initialize the EWM. After calling, the EWM
+ * runs immediately according to the configuration.
+ * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a
+ * CPU reset. Modifying them more than once generates a bus transfer error.
+ *
+ * This is an example.
+ * code
+ *   ewm_config_t config;
+ *   EWM_GetDefaultConfig(&config);
+ *   config.compareHighValue = 0xAAU;
+ *   EWM_Init(ewm_base,&config);
+ * endcode
+ *
+ * param base EWM peripheral base address
+ * param config The configuration of the EWM
+ */
+void EWM_Init(EWM_Type *base, const ewm_config_t *config)
+{
+    assert(NULL != config);
+
+    uint8_t value = 0U;
+
+#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
+      (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_Ewm0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif
+    value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) |
+            EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt);
+#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
+    base->CLKPRESCALER = config->prescaler;
+#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */
+
+#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
+    base->CLKCTRL = (uint8_t)config->clockSource;
+#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/
+
+    base->CMPL = config->compareLowValue;
+    base->CMPH = config->compareHighValue;
+    base->CTRL = value;
+}
+
+/*!
+ * brief Deinitializes the EWM peripheral.
+ *
+ * This function is used to shut down the EWM.
+ *
+ * param base EWM peripheral base address
+ */
+void EWM_Deinit(EWM_Type *base)
+{
+    EWM_DisableInterrupts(base, (uint32_t)kEWM_InterruptEnable);
+#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \
+      (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE))
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_DisableClock(kCLOCK_Ewm0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */
+}
+
+/*!
+ * brief Initializes the EWM configuration structure.
+ *
+ * This function initializes the EWM configuration structure to default values. The default
+ * values are as follows.
+ * code
+ *   ewmConfig->enableEwm = true;
+ *   ewmConfig->enableEwmInput = false;
+ *   ewmConfig->setInputAssertLogic = false;
+ *   ewmConfig->enableInterrupt = false;
+ *   ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0;
+ *   ewmConfig->prescaler = 0;
+ *   ewmConfig->compareLowValue = 0;
+ *   ewmConfig->compareHighValue = 0xFEU;
+ * endcode
+ *
+ * param config Pointer to the EWM configuration structure.
+ * see ewm_config_t
+ */
+void EWM_GetDefaultConfig(ewm_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableEwm           = true;
+    config->enableEwmInput      = false;
+    config->setInputAssertLogic = false;
+    config->enableInterrupt     = false;
+#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
+    config->clockSource = kEWM_LpoClockSource0;
+#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/
+#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER
+    config->prescaler = 0U;
+#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */
+    config->compareLowValue  = 0U;
+    config->compareHighValue = 0xFEU;
+}
+
+/*!
+ * brief Services the EWM.
+ *
+ * This function resets the EWM counter to zero.
+ *
+ * param base EWM peripheral base address
+ */
+void EWM_Refresh(EWM_Type *base)
+{
+    uint32_t primaskValue = 0U;
+
+    /* Disable the global interrupt to protect refresh sequence */
+    primaskValue = DisableGlobalIRQ();
+    base->SERV   = (uint8_t)0xB4U;
+    base->SERV   = (uint8_t)0x2CU;
+    EnableGlobalIRQ(primaskValue);
+}

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_
+#define _FSL_FLEXIO_MCULCD_EDMA_H_
+
+#include "fsl_edma.h"
+#include "fsl_flexio_mculcd.h"
+
+/*!
+ * @addtogroup flexio_edma_mculcd
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*@{*/
+/*! @brief FlexIO MCULCD EDMA driver version. */
+#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*! @brief  typedef for flexio_mculcd_edma_handle_t in advance. */
+typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t;
+
+/*! @brief FlexIO MCULCD master callback for transfer complete.
+ *
+ * When transfer finished, the callback function is called and returns the
+ * @p status as kStatus_FLEXIO_MCULCD_Idle.
+ */
+typedef void (*flexio_mculcd_edma_transfer_callback_t)(FLEXIO_MCULCD_Type *base,
+                                                       flexio_mculcd_edma_handle_t *handle,
+                                                       status_t status,
+                                                       void *userData);
+
+/*! @brief FlexIO MCULCD eDMA transfer handle, users should not touch the
+ * content of the handle.*/
+struct _flexio_mculcd_edma_handle
+{
+    FLEXIO_MCULCD_Type *base;       /*!< Pointer to the FLEXIO_MCULCD_Type. */
+    uint8_t txShifterNum;           /*!< Number of shifters used for TX. */
+    uint8_t rxShifterNum;           /*!< Number of shifters used for RX. */
+    uint32_t minorLoopBytes;        /*!< eDMA transfer minor loop bytes. */
+    edma_modulo_t txEdmaModulo;     /*!< Modulo value for the FlexIO shifter buffer access. */
+    edma_modulo_t rxEdmaModulo;     /*!< Modulo value for the FlexIO shifter buffer access. */
+    uint32_t dataAddrOrSameValue;   /*!< When sending the same value for many times,
+                                         this is the value to send. When writing or
+                                         reading array, this is the address of the
+                                         data array. */
+    size_t dataCount;               /*!< Total count to be transferred. */
+    volatile size_t remainingCount; /*!< Remaining count still not transfered. */
+    volatile uint32_t state;        /*!< FlexIO MCULCD driver internal state. */
+    edma_handle_t *txDmaHandle;     /*!< DMA handle for MCULCD TX */
+    edma_handle_t *rxDmaHandle;     /*!< DMA handle for MCULCD RX */
+    flexio_mculcd_edma_transfer_callback_t completionCallback; /*!< Callback for MCULCD DMA transfer */
+    void *userData;                                            /*!< User Data for MCULCD DMA callback */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXO MCULCD master eDMA handle.
+ *
+ * This function initializes the FLEXO MCULCD master eDMA handle which can be
+ * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
+ * instance, call this API once to get the initialized handle.
+ *
+ * @param base Pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ * @param callback MCULCD transfer complete callback, NULL means no callback.
+ * @param userData callback function parameter.
+ * @param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX,
+ * the DMA request source of this handle should be the first of TX shifters.
+ * @param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX,
+ * the DMA request source of this handle should be the last of RX shifters.
+ * @retval kStatus_Success Successfully create the handle.
+ */
+status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
+                                                flexio_mculcd_edma_handle_t *handle,
+                                                flexio_mculcd_edma_transfer_callback_t callback,
+                                                void *userData,
+                                                edma_handle_t *txDmaHandle,
+                                                edma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Performs a non-blocking FlexIO MCULCD transfer using eDMA.
+ *
+ * This function returns immediately after transfer initiates. To check whether
+ * the transfer is completed, user could:
+ * 1. Use the transfer completed callback;
+ * 2. Polling function FLEXIO_MCULCD_GetTransferCountEDMA
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ * @param xfer Pointer to FlexIO MCULCD transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
+ * transfer.
+ */
+status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
+                                    flexio_mculcd_edma_handle_t *handle,
+                                    flexio_mculcd_transfer_t *xfer);
+/*!
+ * brief Performs a non-blocking FlexIO MCULCD data write using eDMA.
+ *
+ * This function returns immediately after transfer initiates. To check whether
+ * the transfer is completed, user could:
+ * 1. Use the transfer completed callback;
+ * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param handle pointer to flexio_mculcd_edma_handle_t structure to store the
+ * transfer state.
+ * param data Pointer to data.
+ * param size Size(in bytes) of the data
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
+ * transfer.
+ */
+status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base,
+                                    flexio_mculcd_edma_handle_t *handle,
+                                    const void *data, size_t size);
+
+/*!
+ * @brief Aborts a FlexIO MCULCD transfer using eDMA.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle FlexIO MCULCD eDMA handle pointer.
+ */
+void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle FlexIO MCULCD eDMA handle pointer.
+ * @param count Number of count transferred so far by the eDMA transaction.
+ * @retval kStatus_Success Get the transferred count Successfully.
+ * @retval kStatus_NoTransferInProgress No transfer in process.
+ */
+status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
+                                            flexio_mculcd_edma_handle_t *handle,
+                                            size_t *count);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart_edma.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXIO_UART_EDMA_H_
+#define _FSL_FLEXIO_UART_EDMA_H_
+
+#include "fsl_flexio_uart.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexio_edma_uart
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO UART EDMA driver version. */
+#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
+/*@}*/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base,
+                                                     flexio_uart_edma_handle_t *handle,
+                                                     status_t status,
+                                                     void *userData);
+
+/*!
+ * @brief UART eDMA handle
+ */
+struct _flexio_uart_edma_handle
+{
+    flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                                /*!< UART callback function parameter.*/
+
+    size_t txDataSizeAll; /*!< Total bytes to be sent. */
+    size_t rxDataSizeAll; /*!< Total bytes to be received. */
+
+    edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */
+    edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */
+
+    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle which is used in transactional functions.
+ *
+ * @param base Pointer to FLEXIO_UART_Type.
+ * @param handle Pointer to flexio_uart_edma_handle_t structure.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @param rxEdmaHandle User requested DMA handle for RX DMA transfer.
+ * @param txEdmaHandle User requested DMA handle for TX DMA transfer.
+ * @retval kStatus_Success Successfully create the handle.
+ * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
+ */
+status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base,
+                                              flexio_uart_edma_handle_t *handle,
+                                              flexio_uart_edma_transfer_callback_t callback,
+                                              void *userData,
+                                              edma_handle_t *txEdmaHandle,
+                                              edma_handle_t *rxEdmaHandle);
+
+/*!
+ * @brief Sends data using eDMA.
+ *
+ * This function sends data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is sent out, the send callback function is called.
+ *
+ * @param base Pointer to FLEXIO_UART_Type
+ * @param handle UART handle pointer.
+ * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base,
+                                      flexio_uart_edma_handle_t *handle,
+                                      flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using eDMA.
+ *
+ * This function receives data using eDMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base Pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_UART_RxBusy Previous transfer on going.
+ */
+status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base,
+                                         flexio_uart_edma_handle_t *handle,
+                                         flexio_uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the sent data which using eDMA.
+ *
+ * This function aborts sent data which using eDMA.
+ *
+ * @param base Pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle);
+
+/*!
+ * @brief Aborts the receive data which using eDMA.
+ *
+ * This function aborts the receive data which using eDMA.
+ *
+ * @param base Pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ */
+void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes sent out.
+ *
+ * This function gets the number of bytes sent out.
+ *
+ * @param base Pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ * @param count Number of bytes sent so far by the non-blocking transaction.
+ * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Gets the number of bytes received.
+ *
+ * This function gets the number of bytes received.
+ *
+ * @param base Pointer to FLEXIO_UART_Type
+ * @param handle Pointer to flexio_uart_edma_handle_t structure
+ * @param count Number of bytes received so far by the non-blocking transaction.
+ * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress.
+ * @retval kStatus_Success Successfully return the count.
+ */
+status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
+                                                 flexio_uart_edma_handle_t *handle,
+                                                 size_t *count);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UART_EDMA_H_ */

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.h

@@ -0,0 +1,146 @@
+/*
+ * Copyright 2021-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_FLEXSPI_EDMA_H_
+#define _FSL_FLEXSPI_EDMA_H_
+
+#include "fsl_flexspi.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexspi_edma
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FLEXSPI EDMA driver. */
+#define FSL_FLEXSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+typedef struct _flexspi_edma_handle flexspi_edma_handle_t;
+
+/*! @brief FLEXSPI eDMA transfer callback function for finish and error */
+typedef void (*flexspi_edma_callback_t)(FLEXSPI_Type *base,
+                                        flexspi_edma_handle_t *handle,
+                                        status_t status,
+                                        void *userData);
+
+/*! @brief eDMA transfer configuration */
+typedef enum _flexspi_edma_ntransfer_size
+{
+    kFLEXPSI_EDMAnSize1Bytes  = 0x1U,  /*!< Source/Destination data transfer size is 1 byte every time */
+    kFLEXPSI_EDMAnSize2Bytes  = 0x2U,  /*!< Source/Destination data transfer size is 2 bytes every time */
+    kFLEXPSI_EDMAnSize4Bytes  = 0x4U,  /*!< Source/Destination data transfer size is 4 bytes every time */
+    kFLEXPSI_EDMAnSize8Bytes  = 0x8U,  /*!< Source/Destination data transfer size is 8 bytes every time */
+    kFLEXPSI_EDMAnSize32Bytes = 0x20U, /*!< Source/Destination data transfer size is 32 bytes every time */
+} flexspi_edma_transfer_nsize_t;
+
+/*! @brief FLEXSPI DMA transfer handle, users should not touch the content of the handle.*/
+struct _flexspi_edma_handle
+{
+    edma_handle_t *txDmaHandle;                 /*!< eDMA handler for FLEXSPI Tx. */
+    edma_handle_t *rxDmaHandle;                 /*!< eDMA handler for FLEXSPI Rx. */
+    size_t transferSize;                        /*!< Bytes need to transfer. */
+    flexspi_edma_transfer_nsize_t nsize;        /*!< eDMA SSIZE/DSIZE in each transfer. */
+    uint8_t nbytes;                             /*!< eDMA minor byte transfer count initially configured. */
+    uint8_t count;                              /*!< The transfer data count in a DMA request. */
+    uint32_t state;                             /*!< Internal state for FLEXSPI eDMA transfer. */
+    flexspi_edma_callback_t completionCallback; /*!< A callback function called after the eDMA transfer is finished. */
+    void *userData;                             /*!< User callback parameter */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name FLEXSPI eDMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXSPI handle for transfer which is used in transactional functions and set the callback.
+ *
+ * @param base FLEXSPI peripheral base address
+ * @param handle Pointer to flexspi_edma_handle_t structure
+ * @param callback FLEXSPI callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param txDmaHandle User requested DMA handle for TX DMA transfer.
+ * @param rxDmaHandle User requested DMA handle for RX DMA transfer.
+ */
+void FLEXSPI_TransferCreateHandleEDMA(FLEXSPI_Type *base,
+                                      flexspi_edma_handle_t *handle,
+                                      flexspi_edma_callback_t callback,
+                                      void *userData,
+                                      edma_handle_t *txDmaHandle,
+                                      edma_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Update FLEXSPI EDMA transfer source data transfer size(SSIZE) and destination data transfer size(DSIZE).
+ *
+ * @param base FLEXSPI peripheral base address
+ * @param handle Pointer to flexspi_edma_handle_t structure
+ * @param nsize FLEXSPI DMA transfer data transfer size(SSIZE/DSIZE), by default the size is
+ * kFLEXPSI_EDMAnSize1Bytes(one byte).
+ * @see flexspi_edma_transfer_nsize_t               .
+ */
+void FLEXSPI_TransferUpdateSizeEDMA(FLEXSPI_Type *base,
+                                    flexspi_edma_handle_t *handle,
+                                    flexspi_edma_transfer_nsize_t nsize);
+
+/*!
+ * @brief Transfers FLEXSPI data using an eDMA non-blocking method.
+ *
+ * This function writes/receives data to/from the FLEXSPI transmit/receive FIFO. This function is non-blocking.
+ * @param base FLEXSPI peripheral base address.
+ * @param handle Pointer to flexspi_edma_handle_t structure
+ * @param xfer FLEXSPI transfer structure.
+ * @retval kStatus_FLEXSPI_Busy     FLEXSPI is busy transfer.
+ * @retval kStatus_InvalidArgument  The watermark configuration is invalid, the watermark should be power of
+                                    2 to do successfully EDMA transfer.
+ * @retval kStatus_Success          FLEXSPI successfully start edma transfer.
+ */
+status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, flexspi_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the transfer data using eDMA.
+ *
+ * This function aborts the transfer data using eDMA.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle Pointer to flexspi_edma_handle_t structure
+ */
+void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle);
+
+/*!
+ * @brief Gets the transferred counts of transfer.
+ *
+ * @param base FLEXSPI peripheral base address.
+ * @param handle Pointer to flexspi_edma_handle_t structure.
+ * @param count Bytes transfer.
+ * @retval kStatus_Success Succeed get the transfer count.
+ * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
+ */
+status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @} */
+
+#endif /* _FSL_FLEXSPI_EDMA_H_ */

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.c

@@ -0,0 +1,143 @@
+/*
+ * Copyright 2021-2022 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_freqme.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_freqme"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static uint32_t FREQME_GetInstance(FREQME_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Array to map freqme instance number to base address. */
+static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to FREQME clocks for each instance. */
+static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t FREQME_GetInstance(FREQME_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0U; instance < ARRAY_SIZE(s_freqmeBases); instance++)
+    {
+        if (s_freqmeBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_freqmeBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle.
+ *
+ * param base FREQME peripheral base address.
+ * param config The pointer to module basic configuration, please refer to freq_measure_config_t.
+ */
+void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config)
+{
+    assert(config);
+
+    uint32_t tmp32 = 0UL;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable FREQME clock. */
+    CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    if (config->startMeasurement)
+    {
+        tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK;
+    }
+    tmp32 |=
+        FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | FREQME_CTRL_W_PULSE_MODE(config->operateMode);
+    if (config->operateMode == kFREQME_FreqMeasurementMode)
+    {
+        tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor);
+    }
+    else
+    {
+        tmp32 |= FREQME_CTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity);
+    }
+
+    base->CTRL_W = tmp32;
+}
+
+/*!
+ * brief Get default configuration.
+ *
+ * code
+ *      config->operateMode = kFREQME_FreqMeasurementMode;
+ *      config->operateModeAttribute.refClkScaleFactor = 0U;
+ *      config->enableContinuousMode                   = false;
+ *      config->startMeasurement                       = false;
+ * endcode
+ *
+ * param config The pointer to module basic configuration, please refer to freq_measure_config_t.
+ */
+void FREQME_GetDefaultConfig(freq_measure_config_t *config)
+{
+    assert(config);
+
+    (void)memset(config, 0, sizeof(*config));
+
+    config->operateMode                            = kFREQME_FreqMeasurementMode;
+    config->operateModeAttribute.refClkScaleFactor = 0U;
+    config->enableContinuousMode                   = false;
+    config->startMeasurement                       = false;
+}
+
+/*!
+ * brief Calculate the frequency of selected target clock.
+ *
+ * note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE.
+ *
+ * note This function only useful when the operate mode is selected as frequency measurement mode.
+ *
+ * param base FREQME peripheral base address.
+ * param refClkFrequency The frequency of reference clock.
+ * return The frequency of target clock, if the output result is 0, please check the module's operate mode.
+ */
+uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency)
+{
+    uint32_t measureResult = 0UL;
+    uint32_t targetFreq    = 0UL;
+    uint64_t tmp64         = 0ULL;
+
+    while ((base->CTRL_R & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL)
+    {
+    }
+
+    if (!FREQME_CheckOperateMode(base))
+    {
+        measureResult = base->CTRL_R & FREQME_CTRL_R_RESULT_MASK;
+        tmp64         = ((uint64_t)measureResult - 2ULL) * (uint64_t)refClkFrequency;
+        targetFreq    = (uint32_t)(tmp64 / (1ULL << (uint64_t)FREQME_GetReferenceClkScaleValue(base)));
+    }
+
+    return targetFreq;
+}

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.c

@@ -0,0 +1,165 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gdet.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gdet"
+#endif
+
+#define ISOLATE_ON  (0x2u << 2)
+#define ISOLATE_OFF (0x0u << 2)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * Weak implementation of GDET IRQ, should be re-defined by user when using GDET IRQ
+ */
+__WEAK void GDET_DriverIRQHandler(void)
+{
+    /* GDET generates IRQ if voltage glitching is detected
+     */
+}
+
+/*!
+ * brief Initialize GDET
+ *
+ * This function initializes GDET setting and enable interrupts.
+ *
+ * param base GDET peripheral base address
+ * return Status of the init operation
+ */
+status_t GDET_Init(GDET_Type *base)
+{
+    /* Ungate clock to GDET engine and reset it */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_Gdet);
+#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    NVIC_EnableIRQ(GDET_IRQn);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitialize GDET
+ *
+ * This function stops GDET glitch detector.
+ *
+ * param base GDET peripheral base address
+ */
+void GDET_Deinit(GDET_Type *base)
+{
+    NVIC_DisableIRQ(GDET_IRQn);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+    CLOCK_DisableClock(kCLOCK_Gdet);
+#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/* Array of GDET peripheral base address. */
+static GDET_Type *const s_gdetBases[] = GDET_BASE_PTRS;
+
+/*!
+ * brief Get the GDET instance from peripheral base address.
+ *
+ * param base GDET peripheral base address.
+ * return GDET instance.
+ */
+static uint32_t GDET_GetInstance(GDET_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0U; instance < ARRAY_SIZE(s_gdetBases); instance++)
+    {
+        if (s_gdetBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gdetBases));
+
+    return instance;
+}
+
+status_t GDET_IsolateOn(GDET_Type *base)
+{
+    status_t status = kStatus_Fail;
+    uint32_t instance;
+
+    instance = GDET_GetInstance(base);
+
+    SYSCON->GDET_CTRL[instance] = ISOLATE_ON;
+
+    if (ISOLATE_ON != SYSCON->GDET_CTRL[instance])
+    {
+        return kStatus_Fail;
+    }
+    status = kStatus_Success;
+
+    return status;
+}
+
+status_t GDET_IsolateOff(GDET_Type *base)
+{
+    status_t status = kStatus_Fail;
+    uint32_t instance;
+
+    instance = GDET_GetInstance(base);
+
+    SYSCON->GDET_CTRL[instance] = ISOLATE_ON;
+
+    if (ISOLATE_ON != SYSCON->GDET_CTRL[instance])
+    {
+        return kStatus_Fail;
+    }
+    status = kStatus_Success;
+
+    return status;
+}
+
+status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltage)
+{
+    uint32_t tmp0   = 0;
+    status_t status = kStatus_Fail;
+
+    if (voltage != (kGDET_MidVoltage || kGDET_NormalVoltage || kGDET_OverDriveVoltage))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /*Change the GDET_DLY_CTRL to select the new drive mode (and set high also GDET_DLY_CTRL[SW_VOL_CTRL] for a SW
+     * control)*/
+    tmp0 = (((uint32_t)voltage) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT);
+    tmp0 |= GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK;
+    base->GDET_DLY_CTRL = tmp0;
+
+    /*Write high the GDET_RESET[SFT_RST] to issue a fast update of the detector to the new voltage level.*/
+    base->GDET_RESET = GDET_GDET_RESET_SFT_RST(1u);
+
+    /* according to the GDET module documentation, the GDET_CFG[SFT_RST] reads as 0 */
+    if (0u == (GDET_GDET_RESET_SFT_RST_MASK & base->GDET_RESET))
+    {
+        status = kStatus_Success;
+    }
+
+    return status;
+}

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.h

@@ -0,0 +1,116 @@
+/*
+ * Copyright 2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_GDET_H_
+#define _FSL_GDET_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup GDET
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines GDET driver version 2.0.0.
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_GDET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief GDET Core Voltage.
+ *
+ * These constants are used to define core voltage argument to be used with
+ * GDET_ReconfigureVoltageMode().
+ */
+typedef enum _gdet_core_voltage
+{
+    kGDET_MidVoltage       = 0U, /*!< Mid Voltage (1.0V) */
+    kGDET_NormalVoltage    = 1U, /*!< Normal Voltage (1.1V) */
+    kGDET_OverDriveVoltage = 2U, /*!< Over Drive Voltage (1.2V) */
+} gdet_core_voltage_t;
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+extern void GDET_DriverIRQHandler(void);
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name GDET Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Initialize GDET
+ *
+ * This function initializes GDET block and setting.
+ *
+ * @param base GDET peripheral base address
+ * @return Status of the init operation
+ */
+status_t GDET_Init(GDET_Type *base);
+
+/*!
+ * @brief Deinitialize GDET
+ *
+ * This function deinitializes GDET secure counter.
+ *
+ * @param base GDET peripheral base address
+ */
+void GDET_Deinit(GDET_Type *base);
+/*!
+ * @brief Turn on GDET isolation
+ *
+ * This function turns on isolation of GDET peripheral
+ *
+ * @param base GDET peripheral base address
+ */
+status_t GDET_IsolateOn(GDET_Type *base);
+
+/*!
+ * @brief Turn off GDET isolation
+ *
+ * This function turns off isolation of GDET peripheral
+ *
+ * @param base GDET peripheral base address
+ */
+status_t GDET_IsolateOff(GDET_Type *base);
+
+/*!
+ * @brief Change expected core voltage
+ *
+ * This function changes core voltage which Glitch detector expect.
+ *
+ * @param base GDET peripheral base address
+ * @param voltage Expected core voltage
+ * @return Status of the GDET reconfiguration operation
+ */
+status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltage);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/ /* end of group gdet */
+
+#endif /* _FSL_GDET_H_ */

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.c

@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_inputmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.inputmux"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief    Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ *
+ * retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
+#if (defined(FSL_FEATURE_SOC_SCT_COUNT) && (FSL_FEATURE_SOC_SCT_COUNT > 0))
+    CLOCK_EnableClock(kCLOCK_Sct);
+#endif /* FSL_FEATURE_SOC_SCT_COUNT */
+    CLOCK_EnableClock(kCLOCK_Dma);
+#else
+    CLOCK_EnableClock(kCLOCK_InputMux);
+#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ * param index Destination peripheral to attach the signal to.
+ * param connection Selects connection.
+ *
+ * retval None.
+ */
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
+{
+    uint32_t pmux_id;
+    uint32_t output_id;
+
+    /* extract pmux to be used */
+    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
+    /*  extract function number */
+    output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U);
+    /* programm signal */
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id;
+}
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
+/*!
+ * brief Enable/disable a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ * param signal Enable signal register id and bit offset.
+ * param enable Selects enable or disable.
+ *
+ * retval None.
+ */
+void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable)
+{
+    uint32_t ena_id;
+    uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U;
+    uint32_t bit_offset;
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX
+    uint32_t chmux_offset;
+    uint32_t chmux_value;
+
+    /* Only enable need to update channel mux */
+    if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U))
+    {
+        chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL);
+        chmux_value  = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL);
+        *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value;
+    }
+    ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U;
+#endif
+    /* extract enable register to be used */
+    ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask;
+    /* extract enable bit offset */
+    bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U);
+    /* set signal */
+    if (enable)
+    {
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset);
+    }
+    else
+    {
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset);
+    }
+}
+#endif
+
+/*!
+ * brief    Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * param base Base address of the INPUTMUX peripheral.
+ *
+ * retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE
+#if (defined(FSL_FEATURE_SOC_SCT_COUNT) && (FSL_FEATURE_SOC_SCT_COUNT > 0))
+    CLOCK_DisableClock(kCLOCK_Sct);
+#endif /* FSL_FEATURE_SOC_SCT_COUNT */
+    CLOCK_DisableClock(kCLOCK_Dma);
+#else
+    CLOCK_DisableClock(kCLOCK_InputMux);
+#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_INPUTMUX_H_
+#define _FSL_INPUTMUX_H_
+
+#include "fsl_inputmux_connections.h"
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup inputmux_driver
+ * @{
+ */
+
+/*! @file */
+/*! @file fsl_inputmux_connections.h */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Group interrupt driver version for SDK */
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
+/*@}*/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief   Initialize INPUTMUX peripheral.
+
+ * This function enables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Init(INPUTMUX_Type *base);
+
+/*!
+ * @brief Attaches a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param index Destination peripheral to attach the signal to.
+ * @param connection Selects connection.
+ *
+ * @retval None.
+ */
+void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
+
+#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
+/*!
+ * @brief Enable/disable a signal
+ *
+ * This function gates the INPUTPMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ * @param signal Enable signal register id and bit offset.
+ * @param enable Selects enable or disable.
+ *
+ * @retval None.
+ */
+void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable);
+#endif
+
+/*!
+ * @brief   Deinitialize INPUTMUX peripheral.
+
+ * This function disables the INPUTMUX clock.
+ *
+ * @param base Base address of the INPUTMUX peripheral.
+ *
+ * @retval None.
+ */
+void INPUTMUX_Deinit(INPUTMUX_Type *base);
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_INPUTMUX_H_ */

bsp/nxp/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_intm.c

@@ -0,0 +1,86 @@
+/*
+ * Copyright 2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_intm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.intm"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief  Fill in the INTM config struct with the default settings
+ *
+ * The default values are:
+ * code
+ *     config[0].irqnumber = NotAvail_IRQn;
+ *     config[0].maxtimer = 1000U;
+ *     config[1].irqnumber = NotAvail_IRQn;
+ *     config[1].maxtimer = 1000U;
+ *     config[2].irqnumber = NotAvail_IRQn;
+ *     config[2].maxtimer = 1000U;
+ *     config[3].irqnumber = NotAvail_IRQn;
+ *     config[3].maxtimer = 1000U;
+ *     config->enable = false;
+ * endcode
+ * param config Pointer to user's INTM config structure.
+ */
+void INTM_GetDefaultConfig(intm_config_t *config)
+{
+    assert(config);
+
+    for (uint32_t i = 0; i < (uint32_t)FSL_FEATURE_INTM_MONITOR_COUNT; i++)
+    {
+        config->intm[i].irqnumber = NotAvail_IRQn;
+        config->intm[i].maxtimer  = 1000U;
+    }
+
+    /* INTM cycle count timer mode disable*/
+    config->enable = false;
+}
+
+/*!
+ * brief Ungates the INTM clock and configures the peripheral for basic operation.
+ *
+ * note This API should be called at the beginning of the application using the INTM driver.
+ *
+ * param base      INTM peripheral base address
+ * param config    Pointer to user's INTM config structure.
+ */
+void INTM_Init(INTM_Type *base, const intm_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    CLOCK_EnableClock(kCLOCK_Intm);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_INTM_MONITOR_COUNT; i++)
+    {
+        base->MON[i].INTM_IRQSEL  = INTM_MON_INTM_IRQSEL_IRQ(config->intm[i].irqnumber);
+        base->MON[i].INTM_LATENCY = INTM_MON_INTM_LATENCY_LAT(config->intm[i].maxtimer);
+    }
+
+    INTM_EnableCycleCount(base, config->enable);
+}
+
+/*!
+ * brief Disables the INTM module.
+ *
+ * param base INTM peripheral base address
+ */
+void INTM_Deinit(INTM_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Gate the INTM clock*/
+    CLOCK_DisableClock(kCLOCK_Intm);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}