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[bsp][renesas] Add a new BSP: RZN2L-RSK

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This commit is contained in:
Yuqiang Wang
2024-09-16 01:29:20 +08:00
committed by GitHub
parent 6320f184f5
commit beb7bc42de
123 changed files with 90442 additions and 0 deletions
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.github/workflows/bsp_buildings.yml vendored
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@@ -234,6 +234,7 @@ jobs:
- "renesas/ra8d1-ek"
- "renesas/ra8d1-vision-board"
- "renesas/rzt2m_rsk"
- "renesas/rzn2l_rsk"
- "frdm-k64f"
- "xplorer4330/M4"
- RTT_BSP: "gd32_n32_apm32"

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bsp/renesas/README.md
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@@ -19,7 +19,9 @@ RA 系列 BSP 目前支持情况如下表所示：
| [ra8m1-ek](ra8m1-ek) | Renesas 官方 EK-RA8M1 开发板 |
| [ra8d1-ek](ra8d1-ek) | Renesas 官方 EK-RA8D1 开发板 |
| [ra8d1-vision-board](ra8d1-vision-board) | Renesas 联合 RT-Thread RA8D1-Vision-Board 开发板 |
| **RZ 系列** | |
| [rzt2m_rsk](rzt2m_rsk) | Renesas 官方 RSK-RZT2M 开发板 |
| [rzn2l_rsk](rzn2l_rsk) | Renesas 官方 RSK-RZN2L 开发板 |
可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示：

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<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<ddscApi/>

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<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<azone>
<rzone name="R9A07G084M04GBG.rzone"/>
</azone>

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="9">
<generalSettings>
<option key="#Board#" value="board.rzn2lrsk.xspi0_x1"/>
<option key="CPU" value="RZN2L"/>
<option key="Core" value="CR52_0"/>
<option key="#TargetName#" value="R9A07G084M04GBG"/>
<option key="#TargetARCHITECTURE#" value="cortex-r52"/>
<option key="#DeviceCommand#" value="R9A07G084M04"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R9A07G084M04GBG.pincfg"/>
<option key="#FSPVersion#" value="2.0.0"/>
<option key="#ConfigurationFragments#" value="Renesas##BSP##Board##rzn2l_rsk##xspi0_x1_boot"/>
<option key="#SELECTED_TOOLCHAIN#" value="iar.arm.toolchain"/>
</generalSettings>
<raBspConfiguration/>
<raClockConfiguration>
<node id="board.clock.main.freq" option="board.clock.main.freq.25m"/>
<node id="board.clock.loco.enable" option="board.clock.loco.enable.enabled"/>
<node id="board.clock.pll0.display" option="board.clock.pll0.display.value"/>
<node id="board.clock.pll1" option="board.clock.pll1.initial"/>
<node id="board.clock.pll1.display" option="board.clock.pll1.display.value"/>
<node id="board.clock.ethernet.source" option="board.clock.ethernet.source.main"/>
<node id="board.clock.reference.display" option="board.clock.reference.display.value"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.240k"/>
<node id="board.clock.clma0.enable" option="board.clock.clma0.enable.enabled"/>
<node id="board.clock.clma0.error" option="board.clock.clma0.error.not_mask"/>
<node id="board.clock.clma3.error" option="board.clock.clma3.error.not_mask"/>
<node id="board.clock.clma1.error" option="board.clock.clma1.error.mask"/>
<node id="board.clock.clma3.enable" option="board.clock.clma3.enable.enabled"/>
<node id="board.clock.clma1.enable" option="board.clock.clma1.enable.enabled"/>
<node id="board.clock.clma2.enable" option="board.clock.clma2.enable.enabled"/>
<node id="board.clock.clma0.cmpl" mul="1" option="_edit"/>
<node id="board.clock.clma1.cmpl" mul="1" option="_edit"/>
<node id="board.clock.clma2.cmpl" mul="1" option="_edit"/>
<node id="board.clock.clma3.cmpl" mul="1" option="_edit"/>
<node id="board.clock.alternative.source" option="board.clock.alternative.source.loco"/>
<node id="board.clock.clma0.cmph" mul="1023" option="_edit"/>
<node id="board.clock.clma1.cmph" mul="1023" option="_edit"/>
<node id="board.clock.clma2.cmph" mul="1023" option="_edit"/>
<node id="board.clock.clma3.cmph" mul="1023" option="_edit"/>
<node id="board.clock.iclk.freq" option="board.clock.iclk.freq.200m"/>
<node id="board.clock.cpu0clk.mul" option="board.clock.cpu0clk.mul.2"/>
<node id="board.clock.cpu0clk.display" option="board.clock.cpu0clk.display.value"/>
<node id="board.clock.ckio.div" option="board.clock.ckio.div.4"/>
<node id="board.clock.ckio.display" option="board.clock.ckio.display.value"/>
<node id="board.clock.sci0asyncclk.sel" option="board.clock.sci0asyncclk.sel.1"/>
<node id="board.clock.sci1asyncclk.sel" option="board.clock.sci1asyncclk.sel.1"/>
<node id="board.clock.sci2asyncclk.sel" option="board.clock.sci2asyncclk.sel.1"/>
<node id="board.clock.sci3asyncclk.sel" option="board.clock.sci3asyncclk.sel.1"/>
<node id="board.clock.sci4asyncclk.sel" option="board.clock.sci4asyncclk.sel.1"/>
<node id="board.clock.sci5asyncclk.sel" option="board.clock.sci5asyncclk.sel.1"/>
<node id="board.clock.spi0asyncclk.sel" option="board.clock.spi0asyncclk.sel.1"/>
<node id="board.clock.spi1asyncclk.sel" option="board.clock.spi1asyncclk.sel.1"/>
<node id="board.clock.spi2asyncclk.sel" option="board.clock.spi2asyncclk.sel.1"/>
<node id="board.clock.spi3asyncclk.sel" option="board.clock.spi3asyncclk.sel.1"/>
<node id="board.clock.pclkshost.display" option="board.clock.pclkshost.display.value"/>
<node id="board.clock.pclkgptl.display" option="board.clock.pclkgptl.display.value"/>
<node id="board.clock.pclkh.display" option="board.clock.pclkh.display.value"/>
<node id="board.clock.pclkm.display" option="board.clock.pclkm.display.value"/>
<node id="board.clock.pclkl.display" option="board.clock.pclkl.display.value"/>
<node id="board.clock.pclkadc.display" option="board.clock.pclkadc.display.value"/>
<node id="board.clock.pclkcan.freq" option="board.clock.pclkcan.freq.40m"/>
<node id="board.clock.xspi.clk0.freq" option="board.clock.xspi.clk0.freq.12m"/>
<node id="board.clock.xspi.clk1.freq" option="board.clock.xspi.clk1.freq.12m"/>
<node id="board.clock.tclk.freq" option="board.clock.tclk.freq.100m"/>
</raClockConfiguration>
<raPinConfiguration>
<pincfg active="true" name="" symbol="">
<configSetting altId="canfd0.canrx0.p01_7" configurationId="canfd0.canrx0"/>
<configSetting altId="canfd0.cantx0.p02_2" configurationId="canfd0.cantx0"/>
<configSetting altId="ether_gmac.gmac_mdc.p08_7" configurationId="ether_gmac.gmac_mdc"/>
<configSetting altId="ether_gmac.gmac_mdio.p09_0" configurationId="ether_gmac.gmac_mdio"/>
<configSetting altId="iic0.iic_scl0.p13_2" configurationId="iic0.iic_scl0"/>
<configSetting altId="iic0.iic_sda0.p13_3" configurationId="iic0.iic_sda0"/>
<configSetting altId="iic1.iic_scl1.p05_2" configurationId="iic1.iic_scl1"/>
<configSetting altId="iic1.iic_sda1.p05_3" configurationId="iic1.iic_sda1"/>
<configSetting altId="jtag_fslash_swd.tck_swclk.p02_7" configurationId="jtag_fslash_swd.tck_swclk" isUsedByDriver="true"/>
<configSetting altId="jtag_fslash_swd.tdi.p02_5" configurationId="jtag_fslash_swd.tdi" isUsedByDriver="true"/>
<configSetting altId="jtag_fslash_swd.tdo.p02_4" configurationId="jtag_fslash_swd.tdo" isUsedByDriver="true"/>
<configSetting altId="jtag_fslash_swd.tms_swdio.p02_6" configurationId="jtag_fslash_swd.tms_swdio" isUsedByDriver="true"/>
<configSetting altId="p03_0.output.low" configurationId="p03_0"/>
<configSetting altId="p04_1.output.low" configurationId="p04_1"/>
<configSetting altId="p04_4.output.low" configurationId="p04_4"/>
<configSetting altId="p05_0.output.low" configurationId="p05_0"/>
<configSetting altId="p05_4.input" configurationId="p05_4"/>
<configSetting altId="p13_4.output.low" configurationId="p13_4"/>
<configSetting altId="p13_5.input" configurationId="p13_5"/>
<configSetting altId="p13_6.input" configurationId="p13_6"/>
<configSetting altId="p13_7.input" configurationId="p13_7"/>
<configSetting altId="p14_0.input" configurationId="p14_0"/>
<configSetting altId="p16_3.input" configurationId="p16_3"/>
<configSetting altId="p17_3.output.low" configurationId="p17_3"/>
<configSetting altId="p18_2.output.low" configurationId="p18_2"/>
<configSetting altId="p22_1.output.low" configurationId="p22_1"/>
<configSetting altId="p22_3.output.low" configurationId="p22_3"/>
<configSetting altId="sci0.rxd_miso0.p16_6" configurationId="sci0.rxd_miso0" isUsedByDriver="true"/>
<configSetting altId="sci0.txd_mosi0.p16_5" configurationId="sci0.txd_mosi0" isUsedByDriver="true"/>
<configSetting altId="sci3.rxd_miso3.p17_7" configurationId="sci3.rxd_miso3"/>
<configSetting altId="sci3.txd_mosi3.p18_0" configurationId="sci3.txd_mosi3"/>
<configSetting altId="spi2.spi_miso2.p18_6" configurationId="spi2.spi_miso2"/>
<configSetting altId="spi2.spi_mosi2.p18_5" configurationId="spi2.spi_mosi2"/>
<configSetting altId="spi2.spi_rspck2.p18_4" configurationId="spi2.spi_rspck2"/>
<configSetting altId="spi2.spi_ssl20.p21_1" configurationId="spi2.spi_ssl20"/>
<configSetting altId="usb_hs.usb_ovrcur.p17_5" configurationId="usb_hs.usb_ovrcur"/>
<configSetting altId="usb_hs.usb_vbusen.p19_0" configurationId="usb_hs.usb_vbusen"/>
<configSetting altId="usb_hs.usb_vbusin.p07_4" configurationId="usb_hs.usb_vbusin"/>
<configSetting altId="xspi0.xspi0_ckn.p14_5" configurationId="xspi0.xspi0_ckn"/>
<configSetting altId="xspi0.xspi0_ckp.p14_6" configurationId="xspi0.xspi0_ckp"/>
<configSetting altId="xspi0.xspi0_cs0_hash.p15_7" configurationId="xspi0.xspi0_cs0_hash"/>
<configSetting altId="xspi0.xspi0_cs1_hash.p16_0" configurationId="xspi0.xspi0_cs1_hash"/>
<configSetting altId="xspi0.xspi0_ds.p14_4" configurationId="xspi0.xspi0_ds"/>
<configSetting altId="xspi0.xspi0_ecs0_hash.p14_2" configurationId="xspi0.xspi0_ecs0_hash"/>
<configSetting altId="xspi0.xspi0_io0.p14_7" configurationId="xspi0.xspi0_io0"/>
<configSetting altId="xspi0.xspi0_io1.p15_0" configurationId="xspi0.xspi0_io1"/>
<configSetting altId="xspi0.xspi0_io2.p15_1" configurationId="xspi0.xspi0_io2"/>
<configSetting altId="xspi0.xspi0_io3.p15_2" configurationId="xspi0.xspi0_io3"/>
<configSetting altId="xspi0.xspi0_io4.p15_3" configurationId="xspi0.xspi0_io4"/>
<configSetting altId="xspi0.xspi0_io5.p15_4" configurationId="xspi0.xspi0_io5"/>
<configSetting altId="xspi0.xspi0_io6.p15_5" configurationId="xspi0.xspi0_io6"/>
<configSetting altId="xspi0.xspi0_io7.p15_6" configurationId="xspi0.xspi0_io7"/>
<configSetting altId="xspi0.xspi0_reset0_hash.p16_1" configurationId="xspi0.xspi0_reset0_hash"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>

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mainmenu "RT-Thread Configuration"
BSP_DIR := .
RTT_DIR := ../../..
# you can change the RTT_ROOT default "rt-thread"
# example : default "F:/git_repositories/rt-thread"
PKGS_DIR := packages
ENV_DIR := /
source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "../libraries/Kconfig"
source "$(BSP_DIR)/board/Kconfig"

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# Renesas RSK-RZN2L Development Board BSP Documentation
**English** | [**中文**](./README_zh.md)
## Introduction
This document provides the BSP (Board Support Package) for the Renesas RSK-RZN2L development board. By following the Quick Start Guide, developers can quickly get started with the BSP and run RT-Thread on the development board.
The main contents include:
- Development Board Introduction
- BSP Quick Start Guide
## Development Board Introduction
The RSK-RZN2L MCU evaluation board is based on Renesas RZ/N2L and is designed for developing embedded system applications with flexible software package configuration and IDE support.
The front appearance of the development board is shown below:
![image-20240914173709363](figures/image-20240914173709363.png)
The commonly used **onboard resources** for this development board are as follows:
- MPU: R9A07G084M04GBG, maximum operating frequency of 400MHz, Arm® Cortex®-R52 with on-chip FPU (Floating Point Unit) and NEON™, 1.5 MB on-chip SRAM, Ethernet MAC, EtherCAT, USB 2.0 High-Speed, CAN/CANFD, various communication interfaces such as xSPI and ΔΣ interfaces, and security functions.
- Debug Interface: Onboard J-Link interface
- Expansion Interface: Two PMOD connectors
**More detailed information and tools**
## Peripheral Support
The current peripheral support in this BSP is as follows:
| **On-chip Peripheral** | **Support Status** | **Remarks** |
| :----------------- | :----------------- | :------------- |
| UART | Supported | UART0 is the default log output port |
| GPIO | Supported | |
| HWIMER | Supported | |
| IIC | Supported | |
| WDT | Supported | |
| RTC | Supported | |
| ADC | Supported | |
| DAC | Supported | |
| SPI | Supported | |
| FLASH | Supported | |
| PWM | Supported | |
| CAN | Supported | |
| ETH | Supported | |
| More updates... | | |
## Instructions
The instructions are divided into the following two sections:
- Quick Start
This section is for beginners who are new to RT-Thread. By following simple steps, you can run the RT-Thread OS on this development board and observe the experimental results.
- Advanced Usage
This section is for developers who want to use more resources on the development board with RT-Thread. Using the ENV tool to configure the BSP, you can enable more onboard resources and achieve more advanced features.
### Quick Start
Currently, this BSP only provides an IAR project. Below is an example of how to get the system running using the [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) development environment.
**Hardware Connection**
Connect the development board to the PC using a USB data cable, and use the J-Link interface to download and debug programs.
**Compilation and Download**
- Go to the BSP directory, open ENV, and use the command `scons --target=iar` to generate the IAR project.
- Compile: Double-click the `project.eww` file to open the IAR project and compile the program.
- Debug: Click `Project->Download and Debug` in the IAR toolbar to download and start debugging.
**View Running Results**
After successfully downloading the program, the system will run automatically and print system information.
Connect the corresponding serial port of the development board to the PC. Open the corresponding serial port in a terminal tool (115200-8-1-N). After resetting the device, you can see the RT-Thread output. Enter the `help` command to view the supported commands in the system.
```bash
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Mar 14 2024 18:26:01
2006 - 2024 Copyright by RT-Thread team
Hello RT-Thread!
==================================================
This is a iar project which mode is xspi0 execution!
==================================================
msh >help
RT-Thread shell commands:
clear - clear the terminal screen
version - show RT-Thread version information
list - list objects
backtrace - print backtrace of a thread
help - RT-Thread shell help
ps - List threads in the system
free - Show the memory usage in the system
pin - pin [option]
msh >
```
**Application Entry Function**
The application layer's entry function is in `src\hal_entry.c` in the `void hal_entry(void)` function. User source files can be placed directly in the `src` directory.
```c
#define LED_PIN BSP_IO_PORT_18_PIN_2 /* Onboard LED pins */
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
rt_kprintf("==================================================\n");
rt_kprintf("This is a iar project which mode is xspi0 execution!\n");
rt_kprintf("==================================================\n");
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### Advanced Usage
**Resources and Documentation**
- [Development Board Official Homepage](https://www.renesas.cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzn2l-integrated-tsn-compliant-3-port-gigabit-ethernet-switch-enables-various-industrial-applications)
- [Development Board Data Sheet](https://www.renesas.cn/zh/document/dst/rzn2l-group-datasheet?r=1622651)
- [Development Board Hardware Manual](https://www.renesas.cn/zh/document/mah/rzn2l-group-users-manual-hardware?r=1622651)
- [RZ/N2L MCU Quick Start Guide](https://www.renesas.cn/zh/document/apn/rzt2-rzn2-device-setup-guide-flash-boot-application-note?r=1622651)
- [RZ/N2L Easy Download Guide](https://www.renesas.cn/zh/document/gde/rzn2l-easy-download-guide?r=1622651)
- [Renesas RZ/N2L Group](https://www.renesas.cn/zh/document/fly/renesas-rzn2l-group?r=1622651)
**FSP Configuration**
If you need to modify Renesas BSP peripheral configurations or add new peripheral ports, you will need to use the Renesas [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) configuration tool. Please follow the steps below. If you encounter any issues during the configuration, feel free to ask on the [RT-Thread Community Forum](https://club.rt-thread.org/).
1. [Download the Flexible Software Package (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v2.0.0/setup_rznfsp_v2_0_0_rzsc_v2024-01.1.exe), please use version FSP 2.0.0.
2. Refer to the document [How to Import Board Support Package](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191) to add the **"RSK-RZN2L Board Support Package"** to FSP.
3. Refer to the document: [RA Series Using FSP to Configure Peripheral Drivers](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动).
**ENV Configuration**
- How to use the ENV tool: [RT-Thread ENV Tool User Manual](https://www.rt-thread.org/document/site/#/development-tools/env/env)
By default, this BSP only enables UART0. To use more advanced features like components, software packages, etc., you need to configure the BSP using the ENV tool.
Steps:
1. Open the env tool in the BSP directory.
2. Enter the `menuconfig` command to configure the project. After configuration, save and exit.
3. Enter the `pkgs --update` command to update the software packages.
4. Enter the `scons --target=iar` command to regenerate the project.
## Contact Information
If you have any thoughts or suggestions during usage, feel free to contact us via the [RT-Thread Community Forum](https://club.rt-thread.org/).
## Contribute Code
If you are interested in the RSK-RZN2L and have some exciting projects to share with the community, we welcome your code contributions. You can refer to [How to Contribute Code to RT-Thread](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github).

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# 瑞萨 RSK-RZN2L 开发板 BSP 说明
**中文** | [**English**](./README.md)
## 简介
本文档为瑞萨 RSK-RZN2L 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
主要内容如下：
- 开发板介绍
- BSP 快速上手指南
## 开发板介绍
基于瑞萨 RZ/N2L 开发的 RSK-RZN2L MCU 评估板，通过灵活配置软件包和 IDE，对嵌入系统应用程序进行开发。
开发板正面外观如下图：
![image-20240914173709363](figures/image-20240914173709363.png)
该开发板常用 **板载资源** 如下：
- MPU：R9A07G084M04GBG，最大工作频率 400MHz，Arm® Cortex®-R52 片上浮点单元（FPU）和 NEON™，1.5 MB 片上 SRAM，Ethernet MAC，EtherCAT，USB 2.0 高速，CAN/CANFD，xSPI 和 ΔΣ 接口等各种通信接口，以及安全功能。
- 调试接口：板载 J-Link 接口
- 扩展接口：两个 PMOD 连接器
**更多详细资料及工具**
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------------- | :------------- |
| UART | 支持 | UART0 为默认日志输出端口 |
| GPIO | 支持 | |
| HWIMER | 支持 | |
| IIC | 支持 | |
| WDT | 支持 | |
| RTC | 支持 | |
| ADC | 支持 | |
| DAC | 支持 | |
| SPI | 支持 | |
| FLASH | 支持 | |
| PWM | 支持 | |
| CAN | 支持 | |
| ETH | 支持 | |
| 持续更新中... | | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 目前仅提供 IAR 工程。下面以 [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) 开发环境为例，介绍如何将系统运行起来。
**硬件连接**
使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。
**编译下载**
- 进入 bsp 目录下，打开 ENV 使用命令 `scons --target=iar` 生成 IAR工程。
- 编译：双击 project.eww 文件，打开 IAR 工程，编译程序。
- 调试：IAR 左上方导航栏点击 `Project->Download and Debug`下载并启动调试。
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
\ | /
- RT - Thread Operating System
/ | \ 5.1.0 build Mar 14 2024 18:26:01
2006 - 2024 Copyright by RT-Thread team
Hello RT-Thread!
==================================================
This is a iar project which mode is xspi0 execution!
==================================================
msh >help
RT-Thread shell commands:
clear - clear the terminal screen
version - show RT-Thread version information
list - list objects
backtrace - print backtrace of a thread
help - RT-Thread shell help
ps - List threads in the system
free - Show the memory usage in the system
pin - pin [option]
msh >
```
**应用入口函数**
应用层的入口函数在 **src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
```c
#define LED_PIN BSP_IO_PORT_18_PIN_2 /* Onboard LED pins */
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
rt_kprintf("==================================================\n");
rt_kprintf("This is a iar project which mode is xspi0 execution!\n");
rt_kprintf("==================================================\n");
while (1)
{
rt_pin_write(LED_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### 进阶使用
**资料及文档**
- [开发板官网主页](https://www.renesas.cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzn2l-integrated-tsn-compliant-3-port-gigabit-ethernet-switch-enables-various-industrial-applications)
- [开发板数据手册](https://www.renesas.cn/zh/document/dst/rzn2l-group-datasheet?r=1622651)
- [开发板硬件手册](https://www.renesas.cn/zh/document/mah/rzn2l-group-users-manual-hardware?r=1622651)
- [RZ/N2L MCU 快速入门指南](https://www.renesas.cn/zh/document/apn/rzt2-rzn2-device-setup-guide-flash-boot-application-note?r=1622651)
- [RZ/N2L Easy Download Guide](https://www.renesas.cn/zh/document/gde/rzn2l-easy-download-guide?r=1622651)
- [Renesas RZ/N2L Group](https://www.renesas.cn/zh/document/fly/renesas-rzn2l-group?r=1622651)
**FSP 配置**
需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
1. [下载灵活配置软件包 (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v2.0.0/setup_rznfsp_v2_0_0_rzsc_v2024-01.1.exe)，请使用 FSP 2.0.0 版本
2. 如何将 **”RSK-RZN2L板级支持包“**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
3. 请参考文档：[RA系列使用FSP配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)。
**ENV 配置**
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
此 BSP 默认只开启了 UART0 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=iar` 命令重新生成工程。
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## 贡献代码
如果您对 RSK-RZN2L 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

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# for module compiling
import os
Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
CPPPATH = [cwd]
group = []
list = os.listdir(cwd)
if rtconfig.PLATFORM in ['iccarm']:
group = DefineGroup('', src, depend = [''], CPPPATH = CPPPATH)
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
CPPPATH = [cwd]
src = Glob('./src/*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
Return('group')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
rtconfig.BSP_LIBRARY_TYPE = None
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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menu "Hardware Drivers Config"
config SOC_R9A07G084
bool
select SOC_SERIES_R9A07G0
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_ETHERCAT_EOE
bool "Enable EtherCAT EOE example"
select BSP_USING_ETH
default n
if BSP_USING_ETHERCAT_EOE
config RT_LWIP_IPADDR
string "set static ip address for eoe slaver"
default "192.168.10.100"
config RT_LWIP_GWADDR
string "set static gateway address for eoe slaver"
default "192.168.10.1"
config RT_LWIP_MSKADDR
string "set static mask address for eoe slaver"
default "255.255.255.0"
endif
endmenu
menu "On-chip Peripheral Drivers"
rsource "../../libraries/HAL_Drivers/Kconfig"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_UART
menuconfig BSP_USING_UART0
bool "Enable UART0"
default n
if BSP_USING_UART0
config BSP_UART0_RX_USING_DMA
bool "Enable UART0 RX DMA"
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
default n
config BSP_UART0_TX_USING_DMA
bool "Enable UART0 TX DMA"
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
default n
config BSP_UART0_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART0_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_CANFD
bool "Enable CANFD"
default n
select RT_USING_CAN
select RT_CAN_USING_CANFD
if BSP_USING_CANFD
config BSP_USING_CANFD0
bool "Enable CANFD0"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C BUS"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
config BSP_USING_HW_I2C
bool "Enable Hardware I2C BUS"
default n
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C0
bool "Enable Hardware I2C0 BUS"
default n
endif
if BSP_USING_HW_I2C
config BSP_USING_HW_I2C1
bool "Enable Hardware I2C1 BUS"
default n
endif
if !BSP_USING_HW_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default y
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
hex "i2c1 scl pin number"
range 0x0000 0x0B0F
default 0x0B03
config BSP_I2C1_SDA_PIN
hex "I2C1 sda pin number"
range 0x0000 0x0B0F
default 0x050E
endif
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM0
bool "Enable TIM0"
default n
config BSP_USING_TIM1
bool "Enable TIM1"
default n
endif
config BSP_USING_ETH
bool "Enable Ethernet"
select RT_USING_SAL
select RT_USING_LWIP
select RT_USING_NETDEV
default n
endmenu
menu "Board extended module Drivers"
menuconfig BSP_USING_RW007
bool "Enable RW007"
default n
select PKG_USING_RW007
select BSP_USING_SPI
select BSP_USING_SPI2
select RT_USING_MEMPOOL
select RW007_NOT_USE_EXAMPLE_DRIVERS
if BSP_USING_RW007
config RA_RW007_SPI_BUS_NAME
string "RW007 BUS NAME"
default "spi2"
config RA_RW007_CS_PIN
hex "(HEX)CS pin index"
default 0x1207
config RA_RW007_BOOT0_PIN
hex "(HEX)BOOT0 pin index (same as spi clk pin)"
default 0x1204
config RA_RW007_BOOT1_PIN
hex "(HEX)BOOT1 pin index (same as spi cs pin)"
default 0x1207
config RA_RW007_INT_BUSY_PIN
hex "(HEX)INT/BUSY pin index"
default 0x1102
config RA_RW007_RST_PIN
hex "(HEX)RESET pin index"
default 0x1706
endif
endmenu
endmenu

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import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
CPPPATH = [cwd]
src = Glob('*.c')
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-03-11 Wangyuqiang first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <rtdef.h>
#include <cp15.h>
#include <hal_data.h>
#define RZ_SRAM_SIZE 512 /* The SRAM size of the chip needs to be modified */
#define RZ_SRAM_END (0x10000000 + RZ_SRAM_SIZE * 1024 - 1)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
#define HEAP_BEGIN (0x10000000)
#endif
#define HEAP_END RZ_SRAM_END
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define MAX_HANDLERS (512)
#define GIC_IRQ_START 0
#define GIC_ACK_INTID_MASK (0x000003FFU)
/* number of interrupts on board */
#define ARM_GIC_NR_IRQS (448)
/* only one GIC available */
#define ARM_GIC_MAX_NR 1
/* end defined */
#define GICV3_DISTRIBUTOR_BASE_ADDR (0x100000)
/* the basic constants and interfaces needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
rt_uint32_t gic_base;
__get_cp(15, 1, gic_base, 15, 3, 0);
return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR;
}
#ifdef __cplusplus
}
#endif
#endif

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import os
from building import *
objs = []
src = Glob('*.c')
cwd = GetCurrentDir()
CPPPATH = [cwd]
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-03-11 Wangyuqiang first version
*/
/* Number of IRQ channels on the device */
#define RA_IRQ_MAX 16
/* PIN to IRQx table */
#define PIN2IRQX_TABLE \
{ \
switch (pin) \
{ \
case BSP_IO_PORT_00_PIN_1: \
case BSP_IO_PORT_09_PIN_2: \
case BSP_IO_PORT_18_PIN_3: \
return 0; \
case BSP_IO_PORT_00_PIN_3: \
case BSP_IO_PORT_07_PIN_4: \
case BSP_IO_PORT_18_PIN_4: \
return 1; \
case BSP_IO_PORT_01_PIN_2: \
return 2; \
case BSP_IO_PORT_01_PIN_4: \
return 3; \
case BSP_IO_PORT_02_PIN_0: \
case BSP_IO_PORT_22_PIN_2: \
return 4; \
case BSP_IO_PORT_03_PIN_5: \
case BSP_IO_PORT_13_PIN_2: \
return 5; \
case BSP_IO_PORT_14_PIN_2: \
case BSP_IO_PORT_21_PIN_5: \
return 6; \
case BSP_IO_PORT_16_PIN_3: \
return 7; \
case BSP_IO_PORT_03_PIN_6: \
case BSP_IO_PORT_16_PIN_6: \
return 8; \
case BSP_IO_PORT_03_PIN_7: \
case BSP_IO_PORT_21_PIN_6: \
return 9; \
case BSP_IO_PORT_04_PIN_4: \
case BSP_IO_PORT_18_PIN_1: \
case BSP_IO_PORT_21_PIN_7: \
return 10; \
case BSP_IO_PORT_10_PIN_4: \
case BSP_IO_PORT_18_PIN_6: \
return 11; \
case BSP_IO_PORT_05_PIN_0: \
case BSP_IO_PORT_05_PIN_4: \
case BSP_IO_PORT_05_PIN_6: \
return 12; \
case BSP_IO_PORT_00_PIN_4: \
case BSP_IO_PORT_00_PIN_7: \
case BSP_IO_PORT_05_PIN_1: \
return 13; \
case BSP_IO_PORT_02_PIN_2: \
case BSP_IO_PORT_03_PIN_0: \
case BSP_IO_PORT_05_PIN_2: \
return 14; \
case BSP_IO_PORT_02_PIN_3: \
case BSP_IO_PORT_05_PIN_3: \
case BSP_IO_PORT_22_PIN_0: \
return 15; \
default : \
return -1; \
} \
}

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<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<iarProjectConnection version="1.8" name="Flex Software">
<device>
<name>R9A07G084M04</name>
</device>
<includePath>
<path>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</path>
<path>$PROJ_DIR$/rzn/fsp/inc</path>
<path>$PROJ_DIR$/rzn/fsp/inc/api</path>
<path>$PROJ_DIR$/rzn/fsp/inc/instances</path>
<path>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</path>
<path>$PROJ_DIR$/rzn_gen</path>
<path>$PROJ_DIR$/src</path>
<path>$PROJ_DIR$</path>
</includePath>
<defines>
<define>_RZN_ORDINAL=1</define>
<define>_RZN_CORE=CR52_0</define>
<define>_RENESAS_RZN_</define>
</defines>
<asmIncludePath>
<path>$PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include</path>
<path>$PROJ_DIR$/rzn/fsp/inc</path>
<path>$PROJ_DIR$/rzn/fsp/inc/api</path>
<path>$PROJ_DIR$/rzn/fsp/inc/instances</path>
<path>$PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg</path>
<path>$PROJ_DIR$/rzn_cfg/fsp_cfg/bsp</path>
<path>$PROJ_DIR$/rzn_gen</path>
<path>$PROJ_DIR$/src</path>
<path>$PROJ_DIR$</path>
</asmIncludePath>
<asmDefines>
<define>_RZN_ORDINAL=1</define>
<define>_RZN_CORE=CR52_0</define>
<define>_RENESAS_RZN_</define>
</asmDefines>
<linkerFile>
<override>true</override>
<path>$PROJ_DIR$/script/fsp_xspi0_boot.icf</path>
</linkerFile>
<linkerExtraOptions>
<arg>--config_search "$PROJ_DIR$"</arg>
</linkerExtraOptions>
<programEntryPoint>
<symbol>system_init</symbol>
</programEntryPoint>
<customArgVars>
<group name="RA Smart Configurator">
<argVar>
<name>RASC_EXE_PATH</name>
<value>D:\manufacture_apps\Renesas\fsp\rzn_v2.0.0\eclipse\rasc.exe</value>
</argVar>
</group>
</customArgVars>
<files>
<group name="Components">
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h</path>
<path>rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h</path>
<path>rzn/arm/CMSIS_5/LICENSE.txt</path>
<path>rzn/board/rzn2l_rsk/board.h</path>
<path>rzn/board/rzn2l_rsk/board_ethernet_phy.h</path>
<path>rzn/board/rzn2l_rsk/board_init.c</path>
<path>rzn/board/rzn2l_rsk/board_init.h</path>
<path>rzn/board/rzn2l_rsk/board_leds.c</path>
<path>rzn/board/rzn2l_rsk/board_leds.h</path>
<path>rzn/fsp/inc/api/bsp_api.h</path>
<path>rzn/fsp/inc/api/r_ioport_api.h</path>
<path>rzn/fsp/inc/api/r_transfer_api.h</path>
<path>rzn/fsp/inc/api/r_uart_api.h</path>
<path>rzn/fsp/inc/fsp_common_api.h</path>
<path>rzn/fsp/inc/fsp_features.h</path>
<path>rzn/fsp/inc/fsp_version.h</path>
<path>rzn/fsp/inc/instances/r_ioport.h</path>
<path>rzn/fsp/inc/instances/r_sci_uart.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c</path>
<path>rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_cache.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_cache.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_clocks.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_clocks.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_common.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_common.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_delay.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_delay.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_io.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_io.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_irq.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_irq.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_reset.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_reset.h</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c</path>
<path>rzn/fsp/src/bsp/mcu/all/bsp_tfu.h</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c</path>
<path>rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h</path>
<path>rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h</path>
<path>rzn/fsp/src/r_ioport/r_ioport.c</path>
<path>rzn/fsp/src/r_sci_uart/r_sci_uart.c</path>
</group>
<group name="Build Configuration">
<path>rzn_cfg/fsp_cfg/bsp/board_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h</path>
<path>rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h</path>
<path>rzn_cfg/fsp_cfg/r_ioport_cfg.h</path>
<path>rzn_cfg/fsp_cfg/r_sci_uart_cfg.h</path>
</group>
<group name="Generated Data">
<path>rzn_gen/bsp_clock_cfg.h</path>
<path>rzn_gen/common_data.c</path>
<path>rzn_gen/common_data.h</path>
<path>rzn_gen/hal_data.c</path>
<path>rzn_gen/hal_data.h</path>
<path>rzn_gen/main.c</path>
<path>rzn_gen/pin_data.c</path>
<path>rzn_gen/vector_data.c</path>
<path>rzn_gen/vector_data.h</path>
</group>
<group name="Program Entry">
<path>src/hal_entry.c</path>
</group>
</files>
</iarProjectConnection>

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/* generated memory regions file - do not edit */
define symbol ATCM_START = 0x00000000;
define symbol ATCM_LENGTH = 0x20000;
define symbol BTCM_START = 0x00100000;
define symbol BTCM_LENGTH = 0x20000;
define symbol SYSTEM_RAM_START = 0x10000000;
define symbol SYSTEM_RAM_LENGTH = 0x180000;
define symbol SYSTEM_RAM_MIRROR_START = 0x30000000;
define symbol SYSTEM_RAM_MIRROR_LENGTH = 0x180000;
define symbol xSPI0_CS0_SPACE_MIRROR_START = 0x40000000;
define symbol xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol xSPI0_CS1_SPACE_MIRROR_START = 0x44000000;
define symbol xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol xSPI1_CS0_SPACE_MIRROR_START = 0x48000000;
define symbol xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS0_SPACE_MIRROR_START = 0x50000000;
define symbol CS0_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS2_SPACE_MIRROR_START = 0x54000000;
define symbol CS2_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS3_SPACE_MIRROR_START = 0x58000000;
define symbol CS3_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol CS5_SPACE_MIRROR_START = 0x5C000000;
define symbol CS5_SPACE_MIRROR_LENGTH = 0x4000000;
define symbol xSPI0_CS0_SPACE_START = 0x60000000;
define symbol xSPI0_CS0_SPACE_LENGTH = 0x4000000;
define symbol xSPI0_CS1_SPACE_START = 0x64000000;
define symbol xSPI0_CS1_SPACE_LENGTH = 0x4000000;
define symbol xSPI1_CS0_SPACE_START = 0x68000000;
define symbol xSPI1_CS0_SPACE_LENGTH = 0x4000000;
define symbol CS0_SPACE_START = 0x70000000;
define symbol CS0_SPACE_LENGTH = 0x4000000;
define symbol CS2_SPACE_START = 0x74000000;
define symbol CS2_SPACE_LENGTH = 0x4000000;
define symbol CS3_SPACE_START = 0x78000000;
define symbol CS3_SPACE_LENGTH = 0x4000000;
define symbol CS5_SPACE_START = 0x7C000000;
define symbol CS5_SPACE_LENGTH = 0x4000000;

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
/* kservice optimization */
/* end of kservice optimization */
/* klibc optimization */
/* end of klibc optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 512
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* end of RT-Thread Kernel */
#define RT_USING_HW_ATOMIC
#define ARCH_ARM
#define ARCH_ARM_CORTEX_R
#define ARCH_ARM_CORTEX_R52
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
/* end of DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V2
#define RT_SERIAL_USING_DMA
#define RT_USING_PIN
/* end of Device Drivers */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
/* end of Network */
/* Memory protection */
/* end of Memory protection */
/* Utilities */
/* end of Utilities */
/* Using USB legacy version */
/* end of Using USB legacy version */
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* end of Marvell WiFi */
/* Wiced WiFi */
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
/* end of Wi-Fi */
/* IoT Cloud */
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
/* end of sensors drivers */
/* touch drivers */
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* end of project laboratory */
/* samples: kernel and components samples */
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
/* end of Projects and Demos */
/* Sensors */
/* end of Sensors */
/* Display */
/* end of Display */
/* Timing */
/* end of Timing */
/* Data Processing */
/* end of Data Processing */
/* Data Storage */
/* Communication */
/* end of Communication */
/* Device Control */
/* end of Device Control */
/* Other */
/* end of Other */
/* Signal IO */
/* end of Signal IO */
/* Uncategorized */
/* end of Arduino libraries */
/* end of RT-Thread online packages */
#define SOC_FAMILY_RENESAS
#define SOC_SERIES_R9A07G0
/* Hardware Drivers Config */
#define SOC_R9A07G084
/* Onboard Peripheral Drivers */
/* end of Onboard Peripheral Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_UART0_RX_BUFSIZE 256
#define BSP_UART0_TX_BUFSIZE 0
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
/* end of Board extended module Drivers */
/* end of Hardware Drivers Config */
#endif

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import os
import sys
# toolchains options
ARCH='arm'
CPU='cortex-r52'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armclang'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iccarm'
EXEC_PATH = r'D:/IAR Systems/Embedded Workbench 9.2'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
# BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
NM = PREFIX + 'nm'
DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=hard -mfpu=neon-fp-armv8 -munaligned-access -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -funwind-tables'
CFLAGS = DEVICE + ' -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=arm '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp_xspi0_boot.ld -L script/'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g -Wall'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -Os'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n'
# POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'iccarm':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-R52'
CFLAGS += ' -e'
CFLAGS += ' --arm'
CFLAGS += ' --float-abi=hard'
CFLAGS += ' --fpu=neon-fp-armv8'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-R52'
AFLAGS += ' --arm'
AFLAGS += ' --float-abi hard'
AFLAGS += ' --fpu neon-fp-armv8'
# AFLAGS += ' --unaligned-access'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "script/fsp_xspi0_boot.icf"'
LFLAGS += ' --entry Reset_Handler'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
def dist_handle(BSP_ROOT, dist_dir):
import sys
cwd_path = os.getcwd()
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
from sdk_dist import dist_do_building
dist_do_building(BSP_ROOT, dist_dir)

28
bsp/renesas/rzn2l_rsk/rzn/SConscript Normal file
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
from gcc import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
Return('group')
elif rtconfig.PLATFORM in GetGCCLikePLATFORM():
if GetOption('target') != 'mdk5':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += Glob(cwd + '/fsp/src/bsp/mcu/all/cr/*.c')
src += Glob(cwd + '/fsp/src/bsp/mcu/r*/*.c')
src += Glob(cwd + '/fsp/src/r_*/*.c')
src += Glob(cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core_R/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('rzn', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

290
bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h Normal file
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @date 31. August 2021
******************************************************************************/
/*
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This file is based on the "\CMSIS\Core\Include\cmsis_compliler.h"
*
* Changes:
* - No Changes.
*/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @date 31. August 2021
******************************************************************************/
/*
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This file is based on the "\CMSIS\Core\Include\cmsis_version.h"
*
* Changes:
* - No Changes.
*/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cr52.h
* @brief CMSIS Cortex-R52 Core Peripheral Access Layer Header File
* @date 31. August 2021
******************************************************************************/
/*
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This file is based on the "\CMSIS\Core\Include\core_armv8mml.h"
*
* Changes:
* Renesas Electronics Corporation on 2021-08-31
* - Changed to be related to Cortex-R52 by
*/
/*
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CR52_H_GENERIC
#define __CORE_CR52_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_R52
@{
*/
#if defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#define __FPU_D32 1U
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#ifndef __ARMVFP_D16__
#define __FPU_D32 1U
#endif
#else
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0U
#endif
#else
#define __FPU_USED 0U
#endif
#endif
#include "cmsis_version.h"
/* CMSIS CR52 definitions */
#define __CR52_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CR52_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CR52_CMSIS_VERSION ((__CR52_CMSIS_VERSION_MAIN << 16U) | \
__CR52_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_R (52U) /*!< Cortex-R Core */
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CR52_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CR52_H_DEPENDANT
#define __CORE_CR52_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_R52 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_GIC Generic Interrupt Controller (GIC)
\brief Type definitions for the GIC Registers
@{
*/
/**
\brief Structure type to access the Generic Interrupt Controller (GIC) for GICD.
*/
typedef struct
{
__IOM uint32_t GICD_CTLR; /*!< Offset: 0x0000 (R/W) Distributor Control Register */
__IM uint32_t GICD_TYPER; /*!< Offset: 0x0004 (R/ ) Interrupt Controller Type Register */
__IM uint32_t GICD_IIDR; /*!< Offset: 0x0008 (R/ ) Distributor Implementer Identification Register */
uint32_t RESERVED0[30U];
__IOM uint32_t GICD_IGROUPR[30U]; /*!< Offset: 0x0084 (R/W) Interrupt Group Registers 1 - 30 */
uint32_t RESERVED1[2U];
__IOM uint32_t GICD_ISENABLER[30U]; /*!< Offset: 0x0104 (R/W) Interrupt Set-Enable Registers 1 - 30 */
uint32_t RESERVED2[2U];
__IOM uint32_t GICD_ICENABLER[30U]; /*!< Offset: 0x0184 (R/W) Interrupt Clear-Enable Registers 1 - 30 */
uint32_t RESERVED3[2U];
__IOM uint32_t GICD_ISPENDR[30U]; /*!< Offset: 0x0204 (R/W) Interrupt Set-Pending Registers 1 - 30 */
uint32_t RESERVED4[2U];
__IOM uint32_t GICD_ICPENDR[30U]; /*!< Offset: 0x0284 (R/W) Interrupt Clear-Pending Registers 1 - 30 */
uint32_t RESERVED5[2U];
__IOM uint32_t GICD_ISACTIVER[30U]; /*!< Offset: 0x0304 (R/W) Interrupt Set-Active Registers 1 - 30 */
uint32_t RESERVED6[2U];
__IOM uint32_t GICD_ICACTIVER[30U]; /*!< Offset: 0x0384 (R/W) Interrupt Clear-Active Registers 1 - 30 */
uint32_t RESERVED7[9U];
__IOM uint32_t GICD_IPRIORITYR[240U]; /*!< Offset: 0x0420 (R/W) Interrupt Priority Registers 8 - 247 */
uint32_t RESERVED8[266U];
__IOM uint32_t GICD_ICFGR[60U]; /*!< Offset: 0x0C08 (R/W) Interrupt Configuration Registers 2 - 61 */
} GICD_Type;
/**
\brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for Control target.
*/
typedef struct
{
__IM uint32_t GICR_CTLR; /*!< Offset: 0x0000 (R/ ) Redistributor Control Register */
__IM uint32_t GICR_IIDR; /*!< Offset: 0x0004 (R/ ) Redistributor Implementer Identification Register */
__IM uint32_t GICR_TYPER[2]; /*!< Offset: 0x0008 (R/ ) Redistributor Type Register */
uint32_t RESERVED0;
__IOM uint32_t GICR_WAKER; /*!< Offset: 0x0014 (R/W) Redistributor Wake Register */
} GICR_CONTROL_TARGET_Type;
/**
\brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for SGI and PPI.
*/
typedef struct
{
uint32_t RESERVED0[32];
__IOM uint32_t GICR_IGROUPR0; /*!< Offset: 0x0080 (R/W) Interrupt Group Register 0 */
uint32_t RESERVED1[31];
__IOM uint32_t GICR_ISENABLER0; /*!< Offset: 0x0100 (R/W) Interrupt Set-Enable Register 0 */
uint32_t RESERVED2[31];
__IOM uint32_t GICR_ICENABLER0; /*!< Offset: 0x0180 (R/W) Interrupt Clear-Enable Register 0 */
uint32_t RESERVED3[31];
__IOM uint32_t GICR_ISPENDR0; /*!< Offset: 0x0200 (R/W) Interrupt Set-Pending Register 0 */
uint32_t RESERVED4[31];
__IOM uint32_t GICR_ICPENDR0; /*!< Offset: 0x0280 (R/W) Interrupt Clear-Pending Register 0 */
uint32_t RESERVED5[31];
__IOM uint32_t GICR_ISACTIVER0; /*!< Offset: 0x0300 (R/W) Interrupt Set-Active Register 0 */
uint32_t RESERVED6[31];
__IOM uint32_t GICR_ICACTIVER0; /*!< Offset: 0x0380 (R/W) Interrupt Clear-Active Register 0 */
uint32_t RESERVED7[31];
__IOM uint32_t GICR_IPRIORITYR[8]; /*!< Offset: 0x0400 (R/W) Interrupt Priority Registers 0 - 7 */
uint32_t RESERVED8[504];
__IM uint32_t GICR_ICFGR0; /*!< Offset: 0x0C00 (R/ ) Interrupt Configuration Register 0 */
__IOM uint32_t GICR_ICFGR1; /*!< Offset: 0x0C04 (R/W) Interrupt Configuration Register 1 */
} GICR_SGI_PPI_Type;
/*@} end of group CMSIS_GIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define GIC0_BASE (0x94000000UL) /*!< GIC0 Base Address */
#define GIC1_BASE (0x9C000000UL) /*!< GIC1 Base Address */
#define GICR_TARGET0_BASE (0x00100000UL) /*!< GICR Base Address (for Control target 0) */
#define GICR_TARGET0_SGI_PPI_BASE (0x00110000UL) /*!< GICR Base Address (for SGI and PPI target 0) */
#define GICD0 ((GICD_Type *) GIC0_BASE ) /*!< GICD configuration struct */
#define GICD1 ((GICD_Type *) GIC1_BASE ) /*!< GICD configuration struct */
#define GICR0_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC0_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */
#define GICR1_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC1_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */
#define GICR0_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC0_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */
#define GICR1_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC1_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */
/*@} */
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief Get CPSR Register
This function returns the content of the CPSR Register.
\return CPSR Register value
*/
__STATIC_INLINE uint32_t __get_CPSR(void)
{
register uint32_t __regCPSR __ASM("cpsr");
return(__regCPSR);
}
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
#include <intrinsics.h>
#endif
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CR52_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board.h
* Description : Includes and API function available for this board.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARDS
* @defgroup BOARD_RZN2L_RSK
* @brief BSP for the RZN2L_RSK Board
*
* The RZN2L_RSK is a development kit for the Renesas RZN2L microcontroller.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_H
#define BOARD_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* BSP Board Specific Includes. */
#include "board_init.h"
#include "board_leds.h"
#include "board_ethernet_phy.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define BOARD_RZN2L_RSK
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/** @} (end defgroup BSP_CONFIG_RZN2L) */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RZN2_RSK
* @defgroup BOARD_RZN2_RSK_ETHERNET_PHY Board Ethernet Phy
* @brief Ethernet Phy information for this board.
*
* This is code specific to the RZN2_RSK board.
*
* @{
**********************************************************************************************************************/
#ifndef BSP_ETHERNET_PHY_H
#define BSP_ETHERNET_PHY_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define ETHER_PHY_CFG_TARGET_VSC8541_ENABLE (1)
#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_VSC8541
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Public Functions
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RZN2_RSK_ETHERNET_PHY) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_init.c
* Description : This module calls any initialization code specific to this BSP.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RZN2L_RSK_INIT
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RZN2L_RSK)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @brief Performs any initialization specific to this BSP.
*
* @param[in] p_args Pointer to arguments of the user's choice.
**********************************************************************************************************************/
void bsp_init (void * p_args)
{
FSP_PARAMETER_NOT_USED(p_args);
}
#endif
/** @} (end addtogroup BOARD_RZN2L_RSK_INIT) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_init.h
* Description : This module calls any initialization code specific to this BSP.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RZN2L_RSK
* @defgroup BOARD_RZN2L_RSK_INIT
* @brief Board specific code for the RZN2L_RSK Board
*
* This include file is specific to the RZN2L_RSK board.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_INIT_H
#define BOARD_INIT_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
void bsp_init(void * p_args);
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RZN2L_RSK_INIT) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_leds.c
* Description : This module has information about the LEDs on this board.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BOARD_RZN2L_RSK_LEDS
*
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#if defined(BOARD_RZN2L_RSK)
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Private global variables and functions
**********************************************************************************************************************/
/** Array of LED IOPORT pins. */
static const uint32_t g_bsp_prv_leds[][2] =
{
{(uint32_t) BSP_IO_PORT_18_PIN_2, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED0
{(uint32_t) BSP_IO_PORT_22_PIN_3, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED1
{(uint32_t) BSP_IO_PORT_04_PIN_1, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED2
{(uint32_t) BSP_IO_PORT_17_PIN_3, (uint32_t) BSP_IO_REGION_SAFE} ///< RLED3
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
/** Structure with LED information for this board. */
const bsp_leds_t g_bsp_leds =
{
.led_count = (uint16_t) (sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0])),
.p_leds = g_bsp_prv_leds
};
/***********************************************************************************************************************
* Exported global variables (to be accessed by other files)
**********************************************************************************************************************/
#endif
/** @} (end addtogroup BOARD_RZN2L_RSK_LEDS) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/***********************************************************************************************************************
* File Name : board_leds.h
* Description : This module has information about the LEDs on this board.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup BOARD_RZN2L_RSK
* @defgroup BOARD_RZN2L_RSK_LEDS Board LEDs
* @brief LED information for this board.
*
* This is code specific to the RZN2L_RSK board. It includes info on the number of LEDs and which pins are they
* are on.
*
* @{
**********************************************************************************************************************/
#ifndef BOARD_LEDS_H
#define BOARD_LEDS_H
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Information on how many LEDs and what pins they are on. */
typedef struct st_bsp_leds
{
uint16_t led_count; ///< The number of LEDs on this board
uint32_t const (*p_leds)[2]; ///< Pointer to an array of IOPORT pins for controlling LEDs
} bsp_leds_t;
/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
* found in the bsp_leds_t structure. */
typedef enum e_bsp_led
{
BSP_LED_RLED0 = 0, ///< Green
BSP_LED_RLED1 = 1, ///< Yellow
BSP_LED_RLED2 = 2, ///< Red
BSP_LED_RLED3 = 3, ///< Red
} bsp_led_t;
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Public Functions
**********************************************************************************************************************/
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/** @} (end defgroup BOARD_RZN2L_RSK_LEDS) */

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_API_H
#define BSP_API_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* FSP Common Includes. */
#include "fsp_common_api.h"
/* Gets MCU configuration information. */
#include "bsp_cfg.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic push
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
* We are not modifying these files so we will ignore these warnings temporarily. */
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wsign-conversion"
#endif
/* Vector information for this project. This is generated by the tooling. */
#include "../../src/bsp/mcu/all/bsp_exceptions.h"
#include "vector_data.h"
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic pop
#endif
#if defined(BSP_API_OVERRIDE)
#include BSP_API_OVERRIDE
#else
/* BSP Common Includes. */
#include "../../src/bsp/mcu/all/bsp_common.h"
/* BSP MCU Specific Includes. */
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
#include "../../src/bsp/mcu/all/bsp_irq.h"
#include "../../src/bsp/mcu/all/bsp_io.h"
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
#include "../../src/bsp/mcu/all/bsp_clocks.h"
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
#include "../../src/bsp/mcu/all/bsp_security.h"
/* Factory MCU information. */
#include "../../inc/fsp_features.h"
/* BSP Common Includes (Other than bsp_common.h) */
#include "../../src/bsp/mcu/all/bsp_delay.h"
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_SYSTEM_INTERFACES
* @defgroup IOPORT_API I/O Port Interface
* @brief Interface for accessing I/O ports and configuring I/O functionality.
*
* @section IOPORT_API_SUMMARY Summary
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
* Port and pin direction can be changed.
*
*
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_API_H
#define R_IOPORT_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
#ifndef BSP_OVERRIDE_IOPORT_SIZE_T
/** IO port type used with ports */
typedef uint16_t ioport_size_t; ///< IO port size
#endif
/** Pin identifier and pin configuration value */
typedef struct st_ioport_pin_cfg
{
uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure
bsp_io_port_pin_t pin; ///< Pin identifier
} ioport_pin_cfg_t;
/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */
typedef struct st_ioport_cfg
{
uint16_t number_of_pins; ///< Number of pins for which there is configuration data
ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
const void * p_extend; ///< Pointer to hardware extend configuration
} ioport_cfg_t;
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
*/
typedef void ioport_ctrl_t;
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
typedef struct st_ioport_api
{
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
* multiple pins.
*
* @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Close the API.
*
* @param[in] p_ctrl Pointer to control structure.
**/
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
/** Configure multiple pins.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] p_cfg Pointer to pin configuration data array.
*/
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
/** Configure settings for an individual pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] cfg Configuration options for the pin.
*/
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
/** Read the event input data of the specified pin and return the level.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_event Pointer to return the event data.
*/
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
/** Write pin event data.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin event data is to be written to.
* @param[in] pin_value Level to be written to pin output event.
*/
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
/** Read level of a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be read.
* @param[in] p_pin_value Pointer to return the pin level.
*/
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
/** Write specified level to a pin.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] pin Pin to be written to.
* @param[in] level State to be written to the pin.
*/
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
/** Set the direction of one or more pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port being configured.
* @param[in] direction_values Value controlling direction of pins on port.
* @param[in] mask Mask controlling which pins on the port are to be configured.
*/
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
ioport_size_t mask);
/** Read captured event data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_event_data Pointer to return the event data.
*/
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
/** Write event output data for a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port event data will be written to.
* @param[in] event_data Data to be written as event data to specified port.
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
* being written to port.
*/
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
ioport_size_t mask_value);
/** Read states of pins on the specified port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be read.
* @param[in] p_port_value Pointer to return the port value.
*/
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
/** Write to multiple pins on a port.
*
* @param[in] p_ctrl Pointer to control structure.
* @param[in] port Port to be written to.
* @param[in] value Value to be written to the port.
* @param[in] mask Mask controlling which pins on the port are written to.
*/
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
} ioport_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_ioport_instance
{
ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
} ioport_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_TRANSFER_INTERFACES
* @defgroup TRANSFER_API Transfer Interface
*
* @brief Interface for data transfer functions.
*
* @section TRANSFER_API_SUMMARY Summary
* The transfer interface supports background data transfer (no CPU intervention).
*
*
* @{
**********************************************************************************************************************/
#ifndef R_TRANSFER_API_H
#define R_TRANSFER_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Common error codes and definitions. */
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define TRANSFER_SETTINGS_MODE_BITS (30U)
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
*/
typedef void transfer_ctrl_t;
#ifndef BSP_OVERRIDE_TRANSFER_MODE_T
/** Transfer mode describes what will happen when a transfer request occurs. */
typedef enum e_transfer_mode
{
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
* the destination pointer. The transfer length is decremented and the source and address pointers are
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
* will not cause any further transfers. */
TRANSFER_MODE_NORMAL = 0,
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
TRANSFER_MODE_REPEAT = 1,
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
* After each individual transfer, the source and destination pointers are updated according to
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
* further transfers. */
TRANSFER_MODE_BLOCK = 2,
/** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets
* within a block (to split blocks into arrays of their first data, second data, etc.) */
TRANSFER_MODE_REPEAT_BLOCK = 3
} transfer_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T
/** Transfer size specifies the size of each individual transfer.
* Total transfer length = transfer_size_t * transfer_length_t
*/
typedef enum e_transfer_size
{
TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value
TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value
TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value
} transfer_size_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
typedef enum e_transfer_addr_mode
{
/** Address pointer remains fixed after each transfer. */
TRANSFER_ADDR_MODE_FIXED = 0,
/** Offset is added to the address pointer after each transfer. */
TRANSFER_ADDR_MODE_OFFSET = 1,
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_INCREMENTED = 2,
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
TRANSFER_ADDR_MODE_DECREMENTED = 3
} transfer_addr_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK,
* the selected pointer returns to its original value after each transfer. */
typedef enum e_transfer_repeat_area
{
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_DESTINATION = 0,
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
TRANSFER_REPEAT_AREA_SOURCE = 1
} transfer_repeat_area_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T
/** Chain transfer mode options.
* @note Only applies for DTC. */
typedef enum e_transfer_chain_mode
{
/** Chain mode not used. */
TRANSFER_CHAIN_MODE_DISABLED = 0,
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
TRANSFER_CHAIN_MODE_EACH = 2,
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
TRANSFER_CHAIN_MODE_END = 3
} transfer_chain_mode_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T
/** Interrupt options. */
typedef enum e_transfer_irq
{
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
* the interrupt will occur only after subsequent chained transfer(s) are complete.
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
* prevent activation source interrupts until the transfer is complete. */
TRANSFER_IRQ_END = 0,
/** Interrupt occurs after each transfer.
* @note Not available in all HAL drivers. See HAL driver for details. */
TRANSFER_IRQ_EACH = 1
} transfer_irq_t;
#endif
#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T
/** Callback function parameter data. */
typedef struct st_transfer_callback_args_t
{
void const * p_context; ///< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t.
} transfer_callback_args_t;
#endif
/** Driver specific information. */
typedef struct st_transfer_properties
{
uint32_t block_count_max; ///< Maximum number of blocks
uint32_t block_count_remaining; ///< Number of blocks remaining
uint32_t transfer_length_max; ///< Maximum number of transfers
uint32_t transfer_length_remaining; ///< Number of transfers remaining
} transfer_properties_t;
#ifndef BSP_OVERRIDE_TRANSFER_INFO_T
/** This structure specifies the properties of the transfer.
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
* have a unique transfer_info_t.
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
* structure must remain in scope until the transfer it is used for is closed.
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
typedef struct st_transfer_info
{
union
{
struct
{
uint32_t : 16;
uint32_t : 2;
/** Select what happens to destination pointer after each transfer. */
transfer_addr_mode_t dest_addr_mode : 2;
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
transfer_repeat_area_t repeat_area : 1;
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
* transfers. */
transfer_irq_t irq : 1;
/** Select when the chain transfer ends. */
transfer_chain_mode_t chain_mode : 2;
uint32_t : 2;
/** Select what happens to source pointer after each transfer. */
transfer_addr_mode_t src_addr_mode : 2;
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
transfer_size_t size : 2;
/** Select mode from @ref transfer_mode_t. */
transfer_mode_t mode : 2;
} transfer_settings_word_b;
uint32_t transfer_settings_word;
};
void const * volatile p_src; ///< Source pointer
void * volatile p_dest; ///< Destination pointer
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or
* @ref TRANSFER_MODE_REPEAT (DMAC only) or
* @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */
volatile uint16_t num_blocks;
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT,
* and @ref TRANSFER_MODE_REPEAT_BLOCK
* see HAL driver for details. */
volatile uint16_t length;
} transfer_info_t;
#endif
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
* initialized. */
typedef struct st_transfer_cfg
{
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
* an array of chained transfers that will be completed in order. */
transfer_info_t * p_info;
void const * p_extend; ///< Extension parameter for hardware specific settings.
} transfer_cfg_t;
/** Select whether to start single or repeated transfer with software start. */
typedef enum e_transfer_start_mode
{
TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer.
TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete.
} transfer_start_mode_t;
/** Transfer functions implemented at the HAL layer will follow this API. */
typedef struct st_transfer_api
{
/** Initial configuration.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
* must be set by user.
*/
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
/** Reconfigure the transfer.
* Enable the transfer if p_info is valid.
*
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
* @param[in] p_info Pointer to a new transfer info structure.
*/
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
* Enable the transfer if p_src, p_dest, and length are valid.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
* repeat mode. Not used in repeat mode for DTC.
*/
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint16_t const num_transfers);
/** Enable transfer. Transfers occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source).
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
/** Disable transfer. Transfers do not occur after the activation source event (or when
* @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source).
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
* transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
/** Start transfer in software.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
* @note Not supported for DTC.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] mode Select mode from @ref transfer_start_mode_t.
*/
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
* @note Not supported for DTC.
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
* @warning Only works if no peripheral event is chosen as the DMAC activation source.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
/** Provides information about this transfer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[out] p_properties Driver specific information.
*/
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
*/
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
/** To update next transfer information without interruption during transfer.
* Allow further transfer continuation.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
* @param[in] num_transfers Transfer length in normal mode or block mode.
*/
fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
uint32_t const num_transfers);
/** Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
* @param[in] p_callback Callback function to register
* @param[in] p_context Pointer to send to callback function
* @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *),
void const * const p_context, transfer_callback_args_t * const p_callback_memory);
} transfer_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_transfer_instance
{
transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
transfer_api_t const * p_api; ///< Pointer to the API structure for this instance
} transfer_instance_t;
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
/*******************************************************************************************************************//**
* @} (end defgroup TRANSFER_API)
**********************************************************************************************************************/

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @ingroup RENESAS_CONNECTIVITY_INTERFACES
* @defgroup UART_API UART Interface
* @brief Interface for UART communications.
*
* @section UART_INTERFACE_SUMMARY Summary
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
* - Full-duplex UART communication
* - Interrupt driven transmit/receive processing
* - Callback function with returned event code
* - Runtime baud-rate change
* - Hardware resource locking during a transaction
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
*
*
* @{
**********************************************************************************************************************/
#ifndef R_UART_API_H
#define R_UART_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
#include "r_transfer_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** UART Event codes */
#ifndef BSP_OVERRIDE_UART_EVENT_T
typedef enum e_sf_event
{
UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event
UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event
UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received
UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event
UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event
UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event
UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
} uart_event_t;
#endif
#ifndef BSP_OVERRIDE_UART_DATA_BITS_T
/** UART Data bit length definition */
typedef enum e_uart_data_bits
{
UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit
UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit
UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit
} uart_data_bits_t;
#endif
#ifndef BSP_OVERRIDE_UART_PARITY_T
/** UART Parity definition */
typedef enum e_uart_parity
{
UART_PARITY_OFF = 0U, ///< No parity
UART_PARITY_ZERO = 1U, ///< Zero parity
UART_PARITY_EVEN = 2U, ///< Even parity
UART_PARITY_ODD = 3U, ///< Odd parity
} uart_parity_t;
#endif
/** UART Stop bits definition */
typedef enum e_uart_stop_bits
{
UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit
UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit
} uart_stop_bits_t;
/** UART transaction definition */
typedef enum e_uart_dir
{
UART_DIR_RX_TX = 3U, ///< Both RX and TX
UART_DIR_RX = 1U, ///< Only RX
UART_DIR_TX = 2U, ///< Only TX
} uart_dir_t;
/** UART driver specific information */
typedef struct st_uart_info
{
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
uint32_t write_bytes_max;
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
uint32_t read_bytes_max;
} uart_info_t;
/** UART Callback parameter definition */
typedef struct st_uart_callback_arg
{
uint32_t channel; ///< Device channel number
uart_event_t event; ///< Event code
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
uint32_t data;
void const * p_context; ///< Context provided to user during callback
} uart_callback_args_t;
/** UART Configuration */
typedef struct st_uart_cfg
{
/* UART generic configuration */
uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware.
uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9)
uart_parity_t parity; ///< Parity type (none or odd or even)
uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2)
uint8_t rxi_ipl; ///< Receive interrupt priority
IRQn_Type rxi_irq; ///< Receive interrupt IRQ number
uint8_t txi_ipl; ///< Transmit interrupt priority
IRQn_Type txi_irq; ///< Transmit interrupt IRQ number
uint8_t tei_ipl; ///< Transmit end interrupt priority
IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number
uint8_t eri_ipl; ///< Error interrupt priority
IRQn_Type eri_irq; ///< Error interrupt IRQ number
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
transfer_instance_t const * p_transfer_rx;
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
transfer_instance_t const * p_transfer_tx;
/* Configuration for UART Event processing */
void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
void const * p_context; ///< User defined context passed into callback function
/* Pointer to UART peripheral specific configuration */
void const * p_extend; ///< UART hardware dependent configuration
} uart_cfg_t;
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
*/
typedef void uart_ctrl_t;
/** Shared Interface definition for UART */
typedef struct st_uart_api
{
/** Open UART device.
*
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
* user.
*/
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
* the callback function with event UART_EVENT_RX_CHAR.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block for the channel.
* @param[in] p_dest Destination address to read data from.
* @param[in] bytes Read data length.
*/
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
* the callback called with event UART_EVENT_TX_COMPLETE.
* The maximum transfer size is reported by infoGet().
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_src Source address to write data to.
* @param[in] bytes Write data length.
*/
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
/** Change baud rate.
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
* settings have been applied.
*
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
*/
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
/** Get the driver specific information.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] baudrate Baud rate in bps.
*/
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
/**
* Abort ongoing transfer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] communication_to_abort Type of abort request.
*/
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
/**
* Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *),
void const * const p_context, uart_callback_args_t * const p_callback_memory);
/** Close UART device.
*
* @param[in] p_ctrl Pointer to the UART control block.
*/
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
/** Stop ongoing read and return the number of bytes remaining in the read.
*
* @param[in] p_ctrl Pointer to the UART control block.
* @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read.
*/
fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
} uart_api_t;
/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_uart_instance
{
uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
uart_api_t const * p_api; ///< Pointer to the API structure for this instance
} uart_instance_t;
/** @} (end defgroup UART_API) */
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_COMMON_API_H
#define FSP_COMMON_API_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include <assert.h>
#include <stdint.h>
/* Includes FSP version macros. */
#include "fsp_version.h"
/*******************************************************************************************************************//**
* @ingroup RENESAS_COMMON
* @defgroup RENESAS_ERROR_CODES Common Error Codes
* All FSP modules share these common error codes.
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
* about using this implementation is that it does not take any extra RAM or ROM. */
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
/** Determine if a C++ compiler is being used.
* If so, ensure that standard C is used to process the API information. */
#if defined(__cplusplus)
#define FSP_CPP_HEADER extern "C" {
#define FSP_CPP_FOOTER }
#else
#define FSP_CPP_HEADER
#define FSP_CPP_FOOTER
#endif
/** FSP Header and Footer definitions */
#define FSP_HEADER FSP_CPP_HEADER
#define FSP_FOOTER FSP_CPP_FOOTER
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
* defined on the Secure side. */
#define FSP_SECURE_ARGUMENT (NULL)
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Common error codes */
typedef enum e_fsp_err
{
FSP_SUCCESS = 0,
FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed
FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location
FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter
FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist
FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode
FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API
FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open
FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy
FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h
FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked
FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP
FSP_ERR_OVERFLOW = 12, ///< Hardware overflow
FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow
FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration
FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result
FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason
FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met
FSP_ERR_ABORTED = 18, ///< An operation was aborted
FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled
FSP_ERR_TIMEOUT = 20, ///< Timeout error
FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied
FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied
FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation
FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed
FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed
FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made
FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition
FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU
FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state
FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed
FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed
FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer
FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed
/* Start of RTOS only error codes */
FSP_ERR_INTERNAL = 100, ///< Internal error
FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted
/* Start of UART specific */
FSP_ERR_FRAMING = 200, ///< Framing error occurs
FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects
FSP_ERR_PARITY = 202, ///< Parity error occurs
FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow
FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue
FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer
FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer
/* Start of SPI specific */
FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted.
FSP_ERR_MODE_FAULT = 301, ///< Mode fault error.
FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow.
FSP_ERR_SPI_PARITY = 303, ///< Parity error.
FSP_ERR_OVERRUN = 304, ///< Overrun error.
/* Start of CGC Specific */
FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock.
FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first.
FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off
FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off
FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit
FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled
FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out
FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode
/* Start of FLASH Specific */
FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode.
FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state
FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz
FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory
FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed
/* Start of CAC Specific */
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
/* Start of IIRFA Specific */
FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity.
/* Start of GLCD Specific */
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter
FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found
FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter
FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer
FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update
FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry
FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter
/* Start of JPEG Specific */
FSP_ERR_JPEG_ERR = 1100, ///< JPEG error
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected.
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected.
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected.
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected.
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected.
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected.
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default)
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected.
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected.
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected.
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU
/* Start of touch panel framework specific */
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
/* Start of IIRFA specific */
FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected
FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected
/* Start of IP specific */
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device
/* Start of USB specific */
FSP_ERR_USB_FAILED = 1500,
FSP_ERR_USB_BUSY = 1501,
FSP_ERR_USB_SIZE_SHORT = 1502,
FSP_ERR_USB_SIZE_OVER = 1503,
FSP_ERR_USB_NOT_OPEN = 1504,
FSP_ERR_USB_NOT_SUSPEND = 1505,
FSP_ERR_USB_PARAMETER = 1506,
/* Start of Message framework specific */
FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid
FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal
FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released
/* Start of 2DG Driver specific */
FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization
FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering
FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering
/* Start of ETHER Driver specific */
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer.
FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication
FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active.
/* Start of ETHER_PHY Driver specific */
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up.
FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation
/* Start of BYTEQ library specific */
FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data
FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue
/* Start of CTSU Driver specific */
FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning.
FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data.
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning.
FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet.
FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed.
FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed.
FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed.
FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed.
FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed.
FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed.
FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed.
FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed.
FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed.
FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed.
FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed.
FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed.
FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed.
FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed.
/* Start of SDMMC specific */
FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize.
FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed.
FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing.
FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed.
FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected.
FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress.
FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error.
/* Start of FX_IO specific */
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed.
FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed.
/* Start of CAN specific */
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available.
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed.
FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed.
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress.
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full.
/* Start of SF_WIFI Specific */
FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error
FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter
FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters
FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value
FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result
FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow
FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured
FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure
FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure
FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error
/* Start of SF_CELLULAR Specific */
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed
FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed.
FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state.
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed
/* Start of SF_BLE specific */
FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed
FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed
FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled
/* Start of SF_BLE_ABS specific */
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed.
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found.
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid.
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed
FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal.
FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred.
/* Start of Crypto RSIP specific (0x10100) */
FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy
FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return
FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error
FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal
FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed
/* Start of SF_CRYPTO specific */
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long.
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error.
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
* Refer to sf_cryoto_err.h for Crypto error codes.
*/
/* Start of Sensor specific */
FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid.
FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing.
FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished.
/* Start of COMMS specific */
FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open.
} fsp_err_t;
/** @} */
/***********************************************************************************************************************
* Function prototypes
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef FSP_VERSION_H
#define FSP_VERSION_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
/* Includes board and MCU related header files. */
#include "bsp_api.h"
/*******************************************************************************************************************//**
* @addtogroup RENESAS_COMMON
* @{
**********************************************************************************************************************/
/**********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/** FSP pack major version. */
#define FSP_VERSION_MAJOR (2U)
/** FSP pack minor version. */
#define FSP_VERSION_MINOR (0U)
/** FSP pack patch version. */
#define FSP_VERSION_PATCH (0U)
/** FSP pack version build number (currently unused). */
#define FSP_VERSION_BUILD (0U)
/** Public FSP version name. */
#define FSP_VERSION_STRING ("2.0.0")
/** Unique FSP version ID. */
#define FSP_VERSION_BUILD_STRING ("Built with RZ/N Flexible Software Package version 2.0.0")
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** FSP Pack version structure */
typedef union st_fsp_pack_version
{
/** Version id */
uint32_t version_id;
/** Code version parameters, little endian order. */
struct version_id_b_s
{
uint8_t build; ///< Build version of FSP Pack
uint8_t patch; ///< Patch version of FSP Pack
uint8_t minor; ///< Minor version of FSP Pack
uint8_t major; ///< Major version of FSP Pack
} version_id_b;
} fsp_pack_version_t;
/** @} */
#endif

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup IOPORT
* @{
**********************************************************************************************************************/
#ifndef R_IOPORT_H
#define R_IOPORT_H
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
#include "r_ioport_api.h"
#include "r_ioport_cfg.h"
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define IOPORT_SINGLE_PORT_NUM (4)
#define IOPORT_PORT_GROUP_NUM (2)
#define IOPORT_PORT_GROUP_1 (0)
#define IOPORT_PORT_GROUP_2 (1)
#define IOPORT_SINGLE_PORT_0 (0)
#define IOPORT_SINGLE_PORT_1 (1)
#define IOPORT_SINGLE_PORT_2 (2)
#define IOPORT_SINGLE_PORT_3 (3)
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Pin selection for port group
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_pin_selection
{
IOPORT_EVENT_PIN_SELECTION_NONE = 0x00, ///< No pin selection for port group
IOPORT_EVENT_PIN_SELECTION_PIN_0 = 0x01, ///< Select pin 0 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_1 = 0x02, ///< Select pin 1 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_2 = 0x04, ///< Select pin 2 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_3 = 0x08, ///< Select pin 3 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_4 = 0x10, ///< Select pin 4 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_5 = 0x20, ///< Select pin 5 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_6 = 0x40, ///< Select pin 6 to port group
IOPORT_EVENT_PIN_SELECTION_PIN_7 = 0x80, ///< Select pin 7 to port group
} ioport_event_pin_selection_t;
/** Port group operation
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_output_operation
{
IOPORT_EVENT_OUTPUT_OPERATION_LOW = 0x0, ///< Set Low output to output operation
IOPORT_EVENT_OUTPUT_OPERATION_HIGH = 0x1, ///< Set High output to output operation
IOPORT_EVENT_OUTPUT_OPERATION_TOGGLE = 0x2, ///< Set toggle output to output operation
IOPORT_EVENT_OUTPUT_OPERATION_BUFFER = 0x3, ///< Set buffer value output to output operation
} ioport_event_output_operation_t;
/** Input port group event control
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_control
{
IOPORT_EVENT_CONTROL_DISABLE = 0x0, ///< Disable function related with event link
IOPORT_EVENT_CONTROL_ENABLE = 0x1, ///< Enable function related with event link
} ioport_event_control_t;
/** Single port event direction
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_direction
{
IOPORT_EVENT_DIRECTION_OUTPUT = 0x0, ///< Set output direction to single port
IOPORT_EVENT_DIRECTION_INPUT = 0x1, ///< Set input direction to single port
} ioport_event_direction_t;
/** Input event edge detection
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_detection
{
IOPORT_EVENT_DETECTION_RISING_EDGE = 0x0, ///< Set rising edge to event detection for input event
IOPORT_EVENT_DETECTION_FALLING_EDGE = 0x1, ///< Set falling edge to event detection for input event
IOPORT_EVENT_DETECTION_BOTH_EGDE = 0x2, ///< Set both edges to event detection for input event
} ioport_event_detection_t;
/** Initial value for buffer register
* @note Event link must be configured by the ELC
*/
typedef enum e_ioport_event_initial_buffer_value
{
IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW = 0U, ///< Set low input to initial value of buffer register for input port group
IOPORT_EVENT_INITIAL_BUFFER_VALUE_HIGH = 1U, ///< Set high input to initial value of buffer register for input port group
} ioport_event_initial_buffer_value_t;
/** Single port configuration
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_event_single
{
ioport_event_control_t event_control; ///< Event link control for single port
ioport_event_direction_t direction; ///< Event direction for single port
uint16_t port_num; ///< Port number specified to single port
ioport_event_output_operation_t operation; ///< Single port operation select
ioport_event_detection_t edge_detection; ///< Edge detection select
} ioport_event_single_t;
/** Output port group configuration
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_event_group_output
{
uint8_t pin_select; ///< Port number specified to output port group
ioport_event_output_operation_t operation; ///< Port group operation select
} ioport_event_group_output_t;
/** Input port group configuration
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_event_group_input
{
ioport_event_control_t event_control; ///< Event link control for input port group
ioport_event_detection_t edge_detection; ///< Edge detection select
ioport_event_control_t overwrite_control; ///< Buffer register overwrite control
uint8_t pin_select; ///< Port number specified to input port group
uint8_t buffer_init_value; ///< Buffer register initial value
} ioport_event_group_input_t;
/** IOPORT extended configuration for event link function
* @note Event link must be configured by the ELC
*/
typedef struct st_ioport_extend_cfg
{
ioport_event_group_output_t port_group_output_cfg[IOPORT_PORT_GROUP_NUM]; ///< Output port group configuration
ioport_event_group_input_t port_group_input_cfg[IOPORT_PORT_GROUP_NUM]; ///< Input port group configuration
ioport_event_single_t single_port_cfg[IOPORT_SINGLE_PORT_NUM]; ///< Single input port configuration
} ioport_extend_cfg_t;
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
typedef struct st_ioport_instance_ctrl
{
uint32_t open; // Whether or not ioport is open
void const * p_context; // Pointer to context to be passed into callback
ioport_cfg_t const * p_cfg; // Pointer to the configuration block
} ioport_instance_ctrl_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const ioport_api_t g_ioport_on_ioport;
/** @endcond */
/***********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t direction_values,
ioport_size_t mask);
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
bsp_io_port_t port,
ioport_size_t event_data,
ioport_size_t mask_value);
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
/*******************************************************************************************************************//**
* @} (end defgroup IOPORT)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif // R_IOPORT_H

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/***********************************************************************************************************************
* Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only
* be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized.
* Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for
* the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any
* intellectual property right is granted by Renesas. This software is protected under all applicable laws, including
* copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation.
* THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND
* TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY,
* INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE
* SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH.
* TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR
* DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER,
* INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY
* LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE
* POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef R_SCI_UART_H
#define R_SCI_UART_H
/*******************************************************************************************************************//**
* @addtogroup SCI_UART
* @{
**********************************************************************************************************************/
/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_uart_api.h"
#include "r_sci_uart_cfg.h"
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
/**********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/** Enumeration for SCI clock source */
typedef enum e_sci_uart_clock
{
SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation
SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK
SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate
SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate
} sci_uart_clock_t;
/** UART flow control mode definition */
typedef enum e_sci_uart_flow_control
{
SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS
SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS
SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS
SCI_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS
} sci_uart_flow_control_t;
/** UART instance control block. */
typedef struct st_sci_uart_instance_ctrl
{
/* Parameters to control UART peripheral device */
uint8_t fifo_depth; // FIFO depth of the UART channel
uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise
uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data
uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise
uint32_t open; // Used to determine if the channel is configured
bsp_io_port_pin_t flow_pin;
/* Source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint8_t const * p_tx_src;
/* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */
uint32_t tx_src_bytes;
/* Destination buffer pointer used for receiving data. */
uint8_t const * p_rx_dest;
/* Size of destination buffer pointer used for receiving data. */
uint32_t rx_dest_bytes;
/* Pointer to the configuration block. */
uart_cfg_t const * p_cfg;
/* Base register for this channel */
R_SCI0_Type * p_reg;
void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs.
uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.
/* Pointer to context to be passed into callback function */
void const * p_context;
} sci_uart_instance_ctrl_t;
/** Receive FIFO trigger configuration. */
typedef enum e_sci_uart_rx_fifo_trigger
{
SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering
SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)
} sci_uart_rx_fifo_trigger_t;
/** Asynchronous Start Bit Edge Detection configuration. */
typedef enum e_sci_uart_start_bit
{
SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit
SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit
} sci_uart_start_bit_t;
/** Noise cancellation configuration. */
typedef enum e_sci_uart_noise_cancellation
{
SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation
SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation, The base clock signal divided by 1
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1 = 0x2, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 1
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2 = 0x3, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 2
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4 = 0x4, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 4
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8 = 0x5, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 8
} sci_uart_noise_cancellation_t;
/** RS-485 Enable/Disable. */
typedef enum e_sci_uart_rs485_enable
{
SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled.
SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled.
} sci_uart_rs485_enable_t;
/** The polarity of the RS-485 DE signal. */
typedef enum e_sci_uart_rs485_de_polarity
{
SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress.
SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress.
} sci_uart_rs485_de_polarity_t;
/** Source clock selection options for SCI. */
typedef enum e_sci_uart_clock_source
{
SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0,
SCI_UART_CLOCK_SOURCE_SCI1ASYNCCLK = 1,
SCI_UART_CLOCK_SOURCE_SCI2ASYNCCLK = 2,
SCI_UART_CLOCK_SOURCE_SCI3ASYNCCLK = 3,
SCI_UART_CLOCK_SOURCE_SCI4ASYNCCLK = 4,
SCI_UART_CLOCK_SOURCE_SCI5ASYNCCLK = 5,
SCI_UART_CLOCK_SOURCE_PCLKM = 6,
} sci_uart_clock_source_t;
/** Baudrate calculation configuration. */
typedef struct st_sci_uart_baud_calculation
{
uint32_t baudrate; ///< Target baudrate
bool bitrate_modulation; ///< Whether bitrate modulation use or not
uint32_t baud_rate_error_x_1000; ///< Max baudrate percent error
} sci_uart_baud_calculation_t;
/** Register settings to achieve a desired baud rate and modulation duty. */
typedef struct st_sci_baud_setting_t
{
union
{
uint32_t baudrate_bits;
struct
{
uint32_t : 4;
uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select
uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select
uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1
uint32_t : 1;
uint32_t brr : 8; ///< Bit Rate Register setting
uint32_t brme : 1; ///< Bit Rate Modulation Enable
uint32_t : 3;
uint32_t cks : 2; ///< CKS value to get divisor (CKS = N)
uint32_t : 2;
uint32_t mddr : 8; ///< Modulation Duty Register setting
} baudrate_bits_b;
};
} sci_baud_setting_t;
/** Configuration settings for controlling the DE signal for RS-485. */
typedef struct st_sci_uart_rs485_setting
{
sci_uart_rs485_enable_t enable; ///< Enable the DE signal.
sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity.
uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer.
uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated.
} sci_uart_rs485_setting_t;
/** UART on SCI device Configuration */
typedef struct st_sci_uart_extended_cfg
{
sci_uart_clock_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK
sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge
sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting
sci_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate.
sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used.
bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin
sci_uart_flow_control_t flow_control; ///< CTS/RTS function
sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings.
/** Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK. */
sci_uart_clock_source_t clock_source;
} sci_uart_extended_cfg_t;
/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/** @cond INC_HEADER_DEFS_SEC */
/** Filled in Interface API structure for this Instance. */
extern const uart_api_t g_uart_on_sci;
/** @endcond */
fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_ctrl, void const * const p_baud_setting);
fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_ctrl);
fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
fsp_err_t R_SCI_UART_BaudCalculate(sci_uart_baud_calculation_t const * const p_baud_target,
sci_uart_clock_source_t clock_source,
sci_baud_setting_t * const p_baud_setting);
fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_ctrl,
void ( * p_callback)(uart_callback_args_t *),
void const * const p_context,
uart_callback_args_t * const p_callback_memory);
fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
/*******************************************************************************************************************//**
* @} (end addtogroup SCI_UART)
**********************************************************************************************************************/
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif

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