mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-19 16:26:55 +08:00
Merge branch 'master' of https://github.com/RT-Thread/rt-thread
This commit is contained in:
bernard
@@ -0,0 +1,35 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 11. November 2010
|
||||
* $Revision: V1.0.2
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
*
|
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Version 1.0.2 2010/11/11
|
||||
* Documentation updated.
|
||||
*
|
||||
* Version 1.0.1 2010/10/05
|
||||
* Production release and review comments incorporated.
|
||||
*
|
||||
* Version 1.0.0 2010/09/20
|
||||
* Production release and review comments incorporated.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern uint16_t armBitRevTable[256];
|
||||
extern q15_t armRecipTableQ15[64];
|
||||
extern q31_t armRecipTableQ31[64];
|
||||
extern const q31_t realCoefAQ31[1024];
|
||||
extern const q31_t realCoefBQ31[1024];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
File diff suppressed because it is too large
Load Diff
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@@ -0,0 +1,89 @@
|
||||
/**********************************************************************
|
||||
* $Id$ system_LPC177x_8x.h 2011-06-02
|
||||
*//**
|
||||
* @file system_LPC177x_8x.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC177x_8x Device Series
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __SYSTEM_LPC177x_8x_H
|
||||
#define __SYSTEM_LPC177x_8x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
|
||||
extern uint32_t EMCClock; /*!< EMC Clock */
|
||||
extern uint32_t USBClock; /*!< USB Frequency */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
|
||||
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
|
||||
#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC177x_8x_H */
|
||||
+89
@@ -0,0 +1,89 @@
|
||||
/**********************************************************************
|
||||
* $Id$ system_LPC407x_8x_177x_8x.h 2011-06-02
|
||||
*//**
|
||||
* @file system_LPC407x_8x_177x_8x.h
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
|
||||
* for the NXP LPC Device Series
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
|
||||
#define __SYSTEM_LPC407x_8x_177x_8x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
|
||||
extern uint32_t EMCClock; /*!< EMC Clock */
|
||||
extern uint32_t USBClock; /*!< USB Frequency */
|
||||
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit (void);
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @param none
|
||||
* @return none
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clocks
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define XTAL (12000000UL) /* Oscillator frequency */
|
||||
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
|
||||
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
|
||||
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
|
||||
#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
|
||||
|
||||
|
||||
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */
|
||||
+301
@@ -0,0 +1,301 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_LPC177x_8x.s
|
||||
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
|
||||
; * for the NXP LPC177x_8x Device Series
|
||||
; * @version: V1.20
|
||||
; * @date: 07. October 2010
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * Copyright (C) 2010 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 16: Watchdog Timer
|
||||
DCD TIMER0_IRQHandler ; 17: Timer0
|
||||
DCD TIMER1_IRQHandler ; 18: Timer1
|
||||
DCD TIMER2_IRQHandler ; 19: Timer2
|
||||
DCD TIMER3_IRQHandler ; 20: Timer3
|
||||
DCD UART0_IRQHandler ; 21: UART0
|
||||
DCD UART1_IRQHandler ; 22: UART1
|
||||
DCD UART2_IRQHandler ; 23: UART2
|
||||
DCD UART3_IRQHandler ; 24: UART3
|
||||
DCD PWM1_IRQHandler ; 25: PWM1
|
||||
DCD I2C0_IRQHandler ; 26: I2C0
|
||||
DCD I2C1_IRQHandler ; 27: I2C1
|
||||
DCD I2C2_IRQHandler ; 28: I2C2
|
||||
DCD 0 ; 29: reserved, not for SPIFI anymore
|
||||
DCD SSP0_IRQHandler ; 30: SSP0
|
||||
DCD SSP1_IRQHandler ; 31: SSP1
|
||||
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
||||
DCD RTC_IRQHandler ; 33: Real Time Clock
|
||||
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
||||
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
||||
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
||||
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
||||
DCD ADC_IRQHandler ; 38: A/D Converter
|
||||
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
||||
DCD USB_IRQHandler ; 40: USB
|
||||
DCD CAN_IRQHandler ; 41: CAN
|
||||
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
||||
DCD I2S_IRQHandler ; 43: I2S
|
||||
DCD ENET_IRQHandler ; 44: Ethernet
|
||||
DCD MCI_IRQHandler ; 45: SD/MMC card I/F
|
||||
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
||||
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
||||
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
||||
DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
|
||||
DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
|
||||
DCD UART4_IRQHandler ; 51: UART4
|
||||
DCD SSP2_IRQHandler ; 52: SSP2
|
||||
DCD LCD_IRQHandler ; 53: LCD
|
||||
DCD GPIO_IRQHandler ; 54: GPIO
|
||||
DCD PWM0_IRQHandler ; 55: PWM0
|
||||
DCD EEPROM_IRQHandler ; 56: EEPROM
|
||||
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT I2C2_IRQHandler [WEAK]
|
||||
;EXPORT SPIFI_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT PLL0_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT EINT0_IRQHandler [WEAK]
|
||||
EXPORT EINT1_IRQHandler [WEAK]
|
||||
EXPORT EINT2_IRQHandler [WEAK]
|
||||
EXPORT EINT3_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT MCI_IRQHandler [WEAK]
|
||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
|
||||
EXPORT PLL1_IRQHandler [WEAK]
|
||||
EXPORT USBActivity_IRQHandler [WEAK]
|
||||
EXPORT CANActivity_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT SSP2_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT GPIO_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT EEPROM_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
;SPIFI_IRQHandler ;not used
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
PLL0_IRQHandler
|
||||
RTC_IRQHandler
|
||||
EINT0_IRQHandler
|
||||
EINT1_IRQHandler
|
||||
EINT2_IRQHandler
|
||||
EINT3_IRQHandler
|
||||
ADC_IRQHandler
|
||||
BOD_IRQHandler
|
||||
USB_IRQHandler
|
||||
CAN_IRQHandler
|
||||
DMA_IRQHandler
|
||||
I2S_IRQHandler
|
||||
ENET_IRQHandler
|
||||
MCI_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
QEI_IRQHandler
|
||||
PLL1_IRQHandler
|
||||
USBActivity_IRQHandler
|
||||
CANActivity_IRQHandler
|
||||
UART4_IRQHandler
|
||||
SSP2_IRQHandler
|
||||
LCD_IRQHandler
|
||||
GPIO_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
EEPROM_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
+302
@@ -0,0 +1,302 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_LPC407x_8x.s
|
||||
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
|
||||
; * for the NXP LPC407x_8x Device Series
|
||||
; * @version: V1.20
|
||||
; * @date: 16. January 2012
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * Copyright (C) 2012 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
; DCD 0xEFFFF5D6 ; Reserved- vector sum
|
||||
DCD 0xEFFFF39E ; Reserved- vector sum
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 16: Watchdog Timer
|
||||
DCD TIMER0_IRQHandler ; 17: Timer0
|
||||
DCD TIMER1_IRQHandler ; 18: Timer1
|
||||
DCD TIMER2_IRQHandler ; 19: Timer2
|
||||
DCD TIMER3_IRQHandler ; 20: Timer3
|
||||
DCD UART0_IRQHandler ; 21: UART0
|
||||
DCD UART1_IRQHandler ; 22: UART1
|
||||
DCD UART2_IRQHandler ; 23: UART2
|
||||
DCD UART3_IRQHandler ; 24: UART3
|
||||
DCD PWM1_IRQHandler ; 25: PWM1
|
||||
DCD I2C0_IRQHandler ; 26: I2C0
|
||||
DCD I2C1_IRQHandler ; 27: I2C1
|
||||
DCD I2C2_IRQHandler ; 28: I2C2
|
||||
DCD 0 ; 29: reserved, not for SPIFI anymore
|
||||
DCD SSP0_IRQHandler ; 30: SSP0
|
||||
DCD SSP1_IRQHandler ; 31: SSP1
|
||||
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
||||
DCD RTC_IRQHandler ; 33: Real Time Clock
|
||||
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
||||
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
||||
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
||||
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
||||
DCD ADC_IRQHandler ; 38: A/D Converter
|
||||
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
||||
DCD USB_IRQHandler ; 40: USB
|
||||
DCD CAN_IRQHandler ; 41: CAN
|
||||
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
||||
DCD I2S_IRQHandler ; 43: I2S
|
||||
DCD ENET_IRQHandler ; 44: Ethernet
|
||||
DCD MCI_IRQHandler ; 45: SD/MMC card I/F
|
||||
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
||||
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
||||
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
||||
DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
|
||||
DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
|
||||
DCD UART4_IRQHandler ; 51: UART4
|
||||
DCD SSP2_IRQHandler ; 52: SSP2
|
||||
DCD LCD_IRQHandler ; 53: LCD
|
||||
DCD GPIO_IRQHandler ; 54: GPIO
|
||||
DCD PWM0_IRQHandler ; 55: PWM0
|
||||
DCD EEPROM_IRQHandler ; 56: EEPROM
|
||||
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT I2C2_IRQHandler [WEAK]
|
||||
;EXPORT SPIFI_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT PLL0_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT EINT0_IRQHandler [WEAK]
|
||||
EXPORT EINT1_IRQHandler [WEAK]
|
||||
EXPORT EINT2_IRQHandler [WEAK]
|
||||
EXPORT EINT3_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT CAN_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT MCI_IRQHandler [WEAK]
|
||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
|
||||
EXPORT PLL1_IRQHandler [WEAK]
|
||||
EXPORT USBActivity_IRQHandler [WEAK]
|
||||
EXPORT CANActivity_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT SSP2_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT GPIO_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT EEPROM_IRQHandler [WEAK]
|
||||
|
||||
WDT_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
;SPIFI_IRQHandler ;not used
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
PLL0_IRQHandler
|
||||
RTC_IRQHandler
|
||||
EINT0_IRQHandler
|
||||
EINT1_IRQHandler
|
||||
EINT2_IRQHandler
|
||||
EINT3_IRQHandler
|
||||
ADC_IRQHandler
|
||||
BOD_IRQHandler
|
||||
USB_IRQHandler
|
||||
CAN_IRQHandler
|
||||
DMA_IRQHandler
|
||||
I2S_IRQHandler
|
||||
ENET_IRQHandler
|
||||
MCI_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
QEI_IRQHandler
|
||||
PLL1_IRQHandler
|
||||
USBActivity_IRQHandler
|
||||
CANActivity_IRQHandler
|
||||
UART4_IRQHandler
|
||||
SSP2_IRQHandler
|
||||
LCD_IRQHandler
|
||||
GPIO_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
EEPROM_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
+279
@@ -0,0 +1,279 @@
|
||||
/*****************************************************************************/
|
||||
/* startup_LPC17xx.s: Startup file for LPC17xx device series */
|
||||
/*****************************************************************************/
|
||||
/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */
|
||||
/*****************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
//*** <<< Use Configuration Wizard in Context Menu >>> ***
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <h> Stack Configuration
|
||||
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*/
|
||||
|
||||
.equ Stack_Size, 0x00000100
|
||||
.section ".stack", "w"
|
||||
.align 3
|
||||
.globl __cs3_stack_mem
|
||||
.globl __cs3_stack_size
|
||||
__cs3_stack_mem:
|
||||
.if Stack_Size
|
||||
.space Stack_Size
|
||||
.endif
|
||||
.size __cs3_stack_mem, . - __cs3_stack_mem
|
||||
.set __cs3_stack_size, . - __cs3_stack_mem
|
||||
|
||||
|
||||
/*
|
||||
// <h> Heap Configuration
|
||||
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*/
|
||||
|
||||
.equ Heap_Size, 0x00001000
|
||||
|
||||
.section ".heap", "w"
|
||||
.align 3
|
||||
.globl __cs3_heap_start
|
||||
.globl __cs3_heap_end
|
||||
__cs3_heap_start:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
__cs3_heap_end:
|
||||
|
||||
|
||||
/* Vector Table */
|
||||
|
||||
.section ".cs3.interrupt_vector"
|
||||
.globl __cs3_interrupt_vector_cortex_m
|
||||
.type __cs3_interrupt_vector_cortex_m, %object
|
||||
|
||||
__cs3_interrupt_vector_cortex_m:
|
||||
.long __cs3_stack /* Top of Stack */
|
||||
.long __cs3_reset /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External Interrupts */
|
||||
.long WDT_IRQHandler /* 16: Watchdog Timer */
|
||||
.long TIMER0_IRQHandler /* 17: Timer0 */
|
||||
.long TIMER1_IRQHandler /* 18: Timer1 */
|
||||
.long TIMER2_IRQHandler /* 19: Timer2 */
|
||||
.long TIMER3_IRQHandler /* 20: Timer3 */
|
||||
.long UART0_IRQHandler /* 21: UART0 */
|
||||
.long UART1_IRQHandler /* 22: UART1 */
|
||||
.long UART2_IRQHandler /* 23: UART2 */
|
||||
.long UART3_IRQHandler /* 24: UART3 */
|
||||
.long PWM1_IRQHandler /* 25: PWM1 */
|
||||
.long I2C0_IRQHandler /* 26: I2C0 */
|
||||
.long I2C1_IRQHandler /* 27: I2C1 */
|
||||
.long I2C2_IRQHandler /* 28: I2C2 */
|
||||
.long 0 /* 29: Reserved, not for SPIFI anymore */
|
||||
.long SSP0_IRQHandler /* 30: SSP0 */
|
||||
.long SSP1_IRQHandler /* 31: SSP1 */
|
||||
.long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
|
||||
.long RTC_IRQHandler /* 33: Real Time Clock */
|
||||
.long EINT0_IRQHandler /* 34: External Interrupt 0 */
|
||||
.long EINT1_IRQHandler /* 35: External Interrupt 1 */
|
||||
.long EINT2_IRQHandler /* 36: External Interrupt 2 */
|
||||
.long EINT3_IRQHandler /* 37: External Interrupt 3 */
|
||||
.long ADC_IRQHandler /* 38: A/D Converter */
|
||||
.long BOD_IRQHandler /* 39: Brown-Out Detect */
|
||||
.long USB_IRQHandler /* 40: USB */
|
||||
.long CAN_IRQHandler /* 41: CAN */
|
||||
.long DMA_IRQHandler /* 42: General Purpose DMA */
|
||||
.long I2S_IRQHandler /* 43: I2S */
|
||||
.long ENET_IRQHandler /* 44: Ethernet */
|
||||
.long MCI_IRQHandler /* 45: SD/MMC Card */
|
||||
.long MCPWM_IRQHandler /* 46: Motor Control PWM */
|
||||
.long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
|
||||
.long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
|
||||
.long USBActivity_IRQHandler /* 49: USB Activity */
|
||||
.long CANActivity_IRQHandler /* 50: CAN Activity */
|
||||
.long UART4_IRQHandler /* 51: UART4 */
|
||||
.long SSP2_IRQHandler /* 52: SSP2 */
|
||||
.long LCD_IRQHandler /* 53: LCD */
|
||||
.long GPIO_IRQHandler /* 54: GPIO */
|
||||
.long PWM0_IRQHandler /* 55: PWM0 */
|
||||
.long EEPROM_IRQHandler /* 56: EEPROM */
|
||||
|
||||
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
|
||||
|
||||
|
||||
.thumb
|
||||
|
||||
.section ".crp"
|
||||
.globl CRP_Value
|
||||
CRP_Value:
|
||||
.long 0xFFFFFFFF
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.section .cs3.reset,"x",%progbits
|
||||
.thumb_func
|
||||
.globl __cs3_reset_cortex_m
|
||||
.type __cs3_reset_cortex_m, %function
|
||||
__cs3_reset_cortex_m:
|
||||
.fnstart
|
||||
.if (RAM_MODE)
|
||||
/* Clear .bss section (Zero init) */
|
||||
MOV R0, #0
|
||||
LDR R1, =__bss_start__
|
||||
LDR R2, =__bss_end__
|
||||
CMP R1,R2
|
||||
BEQ BSSIsEmpty
|
||||
LoopZI:
|
||||
CMP R1, R2
|
||||
BHS BSSIsEmpty
|
||||
STR R0, [R1]
|
||||
ADD R1, #4
|
||||
BLO LoopZI
|
||||
BSSIsEmpty:
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0,=main
|
||||
BX R0
|
||||
.else
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0,=_start
|
||||
BX R0
|
||||
.endif
|
||||
.pool
|
||||
.cantunwind
|
||||
.fnend
|
||||
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
|
||||
|
||||
.section ".text"
|
||||
|
||||
/* Exception Handlers */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
B .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
B .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.type MemManage_Handler, %function
|
||||
MemManage_Handler:
|
||||
B .
|
||||
.size MemManage_Handler, . - MemManage_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
B .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
B .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
B .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
B .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
B .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
B .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
B .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ UART0_IRQHandler
|
||||
IRQ UART1_IRQHandler
|
||||
IRQ UART2_IRQHandler
|
||||
IRQ UART3_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ I2C0_IRQHandler
|
||||
IRQ I2C1_IRQHandler
|
||||
IRQ I2C2_IRQHandler
|
||||
/* IRQ SPIFI_IRQHandler */
|
||||
IRQ SSP0_IRQHandler
|
||||
IRQ SSP1_IRQHandler
|
||||
IRQ PLL0_IRQHandler
|
||||
IRQ RTC_IRQHandler
|
||||
IRQ EINT0_IRQHandler
|
||||
IRQ EINT1_IRQHandler
|
||||
IRQ EINT2_IRQHandler
|
||||
IRQ EINT3_IRQHandler
|
||||
IRQ ADC_IRQHandler
|
||||
IRQ BOD_IRQHandler
|
||||
IRQ USB_IRQHandler
|
||||
IRQ CAN_IRQHandler
|
||||
IRQ DMA_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
IRQ ENET_IRQHandler
|
||||
IRQ MCI_IRQHandler
|
||||
IRQ MCPWM_IRQHandler
|
||||
IRQ QEI_IRQHandler
|
||||
IRQ PLL1_IRQHandler
|
||||
IRQ USBActivity_IRQHandler
|
||||
IRQ CANActivity_IRQHandler
|
||||
IRQ UART4_IRQHandler
|
||||
IRQ SSP2_IRQHandler
|
||||
IRQ LCD_IRQHandler
|
||||
IRQ GPIO_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ EEPROM_IRQHandler
|
||||
|
||||
.end
|
||||
+279
@@ -0,0 +1,279 @@
|
||||
/*****************************************************************************/
|
||||
/* startup_LPC17xx.s: Startup file for LPC17xx device series */
|
||||
/*****************************************************************************/
|
||||
/* Version: CodeSourcery Sourcery G++ Lite (with CS3) */
|
||||
/*****************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
//*** <<< Use Configuration Wizard in Context Menu >>> ***
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <h> Stack Configuration
|
||||
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*/
|
||||
|
||||
.equ Stack_Size, 0x00000100
|
||||
.section ".stack", "w"
|
||||
.align 3
|
||||
.globl __cs3_stack_mem
|
||||
.globl __cs3_stack_size
|
||||
__cs3_stack_mem:
|
||||
.if Stack_Size
|
||||
.space Stack_Size
|
||||
.endif
|
||||
.size __cs3_stack_mem, . - __cs3_stack_mem
|
||||
.set __cs3_stack_size, . - __cs3_stack_mem
|
||||
|
||||
|
||||
/*
|
||||
// <h> Heap Configuration
|
||||
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
// </h>
|
||||
*/
|
||||
|
||||
.equ Heap_Size, 0x00001000
|
||||
|
||||
.section ".heap", "w"
|
||||
.align 3
|
||||
.globl __cs3_heap_start
|
||||
.globl __cs3_heap_end
|
||||
__cs3_heap_start:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
__cs3_heap_end:
|
||||
|
||||
|
||||
/* Vector Table */
|
||||
|
||||
.section ".cs3.interrupt_vector"
|
||||
.globl __cs3_interrupt_vector_cortex_m
|
||||
.type __cs3_interrupt_vector_cortex_m, %object
|
||||
|
||||
__cs3_interrupt_vector_cortex_m:
|
||||
.long __cs3_stack /* Top of Stack */
|
||||
.long __cs3_reset /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External Interrupts */
|
||||
.long WDT_IRQHandler /* 16: Watchdog Timer */
|
||||
.long TIMER0_IRQHandler /* 17: Timer0 */
|
||||
.long TIMER1_IRQHandler /* 18: Timer1 */
|
||||
.long TIMER2_IRQHandler /* 19: Timer2 */
|
||||
.long TIMER3_IRQHandler /* 20: Timer3 */
|
||||
.long UART0_IRQHandler /* 21: UART0 */
|
||||
.long UART1_IRQHandler /* 22: UART1 */
|
||||
.long UART2_IRQHandler /* 23: UART2 */
|
||||
.long UART3_IRQHandler /* 24: UART3 */
|
||||
.long PWM1_IRQHandler /* 25: PWM1 */
|
||||
.long I2C0_IRQHandler /* 26: I2C0 */
|
||||
.long I2C1_IRQHandler /* 27: I2C1 */
|
||||
.long I2C2_IRQHandler /* 28: I2C2 */
|
||||
.long 0 /* 29: Reserved, not for SPIFI anymore */
|
||||
.long SSP0_IRQHandler /* 30: SSP0 */
|
||||
.long SSP1_IRQHandler /* 31: SSP1 */
|
||||
.long PLL0_IRQHandler /* 32: PLL0 Lock (Main PLL) */
|
||||
.long RTC_IRQHandler /* 33: Real Time Clock */
|
||||
.long EINT0_IRQHandler /* 34: External Interrupt 0 */
|
||||
.long EINT1_IRQHandler /* 35: External Interrupt 1 */
|
||||
.long EINT2_IRQHandler /* 36: External Interrupt 2 */
|
||||
.long EINT3_IRQHandler /* 37: External Interrupt 3 */
|
||||
.long ADC_IRQHandler /* 38: A/D Converter */
|
||||
.long BOD_IRQHandler /* 39: Brown-Out Detect */
|
||||
.long USB_IRQHandler /* 40: USB */
|
||||
.long CAN_IRQHandler /* 41: CAN */
|
||||
.long DMA_IRQHandler /* 42: General Purpose DMA */
|
||||
.long I2S_IRQHandler /* 43: I2S */
|
||||
.long ENET_IRQHandler /* 44: Ethernet */
|
||||
.long MCI_IRQHandler /* 45: SD/MMC Card */
|
||||
.long MCPWM_IRQHandler /* 46: Motor Control PWM */
|
||||
.long QEI_IRQHandler /* 47: Quadrature Encoder Interface */
|
||||
.long PLL1_IRQHandler /* 48: PLL1 Lock (USB PLL) */
|
||||
.long USBActivity_IRQHandler /* 49: USB Activity */
|
||||
.long CANActivity_IRQHandler /* 50: CAN Activity */
|
||||
.long UART4_IRQHandler /* 51: UART4 */
|
||||
.long SSP2_IRQHandler /* 52: SSP2 */
|
||||
.long LCD_IRQHandler /* 53: LCD */
|
||||
.long GPIO_IRQHandler /* 54: GPIO */
|
||||
.long PWM0_IRQHandler /* 55: PWM0 */
|
||||
.long EEPROM_IRQHandler /* 56: EEPROM */
|
||||
|
||||
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
|
||||
|
||||
|
||||
.thumb
|
||||
|
||||
.section ".crp"
|
||||
.globl CRP_Value
|
||||
CRP_Value:
|
||||
.long 0xFFFFFFFF
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.section .cs3.reset,"x",%progbits
|
||||
.thumb_func
|
||||
.globl __cs3_reset_cortex_m
|
||||
.type __cs3_reset_cortex_m, %function
|
||||
__cs3_reset_cortex_m:
|
||||
.fnstart
|
||||
.ifdef RAM_MODE
|
||||
/* Clear .bss section (Zero init) */
|
||||
MOV R0, #0
|
||||
LDR R1, =__bss_start__
|
||||
LDR R2, =__bss_end__
|
||||
CMP R1,R2
|
||||
BEQ BSSIsEmpty
|
||||
LoopZI:
|
||||
CMP R1, R2
|
||||
BHS BSSIsEmpty
|
||||
STR R0, [R1]
|
||||
ADD R1, #4
|
||||
BLO LoopZI
|
||||
BSSIsEmpty:
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0,=main
|
||||
BX R0
|
||||
.else
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0,=_start
|
||||
BX R0
|
||||
.endif
|
||||
.pool
|
||||
.cantunwind
|
||||
.fnend
|
||||
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
|
||||
|
||||
.section ".text"
|
||||
|
||||
/* Exception Handlers */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
B .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
B .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.type MemManage_Handler, %function
|
||||
MemManage_Handler:
|
||||
B .
|
||||
.size MemManage_Handler, . - MemManage_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
B .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
B .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
B .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
B .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
B .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
B .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
B .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ UART0_IRQHandler
|
||||
IRQ UART1_IRQHandler
|
||||
IRQ UART2_IRQHandler
|
||||
IRQ UART3_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ I2C0_IRQHandler
|
||||
IRQ I2C1_IRQHandler
|
||||
IRQ I2C2_IRQHandler
|
||||
/* IRQ SPIFI_IRQHandler */
|
||||
IRQ SSP0_IRQHandler
|
||||
IRQ SSP1_IRQHandler
|
||||
IRQ PLL0_IRQHandler
|
||||
IRQ RTC_IRQHandler
|
||||
IRQ EINT0_IRQHandler
|
||||
IRQ EINT1_IRQHandler
|
||||
IRQ EINT2_IRQHandler
|
||||
IRQ EINT3_IRQHandler
|
||||
IRQ ADC_IRQHandler
|
||||
IRQ BOD_IRQHandler
|
||||
IRQ USB_IRQHandler
|
||||
IRQ CAN_IRQHandler
|
||||
IRQ DMA_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
IRQ ENET_IRQHandler
|
||||
IRQ MCI_IRQHandler
|
||||
IRQ MCPWM_IRQHandler
|
||||
IRQ QEI_IRQHandler
|
||||
IRQ PLL1_IRQHandler
|
||||
IRQ USBActivity_IRQHandler
|
||||
IRQ CANActivity_IRQHandler
|
||||
IRQ UART4_IRQHandler
|
||||
IRQ SSP2_IRQHandler
|
||||
IRQ LCD_IRQHandler
|
||||
IRQ GPIO_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ EEPROM_IRQHandler
|
||||
|
||||
.end
|
||||
+396
@@ -0,0 +1,396 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_LPC177x_8x.s
|
||||
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
|
||||
; * for the NXP LPC17xx Device Series
|
||||
; * @version: V1.03
|
||||
; * @date: 09. February 2010
|
||||
; *----------------------------------------------------------------------------
|
||||
; *
|
||||
; * Copyright (C) 2010 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemManage_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
__vector_table_0x1c
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 16: Watchdog Timer
|
||||
DCD TIMER0_IRQHandler ; 17: Timer0
|
||||
DCD TIMER1_IRQHandler ; 18: Timer1
|
||||
DCD TIMER2_IRQHandler ; 19: Timer2
|
||||
DCD TIMER3_IRQHandler ; 20: Timer3
|
||||
DCD UART0_IRQHandler ; 21: UART0
|
||||
DCD UART1_IRQHandler ; 22: UART1
|
||||
DCD UART2_IRQHandler ; 23: UART2
|
||||
DCD UART3_IRQHandler ; 24: UART3
|
||||
DCD PWM1_IRQHandler ; 25: PWM1
|
||||
DCD I2C0_IRQHandler ; 26: I2C0
|
||||
DCD I2C1_IRQHandler ; 27: I2C1
|
||||
DCD I2C2_IRQHandler ; 28: I2C2
|
||||
DCD 0 ; 29: reserved; not for SPIFI anymore
|
||||
DCD SSP0_IRQHandler ; 30: SSP0
|
||||
DCD SSP1_IRQHandler ; 31: SSP1
|
||||
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
||||
DCD RTC_IRQHandler ; 33: Real Time Clock
|
||||
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
||||
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
||||
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
||||
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
||||
DCD ADC_IRQHandler ; 38: A/D Converter
|
||||
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
||||
DCD USB_IRQHandler ; 40: USB
|
||||
DCD CAN_IRQHandler ; 41: CAN
|
||||
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
||||
DCD I2S_IRQHandler ; 43: I2S
|
||||
DCD ENET_IRQHandler ; 44: Ethernet
|
||||
DCD MCI_IRQHandler ; 45: MCI Card
|
||||
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
||||
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
||||
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
||||
DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
|
||||
DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
|
||||
DCD UART4_IRQHandler ; 51: UART4
|
||||
DCD SSP2_IRQHandler ; 52: SSP2
|
||||
DCD LCD_IRQHandler ; 53: LCD
|
||||
DCD GPIO_IRQHandler ; 54: GPIO
|
||||
DCD PWM0_IRQHandler ; 55: PWM0
|
||||
DCD EEPROM_IRQHandler ; 56: EEPROM
|
||||
|
||||
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
PUBLIC CRP_Value
|
||||
RSEG CRPKEY : CODE(2)
|
||||
CRP_Value
|
||||
DCD 0xFFFFFFFF
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
WDT_IRQHandler
|
||||
B WDT_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER0_IRQHandler
|
||||
B TIMER0_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART0_IRQHandler
|
||||
B UART0_IRQHandler
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
PUBWEAK UART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART2_IRQHandler
|
||||
B UART2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PWM1_IRQHandler
|
||||
B PWM1_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C0_IRQHandler
|
||||
B I2C0_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C1_IRQHandler
|
||||
B I2C1_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C2_IRQHandler
|
||||
B I2C2_IRQHandler
|
||||
|
||||
;PUBWEAK SPIFI_IRQHandler
|
||||
;SECTION .text:CODE:REORDER(1)
|
||||
;SPIFI_IRQHandler
|
||||
;B SPIFI_IRQHandler
|
||||
|
||||
PUBWEAK SSP0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP0_IRQHandler
|
||||
B SSP0_IRQHandler
|
||||
|
||||
PUBWEAK SSP1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP1_IRQHandler
|
||||
B SSP1_IRQHandler
|
||||
|
||||
PUBWEAK PLL0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PLL0_IRQHandler
|
||||
B PLL0_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK EINT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT0_IRQHandler
|
||||
B EINT0_IRQHandler
|
||||
|
||||
PUBWEAK EINT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT1_IRQHandler
|
||||
B EINT1_IRQHandler
|
||||
|
||||
PUBWEAK EINT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT2_IRQHandler
|
||||
B EINT2_IRQHandler
|
||||
|
||||
PUBWEAK EINT3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT3_IRQHandler
|
||||
B EINT3_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK BOD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BOD_IRQHandler
|
||||
B BOD_IRQHandler
|
||||
|
||||
PUBWEAK USB_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USB_IRQHandler
|
||||
B USB_IRQHandler
|
||||
|
||||
PUBWEAK CAN_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN_IRQHandler
|
||||
B CAN_IRQHandler
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2S_IRQHandler
|
||||
B I2S_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK MCI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MCI_IRQHandler
|
||||
B MCI_IRQHandler
|
||||
|
||||
PUBWEAK MCPWM_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MCPWM_IRQHandler
|
||||
B MCPWM_IRQHandler
|
||||
|
||||
PUBWEAK QEI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
QEI_IRQHandler
|
||||
B QEI_IRQHandler
|
||||
|
||||
PUBWEAK PLL1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PLL1_IRQHandler
|
||||
B PLL1_IRQHandler
|
||||
|
||||
PUBWEAK USBActivity_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USBActivity_IRQHandler
|
||||
B USBActivity_IRQHandler
|
||||
|
||||
PUBWEAK CANActivity_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CANActivity_IRQHandler
|
||||
B CANActivity_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK SSP2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP2_IRQHandler
|
||||
B SSP2_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
GPIO_IRQHandler
|
||||
B GPIO_IRQHandler
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PWM0_IRQHandler
|
||||
B PWM0_IRQHandler
|
||||
|
||||
PUBWEAK EEPROM_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EEPROM_IRQHandler
|
||||
B EEPROM_IRQHandler
|
||||
|
||||
END
|
||||
+396
@@ -0,0 +1,396 @@
|
||||
;/*****************************************************************************
|
||||
; * @file: startup_LPC177x_8x.s
|
||||
; * @purpose: CMSIS Cortex-M3 Core Device Startup File
|
||||
; * for the NXP LPC17xx Device Series
|
||||
; * @version: V1.03
|
||||
; * @date: 09. February 2010
|
||||
; *----------------------------------------------------------------------------
|
||||
; *
|
||||
; * Copyright (C) 2010 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemManage_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
__vector_table_0x1c
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WDT_IRQHandler ; 16: Watchdog Timer
|
||||
DCD TIMER0_IRQHandler ; 17: Timer0
|
||||
DCD TIMER1_IRQHandler ; 18: Timer1
|
||||
DCD TIMER2_IRQHandler ; 19: Timer2
|
||||
DCD TIMER3_IRQHandler ; 20: Timer3
|
||||
DCD UART0_IRQHandler ; 21: UART0
|
||||
DCD UART1_IRQHandler ; 22: UART1
|
||||
DCD UART2_IRQHandler ; 23: UART2
|
||||
DCD UART3_IRQHandler ; 24: UART3
|
||||
DCD PWM1_IRQHandler ; 25: PWM1
|
||||
DCD I2C0_IRQHandler ; 26: I2C0
|
||||
DCD I2C1_IRQHandler ; 27: I2C1
|
||||
DCD I2C2_IRQHandler ; 28: I2C2
|
||||
DCD 0 ; 29: reserved; not for SPIFI anymore
|
||||
DCD SSP0_IRQHandler ; 30: SSP0
|
||||
DCD SSP1_IRQHandler ; 31: SSP1
|
||||
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
||||
DCD RTC_IRQHandler ; 33: Real Time Clock
|
||||
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
||||
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
||||
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
||||
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
||||
DCD ADC_IRQHandler ; 38: A/D Converter
|
||||
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
||||
DCD USB_IRQHandler ; 40: USB
|
||||
DCD CAN_IRQHandler ; 41: CAN
|
||||
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
||||
DCD I2S_IRQHandler ; 43: I2S
|
||||
DCD ENET_IRQHandler ; 44: Ethernet
|
||||
DCD MCI_IRQHandler ; 45: MCI Card
|
||||
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
||||
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
||||
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
||||
DCD USBActivity_IRQHandler ; 49: USB Activity Interrupt
|
||||
DCD CANActivity_IRQHandler ; 50: CAN Activity Interrupt
|
||||
DCD UART4_IRQHandler ; 51: UART4
|
||||
DCD SSP2_IRQHandler ; 52: SSP2
|
||||
DCD LCD_IRQHandler ; 53: LCD
|
||||
DCD GPIO_IRQHandler ; 54: GPIO
|
||||
DCD PWM0_IRQHandler ; 55: PWM0
|
||||
DCD EEPROM_IRQHandler ; 56: EEPROM
|
||||
|
||||
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
PUBLIC CRP_Value
|
||||
RSEG CRPKEY : CODE(2)
|
||||
CRP_Value
|
||||
DCD 0xFFFFFFFF
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
WDT_IRQHandler
|
||||
B WDT_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER0_IRQHandler
|
||||
B TIMER0_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART0_IRQHandler
|
||||
B UART0_IRQHandler
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
PUBWEAK UART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART2_IRQHandler
|
||||
B UART2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PWM1_IRQHandler
|
||||
B PWM1_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C0_IRQHandler
|
||||
B I2C0_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C1_IRQHandler
|
||||
B I2C1_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C2_IRQHandler
|
||||
B I2C2_IRQHandler
|
||||
|
||||
;PUBWEAK SPIFI_IRQHandler
|
||||
;SECTION .text:CODE:REORDER(1)
|
||||
;SPIFI_IRQHandler
|
||||
;B SPIFI_IRQHandler
|
||||
|
||||
PUBWEAK SSP0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP0_IRQHandler
|
||||
B SSP0_IRQHandler
|
||||
|
||||
PUBWEAK SSP1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP1_IRQHandler
|
||||
B SSP1_IRQHandler
|
||||
|
||||
PUBWEAK PLL0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PLL0_IRQHandler
|
||||
B PLL0_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK EINT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT0_IRQHandler
|
||||
B EINT0_IRQHandler
|
||||
|
||||
PUBWEAK EINT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT1_IRQHandler
|
||||
B EINT1_IRQHandler
|
||||
|
||||
PUBWEAK EINT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT2_IRQHandler
|
||||
B EINT2_IRQHandler
|
||||
|
||||
PUBWEAK EINT3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT3_IRQHandler
|
||||
B EINT3_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK BOD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BOD_IRQHandler
|
||||
B BOD_IRQHandler
|
||||
|
||||
PUBWEAK USB_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USB_IRQHandler
|
||||
B USB_IRQHandler
|
||||
|
||||
PUBWEAK CAN_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN_IRQHandler
|
||||
B CAN_IRQHandler
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2S_IRQHandler
|
||||
B I2S_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK MCI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MCI_IRQHandler
|
||||
B MCI_IRQHandler
|
||||
|
||||
PUBWEAK MCPWM_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MCPWM_IRQHandler
|
||||
B MCPWM_IRQHandler
|
||||
|
||||
PUBWEAK QEI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
QEI_IRQHandler
|
||||
B QEI_IRQHandler
|
||||
|
||||
PUBWEAK PLL1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PLL1_IRQHandler
|
||||
B PLL1_IRQHandler
|
||||
|
||||
PUBWEAK USBActivity_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USBActivity_IRQHandler
|
||||
B USBActivity_IRQHandler
|
||||
|
||||
PUBWEAK CANActivity_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CANActivity_IRQHandler
|
||||
B CANActivity_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK SSP2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP2_IRQHandler
|
||||
B SSP2_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK GPIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
GPIO_IRQHandler
|
||||
B GPIO_IRQHandler
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PWM0_IRQHandler
|
||||
B PWM0_IRQHandler
|
||||
|
||||
PUBWEAK EEPROM_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EEPROM_IRQHandler
|
||||
B EEPROM_IRQHandler
|
||||
|
||||
END
|
||||
+507
File diff suppressed because it is too large
Load Diff
+571
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,23 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Split('''
|
||||
NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c
|
||||
''')
|
||||
CPPPATH = [cwd + '/NXP/LPC407x_8x_177x_8x/Include', cwd + '/../CMSIS/Include']
|
||||
CPPDEFINES = ['CORE_M4']
|
||||
|
||||
# add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s']
|
||||
|
||||
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,39 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Split('''
|
||||
source/lpc_adc.c
|
||||
source/lpc_bod.c
|
||||
source/lpc_can.c
|
||||
source/lpc_clkpwr.c
|
||||
source/lpc_crc.c
|
||||
source/lpc_dac.c
|
||||
source/lpc_eeprom.c
|
||||
source/lpc_emc.c
|
||||
source/lpc_exti.c
|
||||
source/lpc_gpdma.c
|
||||
source/lpc_gpio.c
|
||||
source/lpc_i2c.c
|
||||
source/lpc_i2s.c
|
||||
source/lpc_iap.c
|
||||
source/lpc_lcd.c
|
||||
source/lpc_mcpwm.c
|
||||
source/lpc_nvic.c
|
||||
source/lpc_pinsel.c
|
||||
source/lpc_pwm.c
|
||||
source/lpc_qei.c
|
||||
source/lpc_rtc.c
|
||||
source/lpc_ssp.c
|
||||
source/lpc_systick.c
|
||||
source/lpc_timer.c
|
||||
source/lpc_uart.c
|
||||
source/lpc_wwdt.c
|
||||
''')
|
||||
CPPPATH = [cwd + '/include']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,114 @@
|
||||
/**********************************************************************
|
||||
* $Id$ debug_frmwrk.h 2011-06-02
|
||||
*//**
|
||||
* @file debug_frmwrk.h
|
||||
* @brief Contains some utilities that used for debugging through UART
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef __DEBUG_FRMWRK_H_
|
||||
#define __DEBUG_FRMWRK_H_
|
||||
|
||||
#include "lpc_uart.h"
|
||||
|
||||
#define USED_UART_DEBUG_PORT 0
|
||||
|
||||
#define NUM_SKIPPED_ALLOWED (10)
|
||||
|
||||
#define DBG_GETVAL_IN_DEC (0)
|
||||
#define DBG_GETVAL_IN_HEX (1)
|
||||
//#define DBG_GETVAL_IN_CHARS (2)
|
||||
|
||||
#if (USED_UART_DEBUG_PORT == 0)
|
||||
#define DEBUG_UART_PORT (UART_0)
|
||||
#elif (USED_UART_DEBUG_PORT == 1)
|
||||
#define DEBUG_UART_PORT (UART_1)
|
||||
#elif (USED_UART_DEBUG_PORT == 2)
|
||||
#define DEBUG_UART_PORT (UART_2)
|
||||
#elif (USED_UART_DEBUG_PORT == 3)
|
||||
#define DEBUG_UART_PORT (UART_3)
|
||||
#elif (USED_UART_DEBUG_PORT == 4)
|
||||
#define DEBUG_UART_PORT (UART_4)
|
||||
#else
|
||||
#error "Invalid UART port selection!"
|
||||
#endif
|
||||
|
||||
#define _DBG(x) _db_msg(DEBUG_UART_PORT, x)
|
||||
#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x)
|
||||
|
||||
#define _DBC(x) _db_char(DEBUG_UART_PORT, x)
|
||||
|
||||
#define _DBD(x) _db_dec(DEBUG_UART_PORT, x)
|
||||
#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x)
|
||||
#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x)
|
||||
|
||||
#define _DBH(x) _db_hex(DEBUG_UART_PORT, x)
|
||||
#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x)
|
||||
#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x)
|
||||
|
||||
#define _DBH_(x) _db_hex_(DEBUG_UART_PORT, x)
|
||||
#define _DBH16_(x) _db_hex_16_(DEBUG_UART_PORT, x)
|
||||
#define _DBH32_(x) _db_hex_32_(DEBUG_UART_PORT, x)
|
||||
|
||||
#define _DG _db_get_char(DEBUG_UART_PORT)
|
||||
#define _DG_NONBLOCK(c) _db_get_char_nonblocking(DEBUG_UART_PORT,c)
|
||||
#define _DGV(option, numCh, val) _db_get_val(DEBUG_UART_PORT, option, numCh, val)
|
||||
|
||||
//void _printf (const char *format, ...);
|
||||
|
||||
extern void (*_db_msg)(UART_ID_Type UartID, const void *s);
|
||||
extern void (*_db_msg_)(UART_ID_Type UartID, const void *s);
|
||||
extern void (*_db_char)(UART_ID_Type UartID, uint8_t ch);
|
||||
extern void (*_db_dec)(UART_ID_Type UartID, uint8_t decn);
|
||||
extern void (*_db_dec_16)(UART_ID_Type UartID, uint16_t decn);
|
||||
extern void (*_db_dec_32)(UART_ID_Type UartID, uint32_t decn);
|
||||
extern void (*_db_hex)(UART_ID_Type UartID, uint8_t hexn);
|
||||
extern void (*_db_hex_16)(UART_ID_Type UartID, uint16_t hexn);
|
||||
extern void (*_db_hex_32)(UART_ID_Type UartID, uint32_t hexn);
|
||||
extern void (*_db_hex_)(UART_ID_Type UartID, uint8_t hexn);
|
||||
extern void (*_db_hex_16_)(UART_ID_Type UartID, uint16_t hexn);
|
||||
extern void (*_db_hex_32_)(UART_ID_Type UartID, uint32_t hexn);
|
||||
|
||||
extern uint8_t (*_db_get_char)(UART_ID_Type UartID);
|
||||
extern Bool (*_db_get_char_nonblocking)(UART_ID_Type UartID, uint8_t* c);
|
||||
extern uint8_t (*_db_get_val)(UART_ID_Type UartID, uint8_t option, uint8_t numCh, uint32_t * val);
|
||||
|
||||
uint8_t UARTGetValue (UART_ID_Type UartID, uint8_t option,
|
||||
uint8_t numCh, uint32_t* val);
|
||||
void UARTPutChar (UART_ID_Type UartID, uint8_t ch);
|
||||
void UARTPuts(UART_ID_Type UartID, const void *str);
|
||||
void UARTPuts_(UART_ID_Type UartID, const void *str);
|
||||
void UARTPutDec(UART_ID_Type UartID, uint8_t decnum);
|
||||
void UARTPutDec16(UART_ID_Type UartID, uint16_t decnum);
|
||||
void UARTPutDec32(UART_ID_Type UartID, uint32_t decnum);
|
||||
void UARTPutHex (UART_ID_Type UartID, uint8_t hexnum);
|
||||
void UARTPutHex16 (UART_ID_Type UartID, uint16_t hexnum);
|
||||
void UARTPutHex32 (UART_ID_Type UartID, uint32_t hexnum);
|
||||
uint8_t UARTGetChar (UART_ID_Type UartID);
|
||||
Bool UARTGetCharInNonBlock(UART_ID_Type UartID, uint8_t* c);
|
||||
void debug_frmwrk_init(void);
|
||||
|
||||
#endif /* __DEBUG_FRMWRK_H_ */
|
||||
@@ -0,0 +1,156 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc17xx_libcfg.h 2010-05-21
|
||||
***
|
||||
* @file lpc17xx_libcfg.h
|
||||
* @brief Library configuration file
|
||||
* @version 2.0
|
||||
* @date 21. May. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _LPC177x_8x_LIBCFG_H_
|
||||
#define _LPC177x_8x_LIBCFG_H_
|
||||
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
/************************** DEBUG MODE DEFINITIONS *********************************/
|
||||
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
|
||||
the "CHECK_PARAM" macro in the FW library code */
|
||||
|
||||
#define DEBUG
|
||||
|
||||
|
||||
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
|
||||
|
||||
/* Comment the line below to disable the specific peripheral inclusion */
|
||||
|
||||
/* DEBUG_FRAMWORK -------------------- */
|
||||
#define _DBGFWK
|
||||
|
||||
/* Clock & Power -------------------- */
|
||||
#define _CLKPWR
|
||||
|
||||
/* CRC -------------------- */
|
||||
#define _CRC
|
||||
|
||||
/* GPIO ------------------------------- */
|
||||
#define _GPIO
|
||||
|
||||
/* NVIC ------------------------------- */
|
||||
#define _NVIC
|
||||
|
||||
/* PINSEL ------------------------------- */
|
||||
#define _PINSEL
|
||||
|
||||
/* EXTI ------------------------------- */
|
||||
#define _EXTI
|
||||
|
||||
/* EMC ------------------------------- */
|
||||
#define _EMC
|
||||
|
||||
/* UART ------------------------------- */
|
||||
#define _UART
|
||||
|
||||
/* SPI ------------------------------- */
|
||||
#define _SPI
|
||||
|
||||
/* SYSTICK --------------------------- */
|
||||
#define _SYSTICK
|
||||
|
||||
/* SSP ------------------------------- */
|
||||
#define _SSP
|
||||
|
||||
|
||||
/* I2C ------------------------------- */
|
||||
#define _I2C
|
||||
|
||||
/* TIMER ------------------------------- */
|
||||
#define _TIM
|
||||
|
||||
/* WDT ------------------------------- */
|
||||
#define _WDT
|
||||
|
||||
|
||||
/* GPDMA ------------------------------- */
|
||||
#define _GPDMA
|
||||
|
||||
|
||||
/* DAC ------------------------------- */
|
||||
#define _DAC
|
||||
|
||||
/* ADC ------------------------------- */
|
||||
#define _ADC
|
||||
|
||||
/* EEPROM ------------------------------- */
|
||||
#define _EEPROM
|
||||
|
||||
/* PWM ------------------------------- */
|
||||
#define _PWM
|
||||
|
||||
/* RTC ------------------------------- */
|
||||
#define _RTC
|
||||
|
||||
/* I2S ------------------------------- */
|
||||
#define _I2S
|
||||
|
||||
/* USB device ------------------------------- */
|
||||
#define _USBDEV
|
||||
#ifdef _USBDEV
|
||||
#define _USB_DEV_AUDIO
|
||||
#define _USB_DEV_MASS_STORAGE
|
||||
#define _USB_DEV_HID
|
||||
#define _USB_DEV_VIRTUAL_COM
|
||||
#endif /*_USBDEV*/
|
||||
|
||||
/* USB Host ------------------------------- */
|
||||
#define _USBHost
|
||||
|
||||
/* QEI ------------------------------- */
|
||||
#define _QEI
|
||||
|
||||
/* MCPWM ------------------------------- */
|
||||
#define _MCPWM
|
||||
|
||||
/* CAN--------------------------------*/
|
||||
#define _CAN
|
||||
|
||||
/* EMAC ------------------------------ */
|
||||
#define _EMAC
|
||||
|
||||
/* LCD ------------------------------ */
|
||||
#define _LCD
|
||||
|
||||
/* MCI ------------------------------ */
|
||||
#define _MCI
|
||||
|
||||
/* IAP------------------------------ */
|
||||
#define _IAP
|
||||
|
||||
/* BOD------------------------------ */
|
||||
#define _BOD
|
||||
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
|
||||
|
||||
|
||||
#endif /* _LPC177x_8x_LIBCFG_H_ */
|
||||
@@ -0,0 +1,303 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_adc.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_adc.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for ADC firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup ADC ADC (Analog-to-Digital Converter)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_ADC_H_
|
||||
#define __LPC_ADC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC control register
|
||||
**********************************************************************/
|
||||
|
||||
/** Selects which of the AD0.0:7 pins (channels) is (are) to be sampled and converted */
|
||||
#define ADC_CR_CH_SEL(n) ((1UL << n))
|
||||
|
||||
/** The APB clock (PCLK) is divided by (this value plus one)
|
||||
* to produce the clock for the A/D */
|
||||
#define ADC_CR_CLKDIV(n) ((n<<8))
|
||||
|
||||
/** Repeated conversions A/D enable bit */
|
||||
#define ADC_CR_BURST ((1UL<<16))
|
||||
|
||||
/** ADC convert in power down mode; if 0, it's in power down mode; if 1, it's in normal
|
||||
* operation mode */
|
||||
#define ADC_CR_PDN ((1UL<<21))
|
||||
|
||||
/** Start mask bits */
|
||||
#define ADC_CR_START_MASK ((7UL<<24))
|
||||
|
||||
/** Select Start Mode controll the AD Converter in case the Burst bit is 0 (zero) */
|
||||
#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
|
||||
|
||||
/** Start conversion now */
|
||||
#define ADC_CR_START_NOW ((1UL<<24))
|
||||
|
||||
/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
|
||||
#define ADC_CR_START_EINT0 ((2UL<<24))
|
||||
|
||||
/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
|
||||
#define ADC_CR_START_CAP01 ((3UL<<24))
|
||||
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
|
||||
#define ADC_CR_START_MAT01 ((4UL<<24))
|
||||
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
|
||||
#define ADC_CR_START_MAT03 ((5UL<<24))
|
||||
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
|
||||
#define ADC_CR_START_MAT10 ((6UL<<24))
|
||||
|
||||
/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
|
||||
#define ADC_CR_START_MAT11 ((7UL<<24))
|
||||
|
||||
/** Start conversion on a falling edge on the selected CAP/MAT signal */
|
||||
#define ADC_CR_EDGE ((1UL<<27))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Global Data register
|
||||
**********************************************************************/
|
||||
|
||||
/** When DONE is 1, this field contains result value of ADC conversion
|
||||
* (in 12-bit value) */
|
||||
#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
|
||||
|
||||
/** These bits contain the channel from which the LS bits were converted */
|
||||
#define ADC_GDR_CH(n) (((n>>24)&0x7))
|
||||
|
||||
/** This bits is used to mask for Channel */
|
||||
#define ADC_GDR_CH_MASK ((7UL<<24))
|
||||
|
||||
/** This bit is 1 in burst mode if the results of one or
|
||||
* more conversions was (were) lost */
|
||||
#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
|
||||
|
||||
/** This bit is set to 1 when an A/D conversion completes */
|
||||
#define ADC_GDR_DONE_FLAG ((1UL<<31))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Interrupt register
|
||||
**********************************************************************/
|
||||
|
||||
/** These bits allow control over which A/D channels generate
|
||||
* interrupts for conversion completion */
|
||||
#define ADC_INTEN_CH(n) ((1UL<<n))
|
||||
|
||||
/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
|
||||
#define ADC_INTEN_GLOBAL ((1UL<<8))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Data register
|
||||
**********************************************************************/
|
||||
|
||||
/** When DONE is 1, this field contains result value of ADC conversion */
|
||||
#define ADC_DR_RESULT(n) (((n>>4)&0xFFF))
|
||||
|
||||
/** These bits mirror the OVERRRUN status flags that appear in the
|
||||
* result register for each A/D channel */
|
||||
#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
|
||||
|
||||
/** This bit is set to 1 when an A/D conversion completes. It is cleared
|
||||
* when this register is read */
|
||||
#define ADC_DR_DONE_FLAG ((1UL<<31))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Status register
|
||||
**********************************************************************/
|
||||
|
||||
/** These bits mirror the DONE status flags that appear in the result
|
||||
* register for each A/D channel */
|
||||
#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
|
||||
|
||||
/** These bits mirror the OVERRRUN status flags that appear in the
|
||||
* result register for each A/D channel */
|
||||
#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
|
||||
|
||||
/** This bit is the A/D interrupt flag */
|
||||
#define ADC_STAT_INT_FLAG ((1UL<<16))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for ADC Trim register
|
||||
**********************************************************************/
|
||||
|
||||
/** Offset trim bits for ADC operation */
|
||||
#define ADC_ADCOFFS(n) (((n&0xF)<<4))
|
||||
|
||||
/** Written to boot code*/
|
||||
#define ADC_TRIM(n) (((n&0xF)<<8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup ADC_Public_Types ADC Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* @brief ADC enumeration
|
||||
**********************************************************************/
|
||||
|
||||
/** @brief Channel Selection */
|
||||
typedef enum
|
||||
{
|
||||
ADC_CHANNEL_0 = 0, /*!< Channel 0 */
|
||||
ADC_CHANNEL_1, /*!< Channel 1 */
|
||||
ADC_CHANNEL_2, /*!< Channel 2 */
|
||||
ADC_CHANNEL_3, /*!< Channel 3 */
|
||||
ADC_CHANNEL_4, /*!< Channel 4 */
|
||||
ADC_CHANNEL_5, /*!< Channel 5 */
|
||||
ADC_CHANNEL_6, /*!< Channel 6 */
|
||||
ADC_CHANNEL_7 /*!< Channel 7 */
|
||||
}ADC_CHANNEL_SELECTION;
|
||||
|
||||
/** @brief Type of start option */
|
||||
typedef enum
|
||||
{
|
||||
ADC_START_CONTINUOUS = 0, /*!< Continuous mode */
|
||||
|
||||
ADC_START_NOW, /*!< Start conversion now */
|
||||
|
||||
ADC_START_ON_EINT0, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on P2.10/EINT0 */
|
||||
ADC_START_ON_CAP01, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on P1.27/CAP0.1 */
|
||||
ADC_START_ON_MAT01, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT0.1 */
|
||||
ADC_START_ON_MAT03, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT0.3 */
|
||||
ADC_START_ON_MAT10, /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT1.0 */
|
||||
ADC_START_ON_MAT11 /*!< Start conversion when the edge selected
|
||||
* by bit 27 occurs on MAT1.1 */
|
||||
} ADC_START_OPT;
|
||||
|
||||
|
||||
/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
|
||||
typedef enum
|
||||
{
|
||||
ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
|
||||
*on the selected CAP/MAT signal */
|
||||
ADC_START_ON_FALLING /*!< Start conversion on a falling edge
|
||||
*on the selected CAP/MAT signal */
|
||||
} ADC_START_ON_EDGE_OPT;
|
||||
|
||||
/** @brief* ADC type interrupt enum */
|
||||
typedef enum
|
||||
{
|
||||
ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
|
||||
ADC_ADINTEN1, /*!< Interrupt channel 1 */
|
||||
ADC_ADINTEN2, /*!< Interrupt channel 2 */
|
||||
ADC_ADINTEN3, /*!< Interrupt channel 3 */
|
||||
ADC_ADINTEN4, /*!< Interrupt channel 4 */
|
||||
ADC_ADINTEN5, /*!< Interrupt channel 5 */
|
||||
ADC_ADINTEN6, /*!< Interrupt channel 6 */
|
||||
ADC_ADINTEN7, /*!< Interrupt channel 7 */
|
||||
ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
|
||||
}ADC_TYPE_INT_OPT;
|
||||
|
||||
/** @brief ADC Data status */
|
||||
typedef enum
|
||||
{
|
||||
ADC_DATA_BURST = 0, /*Burst bit*/
|
||||
ADC_DATA_DONE /*Done bit*/
|
||||
}ADC_DATA_STATUS;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup ADC_Public_Functions ADC Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Init/DeInit ADC peripheral ----------------*/
|
||||
void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate);
|
||||
void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
|
||||
|
||||
/* Enable/Disable ADC functions --------------*/
|
||||
void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
|
||||
void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
|
||||
|
||||
/* Configure ADC functions -------------------*/
|
||||
void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
|
||||
void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
|
||||
|
||||
/* Get ADC information functions -------------------*/
|
||||
uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
|
||||
FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
|
||||
uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx);
|
||||
FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* LPC_ADC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,98 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_bod.h 2011-12-09
|
||||
*//**
|
||||
* @file lpc_bod.h
|
||||
* @brief Contain definitions & functions related to BOD.
|
||||
* @version 1.0
|
||||
* @date 09 December. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup BOD BOD (Brown-Out Detector)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/#ifndef __LPC_BOD_H
|
||||
#define __LPC_BOD_H
|
||||
#include "lpc_types.h"
|
||||
/** @defgroup BOD_Private_Macros BOD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/**********************************************************************
|
||||
** Power Mode Control register definitions
|
||||
**********************************************************************/
|
||||
#define BOD_PCON_BODRPM (0x01 << 2)
|
||||
#define BOD_PCON_BOGD (0x01 << 3)
|
||||
#define BOD_PCON_BORD (0x01 << 4)
|
||||
|
||||
/**********************************************************************
|
||||
** Reset Source Identification Register definitions
|
||||
**********************************************************************/
|
||||
#define BOD_RSID_POR (0x01 << 0)
|
||||
#define BOD_RSID_BODR (0x01 << 3)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BOD_Public_Types BOD Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief The field to configurate BOD
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enabled; /**< Enable BOD Circuit */
|
||||
uint8_t PowerReduced; /**< if ENABLE, BOD will be turned off in Power-down mode or Deep Sleep mode */
|
||||
/**< So, BOD can't be used to wake-up from these mode. */
|
||||
uint8_t ResetOnVoltageDown; /**< if ENABLE, reset the device when the VDD(REG)(3V3) voltage < the BOD reset trip level */
|
||||
}BOD_Config_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup BOD_Public_Functions BOD Public Functions
|
||||
* @{
|
||||
*/
|
||||
void BOD_Init( BOD_Config_Type* pConfig );
|
||||
int32_t BOD_ResetSourceStatus(void);
|
||||
void BOD_ResetSourceClr(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* end __LPC_BOD_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*****************************************************************************
|
||||
** End Of File
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,248 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_clkpwr.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_clkpwr.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Clock and Power Control firmware library on
|
||||
* LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup CLKPWR CLKPWR (Clock Power)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_CLKPWR_H_
|
||||
#define __LPC_CLKPWR_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
#include "system_LPC407x_8x_177x_8x.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/********************************************************************
|
||||
* Clock Source Selection Definitions
|
||||
**********************************************************************/
|
||||
#define CLKPWR_CLKSRCSEL_IRCOSC ((uint32_t)(0))
|
||||
#define CLKPWR_CLKSRCSEL_MAINOSC ((uint32_t)(1))
|
||||
|
||||
/********************************************************************
|
||||
* Clock type/domain Definitions (calculated from input and pre-configuration
|
||||
* parameter(s)
|
||||
**********************************************************************/
|
||||
#define CLKPWR_CLKTYPE_CPU ((uint32_t)(0))
|
||||
#define CLKPWR_CLKTYPE_PER ((uint32_t)(1))
|
||||
#define CLKPWR_CLKTYPE_EMC ((uint32_t)(2))
|
||||
#define CLKPWR_CLKTYPE_USB ((uint32_t)(3))
|
||||
|
||||
/********************************************************************
|
||||
* Power Control for Peripherals Definitions
|
||||
**********************************************************************/
|
||||
/** LCD controller power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCLCD ((uint32_t)(1<<0))
|
||||
|
||||
/** Timer/Counter 0 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
|
||||
|
||||
/* Timer/Counter 1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
|
||||
|
||||
/** UART0 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
|
||||
|
||||
/** UART1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
|
||||
|
||||
/** PWM0 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCPWM0 ((uint32_t)(1<<5))
|
||||
|
||||
/** PWM1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
|
||||
|
||||
/** The I2C0 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
|
||||
|
||||
/** UART4 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART4 ((uint32_t)(1<<8))
|
||||
|
||||
/** The RTC power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
|
||||
|
||||
/** The SSP1 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
|
||||
|
||||
/** External Memory controller power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCEMC ((uint32_t)(1<<11))
|
||||
|
||||
/** A/D converter 0 (ADC0) power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCADC ((uint32_t)(1<<12))
|
||||
|
||||
/** CAN Controller 1 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
|
||||
|
||||
/** CAN Controller 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
|
||||
|
||||
/** GPIO power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
|
||||
|
||||
/** Motor Control PWM */
|
||||
#define CLKPWR_PCONP_PCMCPWM ((uint32_t)(1<<17))
|
||||
|
||||
/** Quadrature Encoder Interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
|
||||
|
||||
/** The I2C1 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
|
||||
|
||||
/** The SSP2 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCSSP2 ((uint32_t)(1<<20))
|
||||
|
||||
/** The SSP0 interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
|
||||
|
||||
/** Timer 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
|
||||
|
||||
/** Timer 3 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
|
||||
|
||||
/** UART 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
|
||||
|
||||
/** UART 3 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
|
||||
|
||||
/** I2C interface 2 power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
|
||||
|
||||
/** I2S interface power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
|
||||
|
||||
/** SD card interface power/clock control bit */
|
||||
#define CLKPWR_PCONP_PCSDC ((uint32_t)(1<<28))
|
||||
|
||||
/** GP DMA function power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
|
||||
|
||||
/** Ethernet block power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
|
||||
|
||||
/** USB interface power/clock control bit*/
|
||||
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
|
||||
|
||||
/********************************************************************
|
||||
* Power Control for Peripherals Definitions
|
||||
**********************************************************************/
|
||||
#define CLKPWR_RSTCON0_LCD ((uint32_t)(0))
|
||||
#define CLKPWR_RSTCON0_TIM0 ((uint32_t)(1))
|
||||
#define CLKPWR_RSTCON0_TIM1 ((uint32_t)(2))
|
||||
#define CLKPWR_RSTCON0_UART0 ((uint32_t)(3))
|
||||
#define CLKPWR_RSTCON0_UART1 ((uint32_t)(4))
|
||||
#define CLKPWR_RSTCON0_PWM0 ((uint32_t)(5))
|
||||
#define CLKPWR_RSTCON0_PWM1 ((uint32_t)(6))
|
||||
#define CLKPWR_RSTCON0_I2C0 ((uint32_t)(7))
|
||||
#define CLKPWR_RSTCON0_UART4 ((uint32_t)(8))
|
||||
#define CLKPWR_RSTCON0_RTC ((uint32_t)(9))
|
||||
#define CLKPWR_RSTCON0_SSP1 ((uint32_t)(10))
|
||||
#define CLKPWR_RSTCON0_EMC ((uint32_t)(11))
|
||||
#define CLKPWR_RSTCON0_ADC ((uint32_t)(12))
|
||||
#define CLKPWR_RSTCON0_CAN1 ((uint32_t)(13))
|
||||
#define CLKPWR_RSTCON0_CAN2 ((uint32_t)(14))
|
||||
#define CLKPWR_RSTCON0_GPIO ((uint32_t)(15))
|
||||
#define CLKPWR_RSTCON0_MCPWM ((uint32_t)(17))
|
||||
#define CLKPWR_RSTCON0_QEI ((uint32_t)(18))
|
||||
#define CLKPWR_RSTCON0_I2C1 ((uint32_t)(19))
|
||||
#define CLKPWR_RSTCON0_SSP2 ((uint32_t)(20))
|
||||
#define CLKPWR_RSTCON0_SSP0 ((uint32_t)(21))
|
||||
#define CLKPWR_RSTCON0_TIM2 ((uint32_t)(22))
|
||||
#define CLKPWR_RSTCON0_TIM3 ((uint32_t)(23))
|
||||
#define CLKPWR_RSTCON0_UART2 ((uint32_t)(24))
|
||||
#define CLKPWR_RSTCON0_UART3 ((uint32_t)(25))
|
||||
#define CLKPWR_RSTCON0_I2C2 ((uint32_t)(26))
|
||||
#define CLKPWR_RSTCON0_I2S ((uint32_t)(27))
|
||||
#define CLKPWR_RSTCON0_SDC ((uint32_t)(28))
|
||||
#define CLKPWR_RSTCON0_GPDMA ((uint32_t)(29))
|
||||
#define CLKPWR_RSTCON0_ENET ((uint32_t)(30))
|
||||
#define CLKPWR_RSTCON0_USB ((uint32_t)(31))
|
||||
|
||||
#define CLKPWR_RSTCON1_IOCON ((uint32_t)(32))
|
||||
#define CLKPWR_RSTCON1_DAC ((uint32_t)(33))
|
||||
#define CLKPWR_RSTCON1_CANACC ((uint32_t)(34))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* External clock variable from system_LPC407x_8x_177x_8x.h */
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency (Pclk) */
|
||||
extern uint32_t EMCClock; /*!< EMC Clock Frequency */
|
||||
|
||||
/* External clock variable from lpc_clkpwr.h */
|
||||
extern uint32_t USBClock; /*!< USB Frequency */
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void CLKPWR_SetCLKDiv(uint8_t ClkType, uint8_t DivVal);
|
||||
uint32_t CLKPWR_GetCLK(uint8_t ClkType);
|
||||
void CLKPWR_ConfigPPWR(uint32_t PPType, FunctionalState NewState);
|
||||
void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState);
|
||||
void CLKPWR_Sleep(void);
|
||||
void CLKPWR_DeepSleep(void);
|
||||
void CLKPWR_PowerDown(void);
|
||||
void CLKPWR_DeepPowerDown(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_CLKPWR_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,110 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_crc.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_crc.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for CRC firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup CRC CRC (Cyclic Redundancy Check)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC__CRC_H_
|
||||
#define __LPC__CRC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* -------------------------- BIT DEFINITIONS ----------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CRC mode register
|
||||
**********************************************************************/
|
||||
#define CRC_BIT_RVS_WR (1<<2)
|
||||
#define CRC_CMPL_WR (1<<3)
|
||||
#define CRC_BIT_RVS_SUM (1<<4)
|
||||
#define CRC_CMPL_SUM (1<<5)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types ------------------------------------------------------------- */
|
||||
typedef enum
|
||||
{
|
||||
CRC_POLY_CRCCCITT = 0, /** CRC CCITT polynomial */
|
||||
CRC_POLY_CRC16, /** CRC-16 polynomial */
|
||||
CRC_POLY_CRC32 /** CRC-32 polynomial */
|
||||
}CRC_Type;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CRC_WR_8BIT = 1, /** 8-bit write: 1-cycle operation */
|
||||
CRC_WR_16BIT = 2, /** 16-bit write: 2-cycle operation */
|
||||
CRC_WR_32BIT = 4, /** 32-bit write: 4-cycle operation */
|
||||
}CRC_WR_SIZE;
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup CRC_Public_Functions CRC Public Functions
|
||||
* @{
|
||||
*/
|
||||
void CRC_Init(CRC_Type CRCType);
|
||||
void CRC_Reset(void);
|
||||
uint32_t CRC_CalcDataChecksum(uint32_t data, CRC_WR_SIZE SizeType);
|
||||
uint32_t CRC_CalcBlockChecksum(void *blockdata, uint32_t blocksize, CRC_WR_SIZE SizeType);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __LPC_CRC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,165 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_dac.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_dac.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for DAC firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup DAC DAC (Digital-to-Analog Converter)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_DAC_H_
|
||||
#define __LPC_DAC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** After the selected settling time after this field is written with a
|
||||
new VALUE, the voltage on the AOUT pin (with respect to VSSA)
|
||||
is VALUE/1024 × VREF */
|
||||
#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))
|
||||
|
||||
/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
|
||||
* and the maximum current is 700 microAmpere
|
||||
* If this bit = 1: The settling time of the DAC is 2.5 microsecond
|
||||
* and the maximum current is 350 microAmpere */
|
||||
#define DAC_BIAS_EN ((uint32_t)(1<<16))
|
||||
|
||||
/** Value to reload interrupt DMA counter */
|
||||
#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))
|
||||
|
||||
/** DCAR double buffering */
|
||||
#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))
|
||||
|
||||
/** DCAR Time out count enable */
|
||||
#define DAC_CNT_ENA ((uint32_t)(1<<2))
|
||||
|
||||
/** DCAR DMA access */
|
||||
#define DAC_DMA_ENA ((uint32_t)(1<<3))
|
||||
|
||||
/** DCAR DACCTRL mask bit */
|
||||
#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))
|
||||
|
||||
/** Macro to determine if it is valid DAC peripheral */
|
||||
#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))
|
||||
|
||||
/** Macro to check DAC current optional parameter */
|
||||
#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
|
||||
||(OPTION == DAC_MAX_CURRENT_350uA))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup DAC_Public_Types DAC Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Current option in DAC configuration option */
|
||||
typedef enum
|
||||
{
|
||||
DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,
|
||||
and the maximum current is 700 uA */
|
||||
DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us
|
||||
and the maximum current is 350 uA */
|
||||
} DAC_CURRENT_OPT;
|
||||
|
||||
/**
|
||||
* @brief Configuration for DAC converter control register */
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint8_t DBLBUF_ENA; /**<
|
||||
- If 0: Disable DACR double buffering
|
||||
|
||||
- If 1: when bit CNT_ENA, enable DACR double buffering feature
|
||||
*/
|
||||
uint8_t CNT_ENA; /*!<
|
||||
- If 0: Time out counter is disable
|
||||
|
||||
-1: Time out conter is enable
|
||||
*/
|
||||
uint8_t DMA_ENA; /*!<
|
||||
- If 0: DMA access is disable
|
||||
|
||||
- If 1: DMA burst request
|
||||
*/
|
||||
uint8_t RESERVED;
|
||||
|
||||
} DAC_CONVERTER_CFG_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup DAC_Public_Functions DAC Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DAC_Init(uint8_t DAC_Id);
|
||||
void DAC_UpdateValue (uint8_t DAC_Id, uint32_t dac_value);
|
||||
void DAC_SetBias (uint8_t DAC_Id,uint32_t bias);
|
||||
void DAC_ConfigDAConverterControl (uint8_t DAC_Id,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
|
||||
void DAC_SetDMATimeOut(uint8_t DAC_Id,uint32_t time_out);
|
||||
uint8_t DAC_IsIntRequested(uint8_t DAC_Id);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __LPC_DAC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
|
||||
@@ -0,0 +1,152 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_eeprom.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_eeprom.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for EEPROM firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup EEPROM EEPROM (Electrically Erasable Programmable Read-Only Memory)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_EEPROM_H_
|
||||
#define __LPC_EEPROM_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Private macros ------------------------------------------------------------- */
|
||||
/** @defgroup EEPROM_Private_Macros EEPROM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* -------------------------- BIT DEFINITIONS --------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for EEPROM command register
|
||||
**********************************************************************/
|
||||
#define EEPROM_CMD_8_BIT_READ (0)
|
||||
#define EEPROM_CMD_16_BIT_READ (1)
|
||||
#define EEPROM_CMD_32_BIT_READ (2)
|
||||
#define EEPROM_CMD_8_BIT_WRITE (3)
|
||||
#define EEPROM_CMD_16_BIT_WRITE (4)
|
||||
#define EEPROM_CMD_32_BIT_WRITE (5)
|
||||
#define EEPROM_CMD_ERASE_PRG_PAGE (6)
|
||||
|
||||
#define EEPROM_CMD_RDPREFETCH (1<<3)
|
||||
|
||||
#define EEPROM_PAGE_SIZE 64
|
||||
#define EEPROM_PAGE_NUM 63
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for EEPROM address register
|
||||
**********************************************************************/
|
||||
#define EEPROM_PAGE_OFFSET(n) (n&0x3F)
|
||||
#define EEPROM_PAGE_ADRESS(n) ((n&0x3F)<<6)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for EEPROM write data register
|
||||
**********************************************************************/
|
||||
#define EEPROM_WDATA_8_BIT(n) (n&0x000000FF)
|
||||
#define EEPROM_WDATA_16_BIT(n) (n&0x0000FFFF)
|
||||
#define EEPROM_WDATA_32_BIT(n) (n&0xFFFFFFFF)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for EEPROM read data register
|
||||
**********************************************************************/
|
||||
#define EEPROM_RDATA_8_BIT(n) (n&0x000000FF)
|
||||
#define EEPROM_RDATA_16_BIT(n) (n&0x0000FFFF)
|
||||
#define EEPROM_RDATA_32_BIT(n) (n&0xFFFFFFFF)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for EEPROM power down register
|
||||
**********************************************************************/
|
||||
#define EEPROM_PWRDWN (1<<0)
|
||||
|
||||
#define EEPROM_ENDOF_RW (26)
|
||||
#define EEPROM_ENDOF_PROG (28)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup EEPROM_Public_Types EEPROM Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MODE_8_BIT = 0,
|
||||
MODE_16_BIT,
|
||||
MODE_32_BIT
|
||||
}EEPROM_Mode_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup EEPROM_Public_Functions EEPROM Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EEPROM_Init(void);
|
||||
void EEPROM_Write(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size);
|
||||
void EEPROM_Read(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size);
|
||||
void EEPROM_Erase(uint16_t address);
|
||||
void EEPROM_PowerDown(FunctionalState NewState);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __LPC_EEPROM_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,158 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_exti.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_exti.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for External Interrupt firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup EXTI EXTI (External Interrupt)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_EXTI_H_
|
||||
#define __LPC_EXTI_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
/*********************************************************************//**
|
||||
* Macro defines for EXTI control register
|
||||
**********************************************************************/
|
||||
#define EXTI_EINT0_BIT_MARK 0x01
|
||||
#define EXTI_EINT1_BIT_MARK 0x02
|
||||
#define EXTI_EINT2_BIT_MARK 0x04
|
||||
#define EXTI_EINT3_BIT_MARK 0x08
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup EXTI_Public_Types EXTI Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI external interrupt line option
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_EINT0, /*!< External interrupt 0, P2.10 */
|
||||
EXTI_EINT1, /*!< External interrupt 0, P2.11 */
|
||||
EXTI_EINT2, /*!< External interrupt 0, P2.12 */
|
||||
EXTI_EINT3 /*!< External interrupt 0, P2.13 */
|
||||
} EXTI_LINE_ENUM;
|
||||
|
||||
/**
|
||||
* @brief EXTI mode option
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_MODE_LEVEL_SENSITIVE, /*!< Level sensitivity is selected */
|
||||
EXTI_MODE_EDGE_SENSITIVE /*!< Edge sensitivity is selected */
|
||||
} EXTI_MODE_ENUM;
|
||||
|
||||
/**
|
||||
* @brief EXTI polarity option
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE, /*!< Low active or falling edge sensitive
|
||||
depending on pin mode */
|
||||
EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE /*!< High active or rising edge sensitive
|
||||
depending on pin mode */
|
||||
} EXTI_POLARITY_ENUM;
|
||||
|
||||
/**
|
||||
* @brief EXTI Initialize structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/** Select external interrupt pin (EINT0, EINT1, EINT 2, EINT3) */
|
||||
EXTI_LINE_ENUM EXTI_Line;
|
||||
|
||||
/** Choose between Level-sensitivity or Edge sensitivity */
|
||||
EXTI_MODE_ENUM EXTI_Mode;
|
||||
|
||||
/** If EXTI mode is level-sensitive: this element use to select low or high active level
|
||||
if EXTI mode is polarity-sensitive: this element use to select falling or rising edge */
|
||||
EXTI_POLARITY_ENUM EXTI_polarity;
|
||||
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup EXTI_Public_Functions EXTI Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EXTI_Init(void);
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
void EXTI_Config(EXTI_InitTypeDef *EXTICfg);
|
||||
void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode);
|
||||
void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity);
|
||||
void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __LPC_EXTI_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,418 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_gpdma.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_gpdma.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for GPDMA firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_GPDMA_H_
|
||||
#define __LPC_GPDMA_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** DMA Connection number definitions */
|
||||
#define GPDMA_CONN_MCI ((1UL)) /** SD card */
|
||||
#define GPDMA_CONN_SSP0_Tx ((2UL)) /**< SSP0 Tx */
|
||||
#define GPDMA_CONN_SSP0_Rx ((3UL)) /**< SSP0 Rx */
|
||||
#define GPDMA_CONN_SSP1_Tx ((4UL)) /**< SSP1 Tx */
|
||||
#define GPDMA_CONN_SSP1_Rx ((5UL)) /**< SSP1 Rx */
|
||||
#define GPDMA_CONN_SSP2_Tx ((6UL)) /**< SSP2 Tx */
|
||||
#define GPDMA_CONN_SSP2_Rx ((7UL)) /**< SSP2 Rx */
|
||||
#define GPDMA_CONN_ADC ((8UL)) /**< ADC */
|
||||
#define GPDMA_CONN_DAC ((9UL)) /**< DAC */
|
||||
#define GPDMA_CONN_UART0_Tx ((10UL)) /**< UART0 Tx */
|
||||
#define GPDMA_CONN_UART0_Rx ((11UL)) /**< UART0 Rx */
|
||||
#define GPDMA_CONN_UART1_Tx ((12UL)) /**< UART1 Tx */
|
||||
#define GPDMA_CONN_UART1_Rx ((13UL)) /**< UART1 Rx */
|
||||
#define GPDMA_CONN_UART2_Tx ((14UL)) /**< UART2 Tx */
|
||||
#define GPDMA_CONN_UART2_Rx ((15UL)) /**< UART2 Rx */
|
||||
#define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
|
||||
#define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
|
||||
#define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
|
||||
#define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
|
||||
#define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
|
||||
#define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
|
||||
#define GPDMA_CONN_I2S_Channel_0 ((22UL)) /**< I2S channel 0 */
|
||||
#define GPDMA_CONN_I2S_Channel_1 ((23UL)) /**< I2S channel 1 */
|
||||
#define GPDMA_CONN_UART3_Tx ((26UL)) /**< UART3 Tx */
|
||||
#define GPDMA_CONN_UART3_Rx ((27UL)) /**< UART3 Rx */
|
||||
#define GPDMA_CONN_UART4_Tx ((28UL)) /**< UART3 Tx */
|
||||
#define GPDMA_CONN_UART4_Rx ((29UL)) /**< UART3 Rx */
|
||||
#define GPDMA_CONN_MAT3_0 ((30UL)) /**< MAT3.0 */
|
||||
#define GPDMA_CONN_MAT3_1 ((31UL)) /**< MAT3.1 */
|
||||
|
||||
/** GPDMA Transfer type definitions: Memory to memory - DMA control */
|
||||
#define GPDMA_TRANSFERTYPE_M2M ((0UL))
|
||||
/** GPDMA Transfer type definitions: Memory to peripheral - DMA control */
|
||||
#define GPDMA_TRANSFERTYPE_M2P ((1UL))
|
||||
/** GPDMA Transfer type definitions: Peripheral to memory - DMA control */
|
||||
#define GPDMA_TRANSFERTYPE_P2M ((2UL))
|
||||
/** Source peripheral to destination peripheral - DMA control */
|
||||
#define GPDMA_TRANSFERTYPE_P2P ((3UL))
|
||||
/** Memory to peripheral - Destination peripheral control */
|
||||
#define GPDMA_TRANSFERTYPE_M2P_DEST_CTRL ((5UL))
|
||||
/** Peripheral to memory - Source peripheral control */
|
||||
#define GPDMA_TRANSFERTYPE_P2M_SRC_CTRL ((6UL))
|
||||
|
||||
/** Burst size in Source and Destination definitions */
|
||||
#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
|
||||
#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
|
||||
#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
|
||||
#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
|
||||
#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
|
||||
#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
|
||||
#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
|
||||
#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
|
||||
|
||||
/** Width in Source transfer width and Destination transfer width definitions */
|
||||
#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
|
||||
#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
|
||||
#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
|
||||
|
||||
/** DMA Request Select Mode definitions */
|
||||
#define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
|
||||
#define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Interrupt Status register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACIntStat_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Interrupt Terminal Count Request Status register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Interrupt Terminal Count Request Clear register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Interrupt Error Status register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Interrupt Error Clear register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Raw Interrupt Terminal Count Status register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Raw Error Interrupt Status register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Enabled Channel register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
|
||||
#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Software Burst Request register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
|
||||
#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Software Single Request register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
|
||||
#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Software Last Burst Request register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
|
||||
#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Software Last Single Request register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
|
||||
#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Configuration register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
|
||||
#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
|
||||
#define GPDMA_DMACConfig_BITMASK ((0x03))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Synchronization register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
|
||||
#define GPDMA_DMACSync_BITMASK ((0xFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Request Select register
|
||||
**********************************************************************/
|
||||
#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
|
||||
#define GPDMA_DMAReqSel_BITMASK ((0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Channel Linked List Item registers
|
||||
**********************************************************************/
|
||||
/** DMA Channel Linked List Item registers bit mask*/
|
||||
#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA channel control registers
|
||||
**********************************************************************/
|
||||
/** Transfer size*/
|
||||
#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0))
|
||||
/** Source burst size*/
|
||||
#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12))
|
||||
/** Destination burst size*/
|
||||
#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15))
|
||||
/** Source transfer width*/
|
||||
#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18))
|
||||
/** Destination transfer width*/
|
||||
#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21))
|
||||
/** Source increment*/
|
||||
#define GPDMA_DMACCxControl_SI ((1UL<<26))
|
||||
/** Destination increment*/
|
||||
#define GPDMA_DMACCxControl_DI ((1UL<<27))
|
||||
/** Indicates that the access is in user mode or privileged mode*/
|
||||
#define GPDMA_DMACCxControl_Prot1 ((1UL<<28))
|
||||
/** Indicates that the access is bufferable or not bufferable*/
|
||||
#define GPDMA_DMACCxControl_Prot2 ((1UL<<29))
|
||||
/** Indicates that the access is cacheable or not cacheable*/
|
||||
#define GPDMA_DMACCxControl_Prot3 ((1UL<<30))
|
||||
/** Terminal count interrupt enable bit */
|
||||
#define GPDMA_DMACCxControl_I ((1UL<<31))
|
||||
/** DMA channel control registers bit mask */
|
||||
#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA Channel Configuration registers
|
||||
**********************************************************************/
|
||||
/** DMA control enable*/
|
||||
#define GPDMA_DMACCxConfig_E ((1UL<<0))
|
||||
/** Source peripheral*/
|
||||
#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1))
|
||||
/** Destination peripheral*/
|
||||
#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6))
|
||||
/** This value indicates the type of transfer*/
|
||||
#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11))
|
||||
/** Interrupt error mask*/
|
||||
#define GPDMA_DMACCxConfig_IE ((1UL<<14))
|
||||
/** Terminal count interrupt mask*/
|
||||
#define GPDMA_DMACCxConfig_ITC ((1UL<<15))
|
||||
/** Lock*/
|
||||
#define GPDMA_DMACCxConfig_L ((1UL<<16))
|
||||
/** Active*/
|
||||
#define GPDMA_DMACCxConfig_A ((1UL<<17))
|
||||
/** Halt*/
|
||||
#define GPDMA_DMACCxConfig_H ((1UL<<18))
|
||||
/** DMA Channel Configuration registers bit mask */
|
||||
#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup GPDMA_Public_Types GPDMA Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPDMA Status enumeration
|
||||
*/
|
||||
typedef enum {
|
||||
GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
|
||||
GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
|
||||
GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
|
||||
GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
|
||||
GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
|
||||
GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
|
||||
} GPDMA_Status_Type;
|
||||
|
||||
/**
|
||||
* @brief GPDMA Interrupt clear status enumeration
|
||||
*/
|
||||
typedef enum{
|
||||
GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
|
||||
GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
|
||||
}GPDMA_StateClear_Type;
|
||||
|
||||
/**
|
||||
* @brief GPDMA Channel configuration structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ChannelNum; /**< DMA channel number, should be in
|
||||
range from 0 to 7.
|
||||
Note: DMA channel 0 has the highest priority
|
||||
and DMA channel 7 the lowest priority.
|
||||
*/
|
||||
uint32_t TransferSize; /**< Length/Size of transfer */
|
||||
uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
|
||||
uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
|
||||
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
|
||||
uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
|
||||
GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
|
||||
uint32_t TransferType; /**< Transfer Type, should be one of the following:
|
||||
- GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
|
||||
- GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
|
||||
- GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
|
||||
- GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
|
||||
*/
|
||||
uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
|
||||
GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
|
||||
following:
|
||||
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
|
||||
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
|
||||
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
|
||||
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
|
||||
- GPDMA_CONN_ADC: ADC
|
||||
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
|
||||
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
|
||||
- GPDMA_CONN_DAC: DAC
|
||||
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
|
||||
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
|
||||
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
|
||||
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
|
||||
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
|
||||
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
|
||||
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
|
||||
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
|
||||
*/
|
||||
uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
|
||||
GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
|
||||
following:
|
||||
- GPDMA_CONN_SSP0_Tx: SSP0, Tx
|
||||
- GPDMA_CONN_SSP0_Rx: SSP0, Rx
|
||||
- GPDMA_CONN_SSP1_Tx: SSP1, Tx
|
||||
- GPDMA_CONN_SSP1_Rx: SSP1, Rx
|
||||
- GPDMA_CONN_ADC: ADC
|
||||
- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
|
||||
- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
|
||||
- GPDMA_CONN_DAC: DAC
|
||||
- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
|
||||
- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
|
||||
- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
|
||||
- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
|
||||
- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
|
||||
- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
|
||||
- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
|
||||
- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
|
||||
*/
|
||||
uint32_t DMALLI; /**< Linker List Item structure data address
|
||||
if there's no Linker List, set as '0'
|
||||
*/
|
||||
} GPDMA_Channel_CFG_Type;
|
||||
|
||||
/**
|
||||
* @brief GPDMA Linker List Item structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t SrcAddr; /**< Source Address */
|
||||
uint32_t DstAddr; /**< Destination address */
|
||||
uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
|
||||
uint32_t Control; /**< GPDMA Control of this LLI */
|
||||
} GPDMA_LLI_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void GPDMA_Init(void);
|
||||
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
|
||||
IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
|
||||
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
|
||||
void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
|
||||
//void GPDMA_IntHandler(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_GPDMA_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,188 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_gpio.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_gpio.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for GPIO firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup GPIO GPIO (General Purpose Input/Output)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_GPIO_H_
|
||||
#define __LPC_GPIO_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Macros GPIO Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_DIRECTION_INPUT (0)
|
||||
#define GPIO_DIRECTION_OUTPUT (1)
|
||||
|
||||
/** Fast GPIO port 0 byte accessible definition */
|
||||
#define GPIO0_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO0_BASE))
|
||||
/** Fast GPIO port 1 byte accessible definition */
|
||||
#define GPIO1_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO1_BASE))
|
||||
/** Fast GPIO port 2 byte accessible definition */
|
||||
#define GPIO2_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO2_BASE))
|
||||
/** Fast GPIO port 3 byte accessible definition */
|
||||
#define GPIO3_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO3_BASE))
|
||||
/** Fast GPIO port 4 byte accessible definition */
|
||||
#define GPIO4_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO4_BASE))
|
||||
/** Fast GPIO port 4 byte accessible definition */
|
||||
#define GPIO5_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO5_BASE))
|
||||
|
||||
|
||||
|
||||
/** Fast GPIO port 0 half-word accessible definition */
|
||||
#define GPIO0_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO0_BASE))
|
||||
/** Fast GPIO port 1 half-word accessible definition */
|
||||
#define GPIO1_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO1_BASE))
|
||||
/** Fast GPIO port 2 half-word accessible definition */
|
||||
#define GPIO2_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO2_BASE))
|
||||
/** Fast GPIO port 3 half-word accessible definition */
|
||||
#define GPIO3_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO3_BASE))
|
||||
/** Fast GPIO port 4 half-word accessible definition */
|
||||
#define GPIO4_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO4_BASE))
|
||||
/** Fast GPIO port 4 half-word accessible definition */
|
||||
#define GPIO5_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO5_BASE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Types GPIO Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Fast GPIO port byte type definition
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint8_t FIODIR[4]; /**< FIO direction register in byte-align */
|
||||
uint32_t RESERVED0[3]; /**< Reserved */
|
||||
__IO uint8_t FIOMASK[4]; /**< FIO mask register in byte-align */
|
||||
__IO uint8_t FIOPIN[4]; /**< FIO pin register in byte align */
|
||||
__IO uint8_t FIOSET[4]; /**< FIO set register in byte-align */
|
||||
__O uint8_t FIOCLR[4]; /**< FIO clear register in byte-align */
|
||||
} GPIO_Byte_TypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast GPIO port half-word type definition
|
||||
*/
|
||||
typedef struct {
|
||||
__IO uint16_t FIODIRL; /**< FIO direction register lower halfword part */
|
||||
__IO uint16_t FIODIRU; /**< FIO direction register upper halfword part */
|
||||
uint32_t RESERVED0[3]; /**< Reserved */
|
||||
__IO uint16_t FIOMASKL; /**< FIO mask register lower halfword part */
|
||||
__IO uint16_t FIOMASKU; /**< FIO mask register upper halfword part */
|
||||
__IO uint16_t FIOPINL; /**< FIO pin register lower halfword part */
|
||||
__IO uint16_t FIOPINU; /**< FIO pin register upper halfword part */
|
||||
__IO uint16_t FIOSETL; /**< FIO set register lower halfword part */
|
||||
__IO uint16_t FIOSETU; /**< FIO set register upper halfword part */
|
||||
__O uint16_t FIOCLRL; /**< FIO clear register lower halfword part */
|
||||
__O uint16_t FIOCLRU; /**< FIO clear register upper halfword part */
|
||||
} GPIO_HalfWord_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup GPIO_Public_Functions GPIO Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* GPIO style ------------------------------- */
|
||||
void GPIO_Init(void);
|
||||
void GPIO_Deinit(void);
|
||||
void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
|
||||
void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
|
||||
void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
|
||||
void GPIO_OutputValue(uint8_t portNum, uint32_t bitMask, uint8_t value);
|
||||
uint32_t GPIO_ReadValue(uint8_t portNum);
|
||||
void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
|
||||
FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
|
||||
void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
|
||||
|
||||
/* FIO (word-accessible) style ------------------------------- */
|
||||
void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
|
||||
void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
|
||||
void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
|
||||
uint32_t FIO_ReadValue(uint8_t portNum);
|
||||
void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
|
||||
void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
|
||||
FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
|
||||
void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
|
||||
|
||||
/* FIO (halfword-accessible) style ------------------------------- */
|
||||
void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);
|
||||
void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);
|
||||
void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
|
||||
void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
|
||||
uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);
|
||||
|
||||
/* FIO (byte-accessible) style ------------------------------- */
|
||||
void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);
|
||||
void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);
|
||||
void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
|
||||
void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
|
||||
uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_GPIO_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,420 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_i2c.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_i2c.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for I2C firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup I2C I2C (Inter-IC Control bus)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_I2C_H_
|
||||
#define __LPC_I2C_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Private_Macros I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*******************************************************************//**
|
||||
* I2C Control Set register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
|
||||
#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
|
||||
#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
|
||||
#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
|
||||
#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
|
||||
|
||||
/*******************************************************************//**
|
||||
* I2C Control Clear register description
|
||||
*********************************************************************/
|
||||
/** Assert acknowledge Clear bit */
|
||||
#define I2C_I2CONCLR_AAC ((1<<2))
|
||||
/** I2C interrupt Clear bit */
|
||||
#define I2C_I2CONCLR_SIC ((1<<3))
|
||||
/** I2C STOP Clear bit */
|
||||
#define I2C_I2CONCLR_STOC ((1<<4))
|
||||
/** START flag Clear bit */
|
||||
#define I2C_I2CONCLR_STAC ((1<<5))
|
||||
/** I2C interface Disable bit */
|
||||
#define I2C_I2CONCLR_I2ENC ((1<<6))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Status Code definition (I2C Status register)
|
||||
*********************************************************************/
|
||||
/* Return Code in I2C status register */
|
||||
#define I2C_STAT_CODE_BITMASK ((0xF8))
|
||||
|
||||
/* I2C return status code definitions ----------------------------- */
|
||||
|
||||
/** No relevant information */
|
||||
#define I2C_I2STAT_NO_INF ((0xF8))
|
||||
|
||||
/** Bus Error */
|
||||
#define I2C_I2STAT_BUS_ERROR ((0x00))
|
||||
|
||||
/* Master transmit mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_START ((0x08))
|
||||
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_TX_RESTART ((0x10))
|
||||
|
||||
/** SLA+W has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
|
||||
|
||||
/** SLA+W has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
|
||||
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
|
||||
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
|
||||
|
||||
/** Arbitration lost in SLA+R/W or Data bytes */
|
||||
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
|
||||
|
||||
/* Master receive mode -------------------------------------------- */
|
||||
/** A start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_START ((0x08))
|
||||
|
||||
/** A repeat start condition has been transmitted */
|
||||
#define I2C_I2STAT_M_RX_RESTART ((0x10))
|
||||
|
||||
/** Arbitration lost */
|
||||
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
|
||||
|
||||
/** SLA+R has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
|
||||
|
||||
/** SLA+R has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
|
||||
|
||||
/** Data has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
|
||||
|
||||
/** Data has been received, NACK has been return */
|
||||
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
|
||||
|
||||
/* Slave receive mode -------------------------------------------- */
|
||||
/** Own slave address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
|
||||
|
||||
/** General call address has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
|
||||
|
||||
/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
|
||||
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
|
||||
|
||||
/** Previously addressed with own SLV address;
|
||||
* Data has been received, ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
|
||||
|
||||
/** Previously addressed with own SLA;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
|
||||
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
|
||||
|
||||
/** Previously addressed with General Call;
|
||||
* Data has been received and NOT ACK has been return */
|
||||
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
|
||||
|
||||
/** A STOP condition or repeated START condition has
|
||||
* been received while still addressed as SLV/REC
|
||||
* (Slave Receive) or SLV/TRX (Slave Transmit) */
|
||||
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
|
||||
|
||||
/** Slave transmit mode */
|
||||
/** Own SLA+R has been received, ACK has been returned */
|
||||
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
|
||||
|
||||
/** Arbitration lost in SLA+R/W as master */
|
||||
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
|
||||
|
||||
/** Data has been transmitted, ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
|
||||
|
||||
/** Data has been transmitted, NACK has been received */
|
||||
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
|
||||
|
||||
/** Last data byte in I2DAT has been transmitted (AA = 0);
|
||||
ACK has been received */
|
||||
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
|
||||
|
||||
/** Time out in case of using I2C slave mode */
|
||||
#define I2C_SLAVE_TIME_OUT 0x10000UL
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data register definition
|
||||
*********************************************************************/
|
||||
/** Mask for I2DAT register*/
|
||||
#define I2C_I2DAT_BITMASK ((0xFF))
|
||||
|
||||
/** Idle data value will be send out in slave mode in case of the actual
|
||||
* expecting data requested from the master is greater than its sending data
|
||||
* length that can be supported */
|
||||
#define I2C_I2DAT_IDLE_CHAR (0xFF)
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Monitor mode control register description
|
||||
*********************************************************************/
|
||||
#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
|
||||
#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
|
||||
#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
|
||||
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Data buffer register description
|
||||
*********************************************************************/
|
||||
/** I2C Data buffer register bit mask */
|
||||
#define I2DATA_BUFFER_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Slave Address registers definition
|
||||
*********************************************************************/
|
||||
/** General Call enable bit */
|
||||
#define I2C_I2ADR_GC ((1<<0))
|
||||
|
||||
/** I2C Slave Address registers bit mask */
|
||||
#define I2C_I2ADR_BITMASK ((0xFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C Mask Register definition
|
||||
*********************************************************************/
|
||||
/** I2C Mask Register mask field */
|
||||
#define I2C_I2MASK_MASK(n) ((n&0xFE))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL HIGH duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL HIGH duty cycle Register bit mask */
|
||||
#define I2C_I2SCLH_BITMASK ((0xFFFF))
|
||||
|
||||
/********************************************************************//**
|
||||
* I2C SCL LOW duty cycle Register definition
|
||||
*********************************************************************/
|
||||
/** I2C SCL LOW duty cycle Register bit mask */
|
||||
#define I2C_I2SCLL_BITMASK ((0xFFFF))
|
||||
|
||||
|
||||
/* I2C status values */
|
||||
#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
|
||||
#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
|
||||
#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
|
||||
|
||||
|
||||
/* I2C state handle return values */
|
||||
#define I2C_OK 0x00
|
||||
#define I2C_BYTE_SENT 0x01
|
||||
#define I2C_BYTE_RECV 0x02
|
||||
#define I2C_LAST_BYTE_RECV 0x04
|
||||
#define I2C_SEND_END 0x08
|
||||
#define I2C_RECV_END 0x10
|
||||
#define I2C_STA_STO_RECV 0x20
|
||||
|
||||
|
||||
#define I2C_ERR (0x10000000)
|
||||
#define I2C_NAK_RECV (0x10000000 |0x01)
|
||||
|
||||
#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Types I2C Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_0 = 0,
|
||||
I2C_1,
|
||||
I2C_2
|
||||
} en_I2C_unitId;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_MASTER_MODE,
|
||||
I2C_SLAVE_MODE,
|
||||
I2C_GENERAL_MODE,
|
||||
} en_I2C_Mode;
|
||||
/**
|
||||
* @brief I2C Own slave address setting structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
|
||||
should be in range from 0..3
|
||||
*/
|
||||
uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
|
||||
uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
|
||||
when I2C control being in Slave mode, should be:
|
||||
- ENABLE: Enable General Call function.
|
||||
- DISABLE: Disable General Call function.
|
||||
*/
|
||||
uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
|
||||
which is set to '1' will cause an automatic compare on
|
||||
the corresponding bit of the received address when it
|
||||
is compared to the SlaveAddr_7bit value associated with this
|
||||
mask register. In other words, bits in SlaveAddr_7bit value
|
||||
which are masked are not taken into account in determining
|
||||
an address match
|
||||
*/
|
||||
} I2C_OWNSLAVEADDR_CFG_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Master transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
|
||||
__IO uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
|
||||
is not used */
|
||||
uint32_t tx_length; /**< Transmit data length - 0 if data transmit
|
||||
is not used*/
|
||||
__IO uint32_t tx_count; /**< Current Transmit data counter */
|
||||
__IO uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
|
||||
is not used */
|
||||
uint32_t rx_length; /**< Receive data length - 0 if data receive is
|
||||
not used */
|
||||
__IO uint32_t rx_count; /**< Current Receive data counter */
|
||||
uint32_t retransmissions_max; /**< Max Re-Transmission value */
|
||||
uint32_t retransmissions_count; /**< Current Re-Transmission counter */
|
||||
__IO uint32_t status; /**< Current status of I2C activity */
|
||||
void (*callback)(void); /**< Pointer to Call back function when transmission complete
|
||||
used in interrupt transfer mode */
|
||||
} I2C_M_SETUP_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Slave transfer setup data structure definitions
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint8_t* tx_data;
|
||||
uint32_t tx_length;
|
||||
__IO uint32_t tx_count;
|
||||
__IO uint8_t* rx_data;
|
||||
uint32_t rx_length;
|
||||
__IO uint32_t rx_count;
|
||||
__IO uint32_t status;
|
||||
void (*callback)(void);
|
||||
} I2C_S_SETUP_Type;
|
||||
|
||||
/**
|
||||
* @brief Transfer option type definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
|
||||
I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
|
||||
} I2C_TRANSFER_OPT_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup I2C_Public_Functions I2C Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I2C Init/DeInit functions ---------- */
|
||||
void I2C_Init(en_I2C_unitId i2cId, uint32_t clockrate);
|
||||
void I2C_DeInit(en_I2C_unitId i2cId);
|
||||
void I2C_Cmd(en_I2C_unitId i2cId, en_I2C_Mode Mode, FunctionalState NewState);
|
||||
|
||||
/* I2C transfer data functions -------- */
|
||||
Status I2C_MasterTransferData(en_I2C_unitId i2cId,
|
||||
I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
Status I2C_SlaveTransferData(en_I2C_unitId i2cId,
|
||||
I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
|
||||
uint32_t I2C_MasterTransferComplete(en_I2C_unitId i2cId);
|
||||
uint32_t I2C_SlaveTransferComplete(en_I2C_unitId i2cId);
|
||||
|
||||
|
||||
void I2C_SetOwnSlaveAddr(en_I2C_unitId i2cId, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
|
||||
uint8_t I2C_GetLastStatusCode(en_I2C_unitId i2cId);
|
||||
|
||||
/* I2C Monitor functions ---------------*/
|
||||
void I2C_MonitorModeConfig(en_I2C_unitId i2cId, uint32_t MonitorCfgType, FunctionalState NewState);
|
||||
void I2C_MonitorModeCmd(en_I2C_unitId i2cId, FunctionalState NewState);
|
||||
uint8_t I2C_MonitorGetDatabuffer(en_I2C_unitId i2cId);
|
||||
BOOL_8 I2C_MonitorHandler(en_I2C_unitId i2cId, uint8_t *buffer, uint32_t size);
|
||||
|
||||
/* I2C Interrupt handler functions ------*/
|
||||
void I2C_IntCmd (en_I2C_unitId i2cId, Bool NewState);
|
||||
void I2C_MasterHandler (en_I2C_unitId i2cId);
|
||||
void I2C_SlaveHandler (en_I2C_unitId i2cId);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_I2C_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,351 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_i2s.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_i2s.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for I2S firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup I2S I2S (Inter-IC Sound bus)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_I2S_H_
|
||||
#define __LPC_I2S_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup I2S_Public_Macros I2S Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* I2S configuration parameter defines
|
||||
**********************************************************************/
|
||||
/** I2S Wordwidth bit */
|
||||
#define I2S_WORDWIDTH_8 ((uint32_t)(0))
|
||||
#define I2S_WORDWIDTH_16 ((uint32_t)(1))
|
||||
#define I2S_WORDWIDTH_32 ((uint32_t)(3))
|
||||
/** I2S Channel bit */
|
||||
#define I2S_STEREO ((uint32_t)(0))
|
||||
#define I2S_MONO ((uint32_t)(1))
|
||||
/** I2S Master/Slave mode bit */
|
||||
#define I2S_MASTER_MODE ((uint8_t)(0))
|
||||
#define I2S_SLAVE_MODE ((uint8_t)(1))
|
||||
/** I2S Stop bit */
|
||||
#define I2S_STOP_ENABLE ((uint8_t)(1))
|
||||
#define I2S_STOP_DISABLE ((uint8_t)(0))
|
||||
/** I2S Reset bit */
|
||||
#define I2S_RESET_ENABLE ((uint8_t)(1))
|
||||
#define I2S_RESET_DISABLE ((uint8_t)(0))
|
||||
/** I2S Mute bit */
|
||||
#define I2S_MUTE_ENABLE ((uint8_t)(1))
|
||||
#define I2S_MUTE_DISABLE ((uint8_t)(0))
|
||||
/** I2S Transmit/Receive bit */
|
||||
#define I2S_TX_MODE ((uint8_t)(0))
|
||||
#define I2S_RX_MODE ((uint8_t)(1))
|
||||
/** I2S Clock Select bit */
|
||||
#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
|
||||
#define I2S_CLKSEL_MCLK ((uint8_t)(2))
|
||||
/** I2S 4-pin Mode bit */
|
||||
#define I2S_4PIN_ENABLE ((uint8_t)(1))
|
||||
#define I2S_4PIN_DISABLE ((uint8_t)(0))
|
||||
/** I2S MCLK Enable bit */
|
||||
#define I2S_MCLK_ENABLE ((uint8_t)(1))
|
||||
#define I2S_MCLK_DISABLE ((uint8_t)(0))
|
||||
/** I2S select DMA bit */
|
||||
#define I2S_DMA_1 ((uint8_t)(0))
|
||||
#define I2S_DMA_2 ((uint8_t)(1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup I2S_Private_Macros I2S Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DAO-Digital Audio Output register
|
||||
**********************************************************************/
|
||||
/** I2S wordwide - the number of bytes in data output - 8 bits*/
|
||||
#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0))
|
||||
/** I2S wordwide - the number of bytes in data output - 16 bits*/
|
||||
#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1))
|
||||
/** I2S wordwide - the number of bytes in data output - 32 bits*/
|
||||
#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3))
|
||||
/** I2S control mono or stereo format */
|
||||
#define I2S_DAO_MONO ((uint32_t)(1<<2))
|
||||
/** I2S control stop mode */
|
||||
#define I2S_DAO_STOP ((uint32_t)(1<<3))
|
||||
/** I2S control reset mode */
|
||||
#define I2S_DAO_RESET ((uint32_t)(1<<4))
|
||||
/** I2S control master/slave mode */
|
||||
#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
|
||||
/** I2S word select half period minus one */
|
||||
#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
|
||||
/** I2S control mute mode */
|
||||
#define I2S_DAO_MUTE ((uint32_t)(1<<15))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DAI-Digital Audio Input register
|
||||
**********************************************************************/
|
||||
/** I2S wordwide - the number of bytes in data input - 8 bit*/
|
||||
#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0))
|
||||
/** I2S wordwide - the number of bytes in data input - 16 bit*/
|
||||
#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1))
|
||||
/** I2S wordwide - the number of bytes in data input - 32 bit*/
|
||||
#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3))
|
||||
/** I2S control mono or stereo format */
|
||||
#define I2S_DAI_MONO ((uint32_t)(1<<2))
|
||||
/** I2S control stop mode */
|
||||
#define I2S_DAI_STOP ((uint32_t)(1<<3))
|
||||
/** I2S control reset mode */
|
||||
#define I2S_DAI_RESET ((uint32_t)(1<<4))
|
||||
/** I2S control master/slave mode */
|
||||
#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
|
||||
/** I2S word select half period minus one (9 bits)*/
|
||||
#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
|
||||
/** I2S control mute mode */
|
||||
#define I2S_DAI_MUTE ((uint32_t)(1<<15))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for STAT register (Status Feedback register)
|
||||
**********************************************************************/
|
||||
/** I2S Status Receive or Transmit Interrupt */
|
||||
#define I2S_STATE_IRQ ((uint32_t)(1))
|
||||
/** I2S Status Receive or Transmit DMA1 */
|
||||
#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
|
||||
/** I2S Status Receive or Transmit DMA2 */
|
||||
#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
|
||||
/** I2S Status Current level of the Receive FIFO (5 bits)*/
|
||||
#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
|
||||
/** I2S Status Current level of the Transmit FIFO (5 bits)*/
|
||||
#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA1 register (DMA1 Configuration register)
|
||||
**********************************************************************/
|
||||
/** I2S control DMA1 for I2S receive */
|
||||
#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
|
||||
/** I2S control DMA1 for I2S transmit */
|
||||
#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
|
||||
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
|
||||
#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
|
||||
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
|
||||
#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMA2 register (DMA2 Configuration register)
|
||||
**********************************************************************/
|
||||
/** I2S control DMA2 for I2S receive */
|
||||
#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
|
||||
/** I2S control DMA1 for I2S transmit */
|
||||
#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
|
||||
/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
|
||||
#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
|
||||
/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
|
||||
#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for IRQ register (Interrupt Request Control register)
|
||||
**********************************************************************/
|
||||
/** I2S control I2S receive interrupt */
|
||||
#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
|
||||
/** I2S control I2S transmit interrupt */
|
||||
#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
|
||||
/** I2S set the FIFO level on which to create an irq request */
|
||||
#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
|
||||
/** I2S set the FIFO level on which to create an irq request */
|
||||
#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
|
||||
|
||||
/********************************************************************************//**
|
||||
* Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
|
||||
*********************************************************************************/
|
||||
/** I2S Transmit MCLK rate denominator */
|
||||
#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
|
||||
/** I2S Transmit MCLK rate denominator */
|
||||
#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
|
||||
/** I2S Receive MCLK rate denominator */
|
||||
#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
|
||||
/** I2S Receive MCLK rate denominator */
|
||||
#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
|
||||
|
||||
/*************************************************************************************//**
|
||||
* Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
|
||||
**************************************************************************************/
|
||||
#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
|
||||
#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
|
||||
|
||||
/**********************************************************************************//**
|
||||
* Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
|
||||
************************************************************************************/
|
||||
/** I2S Transmit select clock source (2 bits)*/
|
||||
#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
|
||||
/** I2S Transmit control 4-pin mode */
|
||||
#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
|
||||
/** I2S Transmit control the TX_MCLK output */
|
||||
#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
|
||||
/** I2S Receive select clock source */
|
||||
#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
|
||||
/** I2S Receive control 4-pin mode */
|
||||
#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
|
||||
/** I2S Receive control the TX_MCLK output */
|
||||
#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup I2S_Public_Types I2S Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2S configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t wordwidth; /** the number of bytes in data as follow:
|
||||
-I2S_WORDWIDTH_8: 8 bit data
|
||||
-I2S_WORDWIDTH_16: 16 bit data
|
||||
-I2S_WORDWIDTH_32: 32 bit data */
|
||||
uint8_t mono; /** Set mono/stereo mode, should be:
|
||||
- I2S_STEREO: stereo mode
|
||||
- I2S_MONO: mono mode */
|
||||
uint8_t stop; /** Disables accesses on FIFOs, should be:
|
||||
- I2S_STOP_ENABLE: enable stop mode
|
||||
- I2S_STOP_DISABLE: disable stop mode */
|
||||
uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
|
||||
- I2S_RESET_ENABLE: enable reset mode
|
||||
- I2S_RESET_DISABLE: disable reset mode */
|
||||
uint8_t ws_sel; /** Set Master/Slave mode, should be:
|
||||
- I2S_MASTER_MODE: I2S master mode
|
||||
- I2S_SLAVE_MODE: I2S slave mode */
|
||||
uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
|
||||
- I2S_MUTE_ENABLE: enable mute mode
|
||||
- I2S_MUTE_DISABLE: disable mute mode */
|
||||
uint8_t Reserved0[2];
|
||||
} I2S_CFG_Type;
|
||||
|
||||
/**
|
||||
* @brief I2S DMA configuration structure definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
|
||||
- I2S_DMA_1: DMA1
|
||||
- I2S_DMA_2: DMA2 */
|
||||
uint8_t depth; /** FIFO level that triggers a DMA request */
|
||||
uint8_t Reserved0[2];
|
||||
}I2S_DMAConf_Type;
|
||||
|
||||
/**
|
||||
* @brief I2S mode configuration structure definition
|
||||
*/
|
||||
typedef struct{
|
||||
uint8_t clksel; /** Clock source selection, should be:
|
||||
- I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
|
||||
- I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
|
||||
uint8_t fpin; /** Select four pin mode, should be:
|
||||
- I2S_4PIN_ENABLE: 4-pin enable
|
||||
- I2S_4PIN_DISABLE: 4-pin disable */
|
||||
uint8_t mcena; /** Select MCLK mode, should be:
|
||||
- I2S_MCLK_ENABLE: MCLK enable for output
|
||||
- I2S_MCLK_DISABLE: MCLK disable for output */
|
||||
uint8_t Reserved;
|
||||
}I2S_MODEConf_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup I2S_Public_Functions I2S Public Functions
|
||||
* @{
|
||||
*/
|
||||
/* I2S Init/DeInit functions ---------*/
|
||||
void I2S_Init(LPC_I2S_TypeDef *I2Sx);
|
||||
void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
|
||||
|
||||
/* I2S configuration functions --------*/
|
||||
void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
|
||||
Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
|
||||
void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
|
||||
void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
|
||||
uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||||
|
||||
/* I2S operate functions -------------*/
|
||||
void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
|
||||
uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
|
||||
void I2S_Start(LPC_I2S_TypeDef *I2Sx);
|
||||
void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||||
void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||||
void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
|
||||
|
||||
/* I2S DMA functions ----------------*/
|
||||
void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
|
||||
void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
|
||||
|
||||
/* I2S IRQ functions ----------------*/
|
||||
void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
|
||||
void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
|
||||
FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
|
||||
uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __LPC_SSP_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,153 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_iap.h 2011-11-21
|
||||
*//**
|
||||
* @file lpc_iap.h
|
||||
* @brief Contains all functions support for IAP
|
||||
* on LPC
|
||||
* @version 1.0
|
||||
* @date 21. November. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _LPC_IAP_H
|
||||
#define _LPC_IAP_H
|
||||
#include "lpc_types.h"
|
||||
|
||||
/** @defgroup IAP IAP (In Application Programming)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IAP_Public_Macros IAP Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** IAP entry location */
|
||||
#define IAP_LOCATION (0x1FFF1FF1UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IAP_Public_Types IAP Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IAP command code definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IAP_PREPARE = 50, // Prepare sector(s) for write operation
|
||||
IAP_COPY_RAM2FLASH = 51, // Copy RAM to Flash
|
||||
IAP_ERASE = 52, // Erase sector(s)
|
||||
IAP_BLANK_CHECK = 53, // Blank check sector(s)
|
||||
IAP_READ_PART_ID = 54, // Read chip part ID
|
||||
IAP_READ_BOOT_VER = 55, // Read chip boot code version
|
||||
IAP_COMPARE = 56, // Compare memory areas
|
||||
IAP_REINVOKE_ISP = 57, // Reinvoke ISP
|
||||
IAP_READ_SERIAL_NUMBER = 58, // Read serial number
|
||||
} IAP_COMMAND_CODE;
|
||||
|
||||
/**
|
||||
* @brief IAP status code definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CMD_SUCCESS, // Command is executed successfully.
|
||||
INVALID_COMMAND, // Invalid command.
|
||||
SRC_ADDR_ERROR, // Source address is not on a word boundary.
|
||||
DST_ADDR_ERROR, // Destination address is not on a correct boundary.
|
||||
SRC_ADDR_NOT_MAPPED, // Source address is not mapped in the memory map.
|
||||
DST_ADDR_NOT_MAPPED, // Destination address is not mapped in the memory map.
|
||||
COUNT_ERROR, // Byte count is not multiple of 4 or is not a permitted value.
|
||||
INVALID_SECTOR, // Sector number is invalid.
|
||||
SECTOR_NOT_BLANK, // Sector is not blank.
|
||||
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, // Command to prepare sector for write operation was not executed.
|
||||
COMPARE_ERROR, // Source and destination data is not same.
|
||||
BUSY, // Flash programming hardware interface is busy.
|
||||
} IAP_STATUS_CODE;
|
||||
|
||||
/**
|
||||
* @brief IAP write length definitions
|
||||
*/
|
||||
typedef enum {
|
||||
IAP_WRITE_256 = 256,
|
||||
IAP_WRITE_512 = 512,
|
||||
IAP_WRITE_1024 = 1024,
|
||||
IAP_WRITE_4096 = 4096,
|
||||
} IAP_WRITE_SIZE;
|
||||
|
||||
/**
|
||||
* @brief IAP command structure
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t cmd; // Command
|
||||
uint32_t param[4]; // Parameters
|
||||
uint32_t status; // status code
|
||||
uint32_t result[4]; // Result
|
||||
} IAP_COMMAND_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup IAP_Public_Functions IAP Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Get sector number of an address */
|
||||
uint32_t GetSecNum (uint32_t adr);
|
||||
/** Prepare sector(s) for write operation */
|
||||
IAP_STATUS_CODE PrepareSector(uint32_t start_sec, uint32_t end_sec);
|
||||
/** Copy RAM to Flash */
|
||||
IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE size);
|
||||
/** Prepare sector(s) for write operation */
|
||||
IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec);
|
||||
/** Blank check sectors */
|
||||
IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec,
|
||||
uint32_t *first_nblank_loc,
|
||||
uint32_t *first_nblank_val);
|
||||
/** Read part identification number */
|
||||
IAP_STATUS_CODE ReadPartID(uint32_t *partID);
|
||||
/** Read boot code version */
|
||||
IAP_STATUS_CODE ReadBootCodeVer(uint8_t *major, uint8_t* minor);
|
||||
/** Read Device serial number */
|
||||
IAP_STATUS_CODE ReadDeviceSerialNum(uint32_t *uid);
|
||||
/** Compare memory */
|
||||
IAP_STATUS_CODE Compare(uint8_t *addr1, uint8_t *addr2, uint32_t size);
|
||||
/** Invoke ISP */
|
||||
void InvokeISP(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /*_LPC_IAP_H*/
|
||||
|
||||
@@ -0,0 +1,232 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_lcd.h 2011-10-14
|
||||
*//**
|
||||
* @file lpc_lcd.h
|
||||
* @brief Contains all functions support for LCD firmware library
|
||||
* on LPC
|
||||
* @version 1.0
|
||||
* @date 14. October. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifndef __LPC_LCD_H_
|
||||
#define __LPC_LCD_H_
|
||||
|
||||
/** @defgroup LCD LCD (Liquid Crystal Display)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Public_Macros LCD Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_PWR_ENA_DIS_DLY 10000
|
||||
#define LCD_FUNC_OK 0
|
||||
#define LCD_FUNC_ERR -1
|
||||
|
||||
#define GET_CURSOR_IMG_SIZE(size) ((size == 32) ? 64:256)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Public_Types LCD Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum __LCD_TYPES
|
||||
{
|
||||
LCD_STN_MONOCHROME,
|
||||
LCD_STN_COLOR,
|
||||
LCD_TFT,
|
||||
LCD_TYPE_UNKNOWN,
|
||||
} LCD_TYPES;
|
||||
|
||||
typedef enum __LCD_BPP
|
||||
{
|
||||
LCD_BPP_1 = 0x00,
|
||||
LCD_BPP_2 = 0x01,
|
||||
LCD_BPP_4 = 0x02,
|
||||
LCD_BPP_8 = 0x03,
|
||||
LCD_BPP_16 = 0x04,
|
||||
LCD_BPP_24 = 0x05,
|
||||
LCD_BPP_16_565Mode = 0x06,
|
||||
LCD_BPP_12_444Mode = 0x07,
|
||||
} LCD_BPP;
|
||||
|
||||
typedef enum __LCD_PANEL
|
||||
{
|
||||
LCD_PANEL_UPPER,
|
||||
LCD_PANEL_LOWER,
|
||||
}LCD_PANEL;
|
||||
|
||||
/**
|
||||
* @brief A struct for Bitmap on LCD screen
|
||||
*/
|
||||
typedef struct _Bmp_t
|
||||
{
|
||||
uint32_t H_Size;
|
||||
uint32_t V_Size;
|
||||
uint32_t BitsPP;
|
||||
uint32_t BytesPP;
|
||||
uint8_t *pPalette;
|
||||
uint8_t *pPicStream;
|
||||
uint8_t *pPicDesc;
|
||||
} Bmp_t, *pBmp_t;
|
||||
|
||||
/**
|
||||
* @brief A struct for Font Type on LCD screen
|
||||
*/
|
||||
|
||||
typedef struct _FontType_t
|
||||
{
|
||||
uint32_t H_Size;
|
||||
uint32_t V_Size;
|
||||
uint32_t CharacterOffset;
|
||||
uint32_t CharactersNuber;
|
||||
uint8_t *pFontStream;
|
||||
uint8_t *pFontDesc;
|
||||
} FontType_t, *pFontType_t;
|
||||
|
||||
/**
|
||||
* @brief A struct for LCD Palette
|
||||
*/
|
||||
|
||||
typedef struct __LCD_PALETTE_Type
|
||||
{
|
||||
uint8_t Red;
|
||||
uint8_t Green;
|
||||
uint8_t Blue;
|
||||
}LCD_PALETTE_Type, *pLCD_PALETTE_Type;
|
||||
|
||||
/**
|
||||
* @brief A struct for Horizontal configuration
|
||||
*/
|
||||
|
||||
typedef struct __LCD_HConfig_Type
|
||||
{
|
||||
uint8_t hfp; // Horizontal front porch
|
||||
uint8_t hbp; // Horizontal back porch
|
||||
uint8_t hsw; // Horizontal synchronization pulse width
|
||||
uint16_t ppl; // Number of pixels per line
|
||||
}LCD_HConfig_Type;
|
||||
|
||||
/**
|
||||
* @brief A struct for Vertical configuration
|
||||
*/
|
||||
|
||||
typedef struct __LCD_VConfig_Type
|
||||
{
|
||||
uint8_t vfp; // Vertical front and back porch
|
||||
uint8_t vbp; // Vertical back porch
|
||||
uint8_t vsw; // Vertical synchronization pulse width
|
||||
uint16_t lpp; // Number of lines per panel
|
||||
}LCD_VConfig_Type;
|
||||
|
||||
/**
|
||||
* @brief A struct for Polarity configuration
|
||||
*/
|
||||
|
||||
typedef struct __LCD_POLARITY_Type
|
||||
{
|
||||
uint16_t cpl; // Number of pixel clocks per line
|
||||
uint8_t active_high; // Signal polarity, active HIGH or LOW
|
||||
uint8_t acb; // AC bias pin frequency
|
||||
uint8_t invert_panel_clock; // Invert Panel clock;
|
||||
uint8_t invert_hsync; // Invert HSYNC
|
||||
uint8_t invert_vsync; // Invert VSYSNC
|
||||
}LCD_POLARITY_Type;
|
||||
|
||||
/**
|
||||
* @brief A struct for LCD Configuration
|
||||
*/
|
||||
|
||||
typedef struct __LCD_Config_Type
|
||||
{
|
||||
LCD_HConfig_Type hConfig; // Horizontal config
|
||||
LCD_VConfig_Type vConfig; // Vertical config
|
||||
LCD_POLARITY_Type polarity; // Polarity config
|
||||
uint32_t panel_clk; // Panel clock frequency
|
||||
LCD_BPP lcd_bpp; // Bits-per-pixel
|
||||
LCD_TYPES lcd_type; // Display type: STN monochrome, STN color, or TFT
|
||||
uint8_t lcd_mono8; // STN 4 or 8-bit interface mode
|
||||
uint8_t lcd_dual; // STN dual or single panel mode
|
||||
uint8_t big_endian_byte; // byte ordering in memory
|
||||
uint8_t big_endian_pixel; // pixel ordering within a byte
|
||||
uint32_t lcd_panel_upper; // base address of frame buffer
|
||||
uint32_t lcd_panel_lower; // base address of frame buffer
|
||||
uint8_t* lcd_palette; // point to palette buffer
|
||||
Bool lcd_bgr; // False: RGB , TRUE: BGR
|
||||
} LCD_Config_Type;
|
||||
|
||||
/**
|
||||
* @brief A struct for Cursor configuration
|
||||
*/
|
||||
|
||||
typedef struct __LCD_Cursor_Config_Type
|
||||
{
|
||||
uint8_t size32; // 32x32 or 64x64
|
||||
uint8_t framesync;
|
||||
LCD_PALETTE_Type palette[2];
|
||||
uint32_t baseaddress;
|
||||
} LCD_Cursor_Config_Type;
|
||||
|
||||
typedef uint32_t LcdPixel_t, *pLcdPixel_t;
|
||||
typedef int32_t LCD_RET_CODE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_Public_Functions LCD Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
LCD_RET_CODE LCD_Init (LCD_Config_Type* pConfig);
|
||||
void LCD_SetBaseAddress(LCD_PANEL panel, uint32_t pAddress);
|
||||
void LCD_SetPalette (const uint8_t* pPallete);
|
||||
void LCD_Enable (Bool bEna);
|
||||
void LCD_Cursor_Cfg(LCD_Cursor_Config_Type* pConfig);
|
||||
void LCD_Cursor_Enable(int enable, int cursor);
|
||||
void LCD_Move_Cursor(int x, int y);
|
||||
void LCD_Cursor_SetImage (const uint32_t *pCursor, int cursor, int size);
|
||||
void LCD_SetImage(LCD_PANEL panel,const uint8_t *pPain);
|
||||
void LCD_FillRect (LCD_PANEL panel, uint32_t startx,uint32_t endx,
|
||||
uint32_t starty, uint32_t endy,
|
||||
LcdPixel_t color);
|
||||
void LCD_PutPixel (LCD_PANEL panel, uint32_t X_Left, uint32_t Y_Up, LcdPixel_t color);
|
||||
void LCD_LoadPic (LCD_PANEL panel,uint32_t X_Left, uint32_t Y_Up, Bmp_t * pBmp, uint32_t Mask);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif // __LPC_LCD_H_
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,158 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_libcfg.h 2010-05-21
|
||||
***
|
||||
* @file lpc_libcfg.h
|
||||
* @brief Library configuration file
|
||||
* @version 3.0
|
||||
* @date 20. June. 2010
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2010, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef _LPC_LIBCFG_DEFAULT_H_
|
||||
#define _LPC_LIBCFG_DEFAULT_H_
|
||||
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
/************************** DEBUG MODE DEFINITIONS *********************************/
|
||||
/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
|
||||
the "CHECK_PARAM" macro in the FW library code */
|
||||
|
||||
#ifndef __CODE_RED
|
||||
#define DEBUG
|
||||
#endif
|
||||
|
||||
|
||||
/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
|
||||
|
||||
/* Comment the line below to disable the specific peripheral inclusion */
|
||||
|
||||
/* DEBUG_FRAMWORK -------------------- */
|
||||
#define _DBGFWK
|
||||
|
||||
/* Clock & Power -------------------- */
|
||||
#define _CLKPWR
|
||||
|
||||
/* CRC -------------------- */
|
||||
#define _CRC
|
||||
|
||||
/* GPIO ------------------------------- */
|
||||
#define _GPIO
|
||||
|
||||
/* NVIC ------------------------------- */
|
||||
#define _NVIC
|
||||
|
||||
/* PINSEL ------------------------------- */
|
||||
#define _PINSEL
|
||||
|
||||
/* EXTI ------------------------------- */
|
||||
#define _EXTI
|
||||
|
||||
/* EMC ------------------------------- */
|
||||
#define _EMC
|
||||
|
||||
/* UART ------------------------------- */
|
||||
#define _UART
|
||||
|
||||
/* SPI ------------------------------- */
|
||||
#define _SPI
|
||||
|
||||
/* SYSTICK --------------------------- */
|
||||
#define _SYSTICK
|
||||
|
||||
/* SSP ------------------------------- */
|
||||
#define _SSP
|
||||
|
||||
|
||||
/* I2C ------------------------------- */
|
||||
#define _I2C
|
||||
|
||||
/* TIMER ------------------------------- */
|
||||
#define _TIM
|
||||
|
||||
/* WDT ------------------------------- */
|
||||
#define _WDT
|
||||
|
||||
|
||||
/* GPDMA ------------------------------- */
|
||||
#define _GPDMA
|
||||
|
||||
|
||||
/* DAC ------------------------------- */
|
||||
#define _DAC
|
||||
|
||||
/* ADC ------------------------------- */
|
||||
#define _ADC
|
||||
|
||||
/* EEPROM ------------------------------- */
|
||||
#define _EEPROM
|
||||
|
||||
/* PWM ------------------------------- */
|
||||
#define _PWM
|
||||
|
||||
/* RTC ------------------------------- */
|
||||
#define _RTC
|
||||
|
||||
/* I2S ------------------------------- */
|
||||
#define _I2S
|
||||
|
||||
/* USB device ------------------------------- */
|
||||
#define _USBDEV
|
||||
#ifdef _USBDEV
|
||||
#define _USB_DEV_AUDIO
|
||||
#define _USB_DEV_MASS_STORAGE
|
||||
#define _USB_DEV_HID
|
||||
#define _USB_DEV_VIRTUAL_COM
|
||||
#endif /*_USBDEV*/
|
||||
|
||||
/* USB Host ------------------------------- */
|
||||
#define _USBHost
|
||||
|
||||
/* QEI ------------------------------- */
|
||||
#define _QEI
|
||||
|
||||
/* MCPWM ------------------------------- */
|
||||
#define _MCPWM
|
||||
|
||||
/* CAN--------------------------------*/
|
||||
#define _CAN
|
||||
|
||||
/* EMAC ------------------------------ */
|
||||
#define _EMAC
|
||||
|
||||
/* LCD ------------------------------ */
|
||||
#define _LCD
|
||||
|
||||
/* MCI ------------------------------ */
|
||||
#define _MCI
|
||||
|
||||
/* IAP------------------------------ */
|
||||
#define _IAP
|
||||
|
||||
/* BOD------------------------------ */
|
||||
#define _BOD
|
||||
/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
|
||||
|
||||
|
||||
#endif /* _LPC_LIBCFG_DEFAULT_H_ */
|
||||
@@ -0,0 +1,463 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_mci.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_mci.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for MCI firmware library on LPC
|
||||
* @version 2.0
|
||||
* @date 29. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup MCI MCI (Multimedia Card Interface)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_MCI_H_
|
||||
#define __LPC_MCI_H_
|
||||
|
||||
/** @defgroup MCI_Public_Macros MCI Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define MCI_DMA_ENABLED (1)
|
||||
|
||||
#define HIGH_LVL (1)
|
||||
#define LOW_LVL (0)
|
||||
|
||||
/* SD/MMC Command list, per MMC spec. SD Memory Card Spec. Simplified version */
|
||||
/* GO_IDLE_STATE(MMC) or RESET(SD) */
|
||||
#define CMD0_GO_IDLE_STATE (0)
|
||||
/* SEND_OP_COND(MMC) or ACMD41(SD) */
|
||||
#define CMD1_SEND_OP_COND (1)
|
||||
/* ALL_SEND_CID */
|
||||
#define CMD2_ALL_SEND_CID (2)
|
||||
/* SET_RELATE_ADDR */
|
||||
#define CMD3_SET_RELATIVE_ADDR (3)
|
||||
/* Set Bus-Width 1 bit or 4 bits */
|
||||
#define ACMD6_SET_BUS_WIDTH (6)
|
||||
/* SELECT/DESELECT_CARD */
|
||||
#define CMD7_SELECT_CARD (7)
|
||||
/**Sending interface condition cmd */
|
||||
#define CMD8_SEND_IF_COND (8)
|
||||
/* SEND_CSD */
|
||||
#define CMD9_SEND_CSD (9)
|
||||
/* Stop either READ or WRITE operation */
|
||||
#define CMD12_STOP_TRANSMISSION 12
|
||||
/* SEND_STATUS */
|
||||
#define CMD13_SEND_STATUS (13)
|
||||
/* SET_BLOCK_LEN */
|
||||
#define CMD16_SET_BLOCK_LEN (16)
|
||||
/* READ_SINGLE_BLOCK */
|
||||
#define CMD17_READ_SINGLE_BLOCK (17)
|
||||
/* READ_MULTIPLE_BLOCK */
|
||||
#define CMD18_READ_MULTIPLE_BLOCK (18)
|
||||
/* WRITE_BLOCK */
|
||||
#define CMD24_WRITE_BLOCK (24)
|
||||
/* WRITE_MULTIPLE_BLOCK */
|
||||
#define CMD25_WRITE_MULTIPLE_BLOCK (25)
|
||||
/* Start erase block number*/
|
||||
#define CMD32_ERASE_WR_BLK_START (32)
|
||||
/* End erase block number*/
|
||||
#define CMD33_ERASE_WR_BLK_END (33)
|
||||
/* Start erase*/
|
||||
#define CMD38_ERASE (38)
|
||||
|
||||
/* ACMD41 for SD card */
|
||||
#define ACMD41_SEND_APP_OP_COND (41)
|
||||
|
||||
/* APP_CMD, the following will a ACMD */
|
||||
#define CMD55_APP_CMD (55)
|
||||
|
||||
#define OCR_INDEX (0x00FF8000)
|
||||
#define RCA_ARGUMENT_POS (16)
|
||||
#define RCA_ARGUMENT_MASK (0xFFFF)
|
||||
|
||||
|
||||
/* Card Status (coded in 32 bits) in R1 & R1b Response */
|
||||
#define CARD_STATUS_OUT_OF_RANGE ( 1 << 31)
|
||||
#define CARD_STATUS_ADDRESS_ERROR ( 1 << 30)
|
||||
#define CARD_STATUS_BLOCK_LEN_ERROR ( 1 << 29)
|
||||
#define CARD_STATUS_ERASE_SEQ_ERROR ( 1 << 28)
|
||||
#define CARD_STATUS_ERASE_PARAM_ERROR ( 1 << 27)
|
||||
#define CARD_STATUS_WP_VIOLATION ( 1 << 26)
|
||||
#define CARD_STATUS_CARD_IS_LOCKED ( 1 << 25)
|
||||
#define CARD_STATUS_COM_CRC_ERROR ( 1 << 23)
|
||||
#define CARD_STATUS_ILLEGAL_COMMAND ( 1 << 22)
|
||||
#define CARD_STATUS_CARD_ECC_FAILED ( 1 << 21)
|
||||
#define CARD_STATUS_CC_ERROR ( 1 << 20)
|
||||
#define CARD_STATUS_GEN_ERROR ( 1 << 19)
|
||||
#define CARD_STATUS_CSD_OVERWRITE ( 1 << 16)
|
||||
#define CARD_STATUS_WP_ERASE_SKIP ( 1 << 15)
|
||||
#define CARD_STATUS_CARD_ECC_DISABLED ( 1 << 14)
|
||||
#define CARD_STATUS_ERASE_RESET ( 1 << 13)
|
||||
#define CARD_STATUS_READY_FOR_DATA ( 1 << 8)
|
||||
#define CARD_STATUS_ACMD_ENABLE ( 1 << 5)
|
||||
#define CARD_STATUS_ERR_MASK (0xFDF88008)
|
||||
#define CARDSTATEOF(x) ((x>>9) & 0x0F)
|
||||
#define CARD_STATE_IDLE (0)
|
||||
#define CARD_STATE_READY (1)
|
||||
#define CARD_STATE_IDENT (2)
|
||||
#define CARD_STATE_STBY (3)
|
||||
#define CARD_STATE_TRAN (4)
|
||||
#define CARD_STATE_DATA (5)
|
||||
#define CARD_STATE_RCV (6)
|
||||
#define CARD_STATE_PRG (7)
|
||||
#define CARD_STATE_DIS (8)
|
||||
|
||||
|
||||
/* CID in R2 reponse (Code length is 136 bits) */
|
||||
#define MCI_CID_MANUFACTURER_ID_WPOS (24) //pos in word 0
|
||||
#define MCI_CID_MANUFACTURER_ID_WBMASK (0xFF)
|
||||
|
||||
#define MCI_CID_OEMAPPLICATION_ID_WPOS (8) //pos in word 0
|
||||
#define MCI_CID_OEMAPPLICATION_ID_WBMASK (0xFFFF)
|
||||
|
||||
#define MCI_CID_PRODUCTNAME_ID_H_WPOS (0) //pos in word 0
|
||||
#define MCI_CID_PRODUCTNAME_ID_H_WBMASK (0xFF)
|
||||
|
||||
#define MCI_CID_PRODUCTNAME_ID_L_WPOS (0) //pos in word 1
|
||||
#define MCI_CID_PRODUCTNAME_ID_L_WBMASK (0xFFFFFFFF)
|
||||
|
||||
#define MCI_CID_PRODUCTREVISION_ID_WPOS (24) //pos in word 2
|
||||
#define MCI_CID_PRODUCTREVISION_ID_WBMASK (0xFF)
|
||||
|
||||
#define MCI_CID_PRODUCTSERIALNUM_ID_H_WPOS (0) //pos in word 2
|
||||
#define MCI_CID_PRODUCTSERIALNUM_ID_H_WBMASK (0x00FFFFFF)
|
||||
#define MCI_CID_PRODUCTSERIALNUM_ID_L_WPOS (24) //pos in word 3
|
||||
#define MCI_CID_PRODUCTSERIALNUM_ID_L_WBMASK (0xFF)
|
||||
#define MCI_CID_PRODUCTSERIALNUM_ID_WBMASK (0xFFFFFFFF)
|
||||
|
||||
#define MCI_CID_RESERVED_ID_WPOS (20) //pos in word 3
|
||||
#define MCI_CID_RESERVED_ID_WBMASK (0x1F)
|
||||
|
||||
#define MCI_CID_MANUFACTURINGDATE_ID_WPOS (8) //in word 3
|
||||
#define MCI_CID_MANUFACTURINGDATE_ID_WBMASK (0x0FFF)
|
||||
|
||||
#define MCI_CID_CHECKSUM_ID_WPOS (1) //in word 3
|
||||
#define MCI_CID_CHECKSUM_ID_WBMASK (0x7F)
|
||||
|
||||
#define MCI_CID_UNUSED_ID_WPOS (0) //in word 3
|
||||
#define MCI_CID_UNUSED_ID_WBMASK (0x01)
|
||||
|
||||
/* R6 (Published RCA response) */
|
||||
#define RCA_RES_CARD_STATUS_POS (0)
|
||||
#define RCA_RES_CARD_STATUS_MASK (0xFFFF)
|
||||
|
||||
#define RCA_RES_NEW_PUBLISHED_RCA_POS (16)
|
||||
#define RCA_RES_NEW_PUBLISHED_RCA_MASK (0xFFFF)
|
||||
|
||||
/* R7 (Card interface condition) */
|
||||
#define MCI_CMD8_VOLTAGESUPPLIED_POS (8)
|
||||
#define MCI_CMD8_VOLTAGESUPPLIED_BMASK (0x0F)
|
||||
#define MCI_CMD8_VOLATAGESUPPLIED_NOT_DEFINED (0)
|
||||
#define MCI_CMD8_VOLATAGESUPPLIED_27_36 (1) /*2.7 - 3.6V*/
|
||||
|
||||
#define MCI_CMD8_CHECKPATTERN_POS (0)
|
||||
#define MCI_CMD8_CHECKPATTERN_BMASK (0xFF)
|
||||
|
||||
|
||||
#define MCI_SLOW_RATE (400000) /* 400KHz */
|
||||
#define MCI_NORMAL_RATE (20000000) /* 20MHz */
|
||||
|
||||
#define SD_1_BIT (0)
|
||||
#define SD_4_BIT (1)
|
||||
|
||||
#define DATA_TIMER_VALUE_R (MCI_NORMAL_RATE/4) // 250ms
|
||||
#define DATA_TIMER_VALUE_W (MCI_NORMAL_RATE) // 1000ms
|
||||
|
||||
#define DATA_RW_MAX_LEN (0xFFFF)
|
||||
|
||||
#define EXPECT_NO_RESP (0)
|
||||
#define EXPECT_SHORT_RESP (1)
|
||||
#define EXPECT_LONG_RESP (2)
|
||||
|
||||
#define MCI_OUTPUT_MODE_PUSHPULL (0)
|
||||
#define MCI_OUTPUT_MODE_OPENDRAIN (1)
|
||||
|
||||
#define NOT_ALLOW_CMD_TIMER (0)
|
||||
#define ALLOW_CMD_TIMER (1)
|
||||
|
||||
#define MCI_DISABLE_CMD_TIMER (1<<8)
|
||||
|
||||
/* For the SD card I tested, the minimum block length is 512 */
|
||||
/* For MMC, the restriction is loose, due to the variety of SD and MMC
|
||||
card support, ideally, the driver should read CSD register to find the
|
||||
speed and block length for the card, and set them accordingly. */
|
||||
/* In this driver example, it will support both MMC and SD cards, it
|
||||
does read the information by send SEND_CSD to poll the card status,
|
||||
but, it doesn't configure them accordingly. this is not intended to
|
||||
support all the SD and MMC card. */
|
||||
|
||||
/* DATA_BLOCK_LEN table
|
||||
DATA_BLOCK_LEN Actual Size( BLOCK_LENGTH )
|
||||
11 2048
|
||||
10 1024
|
||||
9 512
|
||||
8 256
|
||||
7 128
|
||||
6 64
|
||||
5 32
|
||||
4 16
|
||||
3 8
|
||||
2 4
|
||||
1 2
|
||||
*/
|
||||
/* This is the size of the buffer of origin data */
|
||||
#define MCI_DMA_SIZE (1000UL)
|
||||
/* This is the area original data is stored or data to be written to the SD/MMC card. */
|
||||
#define MCI_DMA_SRC_ADDR LPC_PERI_RAM_BASE
|
||||
/* This is the area, after reading from the SD/MMC*/
|
||||
#define MCI_DMA_DST_ADDR (MCI_DMA_SRC_ADDR + MCI_DMA_SIZE)
|
||||
|
||||
|
||||
/* To simplify the programming, please note that, BLOCK_LENGTH is a multiple
|
||||
of FIFO_SIZE */
|
||||
#define DATA_BLOCK_LEN (9) /* Block size field in DATA_CTRL */
|
||||
#define BLOCK_LENGTH (1 << DATA_BLOCK_LEN)
|
||||
/* for SD card, 128, the size of the flash */
|
||||
/* card is 512 * 128 = 64K */
|
||||
#define BLOCK_NUM 0x80
|
||||
#define FIFO_SIZE 16
|
||||
|
||||
#define BUS_WIDTH_1BIT 0
|
||||
#define BUS_WIDTH_4BITS 10
|
||||
|
||||
/* MCI Status register bit information */
|
||||
#define MCI_CMD_CRC_FAIL (1 << 0)
|
||||
#define MCI_DATA_CRC_FAIL (1 << 1)
|
||||
#define MCI_CMD_TIMEOUT (1 << 2)
|
||||
#define MCI_DATA_TIMEOUT (1 << 3)
|
||||
#define MCI_TX_UNDERRUN (1 << 4)
|
||||
#define MCI_RX_OVERRUN (1 << 5)
|
||||
#define MCI_CMD_RESP_END (1 << 6)
|
||||
#define MCI_CMD_SENT (1 << 7)
|
||||
#define MCI_DATA_END (1 << 8)
|
||||
#define MCI_START_BIT_ERR (1 << 9)
|
||||
#define MCI_DATA_BLK_END (1 << 10)
|
||||
#define MCI_CMD_ACTIVE (1 << 11)
|
||||
#define MCI_TX_ACTIVE (1 << 12)
|
||||
#define MCI_RX_ACTIVE (1 << 13)
|
||||
#define MCI_TX_HALF_EMPTY (1 << 14)
|
||||
#define MCI_RX_HALF_FULL (1 << 15)
|
||||
#define MCI_TX_FIFO_FULL (1 << 16)
|
||||
#define MCI_RX_FIFO_FULL (1 << 17)
|
||||
#define MCI_TX_FIFO_EMPTY (1 << 18)
|
||||
#define MCI_RX_FIFO_EMPTY (1 << 19)
|
||||
#define MCI_TX_DATA_AVAIL (1 << 20)
|
||||
#define MCI_RX_DATA_AVAIL (1 << 21)
|
||||
|
||||
|
||||
/***********************************************************************
|
||||
* MCI Data control register definitions
|
||||
**********************************************************************/
|
||||
/** Data transfer enable */
|
||||
#define MCI_DATACTRL_ENABLE_POS (0)
|
||||
#define MCI_DATACTRL_ENABLE_MASK (0x01)
|
||||
#define MCI_DATACTRL_ENABLE (1 << MCI_DATACTRL_ENABLE_POS)
|
||||
#define MCI_DATACTRL_DISABLE (0 << MCI_DATACTRL_ENABLE_POS)
|
||||
|
||||
/** Data transfer direction */
|
||||
#define MCI_DATACTRL_DIR_POS (1)
|
||||
#define MCI_DATACTRL_DIR_MASK (0x01)
|
||||
#define MCI_DATACTRL_DIR_FROM_CARD (1 << MCI_DATACTRL_DIR_POS)
|
||||
#define MCI_DATACTRL_DIR_TO_CARD (0 << MCI_DATACTRL_DIR_POS)
|
||||
|
||||
|
||||
/** Data transfer mode */
|
||||
#define MCI_DATACTRL_XFER_MODE_POS (2)
|
||||
#define MCI_DATACTRL_XFER_MODE_MASK (0x01)
|
||||
#define MCI_DATACTRL_XFER_MODE_STREAM (1 << MCI_DATACTRL_XFER_MODE_POS)
|
||||
#define MCI_DATACTRL_XFER_MODE_BLOCK (0 << MCI_DATACTRL_XFER_MODE_POS)
|
||||
|
||||
/** Enable DMA */
|
||||
#define MCI_DATACTRL_DMA_ENABLE_POS (3)
|
||||
#define MCI_DATACTRL_DMA_ENABLE_MASK (0x01)
|
||||
#define MCI_DATACTRL_DMA_ENABLE (1 << MCI_DATACTRL_DMA_ENABLE_POS)
|
||||
#define MCI_DATACTRL_DMA_DISABLE (0 << MCI_DATACTRL_DMA_ENABLE_POS)
|
||||
|
||||
/** Data block length macro */
|
||||
#define MCI_DTATCTRL_BLOCKSIZE(n) _SBF(4, (n & 0xF))
|
||||
|
||||
|
||||
#define CMD_INT_MASK (MCI_CMD_CRC_FAIL | MCI_CMD_TIMEOUT | MCI_CMD_RESP_END \
|
||||
| MCI_CMD_SENT | MCI_CMD_ACTIVE)
|
||||
|
||||
#define DATA_ERR_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN \
|
||||
| MCI_RX_OVERRUN | MCI_START_BIT_ERR)
|
||||
|
||||
#define ACTIVE_INT_MASK ( MCI_TX_ACTIVE | MCI_RX_ACTIVE)
|
||||
|
||||
#define FIFO_INT_MASK (MCI_TX_HALF_EMPTY | MCI_RX_HALF_FULL \
|
||||
| MCI_TX_FIFO_FULL | MCI_RX_FIFO_FULL \
|
||||
| MCI_TX_FIFO_EMPTY | MCI_RX_FIFO_EMPTY \
|
||||
| MCI_DATA_BLK_END )
|
||||
|
||||
#define FIFO_TX_INT_MASK (MCI_TX_HALF_EMPTY )
|
||||
#define FIFO_RX_INT_MASK (MCI_RX_HALF_FULL )
|
||||
|
||||
#define DATA_END_INT_MASK (MCI_DATA_END | MCI_DATA_BLK_END)
|
||||
|
||||
#define ERR_TX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | MCI_START_BIT_ERR)
|
||||
#define ERR_RX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_START_BIT_ERR)
|
||||
|
||||
/* Error code on the command response. */
|
||||
#define INVALID_RESPONSE 0xFFFFFFFF
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MCI_Public_Types MCI Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum mci_card_state
|
||||
{
|
||||
MCI_CARDSTATE_IDLE = 0,
|
||||
MCI_CARDSTATE_READY,
|
||||
MCI_CARDSTATE_IDENDTIFIED,
|
||||
MCI_CARDSTATE_STBY,
|
||||
MCI_CARDSTATE_TRAN,
|
||||
MCI_CARDSTATE_DATA,
|
||||
MCI_CARDSTATE_RCV,
|
||||
MCI_CARDSTATE_PRG,
|
||||
MCI_CARDSTATE_DIS,
|
||||
}en_Mci_CardState;
|
||||
|
||||
|
||||
typedef enum mci_func_error
|
||||
{
|
||||
MCI_FUNC_OK = 0,
|
||||
MCI_FUNC_FAILED = -1,
|
||||
MCI_FUNC_BAD_PARAMETERS = -2,
|
||||
MCI_FUNC_BUS_NOT_IDLE = -3,
|
||||
MCI_FUNC_TIMEOUT = -3,
|
||||
MCI_FUNC_ERR_STATE = -4,
|
||||
MCI_FUNC_NOT_READY = -5,
|
||||
}en_Mci_Func_Error;
|
||||
|
||||
typedef enum mci_card_type
|
||||
{
|
||||
MCI_SDHC_SDXC_CARD = 3,
|
||||
MCI_SDSC_V2_CARD = 2,
|
||||
MCI_MMC_CARD = 1,
|
||||
MCI_SDSC_V1_CARD = 0,
|
||||
MCI_CARD_UNKNOWN = -1,
|
||||
}en_Mci_CardType;
|
||||
|
||||
typedef struct mci_cid
|
||||
{
|
||||
/** Manufacturer ID */
|
||||
uint8_t MID;
|
||||
/** OEM/Application ID */
|
||||
uint16_t OID;
|
||||
/** Product name 8-bits higher */
|
||||
uint8_t PNM_H;
|
||||
/** Product name 32-bits Lower */
|
||||
uint32_t PNM_L;
|
||||
/** Product revision */
|
||||
uint8_t PRV;
|
||||
/** Product serial number */
|
||||
uint32_t PSN;
|
||||
/** reserved: 4 bit */
|
||||
uint8_t reserved;
|
||||
/** Manufacturing date: 12 bit */
|
||||
uint16_t MDT;
|
||||
/** CRC7 checksum: 7 bit */
|
||||
uint8_t CRC;
|
||||
/** not used, always: 1 bit always 1 */
|
||||
uint8_t unused;
|
||||
} st_Mci_CardId;
|
||||
|
||||
typedef struct cmd_info{
|
||||
/** Command ID*/
|
||||
uint32_t CmdIndex;
|
||||
/** Command Argument*/
|
||||
uint32_t Argument;
|
||||
/** Expected response: no response, short response or long response */
|
||||
uint32_t ExpectResp;
|
||||
/** Allow timeout */
|
||||
uint32_t AllowTimeout;
|
||||
/** Command Response Info */
|
||||
uint32_t *CmdResp;
|
||||
} st_Mci_CmdInfo;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MCI_Public_Functions MCI Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
int32_t MCI_Init(uint8_t powerActiveLevel );
|
||||
void MCI_SendCmd( st_Mci_CmdInfo* pCmdIf );
|
||||
int32_t MCI_GetCmdResp( uint32_t CmdIndex, uint32_t NeedRespFlag, uint32_t *CmdRespStatus );
|
||||
int32_t MCI_CmdResp(st_Mci_CmdInfo *pCmdIf);
|
||||
|
||||
void MCI_Set_MCIClock( uint32_t clockrate );
|
||||
int32_t MCI_SetBusWidth( uint32_t width );
|
||||
int32_t MCI_Acmd_SendOpCond(uint8_t hcsVal);
|
||||
int32_t MCI_CardInit( void );
|
||||
en_Mci_CardType MCI_GetCardType(void);
|
||||
int32_t MCI_CardReset( void );
|
||||
int32_t MCI_Cmd_SendIfCond(void);
|
||||
int32_t MCI_GetCID(st_Mci_CardId* cidValue);
|
||||
int32_t MCI_SetCardAddress( void );
|
||||
uint32_t MCI_GetCardAddress(void);
|
||||
int32_t MCI_GetCSD(uint32_t* csdVal);
|
||||
int32_t MCI_Cmd_SelectCard( void );
|
||||
int32_t MCI_GetCardStatus(int32_t* cardStatus);
|
||||
uint32_t MCI_GetDataXferEndState(void);
|
||||
uint32_t MCI_GetXferErrState(void);
|
||||
int32_t MCI_SetBlockLen( uint32_t blockLength );
|
||||
int32_t MCI_Acmd_SendBusWidth( uint32_t buswidth );
|
||||
int32_t MCI_Cmd_StopTransmission( void );
|
||||
|
||||
int32_t MCI_Cmd_WriteBlock(uint32_t blockNum, uint32_t numOfBlock);
|
||||
int32_t MCI_Cmd_ReadBlock(uint32_t blockNum, uint32_t numOfBlock);
|
||||
|
||||
int32_t MCI_WriteBlock(volatile uint8_t* memblock, uint32_t blockNum, uint32_t numOfBlock);
|
||||
int32_t MCI_ReadBlock(volatile uint8_t* destBlock, uint32_t blockNum, uint32_t numOfBlock);
|
||||
#if MCI_DMA_ENABLED
|
||||
void MCI_DMA_IRQHandler (void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* end __LPC_MCI_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
** End Of File
|
||||
****************************************************************************/
|
||||
@@ -0,0 +1,348 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_mcpwm.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_mcpwm.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Motor Control PWM firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup MCPWM MCPWM (Motor Control PWM)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_MCPWM_H_
|
||||
#define __LPC_MCPWM_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup MCPWM_Public_Macros MCPWM Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** Edge aligned mode for channel in MCPWM */
|
||||
#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
|
||||
|
||||
/** Center aligned mode for channel in MCPWM */
|
||||
#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
|
||||
|
||||
/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
|
||||
#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
|
||||
/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
|
||||
#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
|
||||
|
||||
/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
|
||||
* the six output pins under the control of the bits in this register */
|
||||
#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
|
||||
#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
|
||||
#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
|
||||
#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
|
||||
#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
|
||||
#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
|
||||
|
||||
/* Interrupt type in MCPWM */
|
||||
/** Limit interrupt for channel (0) */
|
||||
#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
|
||||
/** Match interrupt for channel (0) */
|
||||
#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
|
||||
/** Capture interrupt for channel (0) */
|
||||
#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
|
||||
|
||||
/** Limit interrupt for channel (1) */
|
||||
#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
|
||||
/** Match interrupt for channel (1) */
|
||||
#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
|
||||
/** Capture interrupt for channel (1) */
|
||||
#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
|
||||
|
||||
/** Limit interrupt for channel (2) */
|
||||
#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
|
||||
/** Match interrupt for channel (2) */
|
||||
#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
|
||||
/** Capture interrupt for channel (2) */
|
||||
#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
|
||||
|
||||
/** Fast abort interrupt */
|
||||
#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MCPWM Control register
|
||||
**********************************************************************/
|
||||
/* MCPWM Control register, these macro definitions below can be applied for these
|
||||
* register type:
|
||||
* - MCPWM Control read address
|
||||
* - MCPWM Control set address
|
||||
* - MCPWM Control clear address
|
||||
*/
|
||||
/** Stops/starts timer channel n */
|
||||
#define MCPWM_CON_RUN(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+0))) : (0))
|
||||
/** Edge/center aligned operation for channel n */
|
||||
#define MCPWM_CON_CENTER(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+1))) : (0))
|
||||
/** Select polarity of the MCOAn and MCOBn pin */
|
||||
#define MCPWM_CON_POLAR(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+2))) : (0))
|
||||
/** Control the dead-time feature for channel n */
|
||||
#define MCPWM_CON_DTE(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+3))) : (0))
|
||||
/** Enable/Disable update of functional register for channel n */
|
||||
#define MCPWM_CON_DISUP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+4))) : (0))
|
||||
|
||||
/** Control the polarity for all 3 channels */
|
||||
#define MCPWM_CON_INVBDC ((uint32_t)((uint32_t)1<<29))
|
||||
/** 3-phase AC mode select */
|
||||
#define MCPWM_CON_ACMODE ((uint32_t)((uint32_t)1<<30))
|
||||
/** 3-phase DC mode select */
|
||||
#define MCPWM_CON_DCMODE ((uint32_t)((uint32_t)1<<31))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MCPWM Capture Control register
|
||||
**********************************************************************/
|
||||
/* Capture Control register, these macro definitions below can be applied for these
|
||||
* register type:
|
||||
* - MCPWM Capture Control read address
|
||||
* - MCPWM Capture Control set address
|
||||
* - MCPWM Capture control clear address
|
||||
*/
|
||||
/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
|
||||
#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
|
||||
/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
|
||||
#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
|
||||
/** TC(n) is reset by channel (n) capture event */
|
||||
#define MCPWM_CAPCON_RT(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(18+(n)))) : (0))
|
||||
/** Hardware noise filter: channel (n) capture events are delayed */
|
||||
#define MCPWM_CAPCON_HNFCAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(21+(n)))) : (0))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MCPWM Interrupt register
|
||||
**********************************************************************/
|
||||
/* Interrupt registers, these macro definitions below can be applied for these
|
||||
* register type:
|
||||
* - MCPWM Interrupt Enable read address
|
||||
* - MCPWM Interrupt Enable set address
|
||||
* - MCPWM Interrupt Enable clear address
|
||||
* - MCPWM Interrupt Flags read address
|
||||
* - MCPWM Interrupt Flags set address
|
||||
* - MCPWM Interrupt Flags clear address
|
||||
*/
|
||||
/** Limit interrupt for channel (n) */
|
||||
#define MCPWM_INT_ILIM(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+0))) : (0))
|
||||
/** Match interrupt for channel (n) */
|
||||
#define MCPWM_INT_IMAT(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+1))) : (0))
|
||||
/** Capture interrupt for channel (n) */
|
||||
#define MCPWM_INT_ICAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+2))) : (0))
|
||||
|
||||
/** Fast abort interrupt */
|
||||
#define MCPWM_INT_ABORT ((uint32_t)(1<<15))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MCPWM Count Control register
|
||||
**********************************************************************/
|
||||
/* MCPWM Count Control register, these macro definitions below can be applied for these
|
||||
* register type:
|
||||
* - MCPWM Count Control read address
|
||||
* - MCPWM Count Control set address
|
||||
* - MCPWM Count Control clear address
|
||||
*/
|
||||
/** Counter(tc) advances on a rising edge on MCI(mci) pin */
|
||||
#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
|
||||
/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
|
||||
#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
|
||||
/** Channel (n) is in counter mode */
|
||||
#define MCPWM_CNTCON_CNTR(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(29+n))) : (0))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MCPWM Dead-time register
|
||||
**********************************************************************/
|
||||
/** Dead time value x for channel n */
|
||||
#define MCPWM_DT(n,x) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MCPWM Communication Pattern register
|
||||
**********************************************************************/
|
||||
#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
|
||||
#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for MCPWM Capture clear address register
|
||||
**********************************************************************/
|
||||
/** Clear the MCCAP (n) register */
|
||||
#define MCPWM_CAPCLR_CAP(n) ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<n)) : (0))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup MCPWM_Public_Types MCPWM Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MCPWM_CHANNEL_0 = 0,
|
||||
MCPWM_CHANNEL_1,
|
||||
MCPWM_CHANNEL_2,
|
||||
MCPWM_MAX_CHANNEL,
|
||||
} en_MCPWM_Channel_Id;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Motor Control PWM Channel Configuration structure type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t channelType; /**< Edge/center aligned mode for this channel,
|
||||
should be:
|
||||
- MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
|
||||
- MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
|
||||
*/
|
||||
uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
|
||||
- MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
|
||||
- MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
|
||||
*/
|
||||
uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
|
||||
uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
|
||||
should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
|
||||
uint32_t channelPeriodValue; /**< MCPWM Period value */
|
||||
uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
|
||||
} MCPWM_CHANNEL_CFG_Type;
|
||||
|
||||
/**
|
||||
* @brief MCPWM Capture Configuration type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
|
||||
uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
} MCPWM_CAPTURE_CFG_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief MCPWM Count Control Configuration type definition
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
|
||||
uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
|
||||
- ENABLE.
|
||||
- DISABLE.
|
||||
*/
|
||||
} MCPWM_COUNT_CFG_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
|
||||
void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
|
||||
MCPWM_CHANNEL_CFG_Type * channelSetup);
|
||||
void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
|
||||
MCPWM_CHANNEL_CFG_Type *channelSetup);
|
||||
void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
|
||||
MCPWM_CAPTURE_CFG_Type *captureConfig);
|
||||
void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
|
||||
uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
|
||||
void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
|
||||
uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
|
||||
void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
|
||||
void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
|
||||
void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
|
||||
void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
|
||||
uint32_t outputInvered, uint32_t outputPattern);
|
||||
void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
|
||||
void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
|
||||
void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
|
||||
FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_MCPWM_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,77 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_nvic.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_nvic.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Nesting Vectored Interrupt firmware library
|
||||
* on LPC. The main NVIC functions are defined in
|
||||
* core_cm3.h
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup NVIC NVIC (Nested Vectored Interrupt Controller)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_NVIC_H_
|
||||
#define __LPC_NVIC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup NVIC_Public_Functions NVIC Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void NVIC_DeInit(void);
|
||||
void NVIC_SCBDeInit(void);
|
||||
void NVIC_SetVTOR(uint32_t offset);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_NVIC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,199 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_pinsel.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_pinsel.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for Pin-connection block firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup PINSEL PINSEL (Pin Selection)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_PINSEL_H
|
||||
#define __LPC_PINSEL_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup PINSEL_Public_Macros PINSEL Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Macros define IOCON bits*/
|
||||
|
||||
/** Selects pin functions */
|
||||
#define IOCON_FUNC_POS (0)
|
||||
#define IOCON_FUNC_MASK (0x07<<IOCON_FUNC_POS)
|
||||
|
||||
/** Selects output function mode (on-chip pull-up/pull-down resistor control */
|
||||
#define IOCON_MODE_POS (3)
|
||||
#define IOCON_MODE_MASK (0x03<<IOCON_MODE_POS)
|
||||
#define IOCON_MODE_PLAIN ((0<<IOCON_MODE_POS))
|
||||
#define IOCON_MODE_PULLDOWN ((1<<IOCON_MODE_POS))
|
||||
#define IOCON_MODE_PULLUP ((2<<IOCON_MODE_POS))
|
||||
#define IOCON_MODE_REPEATER ((3<<IOCON_MODE_POS))
|
||||
|
||||
/** Hysteresis */
|
||||
#define IOCON_HYS_POS (5)
|
||||
#define IOCON_HYS_MASK (0x01<<IOCON_HYS_POS)
|
||||
#define IOCON_HYS_ENABLE ((1<<IOCON_HYS_POS))
|
||||
|
||||
/** Input polarity */
|
||||
#define IOCON_INVERT_POS (6)
|
||||
#define IOCON_INVERT_MASK (0x01<<IOCON_INVERT_POS)
|
||||
#define IOCON_INVERT_INPUT (1<<IOCON_INVERT_POS)
|
||||
|
||||
/** Selects Analog/Digital mode */
|
||||
#define IOCON_ADMODE_POS (7)
|
||||
#define IOCON_ADMODE_MASK (0x01<<IOCON_ADMODE_POS)
|
||||
#define IOCON_ANALOG_MODE (0<<IOCON_ADMODE_POS)
|
||||
#define IOCON_DIGITIAL_MODE (1<<IOCON_ADMODE_POS)
|
||||
|
||||
/* Controls Glitch Filter */
|
||||
#define IOCON_FILTER_POS (8)
|
||||
#define IOCON_FILTER_MASK (0x01<<IOCON_FILTER_POS)
|
||||
#define IOCON_10ns_FILTER_ENABLE (0<<IOCON_FILTER_POS)
|
||||
#define IOCON_10ns_FILTER_DISABLE (1<<IOCON_FILTER_POS)
|
||||
|
||||
/** I2C 50ns glitch filter and slew rate control */
|
||||
#define IOCON_HS_POS (8)
|
||||
#define IOCON_HS_MASK (0x01<<IOCON_HS_POS)
|
||||
#define IOCON_I2C_FILTER_ENABLE (0<<IOCON_HS_POS)
|
||||
#define IOCON_I2C_FILTER_DISABLE (1<<IOCON_HS_POS)
|
||||
|
||||
/** Driver Output Slew Rate Control*/
|
||||
#define IOCON_SLEW_POS (9)
|
||||
#define IOCON_SLEW_MASK (0x01<<IOCON_SLEW_POS)
|
||||
#define IOCON_SLEW_ENABLE ((1<<IOCON_SLEW_POS))
|
||||
|
||||
/** Controls sink current capability of the pin*/
|
||||
#define IOCON_HIDRIVE_POS (9)
|
||||
#define IOCON_HIDRIVE_MASK (0x01<<IOCON_HIDRIVE_POS)
|
||||
#define IOCON_I2CMODE_FASTPLUS (1<<IOCON_HIDRIVE_POS)
|
||||
|
||||
/** Controls open-drain mode */
|
||||
#define IOCON_OD_POS (10)
|
||||
#define IOCON_OD_MASK (0x01<<IOCON_OD_POS)
|
||||
#define IOCON_OPENDRAIN_MODE (1<<IOCON_OD_POS)
|
||||
|
||||
/** DAC enable control */
|
||||
#define IOCON_DACEN_POS (16)
|
||||
#define IOCON_DACEN_MASK (0x01<<IOCON_DACEN_POS)
|
||||
#define IOCON_DAC_ENABLE (1<<IOCON_DACEN_POS)
|
||||
|
||||
/* Macros define for Return Code */
|
||||
typedef int32_t PINSEL_RET_CODE;
|
||||
#define PINSEL_RET_OK (0)
|
||||
#define PINSEL_RET_INVALID_PIN (0x10000001)
|
||||
#define PINSEL_RET_NOT_SUPPORT (0x10000002)
|
||||
#define PINSEL_RET_ERR (-1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PINSEL_Public_Types PINSEL Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PINSEL_BASICMODE_PLAINOUT = 0, /**< Plain output */
|
||||
PINSEL_BASICMODE_PULLDOWN, /**< Pull-down enabled */
|
||||
PINSEL_BASICMODE_PULLUP, /**< Pull-up enabled (default) */
|
||||
PINSEL_BASICMODE_REPEATER /**< Repeater mode */
|
||||
}PinSel_BasicMode;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
|
||||
PINSEL_I2CMODE_FAST_STANDARD = 0,
|
||||
/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
|
||||
PINSEL_I2CMODE_OPENDRAINIO,
|
||||
/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
|
||||
PINSEL_I2CMODE_FASTMODEPLUS,
|
||||
}PinSel_I2cMode;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
/** Type D IOCON registers */
|
||||
PINSEL_PIN_TYPE_D,
|
||||
/** Type A IOCON registers */
|
||||
PINSEL_PIN_TYPE_A,
|
||||
/** Type U IOCON registers */
|
||||
PINSEL_PIN_TYPE_U,
|
||||
/** Type I IOCON registers */
|
||||
PINSEL_PIN_TYPE_I,
|
||||
/** Type W IOCON registers */
|
||||
PINSEL_PIN_TYPE_W,
|
||||
/** Unknown type */
|
||||
PINSEL_PIN_TYPE_UNKNOWN,
|
||||
}PinSel_PinType;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup PINSEL_Public_Functions PINSEL Public Functions
|
||||
* @{
|
||||
*/
|
||||
PinSel_PinType PINSEL_GetPinType(uint8_t portnum, uint8_t pinnum);
|
||||
PINSEL_RET_CODE PINSEL_ConfigPin(uint8_t portnum, uint8_t pinnum, uint8_t funcnum);
|
||||
PINSEL_RET_CODE PINSEL_SetPinMode(uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum);
|
||||
PINSEL_RET_CODE PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
|
||||
PINSEL_RET_CODE PINSEL_SetInvertInput(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
|
||||
PINSEL_RET_CODE PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
|
||||
PINSEL_RET_CODE PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode);
|
||||
PINSEL_RET_CODE PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
|
||||
PINSEL_RET_CODE PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable);
|
||||
PINSEL_RET_CODE PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable);
|
||||
PINSEL_RET_CODE PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
|
||||
PINSEL_RET_CODE PINSEL_SetI2CFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LPC_PINSEL_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
|
||||
@@ -0,0 +1,357 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_pwm.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_pwm.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for PWM firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup PWM PWM (Pulse Width Modulator)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_PWM_H_
|
||||
#define __LPC_PWM_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup PWM_Private_Macros PWM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/**********************************************************************
|
||||
* IR register definitions
|
||||
**********************************************************************/
|
||||
/** Interrupt flag for PWM match channel for 6 channel */
|
||||
#define PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))
|
||||
|
||||
/** Interrupt flag for capture input */
|
||||
#define PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4)))
|
||||
|
||||
/** IR register mask */
|
||||
#define PWM_IR_BITMASK ((uint32_t)(0x0000073F))
|
||||
|
||||
/**********************************************************************
|
||||
* TCR register definitions
|
||||
**********************************************************************/
|
||||
/** TCR register mask */
|
||||
#define PWM_TCR_BITMASK ((uint32_t)(0x0000000B))
|
||||
|
||||
/** PWM Counter Enable */
|
||||
#define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0))
|
||||
|
||||
/** PWM Counter Reset */
|
||||
#define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1))
|
||||
|
||||
/** PWM Enable */
|
||||
#define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3))
|
||||
|
||||
/**********************************************************************
|
||||
* CTCR register definitions
|
||||
**********************************************************************/
|
||||
/** CTCR register mask */
|
||||
#define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F))
|
||||
|
||||
/** PWM Counter-Timer Mode */
|
||||
#define PWM_CTCR_MODE(n) ((uint32_t)(n&0x03))
|
||||
|
||||
/** PWM Capture input select */
|
||||
#define PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2))
|
||||
|
||||
/**********************************************************************
|
||||
* MCR register definitions
|
||||
**********************************************************************/
|
||||
/** MCR register mask */
|
||||
#define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF))
|
||||
|
||||
/** generate a PWM interrupt when a MATCHn occurs */
|
||||
#define PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))
|
||||
|
||||
/** reset the PWM when a MATCHn occurs */
|
||||
#define PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))
|
||||
|
||||
/** stop the PWM when a MATCHn occurs */
|
||||
#define PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))
|
||||
|
||||
/**********************************************************************
|
||||
* CCR register definitions
|
||||
**********************************************************************/
|
||||
/** CCR register mask */
|
||||
#define PWM_CCR_BITMASK ((uint32_t)(0x0000003F))
|
||||
|
||||
/** PCAPn is rising edge sensitive */
|
||||
#define PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))
|
||||
|
||||
/** PCAPn is falling edge sensitive */
|
||||
#define PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))
|
||||
|
||||
/** PWM interrupt is generated on a PCAP event */
|
||||
#define PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))
|
||||
|
||||
/**********************************************************************
|
||||
* PCR register definitions
|
||||
**********************************************************************/
|
||||
/** PCR register mask */
|
||||
#define PWM_PCR_BITMASK (uint32_t)0x00007E7C
|
||||
|
||||
/** PWM output n is a single edge controlled output */
|
||||
#define PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))
|
||||
|
||||
/** enable PWM output n */
|
||||
#define PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))
|
||||
|
||||
/**********************************************************************
|
||||
* LER register definitions
|
||||
**********************************************************************/
|
||||
/** LER register mask*/
|
||||
#define PWM_LER_BITMASK ((uint32_t)(0x0000007F))
|
||||
|
||||
/** PWM MATCHn register update control */
|
||||
#define PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup PWM_Public_Types PWM Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PWM_0 = 0,
|
||||
PWM_1 = 1
|
||||
} en_PWM_unitId;
|
||||
|
||||
|
||||
/** @brief Configuration structure in PWM TIMER mode */
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint8_t PrescaleOption; /**< Prescale option, should be:
|
||||
- PWM_TIMER_PRESCALE_TICKVAL: Prescale in absolute value
|
||||
- PWM_TIMER_PRESCALE_USVAL: Prescale in microsecond value
|
||||
*/
|
||||
uint8_t Reserved[3];
|
||||
uint32_t PrescaleValue; /**< Prescale value, 32-bit long, should be matched
|
||||
with PrescaleOption
|
||||
*/
|
||||
} PWM_TIMERCFG_Type;
|
||||
|
||||
/** @brief Configuration structure in PWM COUNTER mode */
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint8_t CounterOption; /**< Counter Option, should be:
|
||||
- PWM_COUNTER_RISING: Rising Edge
|
||||
- PWM_COUNTER_FALLING: Falling Edge
|
||||
- PWM_COUNTER_ANY: Both rising and falling mode
|
||||
*/
|
||||
uint8_t CountInputSelect; /**< Counter input select, should be:
|
||||
- PWM_COUNTER_PCAP1_0: PWM Counter input selected is PCAP1.0 pin
|
||||
- PWM_COUNTER_PCAP1_1: PWM Counter input selected is PCAP1.1 pin
|
||||
*/
|
||||
uint8_t Reserved[2];
|
||||
} PWM_COUNTERCFG_Type;
|
||||
|
||||
/** @brief PWM Match channel configuration structure */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t MatchChannel; /**< Match channel, should be in range
|
||||
from 0..6 */
|
||||
uint8_t IntOnMatch; /**< Interrupt On match, should be:
|
||||
- ENABLE: Enable this function.
|
||||
- DISABLE: Disable this function.
|
||||
*/
|
||||
uint8_t StopOnMatch; /**< Stop On match, should be:
|
||||
- ENABLE: Enable this function.
|
||||
- DISABLE: Disable this function.
|
||||
*/
|
||||
uint8_t ResetOnMatch; /**< Reset On match, should be:
|
||||
- ENABLE: Enable this function.
|
||||
- DISABLE: Disable this function.
|
||||
*/
|
||||
} PWM_MATCHCFG_Type;
|
||||
|
||||
|
||||
/** @brief PWM Capture Input configuration structure */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t CaptureChannel; /**< Capture channel, should be in range
|
||||
from 0..1 */
|
||||
uint8_t RisingEdge; /**< caption rising edge, should be:
|
||||
- ENABLE: Enable rising edge.
|
||||
- DISABLE: Disable this function.
|
||||
*/
|
||||
uint8_t FallingEdge; /**< caption falling edge, should be:
|
||||
- ENABLE: Enable falling edge.
|
||||
- DISABLE: Disable this function.
|
||||
*/
|
||||
uint8_t IntOnCaption; /**< Interrupt On caption, should be:
|
||||
- ENABLE: Enable interrupt function.
|
||||
- DISABLE: Disable this function.
|
||||
*/
|
||||
} PWM_CAPTURECFG_Type;
|
||||
|
||||
/* Timer/Counter in PWM configuration type definition -----------------------------------*/
|
||||
|
||||
/** @brief PMW TC mode select option */
|
||||
typedef enum
|
||||
{
|
||||
PWM_MODE_TIMER = 0, /*!< PWM using Timer mode */
|
||||
PWM_MODE_COUNTER, /*!< PWM using Counter mode */
|
||||
} PWM_TC_MODE_OPT;
|
||||
|
||||
#define PARAM_PWM_TC_MODE(n) ((n==PWM_MODE_TIMER) || (n==PWM_MODE_COUNTER))
|
||||
|
||||
|
||||
/** @brief PWM Timer/Counter prescale option */
|
||||
typedef enum
|
||||
{
|
||||
PWM_TIMER_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
|
||||
PWM_TIMER_PRESCALE_USVAL /*!< Prescale in microsecond value */
|
||||
} PWM_TIMER_PRESCALE_OPT;
|
||||
|
||||
#define PARAM_PWM_TIMER_PRESCALE(n) ((n==PWM_TIMER_PRESCALE_TICKVAL) || (n==PWM_TIMER_PRESCALE_USVAL))
|
||||
|
||||
|
||||
/** @brief PWM Input Select in counter mode */
|
||||
typedef enum
|
||||
{
|
||||
PWM_COUNTER_PCAP1_0 = 0, /*!< PWM Counter input selected is PCAP1.0 pin */
|
||||
PWM_COUNTER_PCAP1_1 /*!< PWM counter input selected is CAP1.1 pin */
|
||||
} PWM_COUNTER_INPUTSEL_OPT;
|
||||
|
||||
#define PARAM_PWM_COUNTER_INPUTSEL(n) ((n==PWM_COUNTER_PCAP1_0) || (n==PWM_COUNTER_PCAP1_1))
|
||||
|
||||
/** @brief PWM Input Edge Option in counter mode */
|
||||
typedef enum
|
||||
{
|
||||
PWM_COUNTER_RISING = 1, /*!< Rising edge mode */
|
||||
PWM_COUNTER_FALLING = 2, /*!< Falling edge mode */
|
||||
PWM_COUNTER_ANY = 3 /*!< Both rising and falling mode */
|
||||
} PWM_COUNTER_EDGE_OPT;
|
||||
|
||||
#define PARAM_PWM_COUNTER_EDGE(n) ((n==PWM_COUNTER_RISING) || (n==PWM_COUNTER_FALLING) \
|
||||
|| (n==PWM_COUNTER_ANY))
|
||||
|
||||
|
||||
/* PWM configuration type definition ----------------------------------------------------- */
|
||||
/** @brief PWM operating mode options */
|
||||
typedef enum
|
||||
{
|
||||
PWM_CHANNEL_SINGLE_EDGE, /*!< PWM Channel Single edge mode */
|
||||
PWM_CHANNEL_DUAL_EDGE /*!< PWM Channel Dual edge mode */
|
||||
} PWM_CHANNEL_EDGE_OPT;
|
||||
|
||||
#define PARAM_PWM_CHANNEL_EDGE(n) ((n==PWM_CHANNEL_SINGLE_EDGE) || (n==PWM_CHANNEL_DUAL_EDGE))
|
||||
|
||||
|
||||
/** @brief PWM update type */
|
||||
typedef enum
|
||||
{
|
||||
PWM_MATCH_UPDATE_NOW = 0, /**< PWM Match Channel Update Now */
|
||||
PWM_MATCH_UPDATE_NEXT_RST /**< PWM Match Channel Update on next
|
||||
PWM Counter resetting */
|
||||
} PWM_MATCH_UPDATE_OPT;
|
||||
|
||||
#define PARAM_PWM_MATCH_UPDATE(n) ((n==PWM_MATCH_UPDATE_NOW) || (n==PWM_MATCH_UPDATE_NEXT_RST))
|
||||
|
||||
|
||||
/** @brief PWM interrupt status type definition ----------------------------------------------------- */
|
||||
/** @brief PWM Interrupt status type */
|
||||
typedef enum
|
||||
{
|
||||
PWM_INTSTAT_MR0 = PWM_IR_PWMMRn(0), /**< Interrupt flag for PWM match channel 0 */
|
||||
PWM_INTSTAT_MR1 = PWM_IR_PWMMRn(1), /**< Interrupt flag for PWM match channel 1 */
|
||||
PWM_INTSTAT_MR2 = PWM_IR_PWMMRn(2), /**< Interrupt flag for PWM match channel 2 */
|
||||
PWM_INTSTAT_MR3 = PWM_IR_PWMMRn(3), /**< Interrupt flag for PWM match channel 3 */
|
||||
PWM_INTSTAT_CAP0 = PWM_IR_PWMCAPn(0), /**< Interrupt flag for capture input 0 */
|
||||
PWM_INTSTAT_CAP1 = PWM_IR_PWMCAPn(1), /**< Interrupt flag for capture input 1 */
|
||||
PWM_INTSTAT_MR4 = PWM_IR_PWMMRn(4), /**< Interrupt flag for PWM match channel 4 */
|
||||
PWM_INTSTAT_MR6 = PWM_IR_PWMMRn(5), /**< Interrupt flag for PWM match channel 5 */
|
||||
PWM_INTSTAT_MR5 = PWM_IR_PWMMRn(6), /**< Interrupt flag for PWM match channel 6 */
|
||||
}PWM_INTSTAT_TYPE;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup PWM_Public_Functions PWM Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void PWM_PinConfig(uint8_t pwmId, uint8_t PWM_Channel, uint8_t PinselOption);
|
||||
IntStatus PWM_GetIntStatus(uint8_t pwmId, uint32_t IntFlag);
|
||||
void PWM_ClearIntPending(uint8_t pwmId, uint32_t IntFlag);
|
||||
void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct);
|
||||
void PWM_Init(uint8_t pwmId, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct);
|
||||
void PWM_DeInit (uint8_t pwmId);
|
||||
void PWM_Cmd(uint8_t pwmId, FunctionalState NewState);
|
||||
void PWM_CounterCmd(uint8_t pwmId, FunctionalState NewState);
|
||||
void PWM_ResetCounter(uint8_t pwmId);
|
||||
void PWM_ConfigMatch(uint8_t pwmId, PWM_MATCHCFG_Type *PWM_MatchConfigStruct);
|
||||
void PWM_ConfigCapture(uint8_t pwmId, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct);
|
||||
uint32_t PWM_GetCaptureValue(uint8_t pwmId, uint8_t CaptureChannel);
|
||||
void PWM_MatchUpdate(uint8_t pwmId, uint8_t MatchChannel, \
|
||||
uint32_t MatchValue, uint8_t UpdateType);
|
||||
void PWM_ChannelConfig(uint8_t pwmId, uint8_t PWMChannel, uint8_t ModeOption);
|
||||
void PWM_ChannelCmd(uint8_t pwmId, uint8_t PWMChannel, FunctionalState NewState);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_PWM_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,465 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_rtc.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_rtc.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for RTC firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup RTC RTC (Real Time Clock)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_RTC_H_
|
||||
#define __LPC_RTC_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ----------------------- BIT DEFINITIONS ----------------------------------- */
|
||||
/* Miscellaneous register group --------------------------------------------- */
|
||||
/**********************************************************************
|
||||
* ILR register definitions
|
||||
**********************************************************************/
|
||||
/** ILR register mask */
|
||||
#define RTC_ILR_BITMASK ((0x00000003))
|
||||
|
||||
/** Bit inform the source interrupt is counter increment*/
|
||||
#define RTC_IRL_RTCCIF ((1<<0))
|
||||
|
||||
/** Bit inform the source interrupt is alarm match*/
|
||||
#define RTC_IRL_RTCALF ((1<<1))
|
||||
|
||||
/**********************************************************************
|
||||
* CCR register definitions
|
||||
**********************************************************************/
|
||||
/** CCR register mask */
|
||||
#define RTC_CCR_BITMASK ((0x00000013))
|
||||
|
||||
/** Clock enable */
|
||||
#define RTC_CCR_CLKEN ((1<<0))
|
||||
|
||||
/** Clock reset */
|
||||
#define RTC_CCR_CTCRST ((1<<1))
|
||||
|
||||
/** Calibration counter enable */
|
||||
#define RTC_CCR_CCALEN ((1<<4))
|
||||
|
||||
/**********************************************************************
|
||||
* CIIR register definitions
|
||||
**********************************************************************/
|
||||
/** Counter Increment Interrupt bit for second */
|
||||
#define RTC_CIIR_IMSEC ((1<<0))
|
||||
|
||||
/** Counter Increment Interrupt bit for minute */
|
||||
#define RTC_CIIR_IMMIN ((1<<1))
|
||||
|
||||
/** Counter Increment Interrupt bit for hour */
|
||||
#define RTC_CIIR_IMHOUR ((1<<2))
|
||||
|
||||
/** Counter Increment Interrupt bit for day of month */
|
||||
#define RTC_CIIR_IMDOM ((1<<3))
|
||||
|
||||
/** Counter Increment Interrupt bit for day of week */
|
||||
#define RTC_CIIR_IMDOW ((1<<4))
|
||||
|
||||
/** Counter Increment Interrupt bit for day of year */
|
||||
#define RTC_CIIR_IMDOY ((1<<5))
|
||||
|
||||
/** Counter Increment Interrupt bit for month */
|
||||
#define RTC_CIIR_IMMON ((1<<6))
|
||||
|
||||
/** Counter Increment Interrupt bit for year */
|
||||
#define RTC_CIIR_IMYEAR ((1<<7))
|
||||
|
||||
/** CIIR bit mask */
|
||||
#define RTC_CIIR_BITMASK ((0xFF))
|
||||
|
||||
/**********************************************************************
|
||||
* AMR register definitions
|
||||
**********************************************************************/
|
||||
/** Counter Increment Select Mask bit for second */
|
||||
#define RTC_AMR_AMRSEC ((1<<0))
|
||||
|
||||
/** Counter Increment Select Mask bit for minute */
|
||||
#define RTC_AMR_AMRMIN ((1<<1))
|
||||
|
||||
/** Counter Increment Select Mask bit for hour */
|
||||
#define RTC_AMR_AMRHOUR ((1<<2))
|
||||
|
||||
/** Counter Increment Select Mask bit for day of month */
|
||||
#define RTC_AMR_AMRDOM ((1<<3))
|
||||
|
||||
/** Counter Increment Select Mask bit for day of week */
|
||||
#define RTC_AMR_AMRDOW ((1<<4))
|
||||
|
||||
/** Counter Increment Select Mask bit for day of year */
|
||||
#define RTC_AMR_AMRDOY ((1<<5))
|
||||
|
||||
/** Counter Increment Select Mask bit for month */
|
||||
#define RTC_AMR_AMRMON ((1<<6))
|
||||
|
||||
/** Counter Increment Select Mask bit for year */
|
||||
#define RTC_AMR_AMRYEAR ((1<<7))
|
||||
|
||||
/** AMR bit mask */
|
||||
#define RTC_AMR_BITMASK ((0xFF))
|
||||
|
||||
/**********************************************************************
|
||||
* RTC_AUX register definitions
|
||||
**********************************************************************/
|
||||
/** RTC Oscillator Fail detect flag */
|
||||
#define RTC_AUX_RTC_OSCF ((1<<4))
|
||||
|
||||
/**********************************************************************
|
||||
* RTC_AUXEN register definitions
|
||||
**********************************************************************/
|
||||
/** Oscillator Fail Detect interrupt enable*/
|
||||
#define RTC_AUXEN_RTC_OSCFEN ((1<<4))
|
||||
|
||||
/* Consolidated time register group ----------------------------------- */
|
||||
/**********************************************************************
|
||||
* Consolidated Time Register 0 definitions
|
||||
**********************************************************************/
|
||||
#define RTC_CTIME0_SECONDS_MASK ((0x3F))
|
||||
#define RTC_CTIME0_MINUTES_MASK ((0x3F00))
|
||||
#define RTC_CTIME0_HOURS_MASK ((0x1F0000))
|
||||
#define RTC_CTIME0_DOW_MASK ((0x7000000))
|
||||
|
||||
/**********************************************************************
|
||||
* Consolidated Time Register 1 definitions
|
||||
**********************************************************************/
|
||||
#define RTC_CTIME1_DOM_MASK ((0x1F))
|
||||
#define RTC_CTIME1_MONTH_MASK ((0xF00))
|
||||
#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
|
||||
|
||||
/**********************************************************************
|
||||
* Consolidated Time Register 2 definitions
|
||||
**********************************************************************/
|
||||
#define RTC_CTIME2_DOY_MASK ((0xFFF))
|
||||
|
||||
/**********************************************************************
|
||||
* Time Counter Group and Alarm register group
|
||||
**********************************************************************/
|
||||
/** SEC register mask */
|
||||
#define RTC_SEC_MASK (0x0000003F)
|
||||
|
||||
/** MIN register mask */
|
||||
#define RTC_MIN_MASK (0x0000003F)
|
||||
|
||||
/** HOUR register mask */
|
||||
#define RTC_HOUR_MASK (0x0000001F)
|
||||
|
||||
/** DOM register mask */
|
||||
#define RTC_DOM_MASK (0x0000001F)
|
||||
|
||||
/** DOW register mask */
|
||||
#define RTC_DOW_MASK (0x00000007)
|
||||
|
||||
/** DOY register mask */
|
||||
#define RTC_DOY_MASK (0x000001FF)
|
||||
|
||||
/** MONTH register mask */
|
||||
#define RTC_MONTH_MASK (0x0000000F)
|
||||
|
||||
/** YEAR register mask */
|
||||
#define RTC_YEAR_MASK (0x00000FFF)
|
||||
|
||||
|
||||
/** Maximum value of second */
|
||||
#define RTC_SECOND_MAX 59
|
||||
|
||||
/** Maximum value of minute*/
|
||||
#define RTC_MINUTE_MAX 59
|
||||
|
||||
/** Maximum value of hour*/
|
||||
#define RTC_HOUR_MAX 23
|
||||
|
||||
/** Minimum value of month*/
|
||||
#define RTC_MONTH_MIN 1
|
||||
|
||||
/** Maximum value of month*/
|
||||
#define RTC_MONTH_MAX 12
|
||||
|
||||
/** Minimum value of day of month*/
|
||||
#define RTC_DAYOFMONTH_MIN 1
|
||||
|
||||
/** Maximum value of day of month*/
|
||||
#define RTC_DAYOFMONTH_MAX 31
|
||||
|
||||
/** Maximum value of day of week*/
|
||||
#define RTC_DAYOFWEEK_MAX 6
|
||||
|
||||
/** Minimum value of day of year*/
|
||||
#define RTC_DAYOFYEAR_MIN 1
|
||||
|
||||
/** Maximum value of day of year*/
|
||||
#define RTC_DAYOFYEAR_MAX 366
|
||||
|
||||
/** Maximum value of year*/
|
||||
#define RTC_YEAR_MAX 4095
|
||||
|
||||
/**********************************************************************
|
||||
* Calibration register
|
||||
**********************************************************************/
|
||||
/** Calibration value */
|
||||
#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
|
||||
|
||||
/** Calibration direction */
|
||||
#define RTC_CALIBRATION_LIBDIR ((1<<17))
|
||||
|
||||
/** Calibration max value */
|
||||
#define RTC_CALIBRATION_MAX ((0x20000))
|
||||
|
||||
/** Calibration definitions */
|
||||
#define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))
|
||||
#define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))
|
||||
|
||||
/**********************************************************************
|
||||
* Event Monitor/Recorder Control register
|
||||
**********************************************************************/
|
||||
#define RTC_ERCTRL_EV0_INTWAKE_ENABLE (1<<0)
|
||||
#define RTC_ERCTRL_EV0_GPCLEAR_ENABLE (1<<1)
|
||||
#define RTC_ERCTRL_EV0_POS_EDGE (1<<2)
|
||||
#define RTC_ERCTRL_EV0_NEG_EDGE (0<<2)
|
||||
#define RTC_ERCTRL_EV0_INPUT_ENABLE (1<<3)
|
||||
|
||||
#define RTC_ERCTRL_EV1_INTWAKE_ENABLE (1<<10)
|
||||
#define RTC_ERCTRL_EV1_GPCLEAR_ENABLE (1<<11)
|
||||
#define RTC_ERCTRL_EV1_POS_EDGE (1<<12)
|
||||
#define RTC_ERCTRL_EV1_NEG_EDGE (0<<12)
|
||||
#define RTC_ERCTRL_EV1_INPUT_ENABLE (1<<13)
|
||||
|
||||
|
||||
#define RTC_ERCTRL_EV2_INTWAKE_ENABLE (1<<20)
|
||||
#define RTC_ERCTRL_EV2_GPCLEAR_ENABLE (1<<21)
|
||||
#define RTC_ERCTRL_EV2_POS_EDGE (1<<22)
|
||||
#define RTC_ERCTRL_EV2_NEG_EDGE (0<<22)
|
||||
#define RTC_ERCTRL_EV2_INPUT_ENABLE (1<<23)
|
||||
|
||||
#define RTC_ERCTRL_MODE_MASK (((uint32_t)3)<<30)
|
||||
#define RTC_ERCTRL_MODE_CLK_DISABLE (((uint32_t)0)<<30)
|
||||
#define RTC_ERCTRL_MODE_16HZ (((uint32_t)1)<<30)
|
||||
#define RTC_ERCTRL_MODE_64HZ (((uint32_t)2)<<30)
|
||||
#define RTC_ERCTRL_MODE_1KHZ (((uint32_t)3)<<30)
|
||||
|
||||
#define RTC_ER_INPUT_CHANNEL_NUM (3)
|
||||
|
||||
/**********************************************************************
|
||||
* Event Monitor/Recorder Status register
|
||||
**********************************************************************/
|
||||
#define RTC_ER_STATUS_EV0_BIT (0)
|
||||
#define RTC_ER_STATUS_EV1_BIT (1)
|
||||
#define RTC_ER_STATUS_EV2_BIT (2)
|
||||
#define RTC_ER_STATUS_GPCLEARED_BIT (3)
|
||||
#define RTC_ER_STATUS_WAKEUP_BIT (31)
|
||||
|
||||
#define RTC_ER_EVENTS_ON_EV0_FLG (1<<RTC_ER_STATUS_EV0_BIT)
|
||||
#define RTC_ER_EVENTS_ON_EV1_FLG (1<<RTC_ER_STATUS_EV1_BIT)
|
||||
#define RTC_ER_EVENTS_ON_EV2_FLG (1<<RTC_ER_STATUS_EV2_BIT)
|
||||
#define RTC_ER_STATUS_GP_CLEARED_FLG (1<<RTC_ER_STATUS_GPCLEARED_BIT)
|
||||
#define RTC_ER_STATUS_WAKEUP_REQ_PENDING (((uint32_t)1)<<RTC_ER_STATUS_WAKEUP_BIT)
|
||||
/**********************************************************************
|
||||
* Event Monitor/Recorder Counter register
|
||||
**********************************************************************/
|
||||
#define RTC_ER_EV0_COUNTER(n) (n&0x07)
|
||||
#define RTC_ER_EV1_COUNTER(n) ((n>>8)&0x07)
|
||||
#define RTC_ER_EV2_COUNTER(n) ((n>>16)&0x07)
|
||||
|
||||
/**********************************************************************
|
||||
* Event Monitor/Recorder TimeStamp register
|
||||
**********************************************************************/
|
||||
#define RTC_ER_TIMESTAMP_SEC(n) (n&0x3F)
|
||||
#define RTC_ER_TIMESTAMP_MIN(n) ((n>>6)&0x3F)
|
||||
#define RTC_ER_TIMESTAMP_HOUR(n) ((n>>12)&0x1F)
|
||||
#define RTC_ER_TIMESTAMP_DOY(n) ((n>>17)&0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup RTC_Public_Types RTC Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Time structure definitions for easy manipulate the data */
|
||||
typedef struct
|
||||
{
|
||||
/** Seconds Register */
|
||||
uint32_t SEC;
|
||||
/** Minutes Register */
|
||||
uint32_t MIN;
|
||||
/** Hours Register */
|
||||
uint32_t HOUR;
|
||||
/** Day of Month Register */
|
||||
uint32_t DOM;
|
||||
/** Day of Week Register */
|
||||
uint32_t DOW;
|
||||
/** Day of Year Register */
|
||||
uint32_t DOY;
|
||||
/** Months Register */
|
||||
uint32_t MONTH;
|
||||
/** Years Register */
|
||||
uint32_t YEAR;
|
||||
} RTC_TIME_Type;
|
||||
|
||||
/** @brief RTC interrupt source */
|
||||
typedef enum
|
||||
{
|
||||
/** Counter Increment Interrupt */
|
||||
RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF,
|
||||
/** The alarm interrupt */
|
||||
RTC_INT_ALARM = RTC_IRL_RTCALF,
|
||||
} RTC_INT_OPT;
|
||||
|
||||
|
||||
/** @brief RTC time type option */
|
||||
typedef enum
|
||||
{
|
||||
/** Second */
|
||||
RTC_TIMETYPE_SECOND = 0,
|
||||
/** Month */
|
||||
RTC_TIMETYPE_MINUTE = 1,
|
||||
/** Hour */
|
||||
RTC_TIMETYPE_HOUR = 2,
|
||||
/** Day of week */
|
||||
RTC_TIMETYPE_DAYOFWEEK = 3,
|
||||
/** Day of month */
|
||||
RTC_TIMETYPE_DAYOFMONTH = 4,
|
||||
/** Day of year */
|
||||
RTC_TIMETYPE_DAYOFYEAR = 5,
|
||||
/** Month */
|
||||
RTC_TIMETYPE_MONTH = 6,
|
||||
/** Year */
|
||||
RTC_TIMETYPE_YEAR = 7,
|
||||
} RTC_TIMETYPE_Num;
|
||||
|
||||
/** @brief Event Monitor/Recording Input Channel configuration */
|
||||
typedef struct
|
||||
{
|
||||
Bool EventOnPosEdge; // Event occurs on positive edge on the channel
|
||||
Bool IntWake; // Create interrupt and wake-up request if there is an event
|
||||
Bool GPClear; // Clear GP registers of RTC if there is an event.
|
||||
} RTC_ER_CHANNEL_Init_Type;
|
||||
|
||||
/** @brief Event Monitor/Recording configuration */
|
||||
typedef struct
|
||||
{
|
||||
RTC_ER_CHANNEL_Init_Type InputChannel[RTC_ER_INPUT_CHANNEL_NUM];
|
||||
uint32_t Clk; // Sample clock on input channel. (Hz)
|
||||
} RTC_ER_CONFIG_Type;
|
||||
|
||||
/** @brief Event Monitor/Recording TimeStamp Type */
|
||||
typedef struct
|
||||
{
|
||||
/** Seconds Register */
|
||||
uint32_t SEC;
|
||||
/** Minutes Register */
|
||||
uint32_t MIN;
|
||||
/** Hours Register */
|
||||
uint32_t HOUR;
|
||||
/** Day of Year Register */
|
||||
uint32_t DOY;
|
||||
} RTC_ER_TIMESTAMP_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup RTC_Public_Functions RTC Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void RTC_Init (LPC_RTC_TypeDef *RTCx);
|
||||
void RTC_DeInit(LPC_RTC_TypeDef *RTCx);
|
||||
void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx);
|
||||
void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
|
||||
void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
|
||||
FunctionalState NewState);
|
||||
void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
|
||||
FunctionalState NewState);
|
||||
void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue);
|
||||
uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
|
||||
void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
|
||||
void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
|
||||
void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue);
|
||||
uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
|
||||
void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
|
||||
void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
|
||||
IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
|
||||
void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
|
||||
void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
|
||||
void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir);
|
||||
void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value);
|
||||
uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel);
|
||||
|
||||
void RTC_ER_InitConfigStruct(RTC_ER_CONFIG_Type* pConfig);
|
||||
Status RTC_ER_Init(RTC_ER_CONFIG_Type* pConfig);
|
||||
Status RTC_ER_Cmd(uint8_t channel, FunctionalState state);
|
||||
uint8_t RTC_ER_GetEventCount(uint8_t channel);
|
||||
uint32_t RTC_ER_GetStatus(void);
|
||||
Bool RTC_ER_WakupReqPending(void);
|
||||
Bool RTC_ER_GPCleared(void);
|
||||
Status RTC_ER_GetFirstTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp);
|
||||
Status RTC_ER_GetLastTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp);
|
||||
void RTC_ER_ClearStatus(uint32_t status);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_RTC_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
@@ -0,0 +1,248 @@
|
||||
/***********************************************************************
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
**********************************************************************/
|
||||
|
||||
#ifndef SPIFI_ROM_API_H
|
||||
#define SPIFI_ROM_API_H
|
||||
|
||||
#include <stdint.h>
|
||||
/* define the symbol TESTING in the environment if test output desired */
|
||||
|
||||
/* maintain LONGEST_PROT >= the length (in bytes) of the largest
|
||||
protection block of any serial flash that this driver handles */
|
||||
#define LONGEST_PROT 68
|
||||
|
||||
typedef uint8_t uc;
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL ((void *)0)
|
||||
#endif
|
||||
|
||||
/* protection/sector descriptors */
|
||||
typedef struct {
|
||||
uint32_t base;
|
||||
uc flags;
|
||||
int8_t log2;
|
||||
uint16_t rept;
|
||||
} protEnt;
|
||||
/* bits in the flags byte */
|
||||
enum {RWPROT=1};
|
||||
|
||||
/* overall data structure includes # sectors, length of protection reg,
|
||||
array of descriptors
|
||||
typedef struct {
|
||||
uint16_t sectors;
|
||||
uint16_t protBytes;
|
||||
protEnt *entries;
|
||||
} protDesc; */
|
||||
|
||||
typedef union {
|
||||
uint16_t hw;
|
||||
uc byte[2];
|
||||
}stat_t;
|
||||
/* the object that init returns, and other routines use as an operand */
|
||||
typedef struct {
|
||||
uint32_t base, regbase, devSize, memSize;
|
||||
uc mfger, devType, devID, busy;
|
||||
stat_t stat;
|
||||
uint16_t reserved;
|
||||
uint16_t set_prot, write_prot;
|
||||
uint32_t mem_cmd, prog_cmd;
|
||||
uint16_t sectors, protBytes;
|
||||
uint32_t opts, errCheck;
|
||||
uc erase_shifts[4], erase_ops[4];
|
||||
protEnt *protEnts;
|
||||
char prot[LONGEST_PROT];
|
||||
} SPIFIobj;
|
||||
|
||||
/* operands of program and erase */
|
||||
typedef struct {
|
||||
char *dest;
|
||||
uint32_t length;
|
||||
char *scratch;
|
||||
int32_t protect;
|
||||
uint32_t options;
|
||||
} SPIFIopers;
|
||||
|
||||
/* instruction classes for wait_busy */
|
||||
typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
|
||||
|
||||
/* bits in options operands (MODE3, RCVCLK, and FULLCLK
|
||||
have the same relationship as in the Control register) */
|
||||
#define S_MODE3 1
|
||||
#define S_MODE0 0
|
||||
#define S_MINIMAL 2
|
||||
#define S_MAXIMAL 0
|
||||
#define S_FORCE_ERASE 4
|
||||
#define S_ERASE_NOT_REQD 8
|
||||
#define S_CALLER_ERASE 8
|
||||
#define S_ERASE_AS_REQD 0
|
||||
#define S_VERIFY_PROG 0x10
|
||||
#define S_VERIFY_ERASE 0x20
|
||||
#define S_NO_VERIFY 0
|
||||
#define S_RCVCLK 0x80
|
||||
#define S_INTCLK 0
|
||||
#define S_FULLCLK 0x40
|
||||
#define S_HALFCLK 0
|
||||
#define S_DUAL 0x100
|
||||
#define S_CALLER_PROT 0x200
|
||||
#define S_DRIVER_PROT 0
|
||||
|
||||
/* the following values in the first post-address memory command byte work
|
||||
for all known quad devices that support "no opcode" operation */
|
||||
#define NO_OPCODE_FOLLOWS 0xA5
|
||||
#define OPCODE_FOLLOWS 0xFF
|
||||
|
||||
/* basic SPI commands for serial flash */
|
||||
#define BASE_READ_CMD (CMD_RD<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|UNL_DATA)
|
||||
#define FAST_READ_CMD (CMD_READ_FAST<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|1<<INTLEN_SHIFT|UNL_DATA)
|
||||
#define BASE_PROG_CMD (CMD_PROG<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|DOUT)
|
||||
|
||||
/* the length of a standard program command is 256 on all devices */
|
||||
#define PROG_SIZE 256
|
||||
|
||||
/* options in obj->opts (mostly for setMulti) */
|
||||
/* used by Winbond: send 0xA3 command so hardware can read faster */
|
||||
#define OPT_SEND_A3 1
|
||||
/* used by SST: send 0x38 command to enable quad and allow full command set */
|
||||
#define OPT_SEND_38 2
|
||||
/* used by Winbond and others: read status reg 2, check it,
|
||||
if necessary write it back with Quad Enable set */
|
||||
#define OPT_35_OR02_01 4
|
||||
/* used by Atmel: read Configuration register, if necessary set Quad Enable */
|
||||
#define OPT_3F_OR80_3E 8
|
||||
/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
|
||||
#define OPT_65_CLR_C0_61 0x10
|
||||
/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
|
||||
to set # dummy bytes and allow XIP mode */
|
||||
#define OPT_81 0x20
|
||||
/* set for devices without full device erase command (Numonyx type 0x40) */
|
||||
#define OPT_NO_DEV_ERASE 0x40
|
||||
/* used by Macronix: status reg 2 includes selection between write-protect
|
||||
in status reg and command-based */
|
||||
#define OPT_WPSEL 0x80
|
||||
/* set when protection data has been read into the SPIFI object */
|
||||
#define OPT_PROT_READ 0x100
|
||||
/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
|
||||
#define OPT_4BAD 0x200
|
||||
/* set if setMulti should set the Dual bit in Control reg */
|
||||
#define OPT_DUAL 0x400
|
||||
/* send "# dummy bits" in C0 command to Winbond */
|
||||
#define OPT_C0 0x800
|
||||
/* set QE for Chingis */
|
||||
#define OPT_05_OR40_01 0x1000
|
||||
/* write status does not go busy */
|
||||
#define OPT_01_NO_BUSY 0x2000
|
||||
/* protection mode bits moved from protMode byte to opts Fri May 13 2011 */
|
||||
#define OPT_PROT_STAT 0x4000
|
||||
#define OPT_PROT_REG 0x8000
|
||||
#define OPT_PROT_CMD3 0x10000
|
||||
#define OPT_PROT_CMDE 0x20000
|
||||
#define OPT_PROT_MASK 0x3C000
|
||||
|
||||
#define OPT_ALL_QUAD 0x40000
|
||||
|
||||
#ifndef OMIT_ROM_TABLE
|
||||
/* interface to ROM API */
|
||||
typedef struct {
|
||||
int32_t (*spifi_init) (SPIFIobj *obj, uint32_t csHigh, uint32_t options,
|
||||
uint32_t mhz);
|
||||
int32_t (*spifi_program) (SPIFIobj *obj, char *source, SPIFIopers *opers);
|
||||
int32_t (*spifi_erase) (SPIFIobj *obj, SPIFIopers *opers);
|
||||
/* mode switching */
|
||||
void (*cancel_mem_mode)(SPIFIobj *obj);
|
||||
void (*set_mem_mode) (SPIFIobj *obj);
|
||||
|
||||
/* mid level functions */
|
||||
int32_t (*checkAd) (SPIFIobj *obj, SPIFIopers *opers);
|
||||
int32_t (*setProt) (SPIFIobj *obj, SPIFIopers *opers, char *change,
|
||||
char *saveProt);
|
||||
int32_t (*check_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
|
||||
uint32_t check_program);
|
||||
int32_t (*send_erase_cmd) (SPIFIobj *obj, uint8_t op, uint32_t addr);
|
||||
uint32_t (*ck_erase) (SPIFIobj *obj, uint32_t *addr, uint32_t length);
|
||||
int32_t (*prog_block) (SPIFIobj *obj, char *source, SPIFIopers *opers,
|
||||
uint32_t *left_in_page);
|
||||
uint32_t (*ck_prog) (SPIFIobj *obj, char *source, char *dest, uint32_t length);
|
||||
|
||||
/* low level functions */
|
||||
void(*setSize) (SPIFIobj *obj, int32_t value);
|
||||
int32_t (*setDev) (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd,
|
||||
uint32_t prog_cmd);
|
||||
uint32_t (*cmd) (uc op, uc addrLen, uc intLen, uint16_t len);
|
||||
uint32_t (*readAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr);
|
||||
void (*send04) (SPIFIobj *obj, uc op, uc len, uint32_t value);
|
||||
void (*wren_sendAd) (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
|
||||
int32_t (*write_stat) (SPIFIobj *obj, uc len, uint16_t value);
|
||||
int32_t (*wait_busy) (SPIFIobj *obj, uc prog_or_erase);
|
||||
} SPIFI_RTNS;
|
||||
|
||||
#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR)
|
||||
#endif /* OMIT_ROM_TABLE */
|
||||
|
||||
#ifdef USE_SPIFI_LIB
|
||||
extern SPIFI_RTNS spifi_table;
|
||||
#endif /* USE_SPIFI_LIB */
|
||||
|
||||
/* example of using this interface:
|
||||
#include "spifi_rom_api.h"
|
||||
#define CSHIGH 4
|
||||
#define SPIFI_MHZ 80
|
||||
#define source_data_ad (char *)1234
|
||||
|
||||
int32_t rc;
|
||||
SPIFIopers opers;
|
||||
|
||||
define_spifi_romPtr(spifi);
|
||||
SPIFIobj *obj = malloc(sizeof(SPIFIobj));
|
||||
if (!obj) { can't allocate memory }
|
||||
|
||||
rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
|
||||
if (rc) { investigate init error rc }
|
||||
printf ("the serial flash contains %d bytes\n", obj->devSize);
|
||||
|
||||
opers.dest = where_to_program;
|
||||
opers.length = how_many_bytes;
|
||||
opers.scratch = NULL; // unprogrammed data is not saved/restored
|
||||
opers.protect = -1; // save & restore protection
|
||||
opers.options = S_VERIFY_PROG;
|
||||
|
||||
rc = spifi->spifi_program (obj, source_data_ad, &opers);
|
||||
if (rc) { investigate program error rc }
|
||||
*/
|
||||
|
||||
/* these are for normal users, including boot code */
|
||||
int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
|
||||
int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
|
||||
int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
|
||||
|
||||
/* these are used by the manufacturer-specific init functions */
|
||||
void setSize (SPIFIobj *obj, int32_t value);
|
||||
int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
|
||||
uint32_t read04(SPIFIobj *obj, uc op, uc len);
|
||||
int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
|
||||
void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
|
||||
|
||||
/* needs to be defined for each platform */
|
||||
void pullMISO(int high);
|
||||
|
||||
#ifdef TESTING
|
||||
/* used by testing code */
|
||||
unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
|
||||
/* predeclare a debug routine */
|
||||
void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
|
||||
#endif
|
||||
|
||||
#endif /* SPIFI_ROM_API_H */
|
||||
@@ -0,0 +1,422 @@
|
||||
/**********************************************************************
|
||||
* $Id$ lpc_ssp.h 2011-06-02
|
||||
*//**
|
||||
* @file lpc_ssp.h
|
||||
* @brief Contains all macro definitions and function prototypes
|
||||
* support for SSP firmware library on LPC
|
||||
* @version 1.0
|
||||
* @date 02. June. 2011
|
||||
* @author NXP MCU SW Application Team
|
||||
*
|
||||
* Copyright(C) 2011, NXP Semiconductor
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors'
|
||||
* relevant copyright in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
**********************************************************************/
|
||||
|
||||
/* Peripheral group ----------------------------------------------------------- */
|
||||
/** @defgroup SSP SSP (Synchronous Serial Port)
|
||||
* @ingroup LPC_CMSIS_FwLib_Drivers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __LPC_SSP_H_
|
||||
#define __LPC_SSP_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------- */
|
||||
#include "LPC407x_8x_177x_8x.h"
|
||||
#include "lpc_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Public Macros -------------------------------------------------------------- */
|
||||
/** @defgroup SSP_Public_Macros SSP Public Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************************************//**
|
||||
* SSP configuration parameter defines
|
||||
**********************************************************************/
|
||||
/** Clock phase control bit */
|
||||
#define SSP_CPHA_FIRST ((uint32_t)(0))
|
||||
#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
|
||||
|
||||
|
||||
/** Clock polarity control bit */
|
||||
/* There's no bug here!!!
|
||||
* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
|
||||
* That means the active clock is in HI state.
|
||||
* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
|
||||
* high between frames. That means the active clock is in LO state.
|
||||
*/
|
||||
#define SSP_CPOL_HI ((uint32_t)(0))
|
||||
#define SSP_CPOL_LO SSP_CR0_CPOL_HI
|
||||
|
||||
/** SSP master mode enable */
|
||||
#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
|
||||
#define SSP_MASTER_MODE ((uint32_t)(0))
|
||||
|
||||
/** SSP data bit number defines */
|
||||
#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
|
||||
#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
|
||||
#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
|
||||
#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
|
||||
#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
|
||||
#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
|
||||
#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
|
||||
#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
|
||||
#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
|
||||
#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
|
||||
#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
|
||||
#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
|
||||
#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
|
||||
|
||||
/** SSP Frame Format definition */
|
||||
/** Motorola SPI mode */
|
||||
#define SSP_FRAME_SPI SSP_CR0_FRF_SPI
|
||||
/** TI synchronous serial mode */
|
||||
#define SSP_FRAME_TI SSP_CR0_FRF_TI
|
||||
/** National Micro-wire mode */
|
||||
#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
|
||||
|
||||
/*********************************************************************//**
|
||||
* SSP Status defines
|
||||
**********************************************************************/
|
||||
/** SSP status TX FIFO Empty bit */
|
||||
#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
|
||||
/** SSP status TX FIFO not full bit */
|
||||
#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
|
||||
/** SSP status RX FIFO not empty bit */
|
||||
#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
|
||||
/** SSP status RX FIFO full bit */
|
||||
#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
|
||||
/** SSP status SSP Busy bit */
|
||||
#define SSP_STAT_BUSY SSP_SR_BSY
|
||||
|
||||
/*********************************************************************//**
|
||||
* SSP Interrupt Configuration defines
|
||||
**********************************************************************/
|
||||
/** Receive Overrun */
|
||||
#define SSP_INTCFG_ROR SSP_IMSC_ROR
|
||||
/** Receive TimeOut */
|
||||
#define SSP_INTCFG_RT SSP_IMSC_RT
|
||||
/** Rx FIFO is at least half full */
|
||||
#define SSP_INTCFG_RX SSP_IMSC_RX
|
||||
/** Tx FIFO is at least half empty */
|
||||
#define SSP_INTCFG_TX SSP_IMSC_TX
|
||||
|
||||
/*********************************************************************//**
|
||||
* SSP Configured Interrupt Status defines
|
||||
**********************************************************************/
|
||||
/** Receive Overrun */
|
||||
#define SSP_INTSTAT_ROR SSP_MIS_ROR
|
||||
/** Receive TimeOut */
|
||||
#define SSP_INTSTAT_RT SSP_MIS_RT
|
||||
/** Rx FIFO is at least half full */
|
||||
#define SSP_INTSTAT_RX SSP_MIS_RX
|
||||
/** Tx FIFO is at least half empty */
|
||||
#define SSP_INTSTAT_TX SSP_MIS_TX
|
||||
|
||||
/*********************************************************************//**
|
||||
* SSP Raw Interrupt Status defines
|
||||
**********************************************************************/
|
||||
/** Receive Overrun */
|
||||
#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
|
||||
/** Receive TimeOut */
|
||||
#define SSP_INTSTAT_RAW_RT SSP_RIS_RT
|
||||
/** Rx FIFO is at least half full */
|
||||
#define SSP_INTSTAT_RAW_RX SSP_RIS_RX
|
||||
/** Tx FIFO is at least half empty */
|
||||
#define SSP_INTSTAT_RAW_TX SSP_RIS_TX
|
||||
|
||||
/*********************************************************************//**
|
||||
* SSP Interrupt Clear defines
|
||||
**********************************************************************/
|
||||
/** Writing a 1 to this bit clears the "frame was received when
|
||||
* RxFIFO was full" interrupt */
|
||||
#define SSP_INTCLR_ROR SSP_ICR_ROR
|
||||
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
|
||||
* has not been read for a timeout period" interrupt */
|
||||
#define SSP_INTCLR_RT SSP_ICR_RT
|
||||
|
||||
/*********************************************************************//**
|
||||
* SSP DMA defines
|
||||
**********************************************************************/
|
||||
/** SSP bit for enabling RX DMA */
|
||||
#define SSP_DMA_RX SSP_DMA_RXDMA_EN
|
||||
/** SSP bit for enabling TX DMA */
|
||||
#define SSP_DMA_TX SSP_DMA_TXDMA_EN
|
||||
|
||||
/* SSP Status Implementation definitions */
|
||||
#define SSP_STAT_DONE (1UL<<8) /**< Done */
|
||||
#define SSP_STAT_ERROR (1UL<<9) /**< Error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros ------------------------------------------------------------- */
|
||||
/** @defgroup SSP_Private_Macros SSP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- BIT DEFINITIONS -------------------------------------- */
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CR0 register
|
||||
**********************************************************************/
|
||||
/** SSP data size select, must be 4 bits to 16 bits */
|
||||
#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
|
||||
/** SSP control 0 Motorola SPI mode */
|
||||
#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
|
||||
/** SSP control 0 TI synchronous serial mode */
|
||||
#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
|
||||
/** SSP control 0 National Micro-wire mode */
|
||||
#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
|
||||
/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
|
||||
bus clock high between frames, (0) = low */
|
||||
#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
|
||||
/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
|
||||
on the second clock transition of the frame, (0) = first */
|
||||
#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
|
||||
/** SSP serial clock rate value load macro, divider rate is
|
||||
PERIPH_CLK / (cpsr * (SCR + 1)) */
|
||||
#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
|
||||
/** SSP CR0 bit mask */
|
||||
#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CR1 register
|
||||
**********************************************************************/
|
||||
/** SSP control 1 loopback mode enable bit */
|
||||
#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
|
||||
/** SSP control 1 enable bit */
|
||||
#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
|
||||
/** SSP control 1 slave enable */
|
||||
#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
|
||||
/** SSP control 1 slave out disable bit, disables transmit line in slave
|
||||
mode */
|
||||
#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
|
||||
/** SSP CR1 bit mask */
|
||||
#define SSP_CR1_BITMASK ((uint32_t)(0x0F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DR register
|
||||
**********************************************************************/
|
||||
/** SSP data bit mask */
|
||||
#define SSP_DR_BITMASK(n) ((n)&0xFFFF)
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for SR register
|
||||
**********************************************************************/
|
||||
/** SSP status TX FIFO Empty bit */
|
||||
#define SSP_SR_TFE ((uint32_t)(1<<0))
|
||||
/** SSP status TX FIFO not full bit */
|
||||
#define SSP_SR_TNF ((uint32_t)(1<<1))
|
||||
/** SSP status RX FIFO not empty bit */
|
||||
#define SSP_SR_RNE ((uint32_t)(1<<2))
|
||||
/** SSP status RX FIFO full bit */
|
||||
#define SSP_SR_RFF ((uint32_t)(1<<3))
|
||||
/** SSP status SSP Busy bit */
|
||||
#define SSP_SR_BSY ((uint32_t)(1<<4))
|
||||
/** SSP SR bit mask */
|
||||
#define SSP_SR_BITMASK ((uint32_t)(0x1F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for CPSR register
|
||||
**********************************************************************/
|
||||
/** SSP clock prescaler */
|
||||
#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
|
||||
/** SSP CPSR bit mask */
|
||||
#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro define for (IMSC) Interrupt Mask Set/Clear registers
|
||||
**********************************************************************/
|
||||
/** Receive Overrun */
|
||||
#define SSP_IMSC_ROR ((uint32_t)(1<<0))
|
||||
/** Receive TimeOut */
|
||||
#define SSP_IMSC_RT ((uint32_t)(1<<1))
|
||||
/** Rx FIFO is at least half full */
|
||||
#define SSP_IMSC_RX ((uint32_t)(1<<2))
|
||||
/** Tx FIFO is at least half empty */
|
||||
#define SSP_IMSC_TX ((uint32_t)(1<<3))
|
||||
/** IMSC bit mask */
|
||||
#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro define for (RIS) Raw Interrupt Status registers
|
||||
**********************************************************************/
|
||||
/** Receive Overrun */
|
||||
#define SSP_RIS_ROR ((uint32_t)(1<<0))
|
||||
/** Receive TimeOut */
|
||||
#define SSP_RIS_RT ((uint32_t)(1<<1))
|
||||
/** Rx FIFO is at least half full */
|
||||
#define SSP_RIS_RX ((uint32_t)(1<<2))
|
||||
/** Tx FIFO is at least half empty */
|
||||
#define SSP_RIS_TX ((uint32_t)(1<<3))
|
||||
/** RIS bit mask */
|
||||
#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro define for (MIS) Masked Interrupt Status registers
|
||||
**********************************************************************/
|
||||
/** Receive Overrun */
|
||||
#define SSP_MIS_ROR ((uint32_t)(1<<0))
|
||||
/** Receive TimeOut */
|
||||
#define SSP_MIS_RT ((uint32_t)(1<<1))
|
||||
/** Rx FIFO is at least half full */
|
||||
#define SSP_MIS_RX ((uint32_t)(1<<2))
|
||||
/** Tx FIFO is at least half empty */
|
||||
#define SSP_MIS_TX ((uint32_t)(1<<3))
|
||||
/** MIS bit mask */
|
||||
#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro define for (ICR) Interrupt Clear registers
|
||||
**********************************************************************/
|
||||
/** Writing a 1 to this bit clears the "frame was received when
|
||||
* RxFIFO was full" interrupt */
|
||||
#define SSP_ICR_ROR ((uint32_t)(1<<0))
|
||||
/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
|
||||
* has not been read for a timeout period" interrupt */
|
||||
#define SSP_ICR_RT ((uint32_t)(1<<1))
|
||||
/** ICR bit mask */
|
||||
#define SSP_ICR_BITMASK ((uint32_t)(0x03))
|
||||
|
||||
/*********************************************************************//**
|
||||
* Macro defines for DMACR register
|
||||
**********************************************************************/
|
||||
/** SSP bit for enabling RX DMA */
|
||||
#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
|
||||
/** SSP bit for enabling TX DMA */
|
||||
#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
|
||||
/** DMACR bit mask */
|
||||
#define SSP_DMA_BITMASK ((uint32_t)(0x03))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Types --------------------------------------------------------------- */
|
||||
/** @defgroup SSP_Public_Types SSP Public Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief SSP configuration structure */
|
||||
typedef struct {
|
||||
uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
|
||||
where x is in range from 4 - 16 */
|
||||
uint32_t CPHA; /** Clock phase, should be:
|
||||
- SSP_CPHA_FIRST: first clock edge
|
||||
- SSP_CPHA_SECOND: second clock edge */
|
||||
uint32_t CPOL; /** Clock polarity, should be:
|
||||
- SSP_CPOL_HI: high level
|
||||
- SSP_CPOL_LO: low level */
|
||||
uint32_t Mode; /** SSP mode, should be:
|
||||
- SSP_MASTER_MODE: Master mode
|
||||
- SSP_SLAVE_MODE: Slave mode */
|
||||
uint32_t FrameFormat; /** Frame Format:
|
||||
- SSP_FRAME_SPI: Motorola SPI frame format
|
||||
- SSP_FRAME_TI: TI frame format
|
||||
- SSP_FRAME_MICROWIRE: National Microwire frame format */
|
||||
uint32_t ClockRate; /** Clock rate,in Hz */
|
||||
} SSP_CFG_Type;
|
||||
|
||||
/**
|
||||
* @brief SSP Transfer Type definitions
|
||||
*/
|
||||
typedef enum {
|
||||
SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
|
||||
SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
|
||||
} SSP_TRANSFER_Type;
|
||||
|
||||
/**
|
||||
* @brief SPI Data configuration structure definitions
|
||||
*/
|
||||
typedef struct {
|
||||
void *tx_data; /**< Pointer to transmit data */
|
||||
uint32_t tx_cnt; /**< Transmit counter */
|
||||
void *rx_data; /**< Pointer to transmit data */
|
||||
uint32_t rx_cnt; /**< Receive counter */
|
||||
uint32_t length; /**< Length of transfer data */
|
||||
uint32_t status; /**< Current status of SSP activity */
|
||||
} SSP_DATA_SETUP_Type;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Public Functions ----------------------------------------------------------- */
|
||||
/** @defgroup SSP_Public_Functions SSP Public Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SSP Init/DeInit functions --------------------------------------------------*/
|
||||
void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
|
||||
void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
|
||||
|
||||
/* SSP configure functions ----------------------------------------------------*/
|
||||
void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
|
||||
|
||||
/* SSP enable/disable functions -----------------------------------------------*/
|
||||
void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
|
||||
void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
|
||||
void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
|
||||
void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
|
||||
|
||||
/* SSP get information functions ----------------------------------------------*/
|
||||
FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
|
||||
uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
|
||||
IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
|
||||
uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
|
||||
IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
|
||||
|
||||
/* SSP transfer data functions ------------------------------------------------*/
|
||||
void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
|
||||
uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
|
||||
int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
|
||||
SSP_TRANSFER_Type xfType);
|
||||
|
||||
/* SSP IRQ function ------------------------------------------------------------*/
|
||||
void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
|
||||
void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPC_SSP_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* --------------------------------- End Of File ------------------------------ */
|
||||
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Reference in New Issue
Block a user