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[bsp][n32] n32h497zgl7-evb: add SDRAM port and correct Kconfig defaults
drv_sdram.c includes <sdram_port.h> unconditionally under BSP_USING_SDRAM, and n32h497zgl7-evb had no such header, so the option could not build at all. Add one for the M12L64164A fitted on this board: 4 banks x 1M x 16 bits = 8 MB, 12 row address bits, 8 column address bits, SDRAM1 mapped at 0x98000000. The timing values are the ones validated on this board in hardware. Three of the Kconfig defaults described a different part: BSP_SDRAM_DATA_WIDTH_SEL default 32 -> 16 BSP_SDRAM_COLUMN_BITS_SEL default 9 -> 8 BSP_SDRAM_SIZE default 32 -> 8 BANK1, ROW_BIT_12 and CAS_LATENCY_3 already matched and are unchanged. Verified by building n32h497zgl7-evb with BSP_PERIPH_PIN_CFG_READY and BSP_USING_SDRAM enabled: drv_sdram.c and the SDK's n32h49x_sdram.c compile and link with no warnings.
This commit is contained in:
OnlyoutzZ
Rbb666
@@ -71,7 +71,7 @@ menu "Onboard Peripheral Drivers"
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choice BSP_SDRAM_DATA_WIDTH_SEL
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prompt "Select SDRAM Data Width"
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default BSP_SDRAM_DATA_WIDTH_32
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default BSP_SDRAM_DATA_WIDTH_16
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config BSP_SDRAM_DATA_WIDTH_8
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bool "SDRAM Data Width 8-bits"
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@@ -85,7 +85,7 @@ menu "Onboard Peripheral Drivers"
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choice BSP_SDRAM_COLUMN_BITS_SEL
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prompt "Select SDRAM Column Bits"
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default BSP_SDRAM_COLUMN_BIT_9
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default BSP_SDRAM_COLUMN_BIT_8
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config BSP_SDRAM_COLUMN_BIT_8
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bool "SDRAM SDRAM Column Bits 8-bits"
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@@ -131,7 +131,7 @@ menu "Onboard Peripheral Drivers"
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config BSP_SDRAM_SIZE
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int "SDRAM Size (MBytes)"
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range 8 256
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default 32
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default 8
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endif
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endmenu
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@@ -0,0 +1,135 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2026-09-14 ox-horse first version for N32H497ZGL7-EVB (M12L64164A)
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*/
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/*
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* SDRAM Chip: M12L64164A
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* 4 Banks x 1M x 16 bits = 8 MB
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* 12 row address bits, 8 column address bits
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*
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*
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* N32H49x SDRAM Controller:
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* SDRAM1 base: 0x98000000
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* SDRAM2 base: 0x9C000000
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*/
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#ifndef __SDRAM_PORT_H__
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#define __SDRAM_PORT_H__
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#include "board.h"
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/*============================================================================
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* Part 0: N32cube SDRAM clock and GPIO Configuration
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*============================================================================*/
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/* clock config in RCC_Configuration()*/
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/* gpio config in GPIO_Configuration()*/
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/*============================================================================
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* Part 1: SDRAM Device Configuration
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*============================================================================*/
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/* Bank select: 1 = SDRAM1 (0x98000000), 2 = SDRAM2 (0x9C000000) */
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#ifdef BSP_SDRAM_BANK1
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#define SDRAM_BANK_ADDR ((uint32_t)0x98000000)
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#endif /* BSP_SDRAM_BANK1 */
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#ifdef BSP_SDRAM_BANK2
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#define SDRAM_BANK_ADDR ((uint32_t)0x9C000000)
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#endif /* BSP_SDRAM_BANK2 */
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/* Data bus width: 8 / 16 / 32 */
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#ifdef BSP_SDRAM_DATA_WIDTH_8
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#define SDRAM_DATA_WIDTH 8
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#endif /* BSP_SDRAM_DATA_WIDTH_8 */
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#ifdef BSP_SDRAM_DATA_WIDTH_16
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#define SDRAM_DATA_WIDTH 16
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#endif /* BSP_SDRAM_DATA_WIDTH_16 */
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#ifdef BSP_SDRAM_DATA_WIDTH_32
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#define SDRAM_DATA_WIDTH 32
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#endif /* BSP_SDRAM_DATA_WIDTH_32 */
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/* Column address bits: 8-256 / 9-512 / 10-1024 / 11-2048 */
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#ifdef BSP_SDRAM_COLUMN_BIT_8
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#define SDRAM_COLUMN_BITS 8
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#endif /* BSP_SDRAM_COLUMN_BIT_8 */
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#ifdef BSP_SDRAM_COLUMN_BIT_9
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#define SDRAM_COLUMN_BITS 9
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#endif /* BSP_SDRAM_COLUMN_BIT_9 */
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#ifdef BSP_SDRAM_COLUMN_BIT_10
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#define SDRAM_COLUMN_BITS 10
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#endif /* BSP_SDRAM_COLUMN_BIT_10 */
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#ifdef BSP_SDRAM_COLUMN_BIT_11
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#define SDRAM_COLUMN_BITS 11
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#endif /* BSP_SDRAM_COLUMN_BIT_11 */
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/* Row address bits: 11-2048 / 12-4096 / 13-8192 */
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#ifdef BSP_SDRAM_ROW_BIT_11
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#define SDRAM_ROW_BITS 11
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#endif /* BSP_SDRAM_ROW_BIT_11 */
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#ifdef BSP_SDRAM_ROW_BIT_12
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#define SDRAM_ROW_BITS 12
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#endif /* BSP_SDRAM_ROW_BIT_12 */
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#ifdef BSP_SDRAM_ROW_BIT_13
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#define SDRAM_ROW_BITS 13
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#endif /* BSP_SDRAM_ROW_BIT_13 */
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/* Address mask for device chip-select matching */
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#define SDRAM_ADDRESS_MASK ((uint32_t)(0xFFFFFFFF - ((BSP_SDRAM_SIZE * 1024U * 1024U) - 1)))
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/*============================================================================
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* Part 2: Timing Parameters (unit: SDRAM clock cycles)
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* These are the values validated on this board in hardware. Each line keeps
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* the M12L64164A datasheet minimum it covers, so they can be recomputed if
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* the SDRAM clock changes.
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*============================================================================*/
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/* tRAS: Row Active Time (datasheet min 42ns) */
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#define SELFREFRESHTIME 7
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/* tRC: Row Cycle Time (datasheet min 60ns) */
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#define ROWCYCLEDELAY 9
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/* tRP: Precharge Time (datasheet min 18ns) */
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#define RPDELAY 4
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/* tWR: Write Recovery (datasheet min 12ns) */
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#define WRITERECOVERYTIME 3
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/* tRCD: RAS to CAS Delay (datasheet min 18ns) */
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#define RCDDELAY 4
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/* tRRD: Row Activate to Row Activate delay (datasheet min 12ns) */
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#define SDRAM_RP_DELAY 3
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/* tRFC: Refresh Cycle Time (datasheet min 67.5ns) */
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#define SDRAM_REFRESH_CYCLE 9
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/* Auto-refresh interval counter value
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* Formula: RefreshInterval = SDRAM_CLK_MHz * tREF_ms * 1000 / Nrows
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* For example: SDRAM_CLK=80MHz, tREF=64ms, rows=4096:
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* = 80 * 64 * 1000 / 4096 ≈ 0x04E2
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* Adjust based on actual SDRAMMEMCLK configuration. */
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#define SDRAM_REFRESH_COUNT ((uint32_t)0x04A0) /* whichever is smaller */
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/*============================================================================
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* Part 3: SDRAM Chip Mode Register Value (sent via LOADMODE command)
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* These macros are also defined internally in drv_sdram.c.
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*============================================================================*/
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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#endif /* __SDRAM_PORT_H__ */
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