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[HC32][BSP] Delete PM_TICKLESS_TIMER_ENABLE_MASK in pm_config.h, modify 'NAME_MAX' to 24 #11798

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This commit is contained in:
Leeto
2026-09-16 17:54:41 +08:00
committed by GitHub
parent 69451d1a8e
commit bbc45da16c
52 changed files with 2852 additions and 728 deletions
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bsp/hc32/.clang-format-ignore
+2 -1
View File
@@ -1,2 +1,3 @@
# clang-format ignore file
# clang-format ignore file
/libraries/hc32_drivers/
*/rtconfig.h
bsp/hc32/README.md
+2
View File
@@ -11,8 +11,10 @@ HC32 系列 BSP 目前支持情况如下表所示：
| **F4 系列** | |
| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 |
| [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 |
| [ev_hc32f467_lqfp144](ev_hc32f467_lqfp176) | 小华 官方 EV_F467_LQ144 开发板 |
| [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 |
| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
| [ev_hc32f4a2_lqfp176](ev_hc32f4a2_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
| [lckfb-hc32f4a0-lqfp100](lckfb-hc32f4a0-lqfp100) | 立创开发板 天空星-HC32F4A0PITB |
| [ev_hc32f4a8_lqfp176](ev_hc32f4a8_lqfp176) | 小华 官方 EV_F4A8_LQ176 开发板 |
| **M1 系列** | |
bsp/hc32/ev_hc32f334_lqfp64/.config
+1 -1
View File
@@ -106,7 +106,7 @@
# end of rt_strnlen options
# end of klibc options
CONFIG_RT_NAME_MAX=12
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h
+2 -2
View File
@@ -24,9 +24,9 @@ extern "C" {
For the message RAM:
1. MCAN1 and MCAN2 share 2048 bytes message RAM
2. User can modify the definitions of filter number, Rx FIFO number, Tx FIFO number.
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
If only one FIFO is needed, use Rx FIFO0. If Rx FIFO1 is needed, define it's macro between 1 and 64,
and pay attention the total size of meesage RAM that to be allocated.
and pay attention the total size of message RAM that to be allocated.
*/
#ifdef RT_CAN_USING_CANFD
bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h
+1 -6
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2024-02-20 CDT first version
* 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer
*/
#ifndef __PM_CONFIG_H__
@@ -20,12 +21,6 @@ extern "C" {
#ifdef BSP_USING_PM
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \
((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h
+1 -1
View File
@@ -61,7 +61,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_NAME_MAX 24
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
bsp/hc32/ev_hc32f448_lqfp80/.config
+1 -1
View File
@@ -106,7 +106,7 @@
# end of rt_strnlen options
# end of klibc options
CONFIG_RT_NAME_MAX=12
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
bsp/hc32/ev_hc32f448_lqfp80/board/config/mcan_config.h
+2 -2
View File
@@ -25,9 +25,9 @@ extern "C" {
For the message RAM:
1. MCAN1 and MCAN2 share 2048 bytes message RAM
2. User can modify the definitions of filter number, Rx FIFO number, Tx FIFO number.
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
If only one FIFO is needed, use Rx FIFO0. If Rx FIFO1 is needed, define it's macro between 1 and 64,
and pay attention the total size of meesage RAM that to be allocated.
and pay attention the total size of message RAM that to be allocated.
*/
#ifdef RT_CAN_USING_CANFD
bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h
+1 -6
View File
@@ -7,6 +7,7 @@
* Change Logs:
* Date Author Notes
* 2024-02-20 CDT first version
* 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer
*/
#ifndef __PM_CONFIG_H__
@@ -21,12 +22,6 @@ extern "C" {
#ifdef BSP_USING_PM
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \
((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
bsp/hc32/ev_hc32f460_lqfp100_v2/.config
+1 -1
View File
@@ -106,7 +106,7 @@
# end of rt_strnlen options
# end of klibc options
CONFIG_RT_NAME_MAX=12
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig
+1
View File
@@ -407,6 +407,7 @@ menu "On-chip Peripheral Drivers"
bool "Enable SDIO"
default n
select RT_USING_SDIO
select RT_USING_DFS
if BSP_USING_SDIO
config BSP_USING_SDIO1
bool "Enable SDIO1"
bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h
+1 -4
View File
@@ -8,6 +8,7 @@
* 2023-05-12 CDT first version
* 2024-06-13 CDT disable pm tickless timer
* delete member u16ExBusHold of PM_SLEEP_DEEP_CFG
* 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer
*/
#ifndef __PM_CONFIG_H__
@@ -22,10 +23,6 @@ extern "C" {
#ifdef BSP_USING_PM
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL)
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h
-9
View File
@@ -295,13 +295,4 @@
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
#ifndef usb_phyaddr2ramaddr
#define usb_phyaddr2ramaddr(addr) (addr)
#endif
#ifndef usb_ramaddr2phyaddr
#define usb_ramaddr2phyaddr(addr) (addr)
#endif
#endif
bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h
+1 -1
View File
@@ -61,7 +61,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_NAME_MAX 24
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
bsp/hc32/ev_hc32f467_lqfp144/project.ewp
+14 -5
View File
@@ -323,7 +323,6 @@
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\ports</state>
@@ -344,6 +343,7 @@
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Include</state>
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f467\Include</state>
<state>$PROJ_DIR$\..\platform\tca9539</state>
<state>$PROJ_DIR$\..\tests</state>
<state>$PROJ_DIR$\..\..\..\components\net\utest</state>
</option>
<option>
@@ -1319,7 +1319,6 @@
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\ports</state>
@@ -1340,6 +1339,7 @@
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Include</state>
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f467\Include</state>
<state>$PROJ_DIR$\..\platform\tca9539</state>
<state>$PROJ_DIR$\..\tests</state>
<state>$PROJ_DIR$\..\..\..\components\net\utest</state>
</option>
<option>
@@ -2090,9 +2090,6 @@
<file>
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_irq.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_soft_i2c.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_tmr_capture.c</name>
</file>
@@ -2298,6 +2295,18 @@
<name>$PROJ_DIR$\..\platform\tca9539\tca9539.c</name>
</file>
</group>
<group>
<name>Tests</name>
<file>
<name>$PROJ_DIR$\..\tests\test_uart_v1.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\tests\test_i2c.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\tests\test_gpio.c</name>
</file>
</group>
<group>
<name>utc_UTest</name>
</group>
bsp/hc32/ev_hc32f467_lqfp144/project.uvoptx
+1139 -2
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f467_lqfp144/project.uvprojx
+1291 -211
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f472_lqfp100/.config
+1 -1
View File
@@ -106,7 +106,7 @@
# end of rt_strnlen options
# end of klibc options
CONFIG_RT_NAME_MAX=12
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h
+1 -6
View File
@@ -7,6 +7,7 @@
* Change Logs:
* Date Author Notes
* 2024-02-20 CDT first version
* 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer
*/
#ifndef __PM_CONFIG_H__
@@ -21,12 +22,6 @@ extern "C" {
#ifdef BSP_USING_PM
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \
((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h
-9
View File
@@ -295,13 +295,4 @@
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
#ifndef usb_phyaddr2ramaddr
#define usb_phyaddr2ramaddr(addr) (addr)
#endif
#ifndef usb_ramaddr2phyaddr
#define usb_ramaddr2phyaddr(addr) (addr)
#endif
#endif
bsp/hc32/ev_hc32f472_lqfp100/project.ewp
+124 -59
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f472_lqfp100/project.uvprojx
+154 -22
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h
+1 -1
View File
@@ -61,7 +61,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_NAME_MAX 24
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
bsp/hc32/ev_hc32f4a0_lqfp176/.config
+1 -1
View File
@@ -106,7 +106,7 @@
# end of rt_strnlen options
# end of klibc options
CONFIG_RT_NAME_MAX=12
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig
+1
View File
@@ -679,6 +679,7 @@ menu "On-chip Peripheral Drivers"
bool "Enable SDIO"
default n
select RT_USING_SDIO
select RT_USING_DFS
if BSP_USING_SDIO
config BSP_USING_SDIO1
bool "Enable SDIO1"
bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pm_config.h
+1 -4
View File
@@ -7,6 +7,7 @@
* Date Author Notes
* 2023-05-12 CDT first version
* 2024-06-13 CDT disable pm tickless timer
* 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer
*/
#ifndef __PM_CONFIG_H__
@@ -21,10 +22,6 @@ extern "C" {
#ifdef BSP_USING_PM
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL)
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h
+1 -1
View File
@@ -1,6 +1,6 @@
/**
*******************************************************************************
* @file template/source/hc32f4xx_conf.h
* @file hc32f4xx_conf.h
* @brief This file contains HC32 Series Device Driver Library usage management.
@verbatim
Change Logs:
bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h
-9
View File
@@ -339,13 +339,4 @@
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
#ifndef usb_phyaddr2ramaddr
#define usb_phyaddr2ramaddr(addr) (addr)
#endif
#ifndef usb_ramaddr2phyaddr
#define usb_ramaddr2phyaddr(addr) (addr)
#endif
#endif
bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h
+1 -1
View File
@@ -61,7 +61,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_NAME_MAX 24
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
bsp/hc32/ev_hc32f4a2_lqfp176/.config
+22 -1
View File
@@ -276,10 +276,10 @@ CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_RPMSG is not set
# CONFIG_RT_USING_BLK is not set
# CONFIG_RT_USING_REGULATOR is not set
# CONFIG_RT_USING_POWER_SUPPLY is not set
# CONFIG_RT_USING_VIRTIO is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_CHERRYUSB is not set
# end of Device Drivers
@@ -592,7 +592,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# tools packages
#
# CONFIG_PKG_USING_VECTOR is not set
# CONFIG_PKG_USING_SORCH is not set
# CONFIG_PKG_USING_DICT is not set
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_MCOREDUMP is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
@@ -894,7 +898,24 @@ CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest"
#
# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set
# CONFIG_PKG_USING_GD32VW55X_WIFI is not set
# end of GD32 Drivers
#
# HPMicro SDK
#
# CONFIG_PKG_USING_HPM_SDK is not set
# end of HPMicro SDK
#
# FT32 HAL & SDK Drivers
#
# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set
# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set
# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set
# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set
# end of FT32 HAL & SDK Drivers
# end of HAL & SDK Drivers
#
bsp/hc32/ev_hc32f4a2_lqfp176/project.ewp
+14 -5
View File
@@ -323,7 +323,6 @@
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\ports</state>
@@ -344,6 +343,7 @@
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Include</state>
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Include</state>
<state>$PROJ_DIR$\..\platform\tca9539</state>
<state>$PROJ_DIR$\..\tests</state>
<state>$PROJ_DIR$\..\..\..\components\net\utest</state>
</option>
<option>
@@ -1319,7 +1319,6 @@
<state>$PROJ_DIR$\..\..\..\libcpu\arm\common</state>
<state>$PROJ_DIR$\..\..\..\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\include</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\phy</state>
<state>$PROJ_DIR$\..\..\..\components\drivers\smp_call</state>
<state>$PROJ_DIR$\board</state>
<state>$PROJ_DIR$\board\ports</state>
@@ -1340,6 +1339,7 @@
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Include</state>
<state>$PROJ_DIR$\packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Include</state>
<state>$PROJ_DIR$\..\platform\tca9539</state>
<state>$PROJ_DIR$\..\tests</state>
<state>$PROJ_DIR$\..\..\..\components\net\utest</state>
</option>
<option>
@@ -2087,9 +2087,6 @@
<file>
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_irq.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_soft_i2c.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\libraries\hc32_drivers\drv_usart.c</name>
</file>
@@ -2289,6 +2286,18 @@
<name>$PROJ_DIR$\..\platform\tca9539\tca9539.c</name>
</file>
</group>
<group>
<name>Tests</name>
<file>
<name>$PROJ_DIR$\..\tests\test_uart_v1.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\tests\test_i2c.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\tests\test_gpio.c</name>
</file>
</group>
<group>
<name>utc_UTest</name>
</group>
bsp/hc32/ev_hc32f4a2_lqfp176/project.uvprojx
+26 -9
View File
@@ -333,9 +333,9 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<Define>USE_DDL_DRIVER, RT_USING_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, HC32F4A2, RT_USING_ARMLIBC, __DEBUG</Define>
<Define>USE_DDL_DRIVER, __RTTHREAD__, __STDC_LIMIT_MACROS, RT_USING_LIBC, HC32F4A2, __DEBUG, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC</Define>
<Undefine />
<IncludePath>board\config;..\..\..\components\libc\posix\io\epoll;.;packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Include;..\..\..\components\drivers\phy;..\..\..\components\drivers\smp_call;..\..\..\components\net\utest;board\config\usb_config;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;packages\hc32-f4-series-latest\hc32f4a2\inc;..\..\..\components\drivers\include;board\ports;board;..\platform\tca9539;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;applications;..\libraries\hc32_drivers;..\..\..\components\finsh;packages\hc32-f4-cmsis-latest\Include;..\..\..\components\libc\posix\io\eventfd;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc</IncludePath>
<IncludePath>.;applications;board;board\ports;board\config;board\config\usb_config;packages\hc32-f4-cmsis-latest\Include;packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Include;packages\hc32-f4-series-latest\hc32f4a2\inc;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\epoll;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\components\net\utest;..\libraries\hc32_drivers;..\platform\tca9539;..\tests</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -763,13 +763,6 @@
<FilePath>..\libraries\hc32_drivers\drv_irq.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_soft_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\hc32_drivers\drv_soft_i2c.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>drv_usart.c</FileName>
@@ -1340,6 +1333,30 @@
</File>
</Files>
</Group>
<Group>
<GroupName>Tests</GroupName>
<Files>
<File>
<FileName>test_uart_v1.c</FileName>
<FileType>1</FileType>
<FilePath>..\tests\test_uart_v1.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>test_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\tests\test_i2c.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>test_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\tests\test_gpio.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
bsp/hc32/ev_hc32f4a8_lqfp176/.config
+1 -1
View File
@@ -106,7 +106,7 @@
# end of rt_strnlen options
# end of klibc options
CONFIG_RT_NAME_MAX=12
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig
+3 -2
View File
@@ -687,6 +687,7 @@ menu "On-chip Peripheral Drivers"
bool "Enable SDIO"
default n
select RT_USING_SDIO
select RT_USING_DFS
if BSP_USING_SDIO
config BSP_USING_SDIO1
bool "Enable SDIO1"
@@ -842,7 +843,7 @@ menu "On-chip Peripheral Drivers"
bool
default n
config BSP_USING_USBFS
bool "Use USBFS Core "
bool "Use USBFS Core"
default n
if BSP_USING_USBFS
choice BSP_USBFS_MODE_SEL
@@ -876,7 +877,7 @@ menu "On-chip Peripheral Drivers"
endif
endif
config BSP_USING_USBHS
bool "Use USBHS Core "
bool "Use USBHS Core"
default n
if BSP_USING_USBHS
choice BSP_USBHS_MODE_SEL
bsp/hc32/ev_hc32f4a8_lqfp176/board/config/mcan_config.h
+2 -2
View File
@@ -23,9 +23,9 @@ extern "C" {
/***********************************************************************************************/
/* The default configuration for MCANs. Users can modify the configurations based on the application.
For the message RAM:
1. MCAN1 and MCAN2 share 2048 bytes message RAM
1. MCAN1 and MCAN2 share 4K bytes message RAM
2. User can modify the definitions of filter number, Rx FIFO number, Tx FIFO number.
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
3. MCAN has two configurable Receive FIFOs, Rx FIFO0 and Rx FIFO1. There use Rx FIFO0 only by default.
If only one FIFO is needed, use Rx FIFO0. If Rx FIFO1 is needed, define it's macro between 1 and 64,
and pay attention the total size of message RAM that to be allocated.
*/
bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pm_config.h
+1 -4
View File
@@ -7,6 +7,7 @@
* Date Author Notes
* 2023-05-12 CDT first version
* 2024-06-13 CDT disable pm tickless timer
* 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer
*/
#ifndef __PM_CONFIG_H__
@@ -21,10 +22,6 @@ extern "C" {
#ifdef BSP_USING_PM
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL)
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h
-9
View File
@@ -339,13 +339,4 @@
#define CONFIG_USBHOST_PIPE_NUM 10
#endif
#ifndef usb_phyaddr2ramaddr
#define usb_phyaddr2ramaddr(addr) (addr)
#endif
#ifndef usb_ramaddr2phyaddr
#define usb_ramaddr2phyaddr(addr) (addr)
#endif
#endif
bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h
+1 -1
View File
@@ -61,7 +61,7 @@
/* end of rt_strnlen options */
/* end of klibc options */
#define RT_NAME_MAX 12
#define RT_NAME_MAX 24
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
bsp/hc32/lckfb-hc32f4a0-lqfp100/.config
+1 -1
View File
@@ -106,7 +106,7 @@
# end of rt_strnlen options
# end of klibc options
CONFIG_RT_NAME_MAX=12
CONFIG_RT_NAME_MAX=24
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_NANO is not set
# CONFIG_RT_USING_SMART is not set
bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig
+5 -4
View File
@@ -142,7 +142,7 @@ menu "On-chip Peripheral Drivers"
int "Set UART1 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA
default 64
default 64
endif
menuconfig BSP_USING_UART2
@@ -175,7 +175,7 @@ menu "On-chip Peripheral Drivers"
int "Set UART2 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA
default 64
default 64
endif
menuconfig BSP_USING_UART3
@@ -259,7 +259,7 @@ menu "On-chip Peripheral Drivers"
int "Set UART6 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA
default 64
default 64
endif
menuconfig BSP_USING_UART7
@@ -292,7 +292,7 @@ menu "On-chip Peripheral Drivers"
int "Set UART2 RX DMA ping-pong buffer size"
range 32 65535
depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA
default 64
default 64
endif
@@ -660,6 +660,7 @@ menu "On-chip Peripheral Drivers"
bool "Enable SDIO"
default n
select RT_USING_SDIO
select RT_USING_DFS
if BSP_USING_SDIO
config BSP_USING_SDIO1
bool "Enable SDIO1"
bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h
+1 -6
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2023-05-12 CDT first version
* 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer
*/
#ifndef __PM_CONFIG_H__
@@ -20,12 +21,6 @@ extern "C" {
#ifdef BSP_USING_PM
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \
((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP))
#endif
/**
* @brief run mode config @ref pm_run_mode_config structure
*/
bsp/hc32/libraries/hc32_drivers/drv_can.c
+4
View File
@@ -268,7 +268,9 @@ static rt_uint32_t _get_can_baud_index(rt_uint32_t baud)
for (index = 0; index < len; index++)
{
if (_g_baudrate_tab[index].baud_rate == baud)
{
return index;
}
}
return 0; /* default baud is CAN1MBaud */
@@ -1023,7 +1025,9 @@ static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t
/* get data */
ll_ret = CAN_GetRxFrame(p_can_dev->instance, &ll_rx_frame);
if (ll_ret != LL_OK)
{
return -RT_ERROR;
}
/* get id */
if (0 == ll_rx_frame.IDE)
bsp/hc32/libraries/hc32_drivers/drv_irq.c
+3 -2
View File
@@ -68,14 +68,15 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
stcIrqSignConfig.enIntSrc = irq_config->int_src;
stcIrqSignConfig.pfnCallback = irq_hdr;
if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig))
{
nvic_config:
#elif defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467)
stcIrqSignConfig.enIRQn = irq_config->irq_num;
stcIrqSignConfig.enIntSrc = irq_config->int_src;
stcIrqSignConfig.pfnCallback = irq_hdr;
if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig))
#endif
{
#endif
NVIC_ClearPendingIRQ(irq_config->irq_num);
NVIC_SetPriority(irq_config->irq_num, irq_config->irq_prio);
if (RT_TRUE == irq_enable)
@@ -89,7 +90,7 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
result = RT_EOK;
}
return result;
return result;
}
/*******************************************************************************
bsp/hc32/libraries/hc32_drivers/drv_pm.c
+2
View File
@@ -150,7 +150,9 @@ static void _pm_run(struct rt_pm *pm, uint8_t mode)
static uint8_t last_mode = PM_RUN_MODE_NORMAL_SPEED;
if (mode == last_mode)
{
return;
}
if (_run_switch_func[last_mode][mode] != RT_NULL)
{
bsp/hc32/libraries/hc32_drivers/drv_pwm.c
+6
View File
@@ -657,7 +657,9 @@ static rt_err_t _tmra_pwm_control(struct rt_device_pwm *device, int cmd, void *a
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
if (!configuration->channel)
{
return -RT_EINVAL;
}
configuration->channel = (configuration->channel - 1) % TMRA_CHANNEL_NUM_MAX;
@@ -1065,7 +1067,9 @@ static rt_err_t _tmr4_pwm_control(struct rt_device_pwm *device, int cmd, void *a
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
if (!configuration->channel)
{
return -RT_EPERM;
}
configuration->channel = (configuration->channel - 1) % TMR4_CHANNEL_NUM_MAX;
@@ -1532,7 +1536,9 @@ static rt_err_t _tmr6_pwm_control(struct rt_device_pwm *device, int cmd, void *a
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
if (!configuration->channel)
{
return -RT_EINVAL;
}
configuration->channel = (configuration->channel - 1) % TMR6_CHANNEL_NUM_MAX;
bsp/hc32/libraries/hc32_drivers/drv_spi.c
+8
View File
@@ -555,9 +555,13 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
{
if (device->config.mode & RT_SPI_CS_HIGH)
{
rt_pin_write(device->cs_pin, PIN_HIGH);
}
else
{
rt_pin_write(device->cs_pin, PIN_LOW);
}
}
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
@@ -671,9 +675,13 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess
if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE))
{
if (device->config.mode & RT_SPI_CS_HIGH)
{
rt_pin_write(device->cs_pin, PIN_LOW);
}
else
{
rt_pin_write(device->cs_pin, PIN_HIGH);
}
}
return message->length;
bsp/hc32/libraries/hc32_drivers/drv_usart.c
+1 -2
View File
@@ -401,8 +401,7 @@ static int hc32_putc(struct rt_serial_device *serial, char c)
else
{
/* Polling mode. */
while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET)
;
while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET);
}
USART_WriteData(uart->config->Instance, c);
bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c
+1 -2
View File
@@ -438,8 +438,7 @@ static int hc32_putc(struct rt_serial_device *serial, char c)
RT_ASSERT(RT_NULL != uart->config->Instance);
/* Polling mode. */
while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_CPLT) != SET)
;
while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_CPLT) != SET);
USART_WriteData(uart->config->Instance, c);
return 1;
bsp/hc32/platform/cherryusb/SConscript
-18
View File
@@ -1,18 +0,0 @@
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = []
path = [cwd]
if GetDepend(['RT_USING_CHERRYUSB']):
src += Glob('cherryusb_port.c')
group = DefineGroup('Platform', src, depend = ['RT_USING_CHERRYUSB'], CPPPATH = path)
Return('group')
bsp/hc32/platform/cherryusb/cherryusb_port.c
-290
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/tests/test_clock_timer.c
+1 -2
View File
@@ -151,8 +151,7 @@ static int clock_timer_sample(int argc, char *argv[])
}
/* 确保oneshot模式cb函数执行一次后才关闭定时器 */
while (cb_run == RT_FALSE)
;
while (cb_run == RT_FALSE);
cb_run = RT_FALSE;
/* close */
bsp/hc32/tests/test_soft_i2c.c
+2
View File
@@ -205,7 +205,9 @@ void mOledWriteCharHnWm(struct rt_i2c_bus_device *i2c_dev,
uint8_t page, uint8_t col, uint8_t *ArrChar)
{
if (ArrChar == NULL)
{
return;
}
rt_kprintf("x=%3d, y=%d\n", col, page);
for (uint8_t page_idx = 0; page_idx < SYM_H_BYTE; page_idx++)
{