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This commit is contained in:
jinsheng
2019-02-16 17:40:26 +08:00
parent cdb469cee9
commit bb47d78576
12 changed files with 1075 additions and 182 deletions
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bsp/stm32/stm32f746-st-disco/.config
+4 -1
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@@ -62,7 +62,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40000
CONFIG_RT_VER_NUM=0x40001
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M7=y
@@ -112,6 +112,7 @@ CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
@@ -128,6 +129,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using WiFi
@@ -307,6 +309,7 @@ CONFIG_SOC_STM32F746NG=y
#
CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_QSPI_FLASH is not set
# CONFIG_BSP_USING_ETH is not set
#
# On-chip Peripheral Drivers
bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/.mxproject
+2 -2
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File diff suppressed because one or more lines are too long
bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/CubeMX_Config.ioc
+54 -24
View File
@@ -1,34 +1,46 @@
#MicroXplorer Configuration settings - do not modify
ETH.IPParameters=MediaInterface
ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F7
Mcu.IP0=CORTEX_M7
Mcu.IP1=NVIC
Mcu.IP2=QUADSPI
Mcu.IP3=RCC
Mcu.IP4=SYS
Mcu.IP5=USART1
Mcu.IPNb=6
Mcu.IP1=ETH
Mcu.IP2=NVIC
Mcu.IP3=QUADSPI
Mcu.IP4=RCC
Mcu.IP5=SYS
Mcu.IP6=USART1
Mcu.IPNb=7
Mcu.Name=STM32F746NGHx
Mcu.Package=TFBGA216
Mcu.Pin0=PE2
Mcu.Pin1=PA14
Mcu.Pin10=PH1/OSC_OUT
Mcu.Pin11=PJ8
Mcu.Pin12=PB2
Mcu.Pin13=PD12
Mcu.Pin14=PD13
Mcu.Pin15=PD11
Mcu.Pin16=VP_SYS_VS_Systick
Mcu.Pin2=PA13
Mcu.Pin3=PB7
Mcu.Pin4=PB6
Mcu.Pin5=PC14/OSC32_IN
Mcu.Pin6=PA9
Mcu.Pin7=PC15/OSC32_OUT
Mcu.Pin8=PK1
Mcu.Pin9=PH0/OSC_IN
Mcu.PinsNb=17
Mcu.Pin1=PG14
Mcu.Pin10=PC15/OSC32_OUT
Mcu.Pin11=PK1
Mcu.Pin12=PH0/OSC_IN
Mcu.Pin13=PH1/OSC_OUT
Mcu.Pin14=PJ8
Mcu.Pin15=PC1
Mcu.Pin16=PB2
Mcu.Pin17=PD12
Mcu.Pin18=PD13
Mcu.Pin19=PA1
Mcu.Pin2=PA14
Mcu.Pin20=PC4
Mcu.Pin21=PD11
Mcu.Pin22=PA2
Mcu.Pin23=PC5
Mcu.Pin24=PA7
Mcu.Pin25=VP_SYS_VS_Systick
Mcu.Pin3=PA13
Mcu.Pin4=PG13
Mcu.Pin5=PB7
Mcu.Pin6=PB6
Mcu.Pin7=PG11
Mcu.Pin8=PC14/OSC32_IN
Mcu.Pin9=PA9
Mcu.PinsNb=26
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F746NGHx
@@ -44,10 +56,16 @@ NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false
PA1.Mode=RMII
PA1.Signal=ETH_REF_CLK
PA13.Mode=Serial_Wire
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA2.Mode=RMII
PA2.Signal=ETH_MDIO
PA7.Mode=RMII
PA7.Signal=ETH_CRS_DV
PA9.Locked=true
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
@@ -57,10 +75,16 @@ PB6.Mode=Single Bank 1
PB6.Signal=QUADSPI_BK1_NCS
PB7.Mode=Asynchronous
PB7.Signal=USART1_RX
PC1.Mode=RMII
PC1.Signal=ETH_MDC
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Mode=RMII
PC5.Signal=ETH_RXD1
PCC.Checker=false
PCC.Line=STM32F7x6
PCC.MCU=STM32F746NGHx
@@ -81,6 +105,12 @@ PD13.Signal=QUADSPI_BK1_IO3
PE2.Locked=true
PE2.Mode=Single Bank 1
PE2.Signal=QUADSPI_BK1_IO2
PG11.Mode=RMII
PG11.Signal=ETH_TX_EN
PG13.Mode=RMII
PG13.Signal=ETH_TXD0
PG14.Mode=RMII
PG14.Signal=ETH_TXD1
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Mode=HSE-External-Oscillator
@@ -117,7 +147,7 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_ETH_Init-ETH-false-HAL-true
QUADSPI.ChipSelectHighTime=QSPI_CS_HIGH_TIME_6_CYCLE
QUADSPI.ClockPrescaler=1
QUADSPI.FifoThreshold=4
bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h
+8 -5
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@@ -58,7 +58,7 @@
/* #define HAL_DAC_MODULE_ENABLED */
/* #define HAL_DCMI_MODULE_ENABLED */
/* #define HAL_DMA2D_MODULE_ENABLED */
/* #define HAL_ETH_MODULE_ENABLED */
#define HAL_ETH_MODULE_ENABLED
/* #define HAL_NAND_MODULE_ENABLED */
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
@@ -190,8 +190,8 @@
/* Section 2: PHY configuration section */
/* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* LAN8742A_PHY_ADDRESS Address*/
#define LAN8742A_PHY_ADDRESS 1
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
/* PHY Configuration delay */
@@ -202,8 +202,8 @@
/* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
@@ -226,6 +226,9 @@
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
#define PHY_ISFR ((uint16_t)0x000BU) /*!< PHY Interrupt Source Flag register Offset */
#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/main.c
+50
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@@ -63,6 +63,8 @@
/* Private variables ---------------------------------------------------------*/
ETH_HandleTypeDef heth;
QSPI_HandleTypeDef hqspi;
UART_HandleTypeDef huart1;
@@ -76,6 +78,7 @@ void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_QUADSPI_Init(void);
static void MX_ETH_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@@ -115,6 +118,7 @@ int main(void)
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_QUADSPI_Init();
MX_ETH_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@@ -188,6 +192,51 @@ void SystemClock_Config(void)
}
}
/**
* @brief ETH Initialization Function
* @param None
* @retval None
*/
static void MX_ETH_Init(void)
{
/* USER CODE BEGIN ETH_Init 0 */
/* USER CODE END ETH_Init 0 */
uint8_t MACAddr[6] ;
/* USER CODE BEGIN ETH_Init 1 */
/* USER CODE END ETH_Init 1 */
heth.Instance = ETH;
heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
MACAddr[0] = 0x00;
MACAddr[1] = 0x80;
MACAddr[2] = 0xE1;
MACAddr[3] = 0x00;
MACAddr[4] = 0x00;
MACAddr[5] = 0x00;
heth.Init.MACAddr = &MACAddr[0];
heth.Init.RxMode = ETH_RXPOLLING_MODE;
heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
/* USER CODE BEGIN MACADDRESS */
/* USER CODE END MACADDRESS */
if (HAL_ETH_Init(&heth) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ETH_Init 2 */
/* USER CODE END ETH_Init 2 */
}
/**
* @brief QUADSPI Initialization Function
* @param None
@@ -269,6 +318,7 @@ static void MX_GPIO_Init(void)
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c
+102
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@@ -97,6 +97,108 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
/**
* @brief ETH MSP Initialization
* This function configures the hardware resources used in this example
* @param heth: ETH handle pointer
* @retval None
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(heth->Instance==ETH)
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ETH_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**ETH GPIO Configuration
PG14 ------> ETH_TXD1
PG13 ------> ETH_TXD0
PG11 ------> ETH_TX_EN
PC1 ------> ETH_MDC
PA1 ------> ETH_REF_CLK
PC4 ------> ETH_RXD0
PA2 ------> ETH_MDIO
PC5 ------> ETH_RXD1
PA7 ------> ETH_CRS_DV
*/
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN ETH_MspInit 1 */
/* USER CODE END ETH_MspInit 1 */
}
}
/**
* @brief ETH MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param heth: ETH handle pointer
* @retval None
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
{
if(heth->Instance==ETH)
{
/* USER CODE BEGIN ETH_MspDeInit 0 */
/* USER CODE END ETH_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ETH_CLK_DISABLE();
/**ETH GPIO Configuration
PG14 ------> ETH_TXD1
PG13 ------> ETH_TXD0
PG11 ------> ETH_TX_EN
PC1 ------> ETH_MDC
PA1 ------> ETH_REF_CLK
PC4 ------> ETH_RXD0
PA2 ------> ETH_MDIO
PC5 ------> ETH_RXD1
PA7 ------> ETH_CRS_DV
*/
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_14|GPIO_PIN_13|GPIO_PIN_11);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7);
/* USER CODE BEGIN ETH_MspDeInit 1 */
/* USER CODE END ETH_MspDeInit 1 */
}
}
/**
* @brief QSPI MSP Initialization
* This function configures the hardware resources used in this example
bsp/stm32/stm32f746-st-disco/board/Kconfig
+9
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@@ -18,6 +18,15 @@ menu "Onboard Peripheral Drivers"
select RT_SFUD_USING_QSPI
default n
config PHY_USING_LAN8720A
bool
config BSP_USING_ETH
bool "Enable Ethernet"
select RT_USING_LWIP
select PHY_USING_LAN8720A
default n
endmenu
menu "On-chip Peripheral Drivers"
bsp/stm32/stm32f746-st-disco/board/SConscript
+5
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@@ -7,8 +7,13 @@ cwd = GetCurrentDir()
src = Glob('board.c')
src += Glob('CubeMX_Config/Src/stm32f7xx_hal_msp.c')
if GetDepend(['BSP_USING_ETH']):
src += Glob('ports/phy_reset.c')
if GetDepend(['BSP_USING_QSPI_FLASH']):
src += Glob('ports/drv_qspi_flash.c')
path = [cwd]
path += [cwd + '/CubeMX_Config/Inc']
path += [cwd + '/ports']
bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c
+24
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@@ -0,0 +1,24 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-02-16 jinsheng first version
*/
#include <rtthread.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.phy_reset"
#include <drv_log.h>
//PHY RESET PIN link system reset
/* phy reset */
void phy_reset(void)
{
}
bsp/stm32/stm32f746-st-disco/project.uvoptx
+769 -1
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File diff suppressed because it is too large Load Diff
bsp/stm32/stm32f746-st-disco/project.uvprojx
+46 -148
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File diff suppressed because it is too large Load Diff
bsp/stm32/stm32f746-st-disco/rtconfig.h
+2 -1
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@@ -38,7 +38,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40000
#define RT_VER_NUM 0x40001
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M7
@@ -78,6 +78,7 @@
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using WiFi */