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[libcpu][riscv]整合libcpu/riscv中的移植文件 提供一份公共代码于common (#6941)

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整合libcpu/riscv中的移植文件 提供一份公共代码于common

在提交本pr时，除hpmicro的内核，rv32内核bsp已完成去除大部分的冗余，大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件，从而提供一份公用代码，新移植的RV32内核的BSP可以全部使用common代码。

- 在common中提供一份公用文件：interrupt_gcc.S
- 修改原有的文件，将原有的中断中上下文切换代码替换为interrupt_gcc.S
- 基于上述修改，修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等)
- 在common中提供一份公用文件：trap_common.c；提供统一中断入口函数，中断入口函数初始化，中断入口注册等函数，并完善异常时的信息输出

- 在common中提供一份公用文件：rt_hw_stack_frame.h；将栈帧结构体剥离，供用户使用

- 在上述工作完成后，在上述工作的基础上测试仓库中risc-v内核的BSP

- 完善函数中的命名，完善中断栈的获取

- 提供一份详细的基于现有common文件的移植指南

  #### 在什么测试环境下测试通过 

- 1.CH32V307V-R1-R0
- 2.CH32V208W-R0-1V4
- 3.HPM6750EVKMINI
- 4.GD32VF103V-EVAL
- 5.qemu(CORE-V-MCU )

> 与上述开发板使用同样芯片的BSP均测试通过

在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试，测试过程系统运行正常。
This commit is contained in:
Yaochenger
2023-03-01 01:32:43 -05:00
committed by GitHub
parent 4021b82161
commit b9e4fcfc68
86 changed files with 1381 additions and 2689 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/.ignore_format.yml
+8
View File
@@ -0,0 +1,8 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- core-v-mcu.c
- crt0.S
- vectors.S
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/core-v-mcu.c
+165 -162
View File
@@ -43,7 +43,7 @@
FLASH_DEVICE_OBJECT gFlashDeviceObject[N_QSPIM];
uint8_t gQSPIFlashPresentFlg[N_QSPIM] = {0};
uint8_t gMicronFlashDetectedFlg[N_QSPIM] = {0};
#endif
#endif
#define HEAP_SIZE (( unsigned int) (64 * 1024 ))
@@ -53,20 +53,20 @@ uint8_t gMicronFlashDetectedFlg[N_QSPIM] = {0};
typedef struct
{
volatile uint32_t *rx_saddr; // 0x00
volatile uint32_t rx_size; // 0x04
volatile uint32_t rx_cfg; // 0x08
volatile uint32_t rx_initcfg; // 0x0C
volatile uint32_t *tx_saddr; // 0x10
volatile uint32_t tx_size; // 0x14
volatile uint32_t tx_cfg; // 0x18
volatile uint32_t tx_initcfg; // 0x1C
volatile uint32_t cfg_glob; // 0x20
volatile uint32_t cfg_ll; // 0x24
volatile uint32_t cfg_ur; // 0x28
volatile uint32_t cfg_size; // 0x2C
volatile uint32_t cfg_filter; // 0x30
volatile uint32_t vsync_pol; // 0x34
volatile uint32_t *rx_saddr; // 0x00
volatile uint32_t rx_size; // 0x04
volatile uint32_t rx_cfg; // 0x08
volatile uint32_t rx_initcfg; // 0x0C
volatile uint32_t *tx_saddr; // 0x10
volatile uint32_t tx_size; // 0x14
volatile uint32_t tx_cfg; // 0x18
volatile uint32_t tx_initcfg; // 0x1C
volatile uint32_t cfg_glob; // 0x20
volatile uint32_t cfg_ll; // 0x24
volatile uint32_t cfg_ur; // 0x28
volatile uint32_t cfg_size; // 0x2C
volatile uint32_t cfg_filter; // 0x30
volatile uint32_t vsync_pol; // 0x34
} camera_struct_t;
@@ -75,7 +75,7 @@ void forSimulationTesting(void);
/* test some assumptions we make about compiler settings */
static_assert(sizeof(uintptr_t) == 4,
"uintptr_t is not 4 bytes. Make sure you are using -mabi=ilp32*");
"uintptr_t is not 4 bytes. Make sure you are using -mabi=ilp32*");
/* Allocate heap to special section. Note that we have no references in the
* whole program to this variable (since its just here to allocate space in the
@@ -105,95 +105,95 @@ void flash_readid(const struct cli_cmd_entry *pEntry);
uint8_t setFLLFrequencyInIntegerMode(uint8_t aFLLNum, uint8_t aRefFreqInMHz, uint16_t aMultiplier, uint8_t aDivideRatio_R_Prescale, uint8_t aPS0_L1, uint8_t aPS0_L2)
{
uint8_t lSts = 0;
volatile uint32_t *lPLLStartAddress = (uint32_t *)NULL;
uint32_t lCounter = 0;
uint32_t lCfgVal = 0;
uint8_t lSts = 0;
volatile uint32_t *lPLLStartAddress = (uint32_t *)NULL;
uint32_t lCounter = 0;
uint32_t lCfgVal = 0;
uint8_t lPS0_L1 = aPS0_L1 & 0x03;
uint8_t lPS0_L2 = aPS0_L2 & 0xFF;
uint8_t lPS0_L1 = aPS0_L1 & 0x03;
uint8_t lPS0_L2 = aPS0_L2 & 0xFF;
if (aFLLNum == 0)
lPLLStartAddress = (uint32_t *)FLL1_START_ADDR;
else if (aFLLNum == 1)
lPLLStartAddress = (uint32_t *)FLL2_START_ADDR;
else if (aFLLNum == 2)
lPLLStartAddress = (uint32_t *)FLL3_START_ADDR;
else
lPLLStartAddress = (uint32_t *)NULL;
if (aFLLNum == 0)
lPLLStartAddress = (uint32_t *)FLL1_START_ADDR;
else if (aFLLNum == 1)
lPLLStartAddress = (uint32_t *)FLL2_START_ADDR;
else if (aFLLNum == 2)
lPLLStartAddress = (uint32_t *)FLL3_START_ADDR;
else
lPLLStartAddress = (uint32_t *)NULL;
if (lPLLStartAddress != NULL)
{
if ((aRefFreqInMHz >= 5) && (aRefFreqInMHz <= 500))
{
if ((aMultiplier > 0) && (aMultiplier < 2048))
{
if (aDivideRatio_R_Prescale < 16)
{
*lPLLStartAddress |= (1 << 19); // Bypass on;
*lPLLStartAddress |= (1 << 2); // Reset high
*lPLLStartAddress &= ~(1 << 2); // Reset low;
*lPLLStartAddress &= ~(1 << 18); // PS0_EN is set to low
*lPLLStartAddress |= (lPS0_L1 << 0); // PS0_L1 0 which gives L01 = 1
*lPLLStartAddress |= (lPS0_L2 << 4); // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
*lPLLStartAddress |= (0 << 12); // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
if (lPLLStartAddress != NULL)
{
if ((aRefFreqInMHz >= 5) && (aRefFreqInMHz <= 500))
{
if ((aMultiplier > 0) && (aMultiplier < 2048))
{
if (aDivideRatio_R_Prescale < 16)
{
*lPLLStartAddress |= (1 << 19); // Bypass on;
*lPLLStartAddress |= (1 << 2); // Reset high
*lPLLStartAddress &= ~(1 << 2); // Reset low;
*lPLLStartAddress &= ~(1 << 18); // PS0_EN is set to low
*lPLLStartAddress |= (lPS0_L1 << 0); // PS0_L1 0 which gives L01 = 1
*lPLLStartAddress |= (lPS0_L2 << 4); // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
*lPLLStartAddress |= (0 << 12); // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
// FLL1 Config 1 register not configuring PS1
*(lPLLStartAddress + 1) = 0;
// FLL1 Config 1 register not configuring PS1
*(lPLLStartAddress + 1) = 0;
// FLL1 Config 2 register
lCfgVal = 0;
lCfgVal |= (aMultiplier << 4); // MULT_INT 0x28 = 40 (40*10 = 400MHz) Multiplier cannot hold 0
lCfgVal |= (1 << 27); // INTEGER_MODE is enabled
lCfgVal |= (aDivideRatio_R_Prescale << 28); // PRESCALE value (Divide Ratio R = 1)
// FLL1 Config 2 register
lCfgVal = 0;
lCfgVal |= (aMultiplier << 4); // MULT_INT 0x28 = 40 (40*10 = 400MHz) Multiplier cannot hold 0
lCfgVal |= (1 << 27); // INTEGER_MODE is enabled
lCfgVal |= (aDivideRatio_R_Prescale << 28); // PRESCALE value (Divide Ratio R = 1)
*(lPLLStartAddress + 2) = lCfgVal;
*(lPLLStartAddress + 2) = lCfgVal;
// FLL1 Config 3 register not configuring SSC
*(lPLLStartAddress + 3) = 0;
// FLL1 Config 3 register not configuring SSC
*(lPLLStartAddress + 3) = 0;
// FLL1 Config 4 register
*(lPLLStartAddress + 4) = 0x64;
// FLL1 Config 4 register
*(lPLLStartAddress + 4) = 0x64;
// FLL1 Config 5 register
*(lPLLStartAddress + 5) = 0x269;
// FLL1 Config 5 register
*(lPLLStartAddress + 5) = 0x269;
*lPLLStartAddress |= (1 << 2); // Reset high
*lPLLStartAddress |= (1 << 18); // PS0_EN;
// lCounter = 0;
while ((*(lPLLStartAddress + 4) & 0x80000000) == 0) // Wait for lock detect to go high
{
lCounter++;
if (lCounter >= 0x00010000)
{
lSts = 5; // Unable to achieve lock
lCounter = 0;
break;
}
}
if (lSts == 0)
*(lPLLStartAddress) &= ~(1 << 19); // Bypass off;
}
else
{
lSts = 1; // aDivideRatio_R_Prescale
}
}
else
{
lSts = 2; // Invalid aMultiplier
}
}
else
{
lSts = 3; // Invalid reference freq
}
}
else
{
lSts = 4; // Invalid PLL number
}
return lSts;
*lPLLStartAddress |= (1 << 2); // Reset high
*lPLLStartAddress |= (1 << 18); // PS0_EN;
// lCounter = 0;
while ((*(lPLLStartAddress + 4) & 0x80000000) == 0) // Wait for lock detect to go high
{
lCounter++;
if (lCounter >= 0x00010000)
{
lSts = 5; // Unable to achieve lock
lCounter = 0;
break;
}
}
if (lSts == 0)
*(lPLLStartAddress) &= ~(1 << 19); // Bypass off;
}
else
{
lSts = 1; // aDivideRatio_R_Prescale
}
}
else
{
lSts = 2; // Invalid aMultiplier
}
}
else
{
lSts = 3; // Invalid reference freq
}
}
else
{
lSts = 4; // Invalid PLL number
}
return lSts;
}
int handler_count[32];
@@ -202,118 +202,121 @@ uint8_t gQSPIIdNum = 0;
void system_init(void)
{
uint32_t lFlashID = 0;
SocCtrl_t *soc = APB_SOC_CTRL_ADDR;
soc->soft_reset = 1;
uint32_t val = 0;
uint8_t i = 0;
timer_irq_disable();
uint32_t lFlashID = 0;
SocCtrl_t *soc = APB_SOC_CTRL_ADDR;
soc->soft_reset = 1;
uint32_t val = 0;
uint8_t i = 0;
timer_irq_disable();
uint32_t *lFFL1StartAddress = (uint32_t *)FLL1_START_ADDR;
uint32_t *lFFL2StartAddress = (uint32_t *)FLL2_START_ADDR;
uint32_t *lFFL3StartAddress = (uint32_t *)FLL3_START_ADDR;
uint32_t *lFFL1StartAddress = (uint32_t *)FLL1_START_ADDR;
uint32_t *lFFL2StartAddress = (uint32_t *)FLL2_START_ADDR;
uint32_t *lFFL3StartAddress = (uint32_t *)FLL3_START_ADDR;
setFLLFrequencyInIntegerMode(0, 10, 40, 1, 0, 1); // 400
setFLLFrequencyInIntegerMode(0, 10, 40, 1, 0, 1); // 400
setFLLFrequencyInIntegerMode(1, 10, 40, 1, 0, 2); // 200
setFLLFrequencyInIntegerMode(1, 10, 40, 1, 0, 2); // 200
setFLLFrequencyInIntegerMode(2, 10, 40, 1, 0, 4); // 100
setFLLFrequencyInIntegerMode(2, 10, 40, 1, 0, 4); // 100
/* Hook up isr table. This table is temporary until we figure out how to do proper vectored interrupts. */
for (int i = 0; i < 32; i++)
{
isr_table[i] = undefined_handler;
handler_count[i] = 0;
}
isr_table[0x7] = timer_irq_handler;
isr_table[0xb] = (void (*)(uint32_t))fc_soc_event_handler1; // 11 for cv32
/* Hook up isr table. This table is temporary until we figure out how to do proper vectored interrupts. */
for (int i = 0; i < 32; i++)
{
isr_table[i] = undefined_handler;
handler_count[i] = 0;
}
isr_table[0x7] = timer_irq_handler;
isr_table[0xb] = (void (*)(uint32_t))fc_soc_event_handler1; // 11 for cv32
/* mtvec is set in crt0.S */
rt_hw_interrupt_init();
rt_hw_interrupt_install(0x7, timer_irq_handler, RT_NULL, "timerirq");
rt_hw_interrupt_install(0xb, fc_soc_event_handler1, RT_NULL, "eventirq");
/* mtvec is set in crt0.S */
/* deactivate all soc events as they are enabled by default */
pulp_soc_eu_event_init();
/* deactivate all soc events as they are enabled by default */
pulp_soc_eu_event_init();
/* Setup soc events handler. */
pi_fc_event_handler_init(11);
/* Setup soc events handler. */
pi_fc_event_handler_init(11);
val = csr_read(CSR_MIE);
val = csr_read(CSR_MIE);
/* TODO: enable uart */
for (uint8_t id = 0; id != N_UART; id++)
{
udma_uart_open(id, 115200);
}
/* TODO: enable uart */
for (uint8_t id = 0; id != N_UART; id++)
{
udma_uart_open(id, 115200);
}
#if (FOR_SIMULATION_TESTING == 1)
forSimulationTesting();
forSimulationTesting();
#endif
}
void system_core_clock_update(void)
{
system_core_clock = pi_fll_get_frequency(FLL_SOC, 0);
system_core_clock = pi_fll_get_frequency(FLL_SOC, 0);
}
void system_core_clock_get(void)
{
system_core_clock_update();
return;
system_core_clock_update();
return;
}
uint16_t Writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
UdmaUart_t* puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
while (puart->status_b.tx_busy) { // ToDo: Why is this necessary? Thought the semaphore should have protected
}
while (puart->status_b.tx_busy) { // ToDo: Why is this necessary? Thought the semaphore should have protected
}
puart->tx_saddr = (uint32_t)write_buffer;
puart->tx_size = write_len;
puart->tx_cfg_b.en = 1; //enable the transfer
puart->tx_saddr = (uint32_t)write_buffer;
puart->tx_size = write_len;
puart->tx_cfg_b.en = 1; //enable the transfer
return 0;
return 0;
}
void timer_irq_handler(uint32_t mcause)
{
#warning requires critical section if interrupt nesting is used.
rt_interrupt_enter();
rt_tick_increase();
rt_interrupt_leave();
rt_interrupt_enter();
rt_tick_increase();
rt_interrupt_leave();
}
void vSystemIrqHandler(uint32_t mcause)
{
isr_table[mcause & 0x1f](mcause & 0x1f);
isr_table[mcause & 0x1f](mcause & 0x1f);
}
void undefined_handler(uint32_t mcause)
{
uint32_t RegReadVal = 0;
uint32_t RegReadVal = 0;
#ifdef __PULP_USE_LIBC
abort();
abort();
#else
if ((mcause == 18) || (mcause == 19) || (mcause == 31))
{
gSpecialHandlingIRQCnt++;
if (gSpecialHandlingIRQCnt >= 20)
{
RegReadVal = csr_read(CSR_MIE);
if ((RegReadVal & BIT(mcause)) != 0) // Check if the event interrupt mask is open.
{
// close the event interrupt mask.
csr_read_clear(CSR_MIE, BIT(mcause));
}
}
}
else
{
handler_count[mcause]++;
}
if ((mcause == 18) || (mcause == 19) || (mcause == 31))
{
gSpecialHandlingIRQCnt++;
if (gSpecialHandlingIRQCnt >= 20)
{
RegReadVal = csr_read(CSR_MIE);
if ((RegReadVal & BIT(mcause)) != 0) // Check if the event interrupt mask is open.
{
// close the event interrupt mask.
csr_read_clear(CSR_MIE, BIT(mcause));
}
}
}
else
{
handler_count[mcause]++;
}
#endif
}
void rt_systick_config(void)
{
extern int timer_irq_init(uint32_t ticks);
timer_irq_init(ARCHI_FPGA_FREQUENCY / RT_TICK_PER_SECOND);
extern int timer_irq_init(uint32_t ticks);
timer_irq_init(ARCHI_FPGA_FREQUENCY / RT_TICK_PER_SECOND);
}
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/vectors.S
+33 -33
View File
@@ -19,7 +19,7 @@
* Date Author Notes
* 2022-12-08 WangShun Remove FreeRTOS related code and add RT-Thread code
*/
.extern IRQ_Handler
.extern SW_handler
#ifdef PULP_FREERTOS_VECTORED_CONTEXT_SWITCH
.extern freertos_risc_v_ctxt_handler
#endif
@@ -30,38 +30,38 @@
.section .vectors, "ax"
.option norvc
vector_table:
j IRQ_Handler // irq0
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // irq3
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler //ctxt_handler // irq 7 mtime or timer
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ_Handler
j IRQ_Handler // irq 11 Machine (event Fifo)
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ16
j IRQ_Handler // IRQ17
j IRQ_Handler // IRQ18
j IRQ_Handler // IRQ19
j IRQ_Handler // IRQ20
j IRQ_Handler // IRQ21
j IRQ_Handler // IRQ22
j IRQ_Handler // IRQ23
j IRQ_Handler // IRQ24
j IRQ_Handler // IRQ25
j IRQ_Handler // IRQ26
j IRQ_Handler // IRQ27
j IRQ_Handler // IRQ28
j IRQ_Handler // IRQ29
j IRQ_Handler // IRQ30
j IRQ_Handler // IRQ30
j SW_handler // irq0
j SW_handler
j SW_handler
j SW_handler // irq3
j SW_handler
j SW_handler
j SW_handler
j SW_handler //ctxt_handler // irq 7 mtime or timer
j SW_handler
j SW_handler
j SW_handler // SW_handler
j SW_handler // irq 11 Machine (event Fifo)
j SW_handler
j SW_handler
j SW_handler
j SW_handler
j SW_handler // IRQ16
j SW_handler // IRQ17
j SW_handler // IRQ18
j SW_handler // IRQ19
j SW_handler // IRQ20
j SW_handler // IRQ21
j SW_handler // IRQ22
j SW_handler // IRQ23
j SW_handler // IRQ24
j SW_handler // IRQ25
j SW_handler // IRQ26
j SW_handler // IRQ27
j SW_handler // IRQ28
j SW_handler // IRQ29
j SW_handler // IRQ30
j SW_handler // IRQ30
/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the
new vector table (which is at mtvec) */
bsp/core-v-mcu/core-v-cv32e40p/board/linker_scripts/core-v-mcu.ld
+1
View File
@@ -342,6 +342,7 @@ SECTIONS
__stack_bottom = .;
. += __stack_size;
__stack_top = .;
PROVIDE( __rt_rvstack = . );
__freertos_irq_stack_top = .; /* sytem stack */
stack = .;
} > L2
bsp/core-v-mcu/core-v-cv32e40p/rtconfig.py
+2 -2
View File
@@ -17,8 +17,8 @@ else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
#if os.getenv('RTT_EXEC_PATH'):
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = 'release'
bsp/gd32/risc-v/gd32vf103r-start/rtconfig.py
+2 -2
View File
@@ -22,8 +22,8 @@ else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
#if os.getenv('RTT_EXEC_PATH'):
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
CORE = 'risc-v'
BUILD = 'debug'
bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds
+1
View File
@@ -195,5 +195,6 @@ SECTIONS
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = .);
} >ram AT>ram
}
bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/start.S
+1 -2
View File
@@ -187,7 +187,7 @@ _start0800:
csrw CSR_MTVT, t0
/* Intial the mtvt2 and enable it*/
la t0, irq_entry
la t0, SW_handler
csrw CSR_MTVT2, t0
csrs CSR_MTVT2, 0x1
@@ -236,7 +236,6 @@ _start0800:
call atexit
call __libc_init_array
/* argc = argv = 0 */
li a0, 0
li a1, 0
bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
+1
View File
@@ -195,5 +195,6 @@ SECTIONS
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = .);
} >ram AT>ram
}
bsp/hifive1/drivers/interrupt.c
+1 -1
View File
@@ -51,7 +51,7 @@ void rt_hw_interrupt_init(void)
/* config interrupt vector*/
asm volatile(
"la t0, trap_entry\n"
"la t0, SW_handler\n"
"csrw mtvec, t0"
);
bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-hifive1/flash.lds
Vendored
+1
View File
@@ -181,5 +181,6 @@ SECTIONS
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = .);
} >ram AT>ram :ram
}
bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-hifive1/init.c
Vendored
+2 -2
View File
@@ -6,7 +6,7 @@
#include "encoding.h"
extern int main(int argc, char** argv);
extern void trap_entry();
extern void SW_handler();
static unsigned long mtime_lo(void)
{
@@ -223,7 +223,7 @@ void _init()
rt_kprintf("core freq at %ld Hz\n", get_cpu_freq());
write_csr(mtvec, &trap_entry);
write_csr(mtvec, &SW_handler);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
bsp/hifive1/freedom-e-sdk/bsp/env/start.S
Vendored
+1 -1
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@@ -87,7 +87,7 @@ _start:
#if defined(ENABLE_SMP)
2:
la t0, trap_entry
la t0, SW_handler
csrw mtvec, t0
csrr a0, mhartid
bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld
+1
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@@ -247,6 +247,7 @@ SECTIONS
. += STACK_SIZE;
. = ALIGN(8);
PROVIDE (_stack = .);
PROVIDE( __rt_rvstack = . );
PROVIDE (_stack_in_dlm = .);
} > AXI_SRAM
bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/start.S
+1 -1
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@@ -46,7 +46,7 @@ _start:
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S
+1 -1
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@@ -11,7 +11,7 @@
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evk/startup/HPM6360/trap.c
+1 -1
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@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S
+1 -2
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@@ -45,10 +45,9 @@ _start:
/* Disable Vector mode */
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
/* System reset handler */
call reset_handler
bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/vectors.S
+1 -1
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@@ -9,7 +9,7 @@
.align 9
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c
+1 -1
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@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld
+1
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@@ -247,6 +247,7 @@ SECTIONS
. += STACK_SIZE;
. = ALIGN(8);
PROVIDE (_stack = .);
PROVIDE( __rt_rvstack = . );
PROVIDE (_stack_in_dlm = .);
} > AXI_SRAM
bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S
+1 -1
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@@ -46,7 +46,7 @@ _start:
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S
+1 -1
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@@ -11,7 +11,7 @@
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c
+1 -1
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@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S
+1 -2
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@@ -45,10 +45,9 @@ _start:
/* Disable Vector mode */
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
/* System reset handler */
call reset_handler
bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S
+1 -1
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@@ -9,7 +9,7 @@
.align 9
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c
+1 -1
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@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S
+1 -1
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@@ -52,7 +52,7 @@ _start:
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#define HANDLER_S_TRAP irq_handler_s_trap
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s
+1 -1
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@@ -224,7 +224,7 @@ MARK_FUNC __SEGGER_init_done
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#define HANDLER_S_TRAP irq_handler_s_trap
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c
+3 -3
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@@ -100,11 +100,11 @@ __attribute__((weak)) void mchtmr_s_isr(void)
}
#ifndef CONFIG_FREERTOS
void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
void SW_handler(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
#else
void irq_handler_trap(void) __attribute__ ((section(".isr_vector")));
void SW_handler(void) __attribute__ ((section(".isr_vector")));
#endif
void irq_handler_trap(void)
void SW_handler(void)
{
long mcause = read_csr(CSR_MCAUSE);
long mepc = read_csr(CSR_MEPC);
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h
+1 -1
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@@ -22,7 +22,7 @@ default_irq_handler:
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S
+1 -1
View File
@@ -52,7 +52,7 @@ _start:
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
#endif
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s
+1 -1
View File
@@ -224,7 +224,7 @@ MARK_FUNC __SEGGER_init_done
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
#endif
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c
+3 -3
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@@ -89,11 +89,11 @@ __attribute__((weak)) long exception_handler(long cause, long epc)
}
#ifndef CONFIG_FREERTOS
void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
void SW_handler(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
#else
void irq_handler_trap(void) __attribute__ ((section(".isr_vector")));
void SW_handler(void) __attribute__ ((section(".isr_vector")));
#endif
void irq_handler_trap(void)
void SW_handler(void)
{
long mcause = read_csr(CSR_MCAUSE);
long mepc = read_csr(CSR_MEPC);
bsp/k210/link.lds
+1
View File
@@ -128,6 +128,7 @@ SECTIONS
. += __STACKSIZE__;
__stack_cpu0 = .;
PROVIDE( __rt_rvstack = .);
. += __STACKSIZE__;
__stack_cpu1 = .;
bsp/nuclei/gd32vf103_rvstar/.config
+299 -74
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File diff suppressed because it is too large Load Diff
bsp/nuclei/gd32vf103_rvstar/README.md
+13 -1
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@@ -64,9 +64,21 @@ export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包,修改链接脚本。
```c
.stack ORIGIN(RAM) + LENGTH(RAM) - __TOT_STACK_SIZE (NOLOAD) :
{
...
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = . );//在链接脚本中补充该条语句
} >RAM AT>RAM
```
2. **可选**: 运行 ``menuconfig``来进行内核配置
3. 运行 ``scons -c``清理之前的编译结果
4. 运行 ``scons``来进行代码的编译
### 下载程序
bsp/nuclei/gd32vf103_rvstar/applications/main.c
+2 -2
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -16,4 +16,4 @@ int main(int argc, char *argv[])
return RT_EOK;
}
/******************** end of file *******************/
/******************** end of file *******************/
bsp/nuclei/gd32vf103_rvstar/board/board.c
+43 -3
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,7 +12,9 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "cpuport.h"
#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
#define RT_KERNEL_INTERRUPT_LEVEL 1
#ifdef RT_USING_SERIAL
#include <drv_usart.h>
@@ -122,6 +124,45 @@ void rt_hw_drivers_init(void)
#endif
}
rt_weak void rt_hw_ticksetup(void)
{
uint64_t ticks = SYSTICK_TICK_CONST;
/* Make SWI and SysTick the lowest priority interrupts. */
/* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
SysTick_Config(ticks);
ECLIC_DisableIRQ(SysTimer_IRQn);
ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
ECLIC_EnableIRQ(SysTimer_IRQn);
/* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_EnableIRQ(SysTimerSW_IRQn);
}
#define SysTick_Handler eclic_mtip_handler
/**
* @brief This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* Reload systimer */
SysTick_Reload(SYSTICK_TICK_CONST);
/* enter interrupt */
rt_interrupt_enter();
/* tick increase */
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* @brief Setup hardware board for rt-thread
*
@@ -158,4 +199,3 @@ void rt_hw_board_init(void)
}
/******************** end of file *******************/
bsp/nuclei/gd32vf103_rvstar/board/board.h
+1 -1
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/nuclei/gd32vf103_rvstar/rtconfig.h
+39 -8
View File
@@ -23,10 +23,6 @@
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
@@ -38,6 +34,7 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
@@ -49,7 +46,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart4"
#define RT_VER_NUM 0x40101
#define RT_VER_NUM 0x50000
#define ARCH_RISCV
#define ARCH_RISCV32
@@ -76,6 +73,7 @@
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
@@ -166,6 +164,11 @@
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
@@ -178,6 +181,9 @@
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
@@ -188,15 +194,39 @@
/* entertainment: terminal games and other interesting software packages */
/* Privated Packages of RealThread */
/* Arduino libraries */
/* Network Utilities */
/* Projects */
/* RT-Thread Smart */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers Config */
#define SOC_GD32VF103V
@@ -208,6 +238,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_USING_UART4
/* Board extended module Drivers */
bsp/nuclei/gd32vf103_rvstar/rtconfig.py
+2 -1
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@@ -13,7 +13,7 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'D:/Software/Nuclei/gcc/bin'
EXEC_PATH = r'D:/Software/Nuclei/gcc/bin'
else:
print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
@@ -50,6 +50,7 @@ if PLATFORM == 'gcc':
CPATH = ''
LPATH = ''
LIBS = ['stdc++']
AFLAGS += ' -I. '+ ' -D"irq_entry=SW_handler" '
if BUILD == 'debug':
CFLAGS += ' -O2 -Os -ggdb'
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
+108 -225
View File
@@ -1,12 +1,11 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-23 tyustli first version
* 2020-04-02 hqfang modified for Nuclei
*/
#include <drv_usart.h>
@@ -14,344 +13,228 @@
#ifdef RT_USING_SERIAL
#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
&& !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4)
&& !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
enum
{
struct gd32_usart {
char *name;
rt_uint32_t usart_base;
rt_uint32_t usart_clk;
rt_uint32_t gpio_clk;
rt_uint32_t gpio_port;
rt_uint32_t tx_pin;
rt_uint32_t rx_pin;
IRQn_Type irqn;
struct rt_serial_device serial;
};
enum {
#ifdef BSP_USING_UART0
GDUART0_INDEX,
#endif
#ifdef BSP_USING_UART1
GDUART1_INDEX,
#endif
#ifdef BSP_USING_UART2
GDUART2_INDEX,
#endif
#ifdef BSP_USING_UART3
GDUART3_INDEX,
#endif
#ifdef BSP_USING_UART4
GDUART4_INDEX,
GDUSART0_INDEX,
#endif
};
static struct gd32_uart_config uart_config[] =
{
static struct gd32_usart usart_config[] = {
#ifdef BSP_USING_UART0
{
"uart0",
{ "uart0",
USART0,
USART0_IRQn,
},
#endif
#ifdef BSP_USING_UART1
{
"uart1",
USART1,
USART1_IRQn,
},
#endif
#ifdef BSP_USING_UART2
{
"uart2",
USART2,
USART2_IRQn,
},
#endif
#ifdef BSP_USING_UART3
{
"uart3",
UART3,
UART3_IRQn,
},
#endif
#ifdef BSP_USING_UART4
{
"uart4",
UART4,
UART4_IRQn,
},
RCU_USART0,
RCU_GPIOA,
GPIOA,
GPIO_PIN_9,
GPIO_PIN_10,
USART0_IRQn, },
#endif
};
static struct gd32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
static rt_err_t gd32_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
struct gd32_uart *usart_obj;
struct gd32_uart_config *usart;
struct serial_configure *cfg) {
struct gd32_usart *usart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
usart_obj = (struct gd32_uart *) serial->parent.user_data;
usart = usart_obj->config;
usart = (struct gd32_usart *) serial->parent.user_data;
RT_ASSERT(usart != RT_NULL);
usart_deinit(usart->uart_base);
usart_baudrate_set(usart->uart_base, cfg->baud_rate);
/* enable GPIO clock */
rcu_periph_clock_enable(usart->gpio_clk);
/* enable USART clock */
rcu_periph_clock_enable(usart->usart_clk);
/* connect port to USARTx_Tx */
gpio_init(usart->gpio_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ,
usart->tx_pin);
/* connect port to USARTx_Rx */
gpio_init(usart->gpio_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ,
usart->rx_pin);
switch (cfg->data_bits)
{
usart_deinit(usart->usart_base);
usart_baudrate_set(usart->usart_base, cfg->baud_rate);
switch (cfg->data_bits) {
case DATA_BITS_8:
usart_word_length_set(usart->uart_base, USART_WL_8BIT);
usart_word_length_set(usart->usart_base, USART_WL_8BIT);
break;
case DATA_BITS_9:
usart_word_length_set(usart->uart_base, USART_WL_9BIT);
usart_word_length_set(usart->usart_base, USART_WL_9BIT);
break;
default:
usart_word_length_set(usart->uart_base, USART_WL_8BIT);
usart_word_length_set(usart->usart_base, USART_WL_8BIT);
break;
}
switch (cfg->stop_bits)
{
switch (cfg->stop_bits) {
case STOP_BITS_1:
usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
usart_stop_bit_set(usart->usart_base, USART_STB_1BIT);
break;
case STOP_BITS_2:
usart_stop_bit_set(usart->uart_base, USART_STB_2BIT);
usart_stop_bit_set(usart->usart_base, USART_STB_2BIT);
break;
default:
usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
usart_stop_bit_set(usart->usart_base, USART_STB_1BIT);
break;
}
switch (cfg->parity)
{
switch (cfg->parity) {
case PARITY_NONE:
usart_parity_config(usart->uart_base, USART_PM_NONE);
usart_parity_config(usart->usart_base, USART_PM_NONE);
break;
case PARITY_ODD:
usart_parity_config(usart->uart_base, USART_PM_ODD);
usart_parity_config(usart->usart_base, USART_PM_ODD);
break;
case PARITY_EVEN:
usart_parity_config(usart->uart_base, USART_PM_EVEN);
usart_parity_config(usart->usart_base, USART_PM_EVEN);
break;
default:
usart_parity_config(usart->uart_base, USART_PM_NONE);
usart_parity_config(usart->usart_base, USART_PM_NONE);
break;
}
usart_hardware_flow_rts_config(usart->uart_base, USART_RTS_DISABLE);
usart_hardware_flow_cts_config(usart->uart_base, USART_CTS_DISABLE);
usart_receive_config(usart->uart_base, USART_RECEIVE_ENABLE);
usart_transmit_config(usart->uart_base, USART_TRANSMIT_ENABLE);
usart_enable(usart->uart_base);
usart_hardware_flow_rts_config(usart->usart_base, USART_RTS_DISABLE);
usart_hardware_flow_cts_config(usart->usart_base, USART_RTS_DISABLE);
usart_receive_config(usart->usart_base, USART_RECEIVE_ENABLE);
usart_transmit_config(usart->usart_base, USART_TRANSMIT_ENABLE);
usart_enable(usart->usart_base);
return RT_EOK;
}
static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd,
void *arg)
{
struct gd32_uart *usart_obj;
struct gd32_uart_config *usart;
void *arg) {
struct gd32_usart *usart;
RT_ASSERT(serial != RT_NULL);
usart_obj = (struct gd32_uart *) serial->parent.user_data;
usart = usart_obj->config;
usart = (struct gd32_usart *) serial->parent.user_data;
RT_ASSERT(usart != RT_NULL);
switch (cmd)
{
switch (cmd) {
case RT_DEVICE_CTRL_CLR_INT:
ECLIC_DisableIRQ(usart->irqn);
usart_interrupt_disable(usart->uart_base, USART_INT_RBNE);
eclic_irq_disable(usart->usart_base);
usart_interrupt_disable(usart->usart_base, USART_INT_RBNE);
break;
case RT_DEVICE_CTRL_SET_INT:
ECLIC_EnableIRQ(usart->irqn);
// eclic_set_nlbits(3);
eclic_irq_enable(usart->irqn, 1, 0);
/* enable USART0 receive interrupt */
usart_interrupt_enable(usart->uart_base, USART_INT_RBNE);
usart_interrupt_enable(usart->usart_base, USART_INT_RBNE);
break;
}
return RT_EOK;
}
static int gd32_putc(struct rt_serial_device *serial, char ch)
{
struct gd32_uart *usart_obj;
struct gd32_uart_config *usart;
static int gd32_putc(struct rt_serial_device *serial, char ch) {
struct gd32_usart *usart;
RT_ASSERT(serial != RT_NULL);
usart_obj = (struct gd32_uart *) serial->parent.user_data;
usart = usart_obj->config;
usart = (struct gd32_usart *) serial->parent.user_data;
RT_ASSERT(usart != RT_NULL);
usart_data_transmit(usart->uart_base, (uint8_t) ch);
while (usart_flag_get(usart->uart_base, USART_FLAG_TBE) == RESET);
usart_data_transmit(usart->usart_base, (uint8_t) ch);
while (usart_flag_get(usart->usart_base, USART_FLAG_TBE) == RESET)
;
return 1;
}
static int gd32_getc(struct rt_serial_device *serial)
{
static int gd32_getc(struct rt_serial_device *serial) {
int ch;
struct gd32_uart *usart_obj;
struct gd32_uart_config *usart;
struct gd32_usart *usart;
RT_ASSERT(serial != RT_NULL);
usart_obj = (struct gd32_uart *) serial->parent.user_data;
usart = usart_obj->config;
usart = (struct gd32_usart *) serial->parent.user_data;
RT_ASSERT(usart != RT_NULL);
ch = -1;
if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))
{
ch = usart_data_receive(usart->uart_base) & 0xff;
if (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE)) {
ch = usart_data_receive(usart->usart_base) & 0xff;
}
return ch;
}
static const struct rt_uart_ops gd32_uart_ops = { gd32_configure, gd32_control,
gd32_putc, gd32_getc,
RT_NULL
};
static const struct rt_uart_ops gd32_usart_ops = { gd32_configure, gd32_control,
gd32_putc, gd32_getc,
RT_NULL };
static void usart_isr(struct rt_serial_device *serial)
{
struct gd32_uart *usart_obj;
struct gd32_uart_config *usart;
static void usart_isr(struct rt_serial_device *serial) {
struct gd32_usart *usart;
RT_ASSERT(serial != RT_NULL);
usart_obj = (struct gd32_uart *) serial->parent.user_data;
usart = usart_obj->config;
usart = (struct gd32_usart *) serial->parent.user_data;
RT_ASSERT(usart != RT_NULL);
if ((usart_interrupt_flag_get(usart->uart_base, USART_INT_FLAG_RBNE)
if ((usart_interrupt_flag_get(usart->usart_base, USART_INT_FLAG_RBNE)
!= RESET)
&& (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)))
{
&& (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE))) {
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
usart_interrupt_flag_clear(usart->uart_base, USART_INT_FLAG_RBNE);
usart_flag_clear(usart->uart_base, USART_FLAG_RBNE);
}
else
{
if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET)
{
usart_flag_clear(usart->uart_base, USART_FLAG_CTSF);
usart_interrupt_flag_clear(usart->usart_base, USART_INT_FLAG_RBNE);
usart_flag_clear(usart->usart_base, USART_FLAG_RBNE);
} else {
if (usart_flag_get(usart->usart_base, USART_FLAG_CTSF) != RESET) {
usart_flag_clear(usart->usart_base, USART_FLAG_CTSF);
}
if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET)
{
usart_flag_clear(usart->uart_base, USART_FLAG_LBDF);
if (usart_flag_get(usart->usart_base, USART_FLAG_LBDF) != RESET) {
usart_flag_clear(usart->usart_base, USART_FLAG_LBDF);
}
if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET)
{
usart_flag_clear(usart->uart_base, USART_FLAG_TC);
if (usart_flag_get(usart->usart_base, USART_FLAG_TC) != RESET) {
usart_flag_clear(usart->usart_base, USART_FLAG_TC);
}
}
}
#ifdef BSP_USING_UART0
void USART0_IRQHandler(void)
{
void USART0_IRQHandler(void) {
rt_interrupt_enter();
usart_isr(&uart_obj[GDUART0_INDEX].serial);
usart_isr(&usart_config[GDUSART0_INDEX].serial);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART1
void USART1_IRQHandler(void)
{
rt_interrupt_enter();
usart_isr(&uart_obj[GDUART1_INDEX].serial);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART2
void USART2_IRQHandler(void)
{
rt_interrupt_enter();
usart_isr(&uart_obj[GDUART2_INDEX].serial);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART3
void UART3_IRQHandler(void)
{
rt_interrupt_enter();
usart_isr(&uart_obj[GDUART3_INDEX].serial);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART4
void UART4_IRQHandler(void)
{
rt_interrupt_enter();
usart_isr(&uart_obj[GDUART4_INDEX].serial);
rt_interrupt_leave();
}
#endif
int rt_hw_usart_init(void)
{
int rt_hw_usart_init(void) {
rt_size_t obj_num;
int index;
#ifdef BSP_USING_UART0
rcu_periph_clock_enable(RCU_USART0);
#endif
#ifdef BSP_USING_UART1
rcu_periph_clock_enable(RCU_USART1);
#endif
#ifdef BSP_USING_UART2
rcu_periph_clock_enable(RCU_USART2);
#endif
#ifdef BSP_USING_UART3
rcu_periph_clock_enable(RCU_UART3);
#endif
#ifdef BSP_USING_UART4
rcu_periph_clock_enable(RCU_UART4);
#endif
obj_num = sizeof(uart_obj) / sizeof(struct gd32_uart);
obj_num = sizeof(usart_config) / sizeof(struct gd32_usart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
for (index = 0; index < obj_num; index++)
{
/* init UART object */
uart_obj[index].config = &uart_config[index];
uart_obj[index].serial.ops = &gd32_uart_ops;
uart_obj[index].serial.config = config;
for (index = 0; index < obj_num; index++) {
usart_config[index].serial.ops = &gd32_usart_ops;
usart_config[index].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[index].serial,
uart_obj[index].config->name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX, &uart_obj[index]);
result = rt_hw_serial_register(&usart_config[index].serial,
usart_config[index].name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX, &usart_config[index]);
RT_ASSERT(result == RT_EOK);
}
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
+1 -25
View File
@@ -1,33 +1,9 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-15 hqfang first version
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <drv_config.h>
/* gd32 config class */
struct gd32_uart_config
{
const char *name;
uint32_t uart_base;
IRQn_Type irqn;
};
/* gd32 uart dirver class */
struct gd32_uart
{
struct rt_serial_device serial;
struct gd32_uart_config *config;
};
#include "board.h"
int rt_hw_usart_init(void);
bsp/nuclei/nuclei_fpga_eval/README.md
+14 -1
View File
@@ -73,14 +73,27 @@ export PATH=~/NucleiStudio/toolchain/gcc/bin:~/NucleiStudio/toolchain/openocd/bi
**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包，修改链接脚本。
```c
.stack ORIGIN(RAM) + LENGTH(RAM) - __TOT_STACK_SIZE (NOLOAD) :
{
...
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = . );//在链接脚本中补充该条语句
} >RAM AT>RAM
```
2. **可选**: 运行 ``menuconfig``来进行内核配置
3. 运行 ``scons -c``清理之前的编译结果
4. 根据你当前评估的Nuclei RISC-V内核情况，修改 ``rtconfig.py``中的``NUCLEI_SDK_CORE``和``NUCLEI_SDK_DOWNLOAD``参数。
- ``NUCLEI_SDK_CORE``可选的参数为[Supported Nuclei Cores](https://doc.nucleisys.com/nuclei_sdk/develop/buildsystem.html#core)
- ``NUCLEI_SDK_DOWNLOAD``可选的参数为``ilm``,``flash``或者``flashxip``, 关于该选项的说明参见[Supported Download Modes](https://doc.nucleisys.com/nuclei_sdk/develop/buildsystem.html#download)
- 假设你手头拿到的Nuclei评估处理器内核为N307(rv32imafc), 想程序运行模式为``flash``,
则修改``NUCLEI_SDK_CORE``为``n307``, ``NUCLEI_SDK_DOWNLOAD``为``flash``.
5. 修改完对应的``rtconfig.py``参数配置并保存后，运行 ``scons``来进行代码的编译
### 下载程序
bsp/nuclei/nuclei_fpga_eval/board/board.c
+43 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -14,6 +14,9 @@
#include "board.h"
#include "cpuport.h"
#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
#define RT_KERNEL_INTERRUPT_LEVEL 1
#ifdef RT_USING_SERIAL
#include <drv_uart.h>
#endif
@@ -32,6 +35,45 @@ extern void *_heap_end;
*/
extern void _init(void);
rt_weak void rt_hw_ticksetup(void)
{
uint64_t ticks = SYSTICK_TICK_CONST;
/* Make SWI and SysTick the lowest priority interrupts. */
/* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
SysTick_Config(ticks);
ECLIC_DisableIRQ(SysTimer_IRQn);
ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
ECLIC_EnableIRQ(SysTimer_IRQn);
/* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_EnableIRQ(SysTimerSW_IRQn);
}
#define SysTick_Handler eclic_mtip_handler
/**
* @brief This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* Reload systimer */
SysTick_Reload(SYSTICK_TICK_CONST);
/* enter interrupt */
rt_interrupt_enter();
/* tick increase */
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* @brief Setup hardware board for rt-thread
*
bsp/nuclei/nuclei_fpga_eval/rtconfig.py
+3 -2
View File
@@ -12,9 +12,9 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
if platform.system().lower() == "windows":
EXEC_PATH = 'D:/NucleiStudio/toolchain/gcc/bin'
EXEC_PATH = r'/NucleiStudio/toolchain/gcc/bin'
else:
EXEC_PATH = '~/NucleiStudio/toolchain/gcc/bin'
EXEC_PATH = r'~/NucleiStudio/toolchain/gcc/bin'
if os.path.exists(EXEC_PATH) == False:
print("Warning: Toolchain path %s doesn't exist, assume it is already in PATH" % EXEC_PATH)
EXEC_PATH = '' # Don't set path if not exist
@@ -56,6 +56,7 @@ if PLATFORM == 'gcc':
CPATH = ''
LPATH = ''
LIBS = ['stdc++']
AFLAGS += ' -D"irq_entry=SW_handler" '
if BUILD == 'debug':
CFLAGS += ' -O2 -ggdb'
bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S
+38 -36
View File
@@ -30,38 +30,38 @@
.section .vectors, "ax"
.option norvc;
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
// reset vector
jal x0, Reset_Handler
@@ -97,6 +97,8 @@ Reset_Handler:
# Enable global interrupt. */
# csrsi mstatus, 8
la t0, __stack
csrw mscratch,t0
jal entry
ebreak
@@ -182,16 +184,16 @@ end_except:
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
.weak SW_handler
.type SW_handler, %function
SW_handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.size SW_handler, . - SW_handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S
+36 -36
View File
@@ -29,38 +29,38 @@
.section .vectors, "ax"
.option norvc;
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
// reset vector
jal x0, Reset_Handler
@@ -181,16 +181,16 @@ end_except:
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
.weak SW_handler
.type SW_handler, %function
SW_handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.size SW_handler, . - SW_handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/startup_ch32v30x.S
-6
View File
@@ -379,13 +379,7 @@ handle_reset:
ori t0, t0, 3
csrw mtvec, t0
la t0, _eusrstack
addi t0, t0, -512
csrw mscratch,t0
jal SystemInit
la t0, entry
csrw mepc, t0
mret

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