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[libcpu][riscv]整合libcpu/riscv中的移植文件 提供一份公共代码于common (#6941)

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整合libcpu/riscv中的移植文件 提供一份公共代码于common

在提交本pr时，除hpmicro的内核，rv32内核bsp已完成去除大部分的冗余，大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件，从而提供一份公用代码，新移植的RV32内核的BSP可以全部使用common代码。

- 在common中提供一份公用文件：interrupt_gcc.S
- 修改原有的文件，将原有的中断中上下文切换代码替换为interrupt_gcc.S
- 基于上述修改，修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等)
- 在common中提供一份公用文件：trap_common.c；提供统一中断入口函数，中断入口函数初始化，中断入口注册等函数，并完善异常时的信息输出

- 在common中提供一份公用文件：rt_hw_stack_frame.h；将栈帧结构体剥离，供用户使用

- 在上述工作完成后，在上述工作的基础上测试仓库中risc-v内核的BSP

- 完善函数中的命名，完善中断栈的获取

- 提供一份详细的基于现有common文件的移植指南

  #### 在什么测试环境下测试通过 

- 1.CH32V307V-R1-R0
- 2.CH32V208W-R0-1V4
- 3.HPM6750EVKMINI
- 4.GD32VF103V-EVAL
- 5.qemu(CORE-V-MCU )

> 与上述开发板使用同样芯片的BSP均测试通过

在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试，测试过程系统运行正常。
This commit is contained in:
Yaochenger
2023-03-01 01:32:43 -05:00
committed by GitHub
parent 4021b82161
commit b9e4fcfc68
86 changed files with 1381 additions and 2689 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/.ignore_format.yml
+8
View File
@@ -0,0 +1,8 @@
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- core-v-mcu.c
- crt0.S
- vectors.S
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/core-v-mcu.c
+165 -162
View File
File diff suppressed because it is too large Load Diff
bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/vectors.S
+33 -33
View File
@@ -19,7 +19,7 @@
* Date Author Notes
* 2022-12-08 WangShun Remove FreeRTOS related code and add RT-Thread code
*/
.extern IRQ_Handler
.extern SW_handler
#ifdef PULP_FREERTOS_VECTORED_CONTEXT_SWITCH
.extern freertos_risc_v_ctxt_handler
#endif
@@ -30,38 +30,38 @@
.section .vectors, "ax"
.option norvc
vector_table:
j IRQ_Handler // irq0
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // irq3
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler //ctxt_handler // irq 7 mtime or timer
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ_Handler
j IRQ_Handler // irq 11 Machine (event Fifo)
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler
j IRQ_Handler // IRQ16
j IRQ_Handler // IRQ17
j IRQ_Handler // IRQ18
j IRQ_Handler // IRQ19
j IRQ_Handler // IRQ20
j IRQ_Handler // IRQ21
j IRQ_Handler // IRQ22
j IRQ_Handler // IRQ23
j IRQ_Handler // IRQ24
j IRQ_Handler // IRQ25
j IRQ_Handler // IRQ26
j IRQ_Handler // IRQ27
j IRQ_Handler // IRQ28
j IRQ_Handler // IRQ29
j IRQ_Handler // IRQ30
j IRQ_Handler // IRQ30
j SW_handler // irq0
j SW_handler
j SW_handler
j SW_handler // irq3
j SW_handler
j SW_handler
j SW_handler
j SW_handler //ctxt_handler // irq 7 mtime or timer
j SW_handler
j SW_handler
j SW_handler // SW_handler
j SW_handler // irq 11 Machine (event Fifo)
j SW_handler
j SW_handler
j SW_handler
j SW_handler
j SW_handler // IRQ16
j SW_handler // IRQ17
j SW_handler // IRQ18
j SW_handler // IRQ19
j SW_handler // IRQ20
j SW_handler // IRQ21
j SW_handler // IRQ22
j SW_handler // IRQ23
j SW_handler // IRQ24
j SW_handler // IRQ25
j SW_handler // IRQ26
j SW_handler // IRQ27
j SW_handler // IRQ28
j SW_handler // IRQ29
j SW_handler // IRQ30
j SW_handler // IRQ30
/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the
new vector table (which is at mtvec) */
bsp/core-v-mcu/core-v-cv32e40p/board/linker_scripts/core-v-mcu.ld
+1
View File
@@ -342,6 +342,7 @@ SECTIONS
__stack_bottom = .;
. += __stack_size;
__stack_top = .;
PROVIDE( __rt_rvstack = . );
__freertos_irq_stack_top = .; /* sytem stack */
stack = .;
} > L2
bsp/core-v-mcu/core-v-cv32e40p/rtconfig.py
+2 -2
View File
@@ -17,8 +17,8 @@ else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
#if os.getenv('RTT_EXEC_PATH'):
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = 'release'
bsp/gd32/risc-v/gd32vf103r-start/rtconfig.py
+2 -2
View File
@@ -22,8 +22,8 @@ else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
#if os.getenv('RTT_EXEC_PATH'):
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
CORE = 'risc-v'
BUILD = 'debug'
bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/GD32VF103xB.lds
+1
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@@ -195,5 +195,6 @@ SECTIONS
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = .);
} >ram AT>ram
}
bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/RISCV/env_Eclipse/start.S
+1 -2
View File
@@ -187,7 +187,7 @@ _start0800:
csrw CSR_MTVT, t0
/* Intial the mtvt2 and enable it*/
la t0, irq_entry
la t0, SW_handler
csrw CSR_MTVT2, t0
csrs CSR_MTVT2, 0x1
@@ -236,7 +236,6 @@ _start0800:
call atexit
call __libc_init_array
/* argc = argv = 0 */
li a0, 0
li a1, 0
bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds
+1
View File
@@ -195,5 +195,6 @@ SECTIONS
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = .);
} >ram AT>ram
}
bsp/hifive1/drivers/interrupt.c
+1 -1
View File
@@ -51,7 +51,7 @@ void rt_hw_interrupt_init(void)
/* config interrupt vector*/
asm volatile(
"la t0, trap_entry\n"
"la t0, SW_handler\n"
"csrw mtvec, t0"
);
bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-hifive1/flash.lds
Vendored
+1
View File
@@ -181,5 +181,6 @@ SECTIONS
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = .);
} >ram AT>ram :ram
}
bsp/hifive1/freedom-e-sdk/bsp/env/freedom-e300-hifive1/init.c
Vendored
+2 -2
View File
@@ -6,7 +6,7 @@
#include "encoding.h"
extern int main(int argc, char** argv);
extern void trap_entry();
extern void SW_handler();
static unsigned long mtime_lo(void)
{
@@ -223,7 +223,7 @@ void _init()
rt_kprintf("core freq at %ld Hz\n", get_cpu_freq());
write_csr(mtvec, &trap_entry);
write_csr(mtvec, &SW_handler);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
bsp/hifive1/freedom-e-sdk/bsp/env/start.S
Vendored
+1 -1
View File
@@ -87,7 +87,7 @@ _start:
#if defined(ENABLE_SMP)
2:
la t0, trap_entry
la t0, SW_handler
csrw mtvec, t0
csrr a0, mhartid
bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld
+1
View File
@@ -247,6 +247,7 @@ SECTIONS
. += STACK_SIZE;
. = ALIGN(8);
PROVIDE (_stack = .);
PROVIDE( __rt_rvstack = . );
PROVIDE (_stack_in_dlm = .);
} > AXI_SRAM
bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/start.S
+1 -1
View File
@@ -46,7 +46,7 @@ _start:
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
bsp/hpmicro/hpm6750evk/startup/HPM6360/toolchains/gcc/vectors.S
+1 -1
View File
@@ -11,7 +11,7 @@
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evk/startup/HPM6360/trap.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S
+1 -2
View File
@@ -45,10 +45,9 @@ _start:
/* Disable Vector mode */
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
/* System reset handler */
call reset_handler
bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/vectors.S
+1 -1
View File
@@ -9,7 +9,7 @@
.align 9
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evk/startup/HPM6750/trap.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld
+1
View File
@@ -247,6 +247,7 @@ SECTIONS
. += STACK_SIZE;
. = ALIGN(8);
PROVIDE (_stack = .);
PROVIDE( __rt_rvstack = . );
PROVIDE (_stack_in_dlm = .);
} > AXI_SRAM
bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/start.S
+1 -1
View File
@@ -46,7 +46,7 @@ _start:
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
bsp/hpmicro/hpm6750evkmini/startup/HPM6360/toolchains/gcc/vectors.S
+1 -1
View File
@@ -11,7 +11,7 @@
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evkmini/startup/HPM6360/trap.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S
+1 -2
View File
@@ -45,10 +45,9 @@ _start:
/* Disable Vector mode */
csrci CSR_MMISC_CTL, 2
/* Initialize trap_entry base */
la t0, irq_handler_trap
la t0, SW_handler
csrw mtvec, t0
/* System reset handler */
call reset_handler
bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/vectors.S
+1 -1
View File
@@ -9,7 +9,7 @@
.align 9
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/hpm6750evkmini/startup/HPM6750/trap.c
+1 -1
View File
@@ -7,7 +7,7 @@
#include "hpm_common.h"
#include "hpm_soc.h"
#include <rtthread.h>
#include "riscv-stackframe.h"
#include "rt_hw_stack_frame.h"
#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned
#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/gcc/start.S
+1 -1
View File
@@ -52,7 +52,7 @@ _start:
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#define HANDLER_S_TRAP irq_handler_s_trap
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s
+1 -1
View File
@@ -224,7 +224,7 @@ MARK_FUNC __SEGGER_init_done
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#define HANDLER_S_TRAP irq_handler_s_trap
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/trap.c
+3 -3
View File
@@ -100,11 +100,11 @@ __attribute__((weak)) void mchtmr_s_isr(void)
}
#ifndef CONFIG_FREERTOS
void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
void SW_handler(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
#else
void irq_handler_trap(void) __attribute__ ((section(".isr_vector")));
void SW_handler(void) __attribute__ ((section(".isr_vector")));
#endif
void irq_handler_trap(void)
void SW_handler(void)
{
long mcause = read_csr(CSR_MCAUSE);
long mepc = read_csr(CSR_MEPC);
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/vectors.h
+1 -1
View File
@@ -22,7 +22,7 @@ default_irq_handler:
__vector_table:
.weak default_isr_trap
.set default_isr_trap, irq_handler_trap
.set default_isr_trap, SW_handler
.long default_isr_trap
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/gcc/start.S
+1 -1
View File
@@ -52,7 +52,7 @@ _start:
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
#endif
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s
+1 -1
View File
@@ -224,7 +224,7 @@ MARK_FUNC __SEGGER_init_done
#endif
#ifndef CONFIG_FREERTOS
#define HANDLER_TRAP irq_handler_trap
#define HANDLER_TRAP SW_handler
#else
#define HANDLER_TRAP freertos_risc_v_trap_handler
#endif
bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/trap.c
+3 -3
View File
@@ -89,11 +89,11 @@ __attribute__((weak)) long exception_handler(long cause, long epc)
}
#ifndef CONFIG_FREERTOS
void irq_handler_trap(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
void SW_handler(void) __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)));
#else
void irq_handler_trap(void) __attribute__ ((section(".isr_vector")));
void SW_handler(void) __attribute__ ((section(".isr_vector")));
#endif
void irq_handler_trap(void)
void SW_handler(void)
{
long mcause = read_csr(CSR_MCAUSE);
long mepc = read_csr(CSR_MEPC);
bsp/k210/link.lds
+1
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@@ -128,6 +128,7 @@ SECTIONS
. += __STACKSIZE__;
__stack_cpu0 = .;
PROVIDE( __rt_rvstack = .);
. += __STACKSIZE__;
__stack_cpu1 = .;
bsp/nuclei/gd32vf103_rvstar/.config
+299 -74
View File
File diff suppressed because it is too large Load Diff
bsp/nuclei/gd32vf103_rvstar/README.md
+13 -1
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@@ -64,9 +64,21 @@ export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包,修改链接脚本。
```c
.stack ORIGIN(RAM) + LENGTH(RAM) - __TOT_STACK_SIZE (NOLOAD) :
{
...
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = . );//在链接脚本中补充该条语句
} >RAM AT>RAM
```
2. **可选**: 运行 ``menuconfig``来进行内核配置
3. 运行 ``scons -c``清理之前的编译结果
4. 运行 ``scons``来进行代码的编译
### 下载程序
bsp/nuclei/gd32vf103_rvstar/applications/main.c
+2 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -16,4 +16,4 @@ int main(int argc, char *argv[])
return RT_EOK;
}
/******************** end of file *******************/
/******************** end of file *******************/
bsp/nuclei/gd32vf103_rvstar/board/board.c
+43 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -12,7 +12,9 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "cpuport.h"
#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
#define RT_KERNEL_INTERRUPT_LEVEL 1
#ifdef RT_USING_SERIAL
#include <drv_usart.h>
@@ -122,6 +124,45 @@ void rt_hw_drivers_init(void)
#endif
}
rt_weak void rt_hw_ticksetup(void)
{
uint64_t ticks = SYSTICK_TICK_CONST;
/* Make SWI and SysTick the lowest priority interrupts. */
/* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
SysTick_Config(ticks);
ECLIC_DisableIRQ(SysTimer_IRQn);
ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
ECLIC_EnableIRQ(SysTimer_IRQn);
/* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_EnableIRQ(SysTimerSW_IRQn);
}
#define SysTick_Handler eclic_mtip_handler
/**
* @brief This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* Reload systimer */
SysTick_Reload(SYSTICK_TICK_CONST);
/* enter interrupt */
rt_interrupt_enter();
/* tick increase */
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* @brief Setup hardware board for rt-thread
*
@@ -158,4 +199,3 @@ void rt_hw_board_init(void)
}
/******************** end of file *******************/
bsp/nuclei/gd32vf103_rvstar/board/board.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
bsp/nuclei/gd32vf103_rvstar/rtconfig.h
+39 -8
View File
@@ -23,10 +23,6 @@
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_INIT_CONFIG
#define RT_DEBUG_INIT 1
/* Inter-Thread communication */
@@ -38,6 +34,7 @@
/* Memory Management */
#define RT_PAGE_MAX_ORDER 11
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
@@ -49,7 +46,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart4"
#define RT_VER_NUM 0x40101
#define RT_VER_NUM 0x50000
#define ARCH_RISCV
#define ARCH_RISCV32
@@ -76,6 +73,7 @@
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
@@ -166,6 +164,11 @@
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
@@ -178,6 +181,9 @@
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
@@ -188,15 +194,39 @@
/* entertainment: terminal games and other interesting software packages */
/* Privated Packages of RealThread */
/* Arduino libraries */
/* Network Utilities */
/* Projects */
/* RT-Thread Smart */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers Config */
#define SOC_GD32VF103V
@@ -208,6 +238,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_USING_UART4
/* Board extended module Drivers */
bsp/nuclei/gd32vf103_rvstar/rtconfig.py
+2 -1
View File
@@ -13,7 +13,7 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'D:/Software/Nuclei/gcc/bin'
EXEC_PATH = r'D:/Software/Nuclei/gcc/bin'
else:
print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
@@ -50,6 +50,7 @@ if PLATFORM == 'gcc':
CPATH = ''
LPATH = ''
LIBS = ['stdc++']
AFLAGS += ' -I. '+ ' -D"irq_entry=SW_handler" '
if BUILD == 'debug':
CFLAGS += ' -O2 -Os -ggdb'
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
+108 -225
View File
File diff suppressed because it is too large Load Diff
bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
+1 -25
View File
@@ -1,33 +1,9 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-15 hqfang first version
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <drv_config.h>
/* gd32 config class */
struct gd32_uart_config
{
const char *name;
uint32_t uart_base;
IRQn_Type irqn;
};
/* gd32 uart dirver class */
struct gd32_uart
{
struct rt_serial_device serial;
struct gd32_uart_config *config;
};
#include "board.h"
int rt_hw_usart_init(void);
bsp/nuclei/nuclei_fpga_eval/README.md
+14 -1
View File
@@ -73,14 +73,27 @@ export PATH=~/NucleiStudio/toolchain/gcc/bin:~/NucleiStudio/toolchain/openocd/bi
**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包，修改链接脚本。
```c
.stack ORIGIN(RAM) + LENGTH(RAM) - __TOT_STACK_SIZE (NOLOAD) :
{
...
PROVIDE( _sp = . );
PROVIDE( __rt_rvstack = . );//在链接脚本中补充该条语句
} >RAM AT>RAM
```
2. **可选**: 运行 ``menuconfig``来进行内核配置
3. 运行 ``scons -c``清理之前的编译结果
4. 根据你当前评估的Nuclei RISC-V内核情况，修改 ``rtconfig.py``中的``NUCLEI_SDK_CORE``和``NUCLEI_SDK_DOWNLOAD``参数。
- ``NUCLEI_SDK_CORE``可选的参数为[Supported Nuclei Cores](https://doc.nucleisys.com/nuclei_sdk/develop/buildsystem.html#core)
- ``NUCLEI_SDK_DOWNLOAD``可选的参数为``ilm``,``flash``或者``flashxip``, 关于该选项的说明参见[Supported Download Modes](https://doc.nucleisys.com/nuclei_sdk/develop/buildsystem.html#download)
- 假设你手头拿到的Nuclei评估处理器内核为N307(rv32imafc), 想程序运行模式为``flash``,
则修改``NUCLEI_SDK_CORE``为``n307``, ``NUCLEI_SDK_DOWNLOAD``为``flash``.
5. 修改完对应的``rtconfig.py``参数配置并保存后，运行 ``scons``来进行代码的编译
### 下载程序
bsp/nuclei/nuclei_fpga_eval/board/board.c
+43 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -14,6 +14,9 @@
#include "board.h"
#include "cpuport.h"
#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
#define RT_KERNEL_INTERRUPT_LEVEL 1
#ifdef RT_USING_SERIAL
#include <drv_uart.h>
#endif
@@ -32,6 +35,45 @@ extern void *_heap_end;
*/
extern void _init(void);
rt_weak void rt_hw_ticksetup(void)
{
uint64_t ticks = SYSTICK_TICK_CONST;
/* Make SWI and SysTick the lowest priority interrupts. */
/* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
SysTick_Config(ticks);
ECLIC_DisableIRQ(SysTimer_IRQn);
ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
ECLIC_EnableIRQ(SysTimer_IRQn);
/* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
ECLIC_EnableIRQ(SysTimerSW_IRQn);
}
#define SysTick_Handler eclic_mtip_handler
/**
* @brief This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* Reload systimer */
SysTick_Reload(SYSTICK_TICK_CONST);
/* enter interrupt */
rt_interrupt_enter();
/* tick increase */
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* @brief Setup hardware board for rt-thread
*
bsp/nuclei/nuclei_fpga_eval/rtconfig.py
+3 -2
View File
@@ -12,9 +12,9 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
if platform.system().lower() == "windows":
EXEC_PATH = 'D:/NucleiStudio/toolchain/gcc/bin'
EXEC_PATH = r'/NucleiStudio/toolchain/gcc/bin'
else:
EXEC_PATH = '~/NucleiStudio/toolchain/gcc/bin'
EXEC_PATH = r'~/NucleiStudio/toolchain/gcc/bin'
if os.path.exists(EXEC_PATH) == False:
print("Warning: Toolchain path %s doesn't exist, assume it is already in PATH" % EXEC_PATH)
EXEC_PATH = '' # Don't set path if not exist
@@ -56,6 +56,7 @@ if PLATFORM == 'gcc':
CPATH = ''
LPATH = ''
LIBS = ['stdc++']
AFLAGS += ' -D"irq_entry=SW_handler" '
if BUILD == 'debug':
CFLAGS += ' -O2 -ggdb'
bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S
+38 -36
View File
@@ -30,38 +30,38 @@
.section .vectors, "ax"
.option norvc;
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
// reset vector
jal x0, Reset_Handler
@@ -97,6 +97,8 @@ Reset_Handler:
# Enable global interrupt. */
# csrsi mstatus, 8
la t0, __stack
csrw mscratch,t0
jal entry
ebreak
@@ -182,16 +184,16 @@ end_except:
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
.weak SW_handler
.type SW_handler, %function
SW_handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.size SW_handler, . - SW_handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S
+36 -36
View File
@@ -29,38 +29,38 @@
.section .vectors, "ax"
.option norvc;
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, IRQ_Handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
jal x0, SW_handler
// reset vector
jal x0, Reset_Handler
@@ -181,16 +181,16 @@ end_except:
addi x2, x2, EXCEPTION_STACK_SIZE
mret
.weak IRQ_Handler
.type IRQ_Handler, %function
IRQ_Handler:
.weak SW_handler
.type SW_handler, %function
SW_handler:
addi x2, x2, -EXCEPTION_STACK_SIZE
sw x1, 0x54(x2)
jal x1, store_regs
la x1, end_except
csrr a0, mcause
jal x0, SystemIrqHandler
.size IRQ_Handler, . - IRQ_Handler
.size SW_handler, . - SW_handler
.macro define_exception_entry entry_name handler_name
.weak \entry_name
bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/startup_ch32v30x.S
-6
View File
@@ -379,13 +379,7 @@ handle_reset:
ori t0, t0, 3
csrw mtvec, t0
la t0, _eusrstack
addi t0, t0, -512
csrw mscratch,t0
jal SystemInit
la t0, entry
csrw mepc, t0
mret
bsp/wch/risc-v/ch32v103r-evt/board/linker_scripts/link.lds
+1
View File
@@ -186,6 +186,7 @@ SECTIONS
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
PROVIDE( __rt_rvstack = .);
} >RAM
}
bsp/wch/risc-v/ch32v103r-evt/rtconfig.py
+2 -2
View File
@@ -15,8 +15,8 @@ else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
# if os.getenv('RTT_EXEC_PATH'):
# EXEC_PATH = os.getenv('RTT_EXEC_PATH')
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = 'release'
bsp/wch/risc-v/ch32v208w-r0/board/linker_scripts/link.lds
+1
View File
@@ -194,6 +194,7 @@ SECTIONS
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
PROVIDE( __rt_rvstack = . );
} >RAM
}
bsp/wch/risc-v/ch32v307v-r1/applications/main.c
+1
View File
@@ -10,6 +10,7 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "ch32v30x.h"
/* defined the LED0 pin: PB5 */
#define LED0_PIN rt_pin_get("PB.5")
bsp/wch/risc-v/ch32v307v-r1/board/linker_scripts/link.lds
+1
View File
@@ -202,6 +202,7 @@ SECTIONS
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
PROVIDE( __rt_rvstack = . );
} >RAM
}
libcpu/risc-v/SConscript
+1 -5
View File
@@ -10,14 +10,10 @@ group = []
list = os.listdir(cwd)
# add common code files
if rtconfig.CPU == "nuclei" :
group = group
elif rtconfig.CPU == "virt64" :
if rtconfig.CPU == "virt64" :
group = group
elif rtconfig.CPU == "c906" :
group = group
elif rtconfig.CPU == "hpmicro":
group = group
else :
group = group + SConscript(os.path.join('common', 'SConscript'))
libcpu/risc-v/bumblebee/interrupt_gcc.S
-129
View File
@@ -1,129 +0,0 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include "cpuport.h"
.section .text.entry
.align 6 /* In ECLIC mode, the trap entry must be 64bytes aligned */
.global irq_entry
irq_entry:
/* save all from thread context */
addi sp, sp, -32 * REGBYTES
STORE x1, 1 * REGBYTES(sp)
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x5, 5 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
STORE x8, 8 * REGBYTES(sp)
STORE x9, 9 * REGBYTES(sp)
STORE x10, 10 * REGBYTES(sp)
STORE x11, 11 * REGBYTES(sp)
STORE x12, 12 * REGBYTES(sp)
STORE x13, 13 * REGBYTES(sp)
STORE x14, 14 * REGBYTES(sp)
STORE x15, 15 * REGBYTES(sp)
STORE x16, 16 * REGBYTES(sp)
STORE x17, 17 * REGBYTES(sp)
STORE x18, 18 * REGBYTES(sp)
STORE x19, 19 * REGBYTES(sp)
STORE x20, 20 * REGBYTES(sp)
STORE x21, 21 * REGBYTES(sp)
STORE x22, 22 * REGBYTES(sp)
STORE x23, 23 * REGBYTES(sp)
STORE x24, 24 * REGBYTES(sp)
STORE x25, 25 * REGBYTES(sp)
STORE x26, 26 * REGBYTES(sp)
STORE x27, 27 * REGBYTES(sp)
STORE x28, 28 * REGBYTES(sp)
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
move s0, sp
/* switch to interrupt stack */
la sp, _sp
/* interrupt handle */
call rt_interrupt_enter
csrr a0, mcause
csrr a1, mepc
mv a2, sp
csrrw ra, 0x07ED, ra
call rt_interrupt_leave
/* switch to from thread stack */
move sp, s0
/* need to switch new thread */
la s0, rt_thread_switch_interrupt_flag
lw s2, 0(s0)
beqz s2, spurious_interrupt
/* clear switch interrupt flag */
sw zero, 0(s0)
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
la s0, rt_interrupt_from_thread
LOAD s1, 0(s0)
STORE sp, 0(s1)
la s0, rt_interrupt_to_thread
LOAD s1, 0(s0)
LOAD sp, 0(s1)
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
spurious_interrupt:
LOAD x1, 1 * REGBYTES(sp)
/* Remain in M-mode after mret */
li t0, 0x00001800
csrs mstatus, t0
LOAD t0, 2 * REGBYTES(sp)
csrs mstatus, t0
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)
LOAD x6, 6 * REGBYTES(sp)
LOAD x7, 7 * REGBYTES(sp)
LOAD x8, 8 * REGBYTES(sp)
LOAD x9, 9 * REGBYTES(sp)
LOAD x10, 10 * REGBYTES(sp)
LOAD x11, 11 * REGBYTES(sp)
LOAD x12, 12 * REGBYTES(sp)
LOAD x13, 13 * REGBYTES(sp)
LOAD x14, 14 * REGBYTES(sp)
LOAD x15, 15 * REGBYTES(sp)
LOAD x16, 16 * REGBYTES(sp)
LOAD x17, 17 * REGBYTES(sp)
LOAD x18, 18 * REGBYTES(sp)
LOAD x19, 19 * REGBYTES(sp)
LOAD x20, 20 * REGBYTES(sp)
LOAD x21, 21 * REGBYTES(sp)
LOAD x22, 22 * REGBYTES(sp)
LOAD x23, 23 * REGBYTES(sp)
LOAD x24, 24 * REGBYTES(sp)
LOAD x25, 25 * REGBYTES(sp)
LOAD x26, 26 * REGBYTES(sp)
LOAD x27, 27 * REGBYTES(sp)
LOAD x28, 28 * REGBYTES(sp)
LOAD x29, 29 * REGBYTES(sp)
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
mret
libcpu/risc-v/bumblebee/trap_gcc.S
+18
View File
@@ -0,0 +1,18 @@
#include "cpuport.h"
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
addi sp, sp, -4
STORE ra, 0 * REGBYTES(sp)
csrr a0, mcause
csrr a1, mepc
mv a2, sp
csrrw ra, 0x07ED, ra
li t0, 0x08
csrc mstatus, t0
LOAD ra, 0 * REGBYTES(sp)
addi sp, sp, 4
ret
libcpu/risc-v/ch32/SConscript
+2 -7
View File
@@ -2,16 +2,11 @@
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
ASFLAGS = ' -I ' + cwd
if rtconfig.PLATFORM == 'gcc':
src += Glob('*_gcc.S')
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
Return('group')
libcpu/risc-v/ch32/interrupt.h → libcpu/risc-v/ch32/software_irq.c
+6 -34
View File
@@ -8,6 +8,7 @@
* 2021-09-09 WCH the first version
* 2023-01-04 WangShun Remove redundant files
*/
#include "rtconfig.h"
#if defined (SOC_RISCV_SERIES_CH32V1)
#include "ch32v10x.h"
#elif defined (SOC_RISCV_SERIES_CH32V2)
@@ -17,11 +18,7 @@
#else
#error "CH32 architecture doesn't support!"
#endif
/*
* trigger soft interrupt
*/
void sw_setpend(void)
void rt_trigger_software_interrupt(void)
{
/*CH32V103 does not support systick software interrupt*/
#if defined(SOC_RISCV_SERIES_CH32V1)
@@ -31,39 +28,14 @@ void sw_setpend(void)
#endif
}
/*
* clear soft interrupt
*/
void sw_clearpend(void)
void rt_hw_do_after_save_above(void)
{
__asm volatile ("li t0,0x20" );
__asm volatile ("csrs 0x804, t0");
/*CH32V103 does not support systick software interrupt*/
#if defined(SOC_RISCV_SERIES_CH32V1)
NVIC_ClearPendingIRQ(Software_IRQn);
#else
SysTick->CTLR &= ~(1 << 31);
#endif
}
/*
* disable interrupt and save mstatus
*/
rt_weak rt_base_t rt_hw_interrupt_disable(void)
{
rt_base_t value=0;
#if defined(SOC_RISCV_SERIES_CH32V3)
asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x7800));
#else
asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
#endif
return value;
}
/*
* enable interrupt and resume mstatus
*/
rt_weak void rt_hw_interrupt_enable(rt_base_t level)
{
asm("csrw mstatus, %0": :"r"(level));
}
}
libcpu/risc-v/common/context_gcc.S
+5 -2
View File
@@ -46,6 +46,9 @@ rt_hw_interrupt_enable:
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
la t0, __rt_rvstack
csrw mscratch,t0
LOAD sp, (a0)
#ifdef RT_USING_SMP
@@ -214,9 +217,9 @@ rt_hw_context_switch_exit:
LOAD x1, 1 * REGBYTES(sp)
#ifdef ARCH_RISCV_FPU
li t0, 0x00007800
li t0, 0x7800
#else
li t0, 0x00001800
li t0, 0x1800
#endif
csrw mstatus, t0
LOAD a0, 2 * REGBYTES(sp)
libcpu/risc-v/common/cpuport.c
+16 -75
View File
@@ -14,6 +14,7 @@
#include <rtthread.h>
#include "cpuport.h"
#include "rt_hw_stack_frame.h"
#ifndef RT_USING_SMP
volatile rt_ubase_t rt_interrupt_from_thread = 0;
@@ -21,76 +22,6 @@ volatile rt_ubase_t rt_interrupt_to_thread = 0;
volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
#endif
struct rt_hw_stack_frame
{
rt_ubase_t epc; /* epc - epc - program counter */
rt_ubase_t ra; /* x1 - ra - return address for jumps */
rt_ubase_t mstatus; /* - machine status register */
rt_ubase_t gp; /* x3 - gp - global pointer */
rt_ubase_t tp; /* x4 - tp - thread pointer */
rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
rt_ubase_t s1; /* x9 - s1 - saved register 1 */
rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
rt_ubase_t a2; /* x12 - a2 - function argument 2 */
rt_ubase_t a3; /* x13 - a3 - function argument 3 */
rt_ubase_t a4; /* x14 - a4 - function argument 4 */
rt_ubase_t a5; /* x15 - a5 - function argument 5 */
rt_ubase_t a6; /* x16 - a6 - function argument 6 */
rt_ubase_t a7; /* x17 - s7 - function argument 7 */
rt_ubase_t s2; /* x18 - s2 - saved register 2 */
rt_ubase_t s3; /* x19 - s3 - saved register 3 */
rt_ubase_t s4; /* x20 - s4 - saved register 4 */
rt_ubase_t s5; /* x21 - s5 - saved register 5 */
rt_ubase_t s6; /* x22 - s6 - saved register 6 */
rt_ubase_t s7; /* x23 - s7 - saved register 7 */
rt_ubase_t s8; /* x24 - s8 - saved register 8 */
rt_ubase_t s9; /* x25 - s9 - saved register 9 */
rt_ubase_t s10; /* x26 - s10 - saved register 10 */
rt_ubase_t s11; /* x27 - s11 - saved register 11 */
rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
#ifdef ARCH_RISCV_FPU
rv_floatreg_t f0; /* f0 */
rv_floatreg_t f1; /* f1 */
rv_floatreg_t f2; /* f2 */
rv_floatreg_t f3; /* f3 */
rv_floatreg_t f4; /* f4 */
rv_floatreg_t f5; /* f5 */
rv_floatreg_t f6; /* f6 */
rv_floatreg_t f7; /* f7 */
rv_floatreg_t f8; /* f8 */
rv_floatreg_t f9; /* f9 */
rv_floatreg_t f10; /* f10 */
rv_floatreg_t f11; /* f11 */
rv_floatreg_t f12; /* f12 */
rv_floatreg_t f13; /* f13 */
rv_floatreg_t f14; /* f14 */
rv_floatreg_t f15; /* f15 */
rv_floatreg_t f16; /* f16 */
rv_floatreg_t f17; /* f17 */
rv_floatreg_t f18; /* f18 */
rv_floatreg_t f19; /* f19 */
rv_floatreg_t f20; /* f20 */
rv_floatreg_t f21; /* f21 */
rv_floatreg_t f22; /* f22 */
rv_floatreg_t f23; /* f23 */
rv_floatreg_t f24; /* f24 */
rv_floatreg_t f25; /* f25 */
rv_floatreg_t f26; /* f26 */
rv_floatreg_t f27; /* f27 */
rv_floatreg_t f28; /* f28 */
rv_floatreg_t f29; /* f29 */
rv_floatreg_t f30; /* f30 */
rv_floatreg_t f31; /* f31 */
#endif
};
/**
* This function will initialize thread stack
*
@@ -127,14 +58,24 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
/* force to machine mode(MPP=11) and set MPIE to 1 */
#ifdef ARCH_RISCV_FPU
frame->mstatus = 0x00007880;
frame->mstatus = 0x7880;
#else
frame->mstatus = 0x00001880;
frame->mstatus = 0x1880;
#endif
return stk;
}
rt_weak void rt_trigger_software_interrupt(void)
{
while (0);
}
rt_weak void rt_hw_do_after_save_above(void)
{
while (1);
}
/*
* #ifdef RT_USING_SMP
* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
@@ -150,9 +91,9 @@ rt_weak void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_t
rt_interrupt_to_thread = to;
rt_thread_switch_interrupt_flag = 1;
#if defined(SOC_RISCV_FAMILY_CH32)
sw_setpend();
#endif
rt_trigger_software_interrupt();
return ;
}
#endif /* end of RT_USING_SMP */
libcpu/risc-v/common/cpuport.h
+10 -5
View File
@@ -14,11 +14,6 @@
#define CPUPORT_H__
#include <rtconfig.h>
#if !defined(__ASSEMBLY__)
#if defined(SOC_RISCV_FAMILY_CH32)
#include "interrupt.h"
#endif
#endif
#ifndef __ASSEMBLY__
#ifdef RT_USING_SMP
@@ -32,6 +27,15 @@ typedef union {
#endif
#endif
/* Preprocessor Definition */
#if __riscv_flen == 32
#define ARCH_RISCV_FPU_S
#endif
#if __riscv_flen == 64
#define ARCH_RISCV_FPU_D
#endif
/* bytes of register width */
#ifdef ARCH_CPU_64BIT
#define STORE sd
@@ -43,6 +47,7 @@ typedef union {
#define REGBYTES 4
#endif
/* Preprocessor Definition */
#ifdef ARCH_RISCV_FPU
#ifdef ARCH_RISCV_FPU_D
#define FSTORE fsd
libcpu/risc-v/ch32/interrupt_gcc.S → libcpu/risc-v/common/interrupt_gcc.S
+35 -36
View File
@@ -5,17 +5,23 @@
*
* Change Logs:
* Date Author Notes
* 2021-09-09 WCH the first version
* 2022-12-27 WangShun Merge WCH series mcu port files
* 2023/01/17 WangShun The first version
*/
#define __ASSEMBLY__
#include "cpuport.h"
.global SW_handler
.align 2
.section .text.entry, "ax"
#if defined(SOC_SERIES_GD32VF103V)
.align 6
#else
.align 2
#endif
.global SW_handler
SW_handler:
/* save all from thread context */
li t0, 0x08
csrc mstatus, t0
#ifdef ARCH_RISCV_FPU
addi sp, sp, -32 * FREGBYTES
FSTORE f0, 0 * FREGBYTES(sp)
@@ -51,21 +57,13 @@ SW_handler:
FSTORE f30, 30 * FREGBYTES(sp)
FSTORE f31, 31 * FREGBYTES(sp)
#endif
/* save all from thread context */
addi sp, sp, -32 * REGBYTES
STORE x5, 5 * REGBYTES(sp)
/* saved MPIE */
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
/* Temporarily disable HPE */
#if defined (SOC_RISCV_SERIES_CH32V3)
li t0, 0x20
csrs 0x804, t0
#endif
STORE x1, 1 * REGBYTES(sp)
/* Mandatory set the MPIE of mstatus */
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
@@ -95,20 +93,23 @@ SW_handler:
STORE x31, 31 * REGBYTES(sp)
/* switch to interrupt stack */
csrrw sp,mscratch,sp
csrrw sp,mscratch,sp
/* interrupt handle */
call rt_interrupt_enter
/* clear interrupt */
jal sw_clearpend
/* Do the work after saving the above */
jal rt_hw_do_after_save_above
call rt_interrupt_leave
/* switch to from thread stack */
csrrw sp,mscratch,sp
csrrw sp,mscratch,sp
/* if rt_thread_switch_interrupt_flag=1,then clear it */
/* Determine whether to trigger scheduling at the interrupt function */
la s0, rt_thread_switch_interrupt_flag
lw s2, 0(s0)
beqz s2, 1f
/* clear the flag of rt_thread_switch_interrupt_flag */
sw zero, 0(s0)
#1:
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
@@ -123,16 +124,14 @@ SW_handler:
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
1: LOAD x1, 1 * REGBYTES(sp)
#if defined (SOC_RISCV_SERIES_CH32V3)
li t0,0x7800
csrs mstatus, t0
#else
li t0,0x1800
csrs mstatus, t0
#endif
LOAD t0, 2*REGBYTES(sp)
csrs mstatus, t0
1:
LOAD x1, 1 * REGBYTES(sp)
/* Set the mode after MRET */
li t0, 0x1800
csrs mstatus, t0
LOAD t0, 2 * REGBYTES(sp)
csrs mstatus, t0
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)
@@ -162,9 +161,8 @@ SW_handler:
LOAD x29, 29 * REGBYTES(sp)
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
/* load float reg */
addi sp, sp, 32 * REGBYTES
#ifdef ARCH_RISCV_FPU
FLOAD f0, 0 * FREGBYTES(sp)
FLOAD f1, 1 * FREGBYTES(sp)
@@ -198,6 +196,7 @@ SW_handler:
FLOAD f29, 29 * FREGBYTES(sp)
FLOAD f30, 30 * FREGBYTES(sp)
FLOAD f31, 31 * FREGBYTES(sp)
addi sp, sp, 32 * FREGBYTES
#endif
mret
libcpu/risc-v/hpmicro/riscv-stackframe.h → libcpu/risc-v/common/rt_hw_stack_frame.h
-1
View File
@@ -83,5 +83,4 @@ typedef struct rt_hw_stack_frame
#endif
}rt_hw_stack_frame_t;
#endif /* RISCV_STACKFRAME_H */
libcpu/risc-v/common/trap_common.c
+105
View File
@@ -0,0 +1,105 @@
#include <rthw.h>
#include <rtthread.h>
#include "riscv-ops.h"
#include "rt_hw_stack_frame.h"
#define ISR_NUMBER 32
static volatile rt_hw_stack_frame_t *s_stack_frame;
static struct rt_irq_desc rv32irq_table[ISR_NUMBER];
void rt_show_stack_frame(void);
/**
* Temporary interrupt entry function
*
* @param mcause Machine Cause Register
* @return RT_NULL
*/
rt_weak rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t mcause)
{
rt_kprintf("UN-handled interrupt %d occurred!!!\n", mcause);
return RT_NULL;
}
/**
* Interrupt entry function initialization
*/
rt_weak void rt_hw_interrupt_init(void)
{
int idx = 0;
for (idx = 0; idx < ISR_NUMBER; idx++)
{
rv32irq_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
rv32irq_table[idx].param = RT_NULL;
}
}
/**
* Break Entry Function Binding
*
* @param vector interrupt number
* @param handler Break-in function requiring binding
* @param param NULL
* @param name NULL
* @return NULL
*/
rt_weak rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
void *user_param = param;
char *user_name = name;
if(vector < ISR_NUMBER)
{
if (handler != RT_NULL)
{
rv32irq_table[vector].handler = (rt_isr_handler_t)handler;
rv32irq_table[vector].param = param;
}
}
}
/**
* Query and Distribution Entry for Exception and Interrupt Sources
*
* @param mcause Machine Cause Register
*/
rt_weak void rt_rv32_system_irq_handler(rt_uint32_t mcause)
{
rt_uint32_t mscratch = read_csr(0x340);
rt_uint32_t irq_id = (mcause & 0x1F);
rt_uint32_t exception = !(mcause & 0x80000000);
if(exception)
{
s_stack_frame = (rt_hw_stack_frame_t *)mscratch;
rt_show_stack_frame();
}
else
{
rv32irq_table[irq_id].handler(irq_id, rv32irq_table[irq_id].param);
}
}
/**
* Register Print on Exception
*/
rt_weak void rt_show_stack_frame(void)
{
rt_kprintf("Stack frame:\r\n----------------------------------------\r\n");
rt_kprintf("ra : 0x%08x\r\n", s_stack_frame->ra);
rt_kprintf("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus
rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0);
rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1);
rt_kprintf("t2 : 0x%08x\r\n", s_stack_frame->t2);
rt_kprintf("a0 : 0x%08x\r\n", s_stack_frame->a0);
rt_kprintf("a1 : 0x%08x\r\n", s_stack_frame->a1);
rt_kprintf("a2 : 0x%08x\r\n", s_stack_frame->a2);
rt_kprintf("a3 : 0x%08x\r\n", s_stack_frame->a3);
rt_kprintf("a4 : 0x%08x\r\n", s_stack_frame->a4);
rt_kprintf("a5 : 0x%08x\r\n", s_stack_frame->a5);
rt_kprintf("a6 : 0x%08x\r\n", s_stack_frame->a6);
rt_kprintf("a7 : 0x%08x\r\n", s_stack_frame->a7);
rt_kprintf("t3 : 0x%08x\r\n", s_stack_frame->t3);
rt_kprintf("t4 : 0x%08x\r\n", s_stack_frame->t4);
rt_kprintf("t5 : 0x%08x\r\n", s_stack_frame->t5);
rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6);
}
libcpu/risc-v/cv32e40p/interrupt.c
-18
View File
@@ -1,18 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/01 Bernard The first version
*/
#include <rthw.h>
#include <stdint.h>
#include <rtthread.h>
typedef void (*irq_handler_t)(void);
extern const irq_handler_t isr_table[];
extern void vSystemIrqHandler(uint32_t mcause);
libcpu/risc-v/cv32e40p/interrupt_gcc.S
-130
View File
@@ -1,130 +0,0 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/02 Bernard The first version
*/
#include "cpuport.h"
.section .text.entry
.align 2
.global IRQ_Handler
IRQ_Handler:
/* save all from thread context */
addi sp, sp, -32 * REGBYTES
STORE x1, 1 * REGBYTES(sp)
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x5, 5 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
STORE x8, 8 * REGBYTES(sp)
STORE x9, 9 * REGBYTES(sp)
STORE x10, 10 * REGBYTES(sp)
STORE x11, 11 * REGBYTES(sp)
STORE x12, 12 * REGBYTES(sp)
STORE x13, 13 * REGBYTES(sp)
STORE x14, 14 * REGBYTES(sp)
STORE x15, 15 * REGBYTES(sp)
STORE x16, 16 * REGBYTES(sp)
STORE x17, 17 * REGBYTES(sp)
STORE x18, 18 * REGBYTES(sp)
STORE x19, 19 * REGBYTES(sp)
STORE x20, 20 * REGBYTES(sp)
STORE x21, 21 * REGBYTES(sp)
STORE x22, 22 * REGBYTES(sp)
STORE x23, 23 * REGBYTES(sp)
STORE x24, 24 * REGBYTES(sp)
STORE x25, 25 * REGBYTES(sp)
STORE x26, 26 * REGBYTES(sp)
STORE x27, 27 * REGBYTES(sp)
STORE x28, 28 * REGBYTES(sp)
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
move s0, sp
/* switch to interrupt stack */
la sp, __freertos_irq_stack_top
/* interrupt handle */
call rt_interrupt_enter
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call vSystemIrqHandler
call rt_interrupt_leave
/* switch to from thread stack */
move sp, s0
/* need to switch new thread */
la s0, rt_thread_switch_interrupt_flag
lw s2, 0(s0)
beqz s2, spurious_interrupt
/* clear switch interrupt flag */
sw zero, 0(s0)
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
la s0, rt_interrupt_from_thread
LOAD s1, 0(s0)
STORE sp, 0(s1)
la s0, rt_interrupt_to_thread
LOAD s1, 0(s0)
LOAD sp, 0(s1)
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
spurious_interrupt:
LOAD x1, 1 * REGBYTES(sp)
/* Remain in M-mode after mret */
li t0, 0x00001800
csrs mstatus, t0
LOAD t0, 2 * REGBYTES(sp)
csrs mstatus, t0
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)
LOAD x6, 6 * REGBYTES(sp)
LOAD x7, 7 * REGBYTES(sp)
LOAD x8, 8 * REGBYTES(sp)
LOAD x9, 9 * REGBYTES(sp)
LOAD x10, 10 * REGBYTES(sp)
LOAD x11, 11 * REGBYTES(sp)
LOAD x12, 12 * REGBYTES(sp)
LOAD x13, 13 * REGBYTES(sp)
LOAD x14, 14 * REGBYTES(sp)
LOAD x15, 15 * REGBYTES(sp)
LOAD x16, 16 * REGBYTES(sp)
LOAD x17, 17 * REGBYTES(sp)
LOAD x18, 18 * REGBYTES(sp)
LOAD x19, 19 * REGBYTES(sp)
LOAD x20, 20 * REGBYTES(sp)
LOAD x21, 21 * REGBYTES(sp)
LOAD x22, 22 * REGBYTES(sp)
LOAD x23, 23 * REGBYTES(sp)
LOAD x24, 24 * REGBYTES(sp)
LOAD x25, 25 * REGBYTES(sp)
LOAD x26, 26 * REGBYTES(sp)
LOAD x27, 27 * REGBYTES(sp)
LOAD x28, 28 * REGBYTES(sp)
LOAD x29, 29 * REGBYTES(sp)
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
mret
libcpu/risc-v/cv32e40p/trap_gcc.S
+16
View File
@@ -0,0 +1,16 @@
#include "cpuport.h"
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
addi sp, sp, -4
STORE ra, 0 * REGBYTES(sp)
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call rt_rv32_system_irq_handler
LOAD ra, 0 * REGBYTES(sp)
addi sp, sp, 4
ret
libcpu/risc-v/e310/interrupt_gcc.S
-129
View File
@@ -1,129 +0,0 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/02 Bernard The first version
*/
#include "cpuport.h"
.section .text.entry
.align 2
.global trap_entry
trap_entry:
/* save all from thread context */
addi sp, sp, -32 * REGBYTES
STORE x1, 1 * REGBYTES(sp)
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x5, 5 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
STORE x8, 8 * REGBYTES(sp)
STORE x9, 9 * REGBYTES(sp)
STORE x10, 10 * REGBYTES(sp)
STORE x11, 11 * REGBYTES(sp)
STORE x12, 12 * REGBYTES(sp)
STORE x13, 13 * REGBYTES(sp)
STORE x14, 14 * REGBYTES(sp)
STORE x15, 15 * REGBYTES(sp)
STORE x16, 16 * REGBYTES(sp)
STORE x17, 17 * REGBYTES(sp)
STORE x18, 18 * REGBYTES(sp)
STORE x19, 19 * REGBYTES(sp)
STORE x20, 20 * REGBYTES(sp)
STORE x21, 21 * REGBYTES(sp)
STORE x22, 22 * REGBYTES(sp)
STORE x23, 23 * REGBYTES(sp)
STORE x24, 24 * REGBYTES(sp)
STORE x25, 25 * REGBYTES(sp)
STORE x26, 26 * REGBYTES(sp)
STORE x27, 27 * REGBYTES(sp)
STORE x28, 28 * REGBYTES(sp)
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
/* save break thread stack to s0 */
move s0, sp
/* switch to interrupt stack */
la sp, _sp
/* interrupt handle */
call rt_interrupt_enter
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call handle_trap
call rt_interrupt_leave
/* switch to from_thread stack */
move sp, s0
/* need to switch new thread */
la s0, rt_thread_switch_interrupt_flag
lw s2, 0(s0)
beqz s2, spurious_interrupt
sw zero, 0(s0)
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
la s0, rt_interrupt_from_thread
LOAD s1, 0(s0)
STORE sp, 0(s1)
la s0, rt_interrupt_to_thread
LOAD s1, 0(s0)
LOAD sp, 0(s1)
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
spurious_interrupt:
LOAD x1, 1 * REGBYTES(sp)
/* Remain in M-mode after mret */
li t0, 0x00001800
csrs mstatus, t0
LOAD t0, 2 * REGBYTES(sp)
csrs mstatus, t0
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)
LOAD x6, 6 * REGBYTES(sp)
LOAD x7, 7 * REGBYTES(sp)
LOAD x8, 8 * REGBYTES(sp)
LOAD x9, 9 * REGBYTES(sp)
LOAD x10, 10 * REGBYTES(sp)
LOAD x11, 11 * REGBYTES(sp)
LOAD x12, 12 * REGBYTES(sp)
LOAD x13, 13 * REGBYTES(sp)
LOAD x14, 14 * REGBYTES(sp)
LOAD x15, 15 * REGBYTES(sp)
LOAD x16, 16 * REGBYTES(sp)
LOAD x17, 17 * REGBYTES(sp)
LOAD x18, 18 * REGBYTES(sp)
LOAD x19, 19 * REGBYTES(sp)
LOAD x20, 20 * REGBYTES(sp)
LOAD x21, 21 * REGBYTES(sp)
LOAD x22, 22 * REGBYTES(sp)
LOAD x23, 23 * REGBYTES(sp)
LOAD x24, 24 * REGBYTES(sp)
LOAD x25, 25 * REGBYTES(sp)
LOAD x26, 26 * REGBYTES(sp)
LOAD x27, 27 * REGBYTES(sp)
LOAD x28, 28 * REGBYTES(sp)
LOAD x29, 29 * REGBYTES(sp)
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
mret
libcpu/risc-v/e310/trap_gcc.S
+14
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@@ -0,0 +1,14 @@
#include "cpuport.h"
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
addi sp, sp, -4
STORE ra, 0 * REGBYTES(sp)
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call handle_trap
LOAD ra, 0 * REGBYTES(sp)
addi sp, sp, 4
ret
libcpu/risc-v/hpmicro/SConscript
+1 -1
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@@ -11,7 +11,7 @@ if rtconfig.PLATFORM == 'gcc':
src += Glob('*_gcc.S')
CPPPATH = [cwd]
ASFLAGS = ''
ASFLAGS = ' -I ' + cwd
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
libcpu/risc-v/hpmicro/context_gcc.S
-288
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libcpu/risc-v/hpmicro/cpuport.c
-90
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@@ -1,90 +0,0 @@
/*
#include <rt-thread/libcpu/risc-v/hpmicro/cpuport.h>
#include <rt-thread/libcpu/risc-v/hpmicro/riscv-stackframe.h>
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard The unify RISC-V porting code.
* 2020/11/20 BalanceTWK Add FPU support
*/
#include <rthw.h>
#include <rtthread.h>
#include "riscv-stackframe.h"
volatile rt_ubase_t rt_interrupt_from_thread = 0;
volatile rt_ubase_t rt_interrupt_to_thread = 0;
volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry,
void *parameter,
rt_uint8_t *stack_addr,
void *texit)
{
struct rt_hw_stack_frame *frame;
rt_uint8_t *stk;
int i;
stk = stack_addr + sizeof(rt_ubase_t);
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
stk -= sizeof(struct rt_hw_stack_frame);
frame = (struct rt_hw_stack_frame *)stk;
for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
{
((rt_ubase_t *)frame)[i] = 0xdeadbeef;
}
frame->ra = (rt_ubase_t)texit;
frame->a0 = (rt_ubase_t)parameter;
frame->epc = (rt_ubase_t)tentry;
/* force to machine mode(MPP=11) and set MPIE to 1 */
frame->mstatus = 0x00007880;
return stk;
}
/*
* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
*/
void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
{
if (rt_thread_switch_interrupt_flag == 0)
rt_interrupt_from_thread = from;
rt_interrupt_to_thread = to;
rt_thread_switch_interrupt_flag = 1;
return ;
}
/** shutdown CPU */
rt_weak void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
while (level)
{
RT_ASSERT(0);
}
}
libcpu/risc-v/hpmicro/cpuport.h
-49
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@@ -1,49 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-03 Bernard The first version
* 2020/11/20 BalanceTWK Add FPU support
*/
#ifndef CPUPORT_H__
#define CPUPORT_H__
#include <rtconfig.h>
/* bytes of register width */
#define STORE sw
#define LOAD lw
#define REGBYTES 4
#ifdef __riscv_flen
#define ARCH_RISCV_FPU
#if __riscv_flen == 32
#define ARCH_RISCV_FPU_S
#endif
#if __riscv_flen == 64
#define ARCH_RISCV_FPU_D
#endif
#endif
#ifdef ARCH_RISCV_FPU
#ifdef ARCH_RISCV_FPU_D
#define FSTORE fsd
#define FLOAD fld
#define FREGBYTES 8
#define rv_floatreg_t rt_int64_t
#endif
#ifdef ARCH_RISCV_FPU_S
#define FSTORE fsw
#define FLOAD flw
#define FREGBYTES 4
#define rv_floatreg_t rt_int32_t
#endif
#endif
#endif
libcpu/risc-v/hpmicro/trap_entry_gcc.S
-202
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libcpu/risc-v/hpmicro/trap_gcc.S
+12
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@@ -0,0 +1,12 @@
#include "cpuport.h"
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
addi sp, sp, -4
STORE ra, 0 * REGBYTES(sp)
csrr a0, mscratch
call trap_entry
LOAD ra, 0 * REGBYTES(sp)
addi sp, sp, 4
ret
libcpu/risc-v/nuclei/SConscript
+1 -1
View File
@@ -7,7 +7,7 @@ Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
ASFLAGS = ''
ASFLAGS = ' -I ' + cwd
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
libcpu/risc-v/nuclei/context_gcc.S
-188
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@@ -1,188 +0,0 @@
/*
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/03/26 Huaqi First Nuclei RISC-V porting implementation
*/
#include "riscv_encoding.h"
#ifndef __riscv_32e
#define RT_SAVED_REGNUM 30
#else
#define RT_SAVED_REGNUM 14
#endif
#define RT_CONTEXT_SIZE (RT_SAVED_REGNUM * REGBYTES)
.extern rt_interrupt_from_thread
.extern rt_interrupt_to_thread
.section .text
/*
* void rt_hw_context_switch_to(rt_ubase_t to);
* a0 --> to_thread
*/
.globl rt_hw_context_switch_to
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the stack
for lazy saving of FPU registers. */
.align 3
rt_hw_context_switch_to:
/* Setup Interrupt Stack using
The stack that was used by main()
before the scheduler is started is
no longer required after the scheduler is started.
Interrupt stack pointer is stored in CSR_MSCRATCH */
la t0, _sp
csrw CSR_MSCRATCH, t0
LOAD sp, 0x0(a0) /* Read sp from first TCB member(a0) */
/* Pop PC from stack and set MEPC */
LOAD t0, 0 * REGBYTES(sp)
csrw CSR_MEPC, t0
/* Pop mstatus from stack and set it */
LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
csrw CSR_MSTATUS, t0
/* Interrupt still disable here */
/* Restore Registers from Stack */
LOAD x1, 1 * REGBYTES(sp) /* RA */
LOAD x5, 2 * REGBYTES(sp)
LOAD x6, 3 * REGBYTES(sp)
LOAD x7, 4 * REGBYTES(sp)
LOAD x8, 5 * REGBYTES(sp)
LOAD x9, 6 * REGBYTES(sp)
LOAD x10, 7 * REGBYTES(sp)
LOAD x11, 8 * REGBYTES(sp)
LOAD x12, 9 * REGBYTES(sp)
LOAD x13, 10 * REGBYTES(sp)
LOAD x14, 11 * REGBYTES(sp)
LOAD x15, 12 * REGBYTES(sp)
#ifndef __riscv_32e
LOAD x16, 13 * REGBYTES(sp)
LOAD x17, 14 * REGBYTES(sp)
LOAD x18, 15 * REGBYTES(sp)
LOAD x19, 16 * REGBYTES(sp)
LOAD x20, 17 * REGBYTES(sp)
LOAD x21, 18 * REGBYTES(sp)
LOAD x22, 19 * REGBYTES(sp)
LOAD x23, 20 * REGBYTES(sp)
LOAD x24, 21 * REGBYTES(sp)
LOAD x25, 22 * REGBYTES(sp)
LOAD x26, 23 * REGBYTES(sp)
LOAD x27, 24 * REGBYTES(sp)
LOAD x28, 25 * REGBYTES(sp)
LOAD x29, 26 * REGBYTES(sp)
LOAD x30, 27 * REGBYTES(sp)
LOAD x31, 28 * REGBYTES(sp)
#endif
addi sp, sp, RT_CONTEXT_SIZE
mret
.align 2
.global eclic_msip_handler
eclic_msip_handler:
addi sp, sp, -RT_CONTEXT_SIZE
STORE x1, 1 * REGBYTES(sp) /* RA */
STORE x5, 2 * REGBYTES(sp)
STORE x6, 3 * REGBYTES(sp)
STORE x7, 4 * REGBYTES(sp)
STORE x8, 5 * REGBYTES(sp)
STORE x9, 6 * REGBYTES(sp)
STORE x10, 7 * REGBYTES(sp)
STORE x11, 8 * REGBYTES(sp)
STORE x12, 9 * REGBYTES(sp)
STORE x13, 10 * REGBYTES(sp)
STORE x14, 11 * REGBYTES(sp)
STORE x15, 12 * REGBYTES(sp)
#ifndef __riscv_32e
STORE x16, 13 * REGBYTES(sp)
STORE x17, 14 * REGBYTES(sp)
STORE x18, 15 * REGBYTES(sp)
STORE x19, 16 * REGBYTES(sp)
STORE x20, 17 * REGBYTES(sp)
STORE x21, 18 * REGBYTES(sp)
STORE x22, 19 * REGBYTES(sp)
STORE x23, 20 * REGBYTES(sp)
STORE x24, 21 * REGBYTES(sp)
STORE x25, 22 * REGBYTES(sp)
STORE x26, 23 * REGBYTES(sp)
STORE x27, 24 * REGBYTES(sp)
STORE x28, 25 * REGBYTES(sp)
STORE x29, 26 * REGBYTES(sp)
STORE x30, 27 * REGBYTES(sp)
STORE x31, 28 * REGBYTES(sp)
#endif
/* Push mstatus to stack */
csrr t0, CSR_MSTATUS
STORE t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
/* Push additional registers */
/* Store sp to task stack */
LOAD t0, rt_interrupt_from_thread
STORE sp, 0(t0)
csrr t0, CSR_MEPC
STORE t0, 0(sp)
jal rt_hw_taskswitch
/* Switch task context */
LOAD t0, rt_interrupt_to_thread
LOAD sp, 0x0(t0)
/* Pop PC from stack and set MEPC */
LOAD t0, 0 * REGBYTES(sp)
csrw CSR_MEPC, t0
/* Pop additional registers */
/* Pop mstatus from stack and set it */
LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
csrw CSR_MSTATUS, t0
/* Interrupt still disable here */
/* Restore Registers from Stack */
LOAD x1, 1 * REGBYTES(sp) /* RA */
LOAD x5, 2 * REGBYTES(sp)
LOAD x6, 3 * REGBYTES(sp)
LOAD x7, 4 * REGBYTES(sp)
LOAD x8, 5 * REGBYTES(sp)
LOAD x9, 6 * REGBYTES(sp)
LOAD x10, 7 * REGBYTES(sp)
LOAD x11, 8 * REGBYTES(sp)
LOAD x12, 9 * REGBYTES(sp)
LOAD x13, 10 * REGBYTES(sp)
LOAD x14, 11 * REGBYTES(sp)
LOAD x15, 12 * REGBYTES(sp)
#ifndef __riscv_32e
LOAD x16, 13 * REGBYTES(sp)
LOAD x17, 14 * REGBYTES(sp)
LOAD x18, 15 * REGBYTES(sp)
LOAD x19, 16 * REGBYTES(sp)
LOAD x20, 17 * REGBYTES(sp)
LOAD x21, 18 * REGBYTES(sp)
LOAD x22, 19 * REGBYTES(sp)
LOAD x23, 20 * REGBYTES(sp)
LOAD x24, 21 * REGBYTES(sp)
LOAD x25, 22 * REGBYTES(sp)
LOAD x26, 23 * REGBYTES(sp)
LOAD x27, 24 * REGBYTES(sp)
LOAD x28, 25 * REGBYTES(sp)
LOAD x29, 26 * REGBYTES(sp)
LOAD x30, 27 * REGBYTES(sp)
LOAD x31, 28 * REGBYTES(sp)
#endif
addi sp, sp, RT_CONTEXT_SIZE
mret
libcpu/risc-v/nuclei/cpuport.c
-257
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libcpu/risc-v/nuclei/cpuport.h
-40
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@@ -1,40 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/03/26 hqfang Nuclei RISC-V Core porting code.
*/
#ifndef __CPUPORT_H__
#define __CPUPORT_H__
#include <rtconfig.h>
#include <nuclei_sdk_soc.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Scheduler utilities. */
#define RT_YIELD() \
{ \
/* Set a software interrupt(SWI) request to request a context switch. */ \
SysTimer_SetSWIRQ(); \
/* Barriers are normally not required but do ensure the code is completely \
within the specified behaviour for the architecture. */ \
__RWMB(); \
__FENCE_I(); \
}
extern void rt_hw_ticksetup(void);
extern void rt_hw_taskswitch(void);
#ifdef __cplusplus
}
#endif
#endif
libcpu/risc-v/nuclei/interrupt_gcc.S
-218
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libcpu/risc-v/nuclei/trap_gcc.S
+18
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@@ -0,0 +1,18 @@
#include "cpuport.h"
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
addi sp, sp, -4
STORE ra, 0 * REGBYTES(sp)
csrr a0, mcause
csrr a1, mepc
mv a2, sp
csrrw ra, 0x07ED, ra
li t0, 0x08
csrc mstatus, t0
LOAD ra, 0 * REGBYTES(sp)
addi sp, sp, 4
ret
libcpu/risc-v/readme.md
+212
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libcpu/risc-v/rv32m1/interrupt_gcc.S
-130
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@@ -1,130 +0,0 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/02 Bernard The first version
*/
#include "cpuport.h"
.section .text.entry
.align 2
.global IRQ_Handler
IRQ_Handler:
/* save all from thread context */
addi sp, sp, -32 * REGBYTES
STORE x1, 1 * REGBYTES(sp)
li t0, 0x80
STORE t0, 2 * REGBYTES(sp)
STORE x4, 4 * REGBYTES(sp)
STORE x5, 5 * REGBYTES(sp)
STORE x6, 6 * REGBYTES(sp)
STORE x7, 7 * REGBYTES(sp)
STORE x8, 8 * REGBYTES(sp)
STORE x9, 9 * REGBYTES(sp)
STORE x10, 10 * REGBYTES(sp)
STORE x11, 11 * REGBYTES(sp)
STORE x12, 12 * REGBYTES(sp)
STORE x13, 13 * REGBYTES(sp)
STORE x14, 14 * REGBYTES(sp)
STORE x15, 15 * REGBYTES(sp)
STORE x16, 16 * REGBYTES(sp)
STORE x17, 17 * REGBYTES(sp)
STORE x18, 18 * REGBYTES(sp)
STORE x19, 19 * REGBYTES(sp)
STORE x20, 20 * REGBYTES(sp)
STORE x21, 21 * REGBYTES(sp)
STORE x22, 22 * REGBYTES(sp)
STORE x23, 23 * REGBYTES(sp)
STORE x24, 24 * REGBYTES(sp)
STORE x25, 25 * REGBYTES(sp)
STORE x26, 26 * REGBYTES(sp)
STORE x27, 27 * REGBYTES(sp)
STORE x28, 28 * REGBYTES(sp)
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
move s0, sp
/* switch to interrupt stack */
la sp, __stack
/* interrupt handle */
call rt_interrupt_enter
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call SystemIrqHandler
call rt_interrupt_leave
/* switch to from thread stack */
move sp, s0
/* need to switch new thread */
la s0, rt_thread_switch_interrupt_flag
lw s2, 0(s0)
beqz s2, spurious_interrupt
/* clear switch interrupt flag */
sw zero, 0(s0)
csrr a0, mepc
STORE a0, 0 * REGBYTES(sp)
la s0, rt_interrupt_from_thread
LOAD s1, 0(s0)
STORE sp, 0(s1)
la s0, rt_interrupt_to_thread
LOAD s1, 0(s0)
LOAD sp, 0(s1)
LOAD a0, 0 * REGBYTES(sp)
csrw mepc, a0
spurious_interrupt:
LOAD x1, 1 * REGBYTES(sp)
/* Remain in M-mode after mret */
li t0, 0x00001800
csrs mstatus, t0
LOAD t0, 2 * REGBYTES(sp)
csrs mstatus, t0
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)
LOAD x6, 6 * REGBYTES(sp)
LOAD x7, 7 * REGBYTES(sp)
LOAD x8, 8 * REGBYTES(sp)
LOAD x9, 9 * REGBYTES(sp)
LOAD x10, 10 * REGBYTES(sp)
LOAD x11, 11 * REGBYTES(sp)
LOAD x12, 12 * REGBYTES(sp)
LOAD x13, 13 * REGBYTES(sp)
LOAD x14, 14 * REGBYTES(sp)
LOAD x15, 15 * REGBYTES(sp)
LOAD x16, 16 * REGBYTES(sp)
LOAD x17, 17 * REGBYTES(sp)
LOAD x18, 18 * REGBYTES(sp)
LOAD x19, 19 * REGBYTES(sp)
LOAD x20, 20 * REGBYTES(sp)
LOAD x21, 21 * REGBYTES(sp)
LOAD x22, 22 * REGBYTES(sp)
LOAD x23, 23 * REGBYTES(sp)
LOAD x24, 24 * REGBYTES(sp)
LOAD x25, 25 * REGBYTES(sp)
LOAD x26, 26 * REGBYTES(sp)
LOAD x27, 27 * REGBYTES(sp)
LOAD x28, 28 * REGBYTES(sp)
LOAD x29, 29 * REGBYTES(sp)
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
addi sp, sp, 32 * REGBYTES
mret
libcpu/risc-v/rv32m1/trap_gcc.S
+16
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@@ -0,0 +1,16 @@
#include "cpuport.h"
.globl rt_hw_do_after_save_above
.type rt_hw_do_after_save_above,@function
rt_hw_do_after_save_above:
addi sp, sp, -4
STORE ra, 0 * REGBYTES(sp)
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call SystemIrqHandler
LOAD ra, 0 * REGBYTES(sp)
addi sp, sp, 4
ret