The first submit CY8CKIT-062S2-43012 project

bsp/cypress/libraries/HAL_Drivers/SConscript

@@ -0,0 +1,33 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+drv_common.c
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_usart_v2.c']
+    else:
+        src += ['drv_uart.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += Glob('drv_adc.c')
+
+path =  [cwd]
+path += [cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/cypress/libraries/HAL_Drivers/config/Pre_Include_Global.h

@@ -0,0 +1,37 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'mtb-example-psoc6-rtthread'
+ * Target:  'Target 1'
+ */
+
+#ifndef PRE_INCLUDE_GLOBAL_H
+#define PRE_INCLUDE_GLOBAL_H
+
+/* Cypress::TARGET_CY8CKIT-062S2-43012:ModusToolbox */
+#define HAVE_SIGVAL
+#define HAVE_SIGEVENT
+#define HAVE_SIGINFO
+#define RT_USING_NEWLIB
+#define CY_USING_HAL
+#define CY_APPNAME_mtb_example_psoc6_rtthread
+#define CY_TARGET_DEVICE CY8C624ABZI_S2D44
+#define TARGET_CY8CKIT_062S2_43012
+#define CY_TARGET_BOARD CY8CKIT_062S2_43012
+#define COMPONENT_43012
+#define COMPONENT_BSP_DESIGN_MODUS
+#define COMPONENT_CAT1
+#define COMPONENT_CAT1A
+#define COMPONENT_CM0P_SLEEP
+#define COMPONENT_CM4
+#define COMPONENT_CY8CKIT_062S2_43012
+#define COMPONENT_HCI_UART
+#define COMPONENT_MURATA_1LV
+#define COMPONENT_PSOC6HAL
+#define COMPONENT_SOFTFP
+#define DEBUG
+#define CY_SUPPORTS_DEVICE_VALIDATION
+
+#endif /* PRE_INCLUDE_GLOBAL_H */

bsp/cypress/libraries/HAL_Drivers/config/RTE_Components.h

@@ -0,0 +1,13 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'mtb-example-psoc6-rtthread'
+ * Target:  'Target 1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#endif /* RTE_COMPONENTS_H */

bsp/cypress/libraries/HAL_Drivers/drv_adc.c

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-04     Rbb666       first version
+ */
+#include "drv_common.h"
+#include "drv_adc.h"
+
+#include "cyhal.h"
+#include "cybsp.h"
+
+#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.adc"
+#include <drv_log.h>
+
+#define VPLUS_CHANNEL_0     (P10_0)
+
+struct ifx_adc
+{
+    struct rt_adc_device ifx_adc_device;
+    cyhal_adc_channel_t *adc_ch;
+    char *name;
+};
+
+static struct ifx_adc ifx_adc_obj[] =
+{
+#ifdef BSP_USING_ADC1
+    ADC1_CONFIG,
+#endif
+};
+
+static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    cyhal_adc_channel_t *adc_ch;
+    cy_rslt_t result;
+
+    RT_ASSERT(device != RT_NULL);
+    adc_ch = device->parent.user_data;
+
+    const cyhal_adc_channel_config_t channel_config =
+    {
+        .enable_averaging = false,      // Disable averaging for channel
+        .min_acquisition_ns = 1000,     // Minimum acquisition time set to 1us
+        .enabled = enabled              // Sample this channel when ADC performs a scan
+    };
+
+    if (enabled)
+    {
+        /* Initialize ADC. The ADC block which can connect to pin 10[0] is selected */
+        result = cyhal_adc_init(&adc_obj, VPLUS_CHANNEL_0, NULL);
+        if (result != RT_EOK)
+        {
+            LOG_E("ADC initialization failed. Error: %ld\n", (long unsigned int)result);
+            return -RT_ENOSYS;
+        }
+
+        /* Initialize a channel 0 and configure it to scan P10_0 in single ended mode. */
+        result  = cyhal_adc_channel_init_diff(adc_ch, &adc_obj, VPLUS_CHANNEL_0,
+                                              CYHAL_ADC_VNEG, &channel_config);
+        if (result != RT_EOK)
+        {
+            LOG_E("ADC single ended channel initialization failed. Error: %ld\n", (long unsigned int)result);
+            return -RT_ENOSYS;
+        }
+
+        /* Update ADC configuration */
+        result = cyhal_adc_configure(&adc_obj, &adc_config);
+        if (result != RT_EOK)
+        {
+            printf("ADC configuration update failed. Error: %ld\n", (long unsigned int)result);
+            return -RT_ENOSYS;
+        }
+    }
+    else
+    {
+        cyhal_adc_free(&adc_obj);
+        cyhal_adc_channel_free(adc_ch);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    cyhal_adc_channel_t *adc_ch;
+
+    RT_ASSERT(device != RT_NULL);
+    adc_ch = device->parent.user_data;
+
+    channel = adc_ch->channel_idx;
+
+    *value = cyhal_adc_read(adc_ch);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops at_adc_ops =
+{
+    .enabled = ifx_adc_enabled,
+    .convert = ifx_get_adc_value,
+};
+
+static int rt_hw_adc_init(void)
+{
+    int result = RT_EOK;
+    int i = 0;
+
+    for (i = 0; i < sizeof(ifx_adc_obj) / sizeof(ifx_adc_obj[0]); i++)
+    {
+        /* register ADC device */
+        if (rt_hw_adc_register(&ifx_adc_obj[i].ifx_adc_device, ifx_adc_obj[i].name, &at_adc_ops, ifx_adc_obj[i].adc_ch) == RT_EOK)
+        {
+            LOG_D("%s register success", at32_adc_obj[i].name);
+        }
+        else
+        {
+            LOG_E("%s register failed", ifx_adc_obj[i].name);
+            result = -RT_ERROR;
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_adc_init);
+
+#endif /* BSP_USING_ADC */

bsp/cypress/libraries/HAL_Drivers/drv_adc.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-28     shelton      first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#include "cyhal.h"
+#include "cybsp.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
+
+cyhal_adc_t adc_obj;
+cyhal_adc_channel_t adc_chan_obj;
+
+const cyhal_adc_config_t adc_config =
+{
+    .continuous_scanning = false,   // Continuous Scanning is disabled
+    .average_count = 1,             // Average count disabled
+    .vref = CYHAL_ADC_REF_VDDA,     // VREF for Single ended channel set to VDDA
+    .vneg = CYHAL_ADC_VNEG_VSSA,    // VNEG for Single ended channel set to VSSA
+    .resolution = 12u,              // 12-bit resolution
+    .ext_vref = NC,                 // No connection
+    .bypass_pin = NC                // No connection
+};
+
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                 \
+    {                               \
+        .adc_ch = &adc_chan_obj,    \
+        .name = "adc1",             \
+    }
+#endif /* ADC1_CONFIG */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/cypress/libraries/HAL_Drivers/drv_common.c

@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-1      Rbb666       first version
+ */
+
+#include "drv_common.h"
+
+#ifdef RT_USING_SERIAL
+#include "drv_uart.h"
+#endif
+
+#define DBG_TAG "drv_common"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+/**
+ * this is the timer interrupt service routine.
+ */
+void SysTick_Handler_CB(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/* systick configuration */
+void rt_hw_systick_init(void)
+{
+    Cy_SysTick_Init(CY_SYSTICK_CLOCK_SOURCE_CLK_CPU, SystemCoreClock / RT_TICK_PER_SECOND);
+    Cy_SysTick_SetCallback(0, SysTick_Handler_CB);
+    Cy_SysTick_EnableInterrupt();
+}
+
+/**
+ * @brief  this function is executed in case of error occurrence.
+ * @param  none
+ * @retval none
+ */
+void _Error_Handler(char *s, int num)
+{
+    /* User can add his own implementation to report the HAL error return state */
+    LOG_E("Error_Handler at file:%s num:%d", s, num);
+    while (1)
+    {
+    }
+}
+
+/**
+ * this function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+/**
+ * this function will initial ifx board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+    cy_bsp_all_init();
+
+    /* systick init */
+    rt_hw_systick_init();
+
+    /* heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* usart driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}

bsp/cypress/libraries/HAL_Drivers/drv_common.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-1      Rbb666       first version
+ */
+
+#ifndef __DRV_COMMON_H__
+#define __DRV_COMMON_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_DEVICE
+    #include <rtdevice.h>
+#endif
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _Error_Handler(char *s, int num);
+
+#ifndef Error_Handler
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/cypress/libraries/HAL_Drivers/drv_gpio.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2022-07-1      Rbb666            first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "drv_common.h"
+
+#include "cy_retarget_io.h"
+#include "cyhal_gpio.h"
+#include "cyhal_irq_psoc.h"
+
+#define GPIO_INTERRUPT_PRIORITY (7u)
+
+#define GET_PIN(PORTx,PIN)      ((((uint8_t)(PORTx)) << 3U) + ((uint8_t)(PIN)))
+
+struct pin_irq_map
+{
+    rt_uint16_t pin;
+    IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */

bsp/cypress/libraries/HAL_Drivers/drv_log.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG               "drv"
+#else
+#define DBG_TAG               LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>

bsp/cypress/libraries/HAL_Drivers/drv_uart.c

@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "drv_uart.h"
+
+#include "cy_retarget_io.h"
+#include "cyhal_scb_common.h"
+
+struct ifx_usart
+{
+    char *name;
+    CySCB_Type *usart_x;
+    IRQn_Type intrSrc;
+    struct rt_serial_device serial;
+};
+
+enum
+{
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+};
+
+#ifdef BSP_USING_UART1
+/* UART1 device driver structure */
+const cy_stc_sysint_t UART1_SCB_IRQ_cfg =
+{
+    .intrSrc = scb_5_interrupt_IRQn,
+    .intrPriority = 7u,
+};
+#endif
+
+static struct ifx_usart usart_config[] =
+{
+#ifdef BSP_USING_UART1
+    {
+        "uart1",
+        SCB5,
+        scb_5_interrupt_IRQn,
+    },
+#endif
+};
+
+static void usart_isr(struct rt_serial_device *serial)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+#ifdef BSP_USING_UART1
+    if ((SCB5->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk) != 0)
+    {
+        /* Clear UART "RX fifo not empty interrupt" */
+        SCB5->INTR_RX = SCB5->INTR_RX & SCB_INTR_RX_NOT_EMPTY_Msk;
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+#endif
+}
+
+#ifdef BSP_USING_UART1
+/* UART0 Interrupt Hanlder */
+void uart1_isr_callback(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    usart_isr(&usart_config[UART1_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+/*
+ * UARTHS interface
+ */
+static rt_err_t ifx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct ifx_usart *usart_instance = (struct ifx_usart *) serial->parent.user_data;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(usart_instance != RT_NULL);
+
+    cy_en_scb_uart_status_t result;
+
+    /* Initialize retarget-io to use the debug UART port */
+    result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX,
+                                 CY_RETARGET_IO_BAUDRATE);
+
+    /* retarget-io init failed. Stop program execution */
+    RT_ASSERT(result != RT_ERROR);
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    RT_ASSERT(serial != RT_NULL);
+    struct ifx_usart *usart = (struct ifx_usart *) serial->parent.user_data;
+    RT_ASSERT(usart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Unmasking only the RX fifo not empty interrupt bit */
+        usart->usart_x->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
+
+#ifdef BSP_USING_UART1
+        /* Interrupt Settings for UART */
+        Cy_SysInt_Init(&UART1_SCB_IRQ_cfg, uart1_isr_callback);
+#endif
+
+        /* Enable the interrupt */
+        NVIC_EnableIRQ(usart->intrSrc);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int ifx_uarths_putc(struct rt_serial_device *serial, char c)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    struct ifx_usart *usart = (struct ifx_usart *) serial->parent.user_data;
+
+    RT_ASSERT(usart != RT_NULL);
+
+    if (_cyhal_scb_pm_transition_pending())
+        return CYHAL_SYSPM_RSLT_ERR_PM_PENDING;
+
+    uint32_t count = 0;
+    while (count == 0)
+    {
+        count = Cy_SCB_UART_Put(usart->usart_x, c);
+    }
+
+    return (1);
+}
+
+static int ifx_uarths_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    rt_uint8_t read_data;
+    RT_ASSERT(serial != RT_NULL);
+
+    ch = -1;
+    if (RT_EOK == cyhal_uart_getc(&cy_retarget_io_uart_obj, (uint8_t *)&read_data, 1))
+    {
+        ch = read_data & 0xff;
+    }
+    else
+    {
+        ch = -1;
+    }
+
+    return ch;
+}
+
+const struct rt_uart_ops _uart_ops =
+{
+    ifx_configure,
+    ifx_control,
+    ifx_uarths_putc,
+    ifx_uarths_getc,
+    RT_NULL
+};
+
+void rt_hw_uart_init(void)
+{
+    int index;
+    rt_size_t obj_num;
+
+    obj_num = sizeof(usart_config) / sizeof(struct ifx_usart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (index = 0; index < obj_num; index++)
+    {
+        usart_config[index].serial.ops = &_uart_ops;
+        usart_config[index].serial.config = config;
+
+        /* register uart device */
+        result = rt_hw_serial_register(&usart_config[index].serial,
+                                       usart_config[index].name,
+                                       RT_DEVICE_FLAG_RDWR |
+                                       RT_DEVICE_FLAG_INT_RX,
+                                       &usart_config[index]);
+
+        RT_ASSERT(result == RT_EOK);
+    }
+}

bsp/cypress/libraries/HAL_Drivers/drv_uart.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666	   first version
+ */
+ 
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "cycfg_peripherals.h"
+
+void rt_hw_uart_init(void);
+
+#endif

bsp/cypress/libraries/IFX_PSOC6_HAL/SConscript

@@ -0,0 +1,89 @@
+from building import *
+import rtconfig
+Import('RTT_ROOT')
+
+# get current directory
+cwd = GetCurrentDir()
+src = []
+
+# The set of source files associated with this SConscript file.
+src = Split('''
+            mtb-hal-cat1/source/cyhal_clock.c
+            mtb-hal-cat1/source/cyhal_hwmgr.c
+            mtb-hal-cat1/source/cyhal_syspm.c
+            mtb-hal-cat1/source/cyhal_system.c
+            mtb-hal-cat1/source/cyhal_uart.c
+            mtb-hal-cat1/source/cyhal_gpio.c
+            mtb-hal-cat1/source/cyhal_scb_common.c
+            mtb-hal-cat1/source/cyhal_interconnect.c
+            mtb-hal-cat1/source/cyhal_utils_psoc.c
+            mtb-hal-cat1/source/cyhal_utils.c
+            mtb-hal-cat1/source/cyhal_lptimer.c
+            mtb-hal-cat1/source/cyhal_irq_psoc.c            
+            mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_02.c
+            mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c
+            mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c
+            mtb-pdl-cat1/drivers/source/cy_scb_common.c
+            mtb-pdl-cat1/drivers/source/cy_sysclk.c
+            mtb-pdl-cat1/drivers/source/cy_systick.c
+            mtb-pdl-cat1/drivers/source/cy_gpio.c
+            mtb-pdl-cat1/drivers/source/cy_sysint.c
+            mtb-pdl-cat1/drivers/source/cy_syslib.c
+            mtb-pdl-cat1/drivers/source/cy_scb_i2c.c
+            mtb-pdl-cat1/drivers/source/cy_syspm.c
+            mtb-pdl-cat1/drivers/source/cy_mcwdt.c
+            mtb-pdl-cat1/drivers/source/cy_ipc_pipe.c
+            mtb-pdl-cat1/drivers/source/cy_ipc_sema.c
+            mtb-pdl-cat1/drivers/source/cy_ipc_drv.c
+            mtb-pdl-cat1/drivers/source/cy_trigmux.c
+            mtb-pdl-cat1/drivers/source/cy_prot.c
+            mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.s            
+            TARGET_CY8CKIT-062S2-43012/cybsp.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c            
+            lib/cy_capsense.lib
+            ''')
+
+src += Glob(cwd + '/psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['retarget-io/cy_retarget_io.c']
+    src += ['mtb-hal-cat1/source/cyhal_uart.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_scb_uart.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['mtb-hal-cat1/source/cyhal_dma_dw.c']
+    src += ['mtb-hal-cat1/source/cyhal_dma_dmac.c']
+    src += ['mtb-hal-cat1/source/cyhal_dma.c']
+    src += ['mtb-hal-cat1/source/cyhal_analog_common.c']
+    src += ['mtb-hal-cat1/source/cyhal_adc_sar.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_sar.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_dmac.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_sysanalog.c']
+
+path = [cwd + '/capsense',
+        cwd + '/psoc6cm0p',
+        cwd + '/retarget-io',
+        cwd + '/core-lib/include',
+        cwd + '/mtb-hal-cat1/include',
+        cwd + '/mtb-hal-cat1/include_pvt',
+        cwd + '/mtb-pdl-cat1/cmsis/include',
+        cwd + '/mtb-pdl-cat1/drivers/include',
+        cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include',
+        cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include',
+        cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include',
+        cwd + '/TARGET_CY8CKIT-062S2-43012',
+        cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+
+if rtconfig.PLATFORM == 'gcc':
+    group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
+else:
+    group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
+
+Return('group')

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/.gitignore

@@ -0,0 +1,9 @@
+docs
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 2)
+$(SEARCH_wifi-host-driver)/WiFi_Host_Driver/resources/nvram_deprecated/
+$(SEARCH_bluetooth-freertos)/firmware_deprecated/
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 1)
+../wifi-host-driver/WiFi_Host_Driver/resources/nvram_deprecated/
+../bluetooth-freertos/firmware_deprecated/

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -0,0 +1,39 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+    init_cycfg_system();
+    init_cycfg_clocks();
+    init_cycfg_routing();
+    init_cycfg_peripherals();
+    init_cycfg_pins();
+}

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_connectivity_bt.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -0,0 +1,29 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h

@@ -0,0 +1,140 @@
+/*******************************************************************************
+* File Name: cycfg_capsense_defines.h
+*
+* Description:
+* CAPSENSE configuration defines.
+*
+* Note: This file is required for the CAPSENSE Middleware Library to build 
+* successfully.
+*
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.6195
+*
+********************************************************************************
+* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company) 
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_DEFINES_H)
+#define CYCFG_CAPSENSE_DEFINES_H
+
+#include <stddef.h>
+
+/* General */
+#define CY_CAPSENSE_WIDGET_COUNT                                                 (3u)
+#define CY_CAPSENSE_SENSOR_COUNT                                                 (7u)
+#define CY_CAPSENSE_ELTD_COUNT                                                   (9u)
+#define CY_CAPSENSE_PIN_COUNT                                                    (9u)
+#define CY_CAPSENSE_SHIELD_PIN_COUNT                                             (0u)
+#define CY_CAPSENSE_POSITION_SIZE                                                (1u)
+#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (3u)
+#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (5u)
+#define CY_CAPSENSE_MFS_CH_NUMBER                                                (1u)
+#define CY_CAPSENSE_RAW_HISTORY_SIZE                                             (0u)
+#define CY_CAPSENSE_IIR_HISTORY_LOW_SIZE                                         (0u)
+#define CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE                                 (0u)
+#define CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE                                    (0u)
+#define CY_CAPSENSE_DIPLEX_SIZE                                                  (0u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE                                (0u)
+#define CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE                                      (0u)
+#define CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE                                       (0u)
+#define CY_CAPSENSE_BALLISTIC_WIDGET_COUNT                                       (0u)
+#define CY_CAPSENSE_GESTURE_WIDGET_COUNT                                         (0u)
+
+/* Sensing Methods */
+#define CY_CAPSENSE_CSD_EN                                                       (1u)
+#define CY_CAPSENSE_CSX_EN                                                       (1u)
+#define CY_CAPSENSE_CSD_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_SMARTSENSE_FULL_EN                                           (1u)
+#define CY_CAPSENSE_SMARTSENSE_HW_EN                                             (0u)
+#define CY_CAPSENSE_SMARTSENSE_DISABLED                                          (0u)
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN                                              (CY_CAPSENSE_SMARTSENSE_FULL_EN || CY_CAPSENSE_SMARTSENSE_HW_EN)
+#define CY_CAPSENSE_CSD_SHIELD_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SHIELD_CAP_EN                                            (0u)
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER                                          (CY_CAPSENSE_IDAC_SOURCING)
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN                                             (1u)
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN                                        (1u)
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN                                    (1u)
+#define CY_CAPSENSE_LFSR_EN                                                      (1u)
+#define CY_CAPSENSE_LFSR_AUTO_EN                                                 (1u)
+#define CY_CAPSENSE_CLOCK_SOURCE_AUTO_EN                                         (1u)
+
+/* Filtering */
+#define CY_CAPSENSE_ADAPTIVE_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN                                      (0u)
+#define CY_CAPSENSE_RAWCOUNT_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN                                  (0u)
+#define CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN                                 (0u)
+#define CY_CAPSENSE_REGULAR_RC_FILTER_EN                                         (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN || CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_PROX_RC_IIR_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN                                    (0u)
+#define CY_CAPSENSE_PROX_RC_FILTER_EN                                            (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN || CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_POSITION_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_CSD_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_CSX_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_POS_IIR_FILTER_EN                                            (0u)
+#define CY_CAPSENSE_POS_MEDIAN_FILTER_EN                                         (0u)
+#define CY_CAPSENSE_POS_AVERAGE_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_POS_JITTER_FILTER_EN                                         (0u)
+
+/* Widgets */
+#define CY_CAPSENSE_CSD_BUTTON_EN                                                (0u)
+#define CY_CAPSENSE_CSD_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SLIDER_EN                                                (1u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_CSD_PROXIMITY_EN                                             (0u)
+#define CY_CAPSENSE_CSX_BUTTON_EN                                                (1u)
+#define CY_CAPSENSE_CSX_SLIDER_EN                                                (0u)
+#define CY_CAPSENSE_CSX_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSX_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN                                     (0u)
+#define CY_CAPSENSE_CSD_LINEAR_SLIDER_EN                                         (1u)
+#define CY_CAPSENSE_CSD_RADIAL_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSD_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_LINEAR_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_GANGED_SNS_EN                                                (0u)
+#define CY_CAPSENSE_CSD_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_CSX_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_BUTTON_EN                                                    (1u)
+#define CY_CAPSENSE_MATRIX_EN                                                    (0u)
+#define CY_CAPSENSE_SLIDER_EN                                                    (1u)
+#define CY_CAPSENSE_TOUCHPAD_EN                                                  (0u)
+
+/* Features */
+#define CY_CAPSENSE_GESTURE_EN                                                   (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_SCAN_EN                                      (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_WIDGET_EN                                    (0u)
+#define CY_CAPSENSE_SNS_AUTO_RESET_EN                                            (0u)
+
+/* Self-test */
+#define CY_CAPSENSE_BIST_EN                                                      (0u)
+#define CY_CAPSENSE_TST_WDGT_CRC_EN                                              (0u)
+#define CY_CAPSENSE_TST_BSLN_INTEGRITY_EN                                        (0u)
+#define CY_CAPSENSE_TST_RAW_INTEGRITY_EN                                         (0u)
+#define CY_CAPSENSE_TST_SNS_SHORT_EN                                             (0u)
+#define CY_CAPSENSE_TST_SNS_CAP_EN                                               (0u)
+#define CY_CAPSENSE_TST_SH_CAP_EN                                                (0u)
+#define CY_CAPSENSE_TST_EXTERNAL_CAP_EN                                          (0u)
+#define CY_CAPSENSE_TST_VDDA_EN                                                  (0u)
+
+
+#endif /* CYCFG_CAPSENSE_DEFINES_H */
+
+/* [] END OF FILE */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -0,0 +1,50 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+    {
+        .type = CYHAL_RSC_CLOCK,
+        .block_num = CYBSP_CSD_CLK_DIV_HW,
+        .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+    Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+    Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+    Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+}

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+    #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c

@@ -0,0 +1,31 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.c
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_connectivity_bt.h"
+

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h

@@ -0,0 +1,55 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.h
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CONNECTIVITY_BT_H)
+#define CYCFG_CONNECTIVITY_BT_H
+
+#include "cycfg_notices.h"
+#include "cycfg_pins.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define bt_0_power_0_ENABLED 1U
+#define CYCFG_BT_LP_ENABLED (1u)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
+#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
+#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CONNECTIVITY_BT_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c

@@ -0,0 +1,181 @@
+/*******************************************************************************
+* File Name: cycfg_dmas.c
+*
+* Description:
+* DMA configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.14850
+* personalities 6.0.0.0
+* udd 3.0.0.2024
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_dmas.h"
+
+const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config = 
+{
+    .retrigger = CY_DMA_RETRIG_4CYC,
+    .interruptType = CY_DMA_DESCR,
+    .triggerOutType = CY_DMA_1ELEMENT,
+    .channelState = CY_DMA_CHANNEL_ENABLED,
+    .triggerInType = CY_DMA_1ELEMENT,
+    .dataSize = CY_DMA_BYTE,
+    .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
+    .descriptorType = CY_DMA_SINGLE_TRANSFER,
+    .srcAddress = NULL,
+    .dstAddress = NULL,
+    .srcXincrement = 1,
+    .dstXincrement = 0,
+    .xCount = 1,
+    .srcYincrement = 1,
+    .dstYincrement = 1,
+    .yCount = 1,
+    .nextDescriptor = NULL,
+};
+cy_stc_dma_descriptor_t TxDma_Descriptor_0 = 
+{
+    .ctl = 0UL,
+    .src = 0UL,
+    .dst = 0UL,
+    .xCtl = 0UL,
+    .yCtl = 0UL,
+    .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t TxDma_channelConfig = 
+{
+    .descriptor = &TxDma_Descriptor_0,
+    .preemptable = false,
+    .priority = 3,
+    .enable = false,
+    .bufferable = false,
+};
+const cy_stc_dma_crc_config_t TxDma_crcConfig = 
+{
+    .dataReverse = false,
+    .dataXor = 0,
+    .reminderReverse = false,
+    .reminderXor = 0,
+    .polynomial = 79764919,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t TxDma_obj = 
+    {
+        .type = CYHAL_RSC_DMA,
+        .block_num = 0U,
+        .channel_num = TxDma_CHANNEL,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config = 
+{
+    .retrigger = CY_DMA_RETRIG_4CYC,
+    .interruptType = CY_DMA_1ELEMENT,
+    .triggerOutType = CY_DMA_1ELEMENT,
+    .channelState = CY_DMA_CHANNEL_ENABLED,
+    .triggerInType = CY_DMA_1ELEMENT,
+    .dataSize = CY_DMA_BYTE,
+    .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
+    .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .descriptorType = CY_DMA_SINGLE_TRANSFER,
+    .srcAddress = NULL,
+    .dstAddress = NULL,
+    .srcXincrement = 0,
+    .dstXincrement = 1,
+    .xCount = 1,
+    .srcYincrement = 1,
+    .dstYincrement = 1,
+    .yCount = 1,
+    .nextDescriptor = &RxDma_Descriptor_1,
+};
+const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config = 
+{
+    .retrigger = CY_DMA_RETRIG_4CYC,
+    .interruptType = CY_DMA_DESCR,
+    .triggerOutType = CY_DMA_1ELEMENT,
+    .channelState = CY_DMA_CHANNEL_ENABLED,
+    .triggerInType = CY_DMA_1ELEMENT,
+    .dataSize = CY_DMA_BYTE,
+    .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
+    .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .descriptorType = CY_DMA_SINGLE_TRANSFER,
+    .srcAddress = NULL,
+    .dstAddress = NULL,
+    .srcXincrement = 0,
+    .dstXincrement = 1,
+    .xCount = 1,
+    .srcYincrement = 1,
+    .dstYincrement = 1,
+    .yCount = 1,
+    .nextDescriptor = &RxDma_Descriptor_0,
+};
+cy_stc_dma_descriptor_t RxDma_Descriptor_0 = 
+{
+    .ctl = 0UL,
+    .src = 0UL,
+    .dst = 0UL,
+    .xCtl = 0UL,
+    .yCtl = 0UL,
+    .nextPtr = 0UL,
+};
+cy_stc_dma_descriptor_t RxDma_Descriptor_1 = 
+{
+    .ctl = 0UL,
+    .src = 0UL,
+    .dst = 0UL,
+    .xCtl = 0UL,
+    .yCtl = 0UL,
+    .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t RxDma_channelConfig = 
+{
+    .descriptor = &RxDma_Descriptor_0,
+    .preemptable = false,
+    .priority = 3,
+    .enable = false,
+    .bufferable = false,
+};
+const cy_stc_dma_crc_config_t RxDma_crcConfig = 
+{
+    .dataReverse = false,
+    .dataXor = 0,
+    .reminderReverse = false,
+    .reminderXor = 0,
+    .polynomial = 79764919,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t RxDma_obj = 
+    {
+        .type = CYHAL_RSC_DMA,
+        .block_num = 0U,
+        .channel_num = RxDma_CHANNEL,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_dmas(void)
+{
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&TxDma_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&RxDma_obj);
+#endif //defined (CY_USING_HAL)
+}

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h

@@ -0,0 +1,76 @@
+/*******************************************************************************
+* File Name: cycfg_dmas.h
+*
+* Description:
+* DMA configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.14850
+* personalities 6.0.0.0
+* udd 3.0.0.2024
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_DMAS_H)
+#define CYCFG_DMAS_H
+
+#include "cycfg_notices.h"
+#include "cy_dma.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define TxDma_ENABLED 1U
+#define TxDma_HW DW0
+#define TxDma_CHANNEL 26U
+#define TxDma_IRQ cpuss_interrupts_dw0_26_IRQn
+#define RxDma_ENABLED 1U
+#define RxDma_HW DW0
+#define RxDma_CHANNEL 27U
+#define RxDma_IRQ cpuss_interrupts_dw0_27_IRQn
+
+extern const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config;
+extern cy_stc_dma_descriptor_t TxDma_Descriptor_0;
+extern const cy_stc_dma_channel_config_t TxDma_channelConfig;
+extern const cy_stc_dma_crc_config_t TxDma_crcConfig;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t TxDma_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config;
+extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config;
+extern cy_stc_dma_descriptor_t RxDma_Descriptor_0;
+extern cy_stc_dma_descriptor_t RxDma_Descriptor_1;
+extern const cy_stc_dma_channel_config_t RxDma_channelConfig;
+extern const cy_stc_dma_crc_config_t RxDma_crcConfig;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t RxDma_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_dmas(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_DMAS_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -0,0 +1,41 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+#ifdef CY_SUPPORTS_DEVICE_VALIDATION
+#ifndef CY8C624ABZI_S2D44
+    #error "Unexpected target MCU; expected CY8C624ABZI-S2D44. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
+
+#endif /* CYCFG_NOTICES_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -0,0 +1,41 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+cy_stc_csd_context_t cy_csd_0_context = 
+{
+    .lockKey = CY_CSD_NONE_KEY,
+};
+
+
+void init_cycfg_peripherals(void)
+{
+    Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+}

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -0,0 +1,87 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_csd.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_ENABLED 1U
+#define CY_CAPSENSE_CORE 4u
+#define CY_CAPSENSE_CPU_CLK 100000000u
+#define CY_CAPSENSE_PERI_CLK 100000000u
+#define CY_CAPSENSE_VDDA_MV 3300u
+#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
+#define CY_CAPSENSE_PERI_DIV_INDEX 0u
+#define Cmod_PORT GPIO_PRT7
+#define CintA_PORT GPIO_PRT7
+#define CintB_PORT GPIO_PRT7
+#define Button0_Rx0_PORT GPIO_PRT1
+#define Button0_Tx_PORT GPIO_PRT8
+#define Button1_Rx0_PORT GPIO_PRT1
+#define Button1_Tx_PORT GPIO_PRT8
+#define LinearSlider0_Sns0_PORT GPIO_PRT8
+#define LinearSlider0_Sns1_PORT GPIO_PRT8
+#define LinearSlider0_Sns2_PORT GPIO_PRT8
+#define LinearSlider0_Sns3_PORT GPIO_PRT8
+#define LinearSlider0_Sns4_PORT GPIO_PRT8
+#define Cmod_PIN 7u
+#define CintA_PIN 1u
+#define CintB_PIN 2u
+#define Button0_Rx0_PIN 0u
+#define Button0_Tx_PIN 1u
+#define Button1_Rx0_PIN 0u
+#define Button1_Tx_PIN 2u
+#define LinearSlider0_Sns0_PIN 3u
+#define LinearSlider0_Sns1_PIN 4u
+#define LinearSlider0_Sns2_PIN 5u
+#define LinearSlider0_Sns3_PIN 6u
+#define LinearSlider0_Sns4_PIN 7u
+#define Cmod_PORT_NUM 7u
+#define CintA_PORT_NUM 7u
+#define CintB_PORT_NUM 7u
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+
+extern cy_stc_csd_context_t cy_csd_0_context;
+
+void init_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -0,0 +1,488 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_IN_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_IN_PORT_NUM,
+        .channel_num = CYBSP_WCO_IN_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_OUT_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_OUT_PORT_NUM,
+        .channel_num = CYBSP_WCO_OUT_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_RX_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_RX_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_RX_PORT_NUM,
+        .channel_num = CYBSP_CSD_RX_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+    .hsiom = CYBSP_SWO_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWO_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWO_PORT_NUM,
+        .channel_num = CYBSP_SWO_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLUP,
+    .hsiom = CYBSP_SWDIO_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDIO_PORT_NUM,
+        .channel_num = CYBSP_SWDIO_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLDOWN,
+    .hsiom = CYBSP_SWDCK_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDCK_PORT_NUM,
+        .channel_num = CYBSP_SWDCK_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CINA_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CINA_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CINA_PORT_NUM,
+        .channel_num = CYBSP_CINA_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CINB_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CINB_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CINB_PORT_NUM,
+        .channel_num = CYBSP_CINB_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CMOD_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CMOD_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CMOD_PORT_NUM,
+        .channel_num = CYBSP_CMOD_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_BTN0_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_BTN0_PORT_NUM,
+        .channel_num = CYBSP_CSD_BTN0_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_BTN1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_BTN1_PORT_NUM,
+        .channel_num = CYBSP_CSD_BTN1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD0_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD0_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD0_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD1_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD2_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD2_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD2_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD3_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD3_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD3_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD4_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD4_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD4_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_pins(void)
+{
+    Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
+}

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -0,0 +1,271 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 2.20.0.2857
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xECU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_QUAD,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0x01U,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 4U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x06U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x04U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xDCU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x60U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x34U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x35U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x05U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x01U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+{
+    /* Specifies the number of address bytes used by the memory slave device. */
+    .numOfAddrBytes = 0x04U,
+    /* The size of the memory. */
+    .memSize = 0x04000000U,
+    /* Specifies the Read command. */
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
+    /* Specifies the Write Enable command. */
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
+    /* Specifies the Write Disable command. */
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
+    /* Specifies the Erase command. */
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
+    /* Specifies the sector size of each erase. */
+    .eraseSize = 0x00040000U,
+    /* Specifies the Chip Erase command. */
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
+    /* Specifies the Program command. */
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
+    /* Specifies the page size for programming. */
+    .programSize = 0x00000200U,
+    /* Specifies the command to read the QE-containing status register. */
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    /* Specifies the command to read the WIP-containing status register. */
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    /* Specifies the command to write into the QE-containing status register. */
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    /* The mask for the status register. */
+    .stsRegBusyMask = 0x01U,
+    /* The mask for the status register. */
+    .stsRegQuadEnableMask = 0x02U,
+    /* The max time for the erase type-1 cycle-time in ms. */
+    .eraseTime = 2600U,
+    /* The max time for the chip-erase cycle-time in ms. */
+    .chipEraseTime = 460000U,
+    /* The max time for the page-program cycle-time in us. */
+    .programTime = 1300U,
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+    /* Points to NULL or to structure with info about sectors for hybrid memory. */
+    .hybridRegionCount = 0U,
+    .hybridRegionInfo = NULL
+#endif
+};
+
+const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+{
+    /* Determines the slot number where the memory device is placed. */
+    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+    /* Flags. */
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
+    /* The data-line selection options for a slave device. */
+    .dataSelect = CY_SMIF_DATA_SEL0,
+    /* The base address the memory slave is mapped to in the PSoC memory map.
+    Valid when the memory-mapped mode is enabled. */
+    .baseAddress = 0x18000000U,
+    /* The size allocated in the PSoC memory map, for the memory slave device.
+    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+    .memMappedSize = 0x4000000U,
+    /* If this memory device is one of the devices in the dual quad SPI configuration.
+    Valid when the memory mapped mode is enabled. */
+    .dualQuadSlots = 0,
+    /* The configuration of the device. */
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+    /* The number of SMIF memories defined. */
+    .memCount = CY_SMIF_DEVICE_NUM,
+    /* The pointer to the array of memory config structures of size memCount. */
+    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+    /* The version of the SMIF driver. */
+    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+    /* The version of the SMIF driver. */
+    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
+

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -0,0 +1,65 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 2.20.0.2857
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_CFG_TOOL_VERSION           (220)
+
+/* Supported QSPI Driver version */
+#define CY_SMIF_DRV_VERSION_REQUIRED       (100)
+
+#if !defined(CY_SMIF_DRV_VERSION)
+    #define CY_SMIF_DRV_VERSION            (100)
+#endif
+
+/* Check the used Driver version */
+#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
+   #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
+#endif
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CYCFG_QSPI_MEMSLOT_H*/
+

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -0,0 +1,44 @@
+/*******************************************************************************
+* File Name: cycfg_routing.c
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_routing.h"
+
+#include "cy_device_headers.h"
+
+void init_cycfg_routing(void)
+{
+    HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+    HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+}

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+void init_cycfg_routing(void);
+#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
+#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
+#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -0,0 +1,116 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_pra.h"
+#include "cy_pra_cfg.h"
+#include "cy_systick.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_pathmux_5_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg

@@ -0,0 +1,29 @@
+################################################################################
+# File Name: qspi_config.cfg
+#
+# Description:
+# This file contains a SMIF Bank layout for use with OpenOCD.
+# This file was automatically generated and should not be modified.
+# QSPI Configurator: 2.20.0.2857
+#
+################################################################################
+# Copyright 2020 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,20 @@
+[Device=CY8C624ABZI-S2D44]
+
+[Blocks]
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense

@@ -0,0 +1,415 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by CapSense Configurator 4.0.0.5470-->
+<Configuration app="Capsense" major="4" minor="0" lastSavedWithToolName="CapSense Configurator" formatVersion="1">
+    <DesignProperties>
+        <Property id="DEVICE_TYPE" value="P6_CSDV2"/>
+    </DesignProperties>
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="BIST_EN" value="false"/>
+        <Property id="BIST_SHIELD_CAP_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_SNS_CAP_CSD_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_SNS_CAP_CSX_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_FINE_INIT_TIME" value="10"/>
+        <Property id="BIST_ELTD_CAP_MOD_CLC_DIVIDER" value="2"/>
+        <Property id="BIST_ELTD_CAP_SNS_CLC_DIVIDER" value="0"/>
+        <Property id="BIST_ELTD_CAP_RESOLUTION" value="12"/>
+        <Property id="BIST_ELTD_CAP_VREF_MV" value="1200"/>
+        <Property id="BIST_SHORT_SETTLING_TIME" value="2"/>
+        <Property id="VDDA_MOD_CLK" value="2"/>
+        <Property id="VDDA_VREF_MV" value="1200"/>
+        <Property id="EXT_CAP_MOD_CLK" value="2"/>
+        <Property id="EXT_CAP_SNS_CLK" value="1024"/>
+        <Property id="EXT_CAP_VREF_MV" value="1200"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.2857-->
+<Configuration app="QSPI" major="2" minor="20">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <MemoryId>S25FL512S-4byteaddr</MemoryId>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct

@@ -0,0 +1,272 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm0plus.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
+; RAM
+#define RAM_START               0x08000000
+#define RAM_SIZE                0x00002000
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00002000
+
+; The size of the stack section at the end of CM0+ SRAM
+#define STACK_SIZE              0x00001000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+; Public RAM 
+; This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+; This region is used to place objects that require full access from both cores.
+; Uncomment the following lines, define the region size and uncomment placement of
+; .cy_sharedmem section below.
+; #define PUBLIC_RAM_SIZE         %REGION_SIZE%
+; #define PUBLIC_RAM_START        (RAM_START + RAM_SIZE - STACK_SIZE - PUBLIC_RAM_SIZE)
+
+; Cortex-M0+ application flash area
+LR_IROM1 FLASH_START FLASH_SIZE
+{
+    .cy_app_header +0
+    {
+        * (.cy_app_header)
+    }
+
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; To use unprotected public RAM uncomment the following .cy_sharedmem section placement. Recalculate the HEAP start address.
+    ;RW_IRAM2 PUBLIC_RAM_START UNINIT
+    ;{
+    ;    * (.cy_sharedmem)
+    ;}
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    { 
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.s

@@ -0,0 +1,223 @@
+;/**************************************************************************//**
+; * @file     startup_psoc6_02_cm0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device Series
+; * @version  V5.00
+; * @date     02. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
+                
+__Vectors       DCD    |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack
+
+                DCD     Reset_Handler             ; Reset Handler
+
+                DCD     0x0000000D                ; NMI Handler located at ROM code
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External interrupts                           Description
+                DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0 
+                DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1 
+                DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2 
+                DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3 
+                DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4 
+                DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5 
+                DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6 
+                DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7 
+                DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0 
+                DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1 
+                DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2 
+                DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3 
+                DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4 
+                DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5 
+                DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6 
+                DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7 
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+                EXPORT __ramVectors
+                AREA    RESET_RAM, READWRITE, NOINIT
+__ramVectors    SPACE   __Vectors_Size
+
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Weak function for startup customization
+;
+; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+; because this function is executed as the first instruction in the ResetHandler.
+; The PDL is also not initialized to use the proper register offsets.
+; The user of this function is responsible for initializing the PDL and resources before using them.
+;
+Cy_OnResetUser  PROC
+                EXPORT  Cy_OnResetUser            [WEAK]
+                BX      LR
+                ENDP
+
+; Reset Handler
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  __main
+
+                ; Define strong function for startup customization
+                BL      Cy_OnResetUser
+
+                ; Disable global interrupts
+                CPSID I
+
+                ; Copy vectors from ROM to RAM
+                LDR r1, =__Vectors
+                LDR r0, =__ramVectors
+                LDR r2, =__Vectors_Size
+Vectors_Copy
+                LDR r3, [r1]
+                STR r3, [r0]
+                ADDS r0, r0, #4
+                ADDS r1, r1, #4
+                SUBS r2, r2, #1
+                CMP r2, #0
+                BNE Vectors_Copy
+
+                ; Update Vector Table Offset Register. */
+                LDR r0, =__ramVectors
+                LDR r1, =0xE000ED08
+                STR r0, [r1]
+                dsb 0xF
+
+                LDR     R0, =__main
+                BLX     R0
+
+                ; Should never get here
+                B       .
+
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler         PROC
+                    EXPORT  NMI_Handler               [WEAK]
+                    B       .
+                    ENDP
+
+Cy_SysLib_FaultHandler PROC
+                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
+                    B       .
+                    ENDP
+
+HardFault_Handler   PROC
+                    EXPORT HardFault_Handler          [WEAK]
+                    movs r0, #4
+                    mov r1, LR
+                    tst r0, r1
+                    beq L_MSP
+                    mrs r0, PSP
+                    bl L_API_call
+L_MSP
+                    mrs r0, MSP
+L_API_call
+                    bl Cy_SysLib_FaultHandler
+                    ENDP
+
+SVC_Handler         PROC
+                    EXPORT  SVC_Handler               [WEAK]
+                    B       .
+                    ENDP
+PendSV_Handler      PROC
+                    EXPORT  PendSV_Handler            [WEAK]
+                    B       .
+                    ENDP
+SysTick_Handler     PROC
+                    EXPORT  SysTick_Handler           [WEAK]
+                    B       .
+                    ENDP
+
+Default_Handler     PROC
+                    EXPORT  Default_Handler                       [WEAK]
+                    EXPORT  NvicMux0_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux1_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux2_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux3_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux4_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux5_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux6_IRQHandler                   [WEAK]
+                    EXPORT  NvicMux7_IRQHandler                   [WEAK]
+                    EXPORT  Internal0_IRQHandler                  [WEAK]
+                    EXPORT  Internal1_IRQHandler                  [WEAK]
+                    EXPORT  Internal2_IRQHandler                  [WEAK]
+                    EXPORT  Internal3_IRQHandler                  [WEAK]
+                    EXPORT  Internal4_IRQHandler                  [WEAK]
+                    EXPORT  Internal5_IRQHandler                  [WEAK]
+                    EXPORT  Internal6_IRQHandler                  [WEAK]
+                    EXPORT  Internal7_IRQHandler                  [WEAK]
+
+NvicMux0_IRQHandler
+NvicMux1_IRQHandler
+NvicMux2_IRQHandler
+NvicMux3_IRQHandler
+NvicMux4_IRQHandler
+NvicMux5_IRQHandler
+NvicMux6_IRQHandler
+NvicMux7_IRQHandler
+Internal0_IRQHandler
+Internal1_IRQHandler
+Internal2_IRQHandler
+Internal3_IRQHandler
+Internal4_IRQHandler
+Internal5_IRQHandler
+Internal6_IRQHandler
+Internal7_IRQHandler
+
+                B       .
+                ENDP
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+                IMPORT   __use_two_region_memory
+
+                END
+
+
+; [] END OF FILE

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_A_Clang/startup_psoc6_02_cm0plus.S

@@ -0,0 +1,254 @@
+/**************************************************************************//**
+ * @file     startup_psoc6_02_cm0plus.S
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+    /* Address of the NMI handler */
+    #define CY_NMI_HANLDER_ADDR         0x0000000D
+
+    /* The CPU VTOR register */
+    #define CY_CPU_VTOR_ADDR            0xE000ED08
+
+    .syntax    unified
+
+    .section __STACK, __stack
+    .align    3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x00001000
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+
+__StackLimit:
+    .space    Stack_Size
+    .equ    __StackTop, . - Stack_Size
+
+    .section __HEAP, __heap
+    .align    3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x00000400
+#endif
+    .globl    __HeapBase
+__HeapBase:
+    .if    Heap_Size
+    .space    Heap_Size
+    .endif
+
+    .section __VECT, ___Vectors
+    .align 2
+    .globl    ___Vectors
+___Vectors:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+     /* External interrupts                             Description */
+    .long    NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    .long    NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    .long    NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    .long    NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    .long    NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    .long    NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    .long    NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    .long    NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    .long    Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    .long    Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    .long    Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    .long    Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    .long    Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    .long    Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    .long    Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    .long    Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .equ    __VectorsSize, . - ___Vectors
+
+    .section __RAMVECTORS, ___ramVectors
+    .align 2
+    .globl ___ramVectors
+
+___ramVectors:
+    .space  __VectorsSize
+
+
+    .text
+    .thumb_func
+    .align 2
+    /* Reset handler */
+    .globl Reset_Handler
+
+Reset_Handler:
+    bl Cy_OnResetUser
+    cpsid i
+
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r0, =___ramVectors
+    ldr    r1, =___Vectors
+    ldr    r2, =__VectorsSize
+    bl     _memcpy
+
+    ldr    r0, =segment$start$__DATA
+    ldr    r1, =segment$end$__TEXT
+    ldr    r2, =section$start$__DATA$__zerofill
+    sub    r2, r0
+    bl     _memcpy
+
+    ldr    r0, =section$start$__DATA$__zerofill
+    eor    r1, r1
+    ldr    r2, =section$end$__DATA$__zerofill
+    sub    r2, r0
+    bl     _memset
+
+    /* Update Vector Table Offset Register. */
+    ldr r0, =___ramVectors
+    ldr r1, =CY_CPU_VTOR_ADDR
+    str r0, [r1]
+    dsb 0xF
+
+    bl _HeapInit
+#ifndef __NO_SYSTEM_INIT
+    bl  _SystemInit
+#endif
+
+    bl  _main
+
+    /* Should never get here */
+    b   .
+
+    .pool
+
+    .text
+    .thumb
+    .thumb_func
+    .align 2
+
+    /* Device startup customization */
+    .weak_definition   Cy_OnResetUser
+    .global Cy_OnResetUser, Cy_OnResetUser
+Cy_OnResetUser:
+    bx lr
+
+    .text
+    .align    1
+    .thumb_func
+    .weak_reference    Default_Handler
+
+Default_Handler:
+    b    .
+
+    .text
+    .thumb_func
+    .align  2
+    .weak_definition    Cy_SysLib_FaultHandler
+
+Cy_SysLib_FaultHandler:
+    b    .
+
+    .text
+    .thumb_func
+    .align  2
+
+Fault_Handler:
+    /* Storing LR content for Creator call stack trace */
+    push {LR}
+    movs r0, #4
+    mov r1, LR
+    tst r0, r1
+    beq .L_MSP
+    mrs r0, PSP
+    b .L_API_call
+.L_MSP:
+    mrs r0, MSP
+    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+    adds r0, r0, #4
+    nop
+.L_API_call:
+    bl Cy_SysLib_FaultHandler
+    b   .
+
+.macro    def_fault_Handler    fault_handler_name
+    .weak_definition    \fault_handler_name
+    .set    \fault_handler_name, Fault_Handler
+    .endm
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_irq_handler    handler_name
+    .weak_definition    \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler    NMI_Handler
+
+    def_fault_Handler  HardFault_Handler
+
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+
+    def_irq_handler  NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    def_irq_handler  NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    def_irq_handler  NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    def_irq_handler  NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    def_irq_handler  NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    def_irq_handler  NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    def_irq_handler  NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    def_irq_handler  NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    def_irq_handler  Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    def_irq_handler  Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    def_irq_handler  Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    def_irq_handler  Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    def_irq_handler  Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    def_irq_handler  Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    def_irq_handler  Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    def_irq_handler  Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .end
+
+
+/* [] END OF FILE */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld

@@ -0,0 +1,441 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm0plus.ld
+* \version 2.91
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM0+ SRAM */
+STACK_SIZE = 0x1000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+     * Using this memory region for other purposes will lead to unexpected behavior.
+     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
+     * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
+     */
+    ram               (rwx)   : ORIGIN = 0x08000000, LENGTH = 0x2000
+    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x2000
+
+
+    /* This is an unprotected public RAM region, with the placed .cy_sharedmem.
+     * This region is used to place objects that require full access from both cores.
+     * Uncomment the following line, define the region origin and length, and uncomment the placement of
+     * the .cy_sharedmem section below.
+     */
+    /* public_ram        (rw)    : ORIGIN = %REGION_START_ADDRESS%, LENGTH = %REGION_SIZE% */
+
+    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+     * You can assign sections to this memory region for only one of the cores.
+     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+     * Therefore, repurposing this memory region will prevent such middleware from operation.
+     */
+    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
+
+    /* The following regions define device specific memory regions and must not be changed. */
+    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
+    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
+    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
+    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
+    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
+    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
+    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+
+
+SECTIONS
+{
+    .cy_app_header :
+    {
+        KEEP(*(.cy_app_header))
+    } > flash
+
+    /* Cortex-M0+ application flash area */
+    .text :
+    {
+        . = ALIGN(4);
+        __Vectors = . ;
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        . = ALIGN(4);
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* Read-only code (constants). */
+        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+        KEEP(*(.eh_frame*))
+    } > flash
+
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    __exidx_start = .;
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash
+    __exidx_end = .;
+
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+
+        /* Copy interrupt vectors from flash to RAM */
+        LONG (__Vectors)                                    /* From */
+        LONG (__ram_vectors_start__)                        /* To   */
+        LONG (__Vectors_End - __Vectors)                    /* Size */
+
+        /* Copy data section to RAM */
+        LONG (__etext)                                      /* From */
+        LONG (__data_start__)                               /* To   */
+        LONG (__data_end__ - __data_start__)                /* Size */
+
+        __copy_table_end__ = .;
+    } > flash
+
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm0plus.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > flash
+
+    __etext =  . ;
+
+
+    .ramVectors (NOLOAD) : ALIGN(8)
+    {
+        __ram_vectors_start__ = .;
+        KEEP(*(.ram_vectors))
+        __ram_vectors_end__   = .;
+    } > ram
+
+
+    .data __ram_vectors_end__ :
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        KEEP(*(.cy_ramfunc*))
+        . = ALIGN(4);
+
+        __data_end__ = .;
+
+    } > ram AT>flash
+
+
+    /* Place variables in the section that should not be initialized during the
+    *  device startup.
+    */
+    .noinit (NOLOAD) : ALIGN(8)
+    {
+      KEEP(*(.noinit))
+    } > ram
+
+
+    /* The uninitialized global or static variables are placed in this section.
+    *
+    * The NOLOAD attribute tells linker that .bss section does not consume
+    * any space in the image. The NOLOAD attribute changes the .bss type to
+    * NOBITS, and that  makes linker to A) not allocate section in memory, and
+    * A) put information to clear the section with all zeros during application
+    * loading.
+    *
+    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+    * This  makes linker to A) allocate zeroed section in memory, and B) copy
+    * this section to RAM during application loading.
+    */
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram
+
+
+    .heap (NOLOAD):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+        __HeapLimit = .;
+    } > ram
+
+
+    /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/
+    /*
+    .cy_sharedmem (NOLOAD):
+    {
+        . = ALIGN(4);
+        __public_ram_start__ = .;
+        KEEP(*(.cy_sharedmem))
+        . = ALIGN(4);
+        __public_ram_end__ = .;
+    } > public_ram
+    */
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        KEEP(*(.stack*))
+    } > ram
+
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(ram) + LENGTH(ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+    /* Emulated EEPROM Flash area */
+    .cy_em_eeprom :
+    {
+        KEEP(*(.cy_em_eeprom))
+    } > em_eeprom
+
+
+    /* Supervisory Flash: User data */
+    .cy_sflash_user_data :
+    {
+        KEEP(*(.cy_sflash_user_data))
+    } > sflash_user_data
+
+
+    /* Supervisory Flash: Normal Access Restrictions (NAR) */
+    .cy_sflash_nar :
+    {
+        KEEP(*(.cy_sflash_nar))
+    } > sflash_nar
+
+
+    /* Supervisory Flash: Public Key */
+    .cy_sflash_public_key :
+    {
+        KEEP(*(.cy_sflash_public_key))
+    } > sflash_public_key
+
+
+    /* Supervisory Flash: Table of Content # 2 */
+    .cy_toc_part2 :
+    {
+        KEEP(*(.cy_toc_part2))
+    } > sflash_toc_2
+
+
+    /* Supervisory Flash: Table of Content # 2 Copy */
+    .cy_rtoc_part2 :
+    {
+        KEEP(*(.cy_rtoc_part2))
+    } > sflash_rtoc_2
+
+
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+    *  documentation for details.
+    */
+    cy_xip :
+    {
+        __cy_xip_start = .;
+        KEEP(*(.cy_xip))
+        __cy_xip_end = .;
+    } > xip
+
+
+    /* eFuse */
+    .cy_efuse :
+    {
+        KEEP(*(.cy_efuse))
+    } > efuse
+
+
+    /* These sections are used for additional metadata (silicon revision,
+    *  Silicon/JTAG ID, etc.) storage.
+    */
+    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start    = 0x10000000;
+__cy_memory_0_length   = 0x00200000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start    = 0x14000000;
+__cy_memory_1_length   = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start    = 0x16000000;
+__cy_memory_2_length   = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start    = 0x18000000;
+__cy_memory_3_length   = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start    = 0x90700000;
+__cy_memory_4_length   = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S

@@ -0,0 +1,372 @@
+/**************************************************************************//**
+ * @file     startup_psoc6_02_cm0plus.S
+ * @brief    CMSIS Core Device Startup File for
+ *           ARMCM0plus Device Series
+ * @version  V5.00
+ * @date     02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+    /* Address of the NMI handler */
+    #define CY_NMI_HANLDER_ADDR         0x0000000D
+
+    /* The CPU VTOR register */
+    #define CY_CPU_VTOR_ADDR            0xE000ED08
+
+    /* Copy flash vectors and data section to RAM */
+    #define __STARTUP_COPY_MULTIPLE
+
+    /* Clear single BSS section */
+    #define __STARTUP_CLEAR_BSS
+
+    .syntax    unified
+    .arch    armv6-m
+
+    .section .stack
+    .align    3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x00001000
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size    __StackLimit, . - __StackLimit
+__StackTop:
+    .size    __StackTop, . - __StackTop
+
+    .section .heap
+    .align    3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x00000400
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .if    Heap_Size
+    .space    Heap_Size
+    .endif
+    .size    __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size    __HeapLimit, . - __HeapLimit
+
+    .section .vectors
+    .align 2
+    .globl    __Vectors
+__Vectors:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+     /* External interrupts                             Description */
+    .long    NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    .long    NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    .long    NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    .long    NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    .long    NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    .long    NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    .long    NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    .long    NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    .long    Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    .long    Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    .long    Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    .long    Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    .long    Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    .long    Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    .long    Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    .long    Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .size    __Vectors, . - __Vectors
+    .equ    __VectorsSize, . - __Vectors
+
+    .section .ram_vectors
+    .align 2
+    .globl __ramVectors
+__ramVectors:
+    .space  __VectorsSize
+    .size   __ramVectors, . - __ramVectors
+
+
+    .text
+    .thumb
+    .thumb_func
+    .align  2
+
+    /* 
+     * Device startup customization 
+     *
+     * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
+     * because this function is executed as the first instruction in the ResetHandler.
+     * The PDL is also not initialized to use the proper register offsets.
+     * The user of this function is responsible for initializing the PDL and resources before using them.
+     */
+    .weak   Cy_OnResetUser
+    .func   Cy_OnResetUser, Cy_OnResetUser
+    .type   Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+    bx lr
+    .size   Cy_OnResetUser, . - Cy_OnResetUser
+    .endfunc
+
+    /* Reset handler */
+    .weak    Reset_Handler
+    .type    Reset_Handler, %function
+
+Reset_Handler:
+    bl Cy_OnResetUser
+    cpsid i
+
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r4, =__copy_table_start__
+    ldr    r5, =__copy_table_end__
+
+.L_loop0:
+    cmp    r4, r5
+    bge    .L_loop0_done
+    ldr    r1, [r4]
+    ldr    r2, [r4, #4]
+    ldr    r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    blt    .L_loop0_0_done
+    ldr    r0, [r1, r3]
+    str    r0, [r2, r3]
+    b    .L_loop0_0
+
+.L_loop0_0_done:
+    adds    r4, #12
+    b    .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble    .L_loop1_done
+
+.L_loop1:
+    subs    r3, #4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr    r3, =__zero_table_start__
+    ldr    r4, =__zero_table_end__
+
+.L_loop2:
+    cmp    r3, r4
+    bge    .L_loop2_done
+    ldr    r1, [r3]
+    ldr    r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    blt    .L_loop2_0_done
+    str    r0, [r1, r2]
+    b    .L_loop2_0
+.L_loop2_0_done:
+
+    adds    r3, #8
+    b    .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r1, =__bss_start__
+    ldr    r2, =__bss_end__
+
+    movs    r0, 0
+
+    subs    r2, r1
+    ble    .L_loop3_done
+
+.L_loop3:
+    subs    r2, #4
+    str    r0, [r1, r2]
+    bgt    .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+    /* Update Vector Table Offset Register. */
+    ldr r0, =__ramVectors
+    ldr r1, =CY_CPU_VTOR_ADDR
+    str r0, [r1]
+    dsb 0xF
+
+#ifndef __NO_SYSTEM_INIT
+    bl    SystemInit
+#endif
+
+    bl    main
+
+    /* Should never get here */
+    b   .
+
+    .pool
+    .size    Reset_Handler, . - Reset_Handler
+
+    .align    1
+    .thumb_func
+    .weak    Default_Handler
+    .type    Default_Handler, %function
+Default_Handler:
+    b    .
+    .size    Default_Handler, . - Default_Handler
+    .weak    Cy_SysLib_FaultHandler
+    .type    Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+    b    .
+    .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+    .type Fault_Handler, %function
+
+Fault_Handler:
+    /* Storing LR content for Creator call stack trace */
+    push {LR}
+    movs r0, #4
+    mov r1, LR
+    tst r0, r1
+    beq .L_MSP
+    mrs r0, PSP
+    b .L_API_call
+.L_MSP:
+    mrs r0, MSP
+    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+    adds r0, r0, #4
+.L_API_call:
+    bl Cy_SysLib_FaultHandler
+    b   .
+    .size    Fault_Handler, . - Fault_Handler
+
+.macro    def_fault_Handler    fault_handler_name
+    .weak    \fault_handler_name
+    .set    \fault_handler_name, Fault_Handler
+    .endm
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_irq_handler    handler_name
+    .weak    \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler    NMI_Handler
+
+    def_fault_Handler  HardFault_Handler
+
+    def_irq_handler    SVC_Handler
+    def_irq_handler    PendSV_Handler
+    def_irq_handler    SysTick_Handler
+
+    def_irq_handler  NvicMux0_IRQHandler                     /* CPU User Interrupt #0 */
+    def_irq_handler  NvicMux1_IRQHandler                     /* CPU User Interrupt #1 */
+    def_irq_handler  NvicMux2_IRQHandler                     /* CPU User Interrupt #2 */
+    def_irq_handler  NvicMux3_IRQHandler                     /* CPU User Interrupt #3 */
+    def_irq_handler  NvicMux4_IRQHandler                     /* CPU User Interrupt #4 */
+    def_irq_handler  NvicMux5_IRQHandler                     /* CPU User Interrupt #5 */
+    def_irq_handler  NvicMux6_IRQHandler                     /* CPU User Interrupt #6 */
+    def_irq_handler  NvicMux7_IRQHandler                     /* CPU User Interrupt #7 */
+    def_irq_handler  Internal0_IRQHandler                    /* Internal SW Interrupt #0 */
+    def_irq_handler  Internal1_IRQHandler                    /* Internal SW Interrupt #1 */
+    def_irq_handler  Internal2_IRQHandler                    /* Internal SW Interrupt #2 */
+    def_irq_handler  Internal3_IRQHandler                    /* Internal SW Interrupt #3 */
+    def_irq_handler  Internal4_IRQHandler                    /* Internal SW Interrupt #4 */
+    def_irq_handler  Internal5_IRQHandler                    /* Internal SW Interrupt #5 */
+    def_irq_handler  Internal6_IRQHandler                    /* Internal SW Interrupt #6 */
+    def_irq_handler  Internal7_IRQHandler                    /* Internal SW Interrupt #7 */
+
+    .end
+
+
+/* [] END OF FILE */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf

@@ -0,0 +1,253 @@
+/*******************************************************************************
+* \file cy8c6xxa_cm0plus.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM0+ core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x08001FFF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x10001FFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+/* Public RAM 
+ * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
+ * This region is used to place objects that require full access from both cores.
+ * Uncomment the following lines, define region size, and uncomment the placement of
+ * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
+ *  and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
+ */
+/*
+define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
+*/
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application */
+".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
+place in          IROM1_region  { block RO };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* Public RAM 
+ *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
+ */
+/*
+place at start of IRAM2_region  { section .cy_sharedmem };
+*/
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_app_header,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

bsp/cypress/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.s

@@ -0,0 +1,331 @@
+;/**************************************************************************//**
+; * @file     startup_psoc6_02_cm0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device Series
+; * @version  V5.00
+; * @date     08. March 2016
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec_ram:DATA:NOROOT(2)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        EXTERN __iar_data_init3
+        EXTERN __iar_dynamic_initialization        
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+        PUBLIC  __ramVectors
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     0x0000000D      ; NMI_Handler is defined in ROM code
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External interrupts                           Description
+        DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0
+        DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1
+        DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2
+        DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3
+        DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4
+        DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5
+        DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6
+        DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7
+        DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0
+        DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1
+        DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2
+        DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3
+        DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4
+        DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5
+        DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6
+        DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+        SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
+__ramVectors
+        DS32     __Vectors_Size
+
+
+        THUMB
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default handlers
+;;
+        PUBWEAK Default_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Default_Handler
+        B Default_Handler
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Weak function for startup customization
+;;
+;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
+;; because this function is executed as the first instruction in the ResetHandler.
+;; The PDL is also not initialized to use the proper register offsets.
+;; The user of this function is responsible for initializing the PDL and resources before using them.
+;;
+        PUBWEAK Cy_OnResetUser
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_OnResetUser
+        BX LR
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Define strong version to return zero for
+;; __iar_program_start to skip data sections
+;; initialization.
+;;
+        PUBLIC __low_level_init
+        SECTION .text:CODE:REORDER:NOROOT(2)
+__low_level_init
+        MOVS R0, #0
+        BX LR
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+
+        ; Define strong function for startup customization
+        LDR     R0, =Cy_OnResetUser
+        BLX     R0
+
+        ; Disable global interrupts
+        CPSID I
+
+        ; Copy vectors from ROM to RAM
+        LDR r1, =__vector_table
+        LDR r0, =__ramVectors
+        LDR r2, =__Vectors_Size
+intvec_copy
+        LDR r3, [r1]
+        STR r3, [r0]
+        ADDS r0, r0, #4
+        ADDS r1, r1, #4
+        SUBS r2, r2, #1
+        CMP r2, #0
+        BNE intvec_copy
+
+        ; Update Vector Table Offset Register
+        LDR r0, =__ramVectors
+        LDR r1, =0xE000ED08
+        STR r0, [r1]
+        dsb
+
+        ; Initialize data sections
+        LDR     R0, =__iar_data_init3
+        BLX     R0
+
+        ; --manual_dynamic_initialization
+        BL      __iar_dynamic_initialization
+
+        LDR     R0, =SystemInit
+        BLX     R0
+
+        LDR     R0, =__iar_program_start
+        BLX     R0
+
+; Should never get here
+Cy_Main_Exited
+        B Cy_Main_Exited
+
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+
+
+        PUBWEAK Cy_SysLib_FaultHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Cy_SysLib_FaultHandler
+        B Cy_SysLib_FaultHandler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        IMPORT Cy_SysLib_FaultHandler
+        movs r0, #4
+        mov r1, LR
+        tst r0, r1
+        beq L_MSP
+        mrs r0, PSP
+        b L_API_call
+L_MSP
+        mrs r0, MSP
+L_API_call
+        ; Storing LR content for Creator call stack trace
+        push {LR}
+        bl Cy_SysLib_FaultHandler
+
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+
+
+        ; External interrupts
+        PUBWEAK NvicMux0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux0_IRQHandler
+        B       NvicMux0_IRQHandler
+
+        PUBWEAK NvicMux1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux1_IRQHandler
+        B       NvicMux1_IRQHandler
+
+        PUBWEAK NvicMux2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux2_IRQHandler
+        B       NvicMux2_IRQHandler
+
+        PUBWEAK NvicMux3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux3_IRQHandler
+        B       NvicMux3_IRQHandler
+
+        PUBWEAK NvicMux4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux4_IRQHandler
+        B       NvicMux4_IRQHandler
+
+        PUBWEAK NvicMux5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux5_IRQHandler
+        B       NvicMux5_IRQHandler
+
+        PUBWEAK NvicMux6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux6_IRQHandler
+        B       NvicMux6_IRQHandler
+
+        PUBWEAK NvicMux7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NvicMux7_IRQHandler
+        B       NvicMux7_IRQHandler
+
+        PUBWEAK Internal0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal0_IRQHandler
+        B       Internal0_IRQHandler
+
+        PUBWEAK Internal1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal1_IRQHandler
+        B       Internal1_IRQHandler
+
+        PUBWEAK Internal2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal2_IRQHandler
+        B       Internal2_IRQHandler
+
+        PUBWEAK Internal3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal3_IRQHandler
+        B       Internal3_IRQHandler
+
+        PUBWEAK Internal4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal4_IRQHandler
+        B       Internal4_IRQHandler
+
+        PUBWEAK Internal5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal5_IRQHandler
+        B       Internal5_IRQHandler
+
+        PUBWEAK Internal6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal6_IRQHandler
+        B       Internal6_IRQHandler
+
+        PUBWEAK Internal7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Internal7_IRQHandler
+        B       Internal7_IRQHandler
+
+
+        END
+
+
+; [] END OF FILE