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update eth driver and clean code

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This commit is contained in:
tanek liang
2017-08-30 10:10:32 +08:00
parent 0ecc0f96f5
commit b7cf7c5fc0
4 changed files with 239 additions and 342 deletions
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47
bsp/gd32450z-eval/drivers/board.c
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@@ -19,11 +19,6 @@
#include <board.h>
#include <drv_usart.h>
void _init(void)
{
}
/**
* @brief This function is executed in case of error occurrence.
* @param None
@@ -43,48 +38,6 @@ void Error_Handler(void)
*/
void SystemClock_Config(void)
{
// RCC_OscInitTypeDef RCC_OscInitStruct;
// RCC_ClkInitTypeDef RCC_ClkInitStruct;
// RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
// __HAL_RCC_PWR_CLK_ENABLE();
// __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
// RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
// RCC_OscInitStruct.HSEState = RCC_HSE_ON;
// RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
// RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
// RCC_OscInitStruct.PLL.PLLM = 25;
// RCC_OscInitStruct.PLL.PLLN = 360;
// RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
// RCC_OscInitStruct.PLL.PLLQ = 8;
// if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
// {
// Error_Handler();
// }
// RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
// |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
// RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
// RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
// RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
// RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
// if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
// {
// Error_Handler();
// }
// PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
// PeriphClkInitStruct.PLLSAI.PLLSAIN = 260;
// PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
// PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
// if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
// {
// Error_Handler();
// }
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0);
}

18
bsp/gd32450z-eval/drivers/drv_enet.c
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@@ -59,17 +59,19 @@ struct gd32_emac
struct rt_synopsys_eth * ETHERNET_MAC;
IRQn_Type ETHER_MAC_IRQ;
ALIGN(RT_ALIGN_SIZE)
EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB], DMATxDscrTab[EMAC_TXBUFNB];
ALIGN(RT_ALIGN_SIZE)
rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
ALIGN(RT_ALIGN_SIZE)
rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE];
EMAC_DMADESCTypeDef *DMATxDescToSet;
EMAC_DMADESCTypeDef *DMARxDescToGet;
#pragma pack(4)
EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB];
#pragma pack(4)
EMAC_DMADESCTypeDef DMATxDscrTab[EMAC_TXBUFNB];
#pragma pack(4)
rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
#pragma pack(4)
rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE];
struct rt_semaphore tx_buf_free;
};

300
bsp/gd32450z-eval/project.ewp
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216
bsp/gd32450z-eval/project.uvprojx
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