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Merge pull request #2052 from jesven/lwp_ok

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add lwp support
This commit is contained in:
Bernard Xiong authored and GitHub committed 2018-12-10 20:00:25 +08:00
2 parents 92338d50c4 2b21d2316a
commit b628ac0e7e
31 files changed
+3165 -17
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bsp/allwinner_tina/libcpu/start_gcc.S
+4 -2
View File
@@ -48,7 +48,7 @@ _vector_reset:
_vector_undef:
.word vector_undef
_vector_swi:
.word vector_swi
.word SVC_Handler
_vector_pabt:
.word vector_pabt
_vector_dabt:
@@ -314,7 +314,9 @@ rt_hw_context_switch_interrupt_do:
str lr, [r0, #14*4]
.endm
.align 5
.align 5
.weak SVC_Handler
SVC_Handler:
vector_swi:
push_svc_reg
bl rt_hw_trap_swi
bsp/allwinner_tina/rtconfig.py
+2 -2
View File
@@ -2,7 +2,7 @@ import os
# toolchains options
ARCH ='arm'
CPU ='R6'
CPU ='arm9'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
@@ -55,4 +55,4 @@ if PLATFORM == 'gcc':
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
bsp/qemu-vexpress-a9/.config
+55 -4
View File
@@ -66,6 +66,7 @@ CONFIG_RT_USING_INTERRUPT_INFO=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40000
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_A=y
CONFIG_ARCH_ARM_CORTEX_A9=y
@@ -109,7 +110,7 @@ CONFIG_FINSH_ARG_MAX=10
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=8
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
@@ -165,10 +166,12 @@ CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
CONFIG_RT_USING_SPI_MSD=y
CONFIG_RT_USING_SFUD=y
CONFIG_RT_SFUD_USING_SFDP=y
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_USING_QSPI is not set
# CONFIG_RT_DEBUG_SFUD is not set
# CONFIG_RT_USING_W25QXX is not set
# CONFIG_RT_USING_GD is not set
@@ -298,6 +301,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_LOG_TRACE_USING_MEMLOG is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
CONFIG_RT_USING_LWP=y
#
# RT-Thread online packages
@@ -308,6 +312,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
@@ -333,6 +338,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
@@ -341,6 +347,7 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
#
# security packages
@@ -369,6 +376,9 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
#
# system packages
@@ -383,15 +393,24 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
@@ -405,16 +424,48 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
# CONFIG_PKG_USING_SAMPLES is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_MDNS is not set
# CONFIG_PKG_USING_UPNP is not set
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
CONFIG_SOC_VEXPRESS_A9=y
CONFIG_RT_USING_UART0=y
CONFIG_RT_USING_UART1=y
bsp/qemu-vexpress-a9/cpu/context_gcc.S
+25
View File
@@ -63,6 +63,11 @@ rt_hw_context_switch_to:
bl rt_cpus_lock_status_restore
#endif /*RT_USING_SMP*/
#ifdef RT_USING_LWP
ldmfd sp, {r13, r14}^ @ pop usr_sp usr_lr
add sp, #8
#endif
ldmfd sp!, {r4} @ pop new task spsr
msr spsr_cxsf, r4
@@ -89,6 +94,11 @@ rt_hw_context_switch:
stmfd sp!, {r4} @ push cpsr
#ifdef RT_USING_LWP
stmfd sp, {r13, r14}^ @ push usr_sp usr_lr
sub sp, #8
#endif
str sp, [r0] @ store sp in preempted tasks TCB
ldr sp, [r1] @ get new task stack pointer
@@ -97,6 +107,11 @@ rt_hw_context_switch:
bl rt_cpus_lock_status_restore
#endif /*RT_USING_SMP*/
#ifdef RT_USING_LWP
ldmfd sp, {r13, r14}^ @ pop usr_sp usr_lr
add sp, #8
#endif
ldmfd sp!, {r4} @ pop new task cpsr to spsr
msr spsr_cxsf, r4
ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
@@ -142,6 +157,11 @@ rt_hw_context_switch_interrupt:
stmfd sp!, {r4-r7} @ push old task's r0-r3
stmfd sp!, {r3} @ push old task's cpsr
#ifdef RT_USING_LWP
stmfd sp, {r13,r14}^ @push usr_sp usr_lr
sub sp, #8
#endif
msr cpsr_c, #I_Bit|F_Bit|Mode_IRQ
pop {r1 - r3}
mov sp, r0
@@ -152,6 +172,11 @@ rt_hw_context_switch_interrupt:
mov r0, r3
bl rt_cpus_lock_status_restore
#ifdef RT_USING_LWP
ldmfd sp, {r13,r14}^ @pop usr_sp usr_lr
add sp, #8
#endif
ldmfd sp!, {r4} @ pop new task's cpsr to spsr
msr spsr_cxsf, r4
bsp/qemu-vexpress-a9/cpu/stack.c
+5 -1
View File
@@ -51,13 +51,17 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
/* cpsr */
if ((rt_uint32_t)tentry & 0x01)
*(--stk) = SVCMODE | 0x20; /* thumb mode */
else
*(--stk) = SVCMODE; /* arm mode */
#ifdef RT_USING_LWP
*(--stk) = 0; /* user lr */
*(--stk) = 0; /* user sp*/
#endif
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
bsp/qemu-vexpress-a9/cpu/start_gcc.S
+14 -2
View File
@@ -288,6 +288,11 @@ rt_hw_context_switch_interrupt_do:
stmfd sp!, {r1-r4} @ push old task's r0-r3
stmfd sp!, {r0} @ push old task's cpsr
#ifdef RT_USING_LWP
stmfd sp, {r13, r14}^ @push usr_sp, usr_lr
sub sp, #8
#endif
ldr r4, =rt_interrupt_from_thread
ldr r5, [r4]
str sp, [r5] @ store sp in preempted tasks's TCB
@@ -296,6 +301,11 @@ rt_hw_context_switch_interrupt_do:
ldr r6, [r6]
ldr sp, [r6] @ get new task's stack pointer
#ifdef RT_USING_LWP
ldmfd sp, {r13, r14}^ @pop usr_sp, usr_lr
add sp, #8
#endif
ldmfd sp!, {r4} @ pop new task's cpsr to spsr
msr spsr_cxsf, r4
@@ -317,6 +327,8 @@ rt_hw_context_switch_interrupt_do:
.align 5
.globl vector_swi
.weak SVC_Handler
SVC_Handler:
vector_swi:
push_svc_reg
bl rt_hw_trap_swi
@@ -400,8 +412,8 @@ irq_stack_2:
irq_stack_2_limit:
.data
#define DEVICE_MEM 0x10406
#define NORMAL_MEM 0x1140e
#define DEVICE_MEM 0x10c06
#define NORMAL_MEM 0x11c0e
.align 14
mtbl:
bsp/qemu-vexpress-a9/cpu/vector_gcc.S
+2 -1
View File
@@ -21,6 +21,7 @@
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.section .vectors, "ax"
.code 32
@@ -49,7 +50,7 @@ _vector_reset:
_vector_undef:
.word vector_undef
_vector_swi:
.word vector_swi
.word SVC_Handler
_vector_pabt:
.word vector_pabt
_vector_dabt:
bsp/qemu-vexpress-a9/rtconfig.h
+51 -4
View File
@@ -63,6 +63,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40000
#define ARCH_ARM
#define ARCH_ARM_CORTEX_A
#define ARCH_ARM_CORTEX_A9
@@ -102,7 +103,7 @@
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 8
#define DFS_FD_MAX 16
/* RT_USING_DFS_MNTTABLE is not set */
#define RT_USING_DFS_ELMFAT
@@ -156,10 +157,12 @@
#define RT_MMCSD_MAX_PARTITION 16
/* RT_SDIO_DEBUG is not set */
#define RT_USING_SPI
/* RT_USING_QSPI is not set */
#define RT_USING_SPI_MSD
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
/* RT_SFUD_USING_QSPI is not set */
/* RT_DEBUG_SFUD is not set */
/* RT_USING_W25QXX is not set */
/* RT_USING_GD is not set */
@@ -276,6 +279,7 @@
/* LOG_TRACE_USING_MEMLOG is not set */
/* RT_USING_RYM is not set */
/* RT_USING_ULOG is not set */
#define RT_USING_LWP
/* RT-Thread online packages */
@@ -283,6 +287,7 @@
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_WEBNET is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
@@ -304,6 +309,7 @@
/* PKG_USING_NOPOLL is not set */
/* PKG_USING_NETUTILS is not set */
/* PKG_USING_AT_DEVICE is not set */
/* PKG_USING_WIZNET is not set */
/* IoT Cloud */
@@ -311,6 +317,7 @@
/* PKG_USING_GAGENT_CLOUD is not set */
/* PKG_USING_ALI_IOTKIT is not set */
/* PKG_USING_AZURE is not set */
/* PKG_USING_TENCENT_IOTKIT is not set */
/* security packages */
@@ -335,6 +342,9 @@
/* PKG_USING_EASYFLASH is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* PKG_USING_RDB is not set */
/* PKG_USING_QRCODE is not set */
/* PKG_USING_ULOG_EASYFLASH is not set */
/* system packages */
@@ -348,14 +358,23 @@
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* PKG_USING_LITTLEVGL2RTT is not set */
/* PKG_USING_CMSIS is not set */
/* PKG_USING_DFS_YAFFS is not set */
/* PKG_USING_LITTLEFS is not set */
/* peripheral libraries and drivers */
/* PKG_USING_STM32F4_HAL is not set */
/* PKG_USING_STM32F4_DRIVERS is not set */
/* PKG_USING_REALTEK_AMEBA is not set */
/* PKG_USING_SHT2X is not set */
/* PKG_USING_AHT10 is not set */
/* PKG_USING_AP3216C is not set */
/* PKG_USING_STM32_SDIO is not set */
/* PKG_USING_ICM20608 is not set */
/* PKG_USING_U8G2 is not set */
/* PKG_USING_BUTTON is not set */
/* PKG_USING_MPU6XXX is not set */
/* PKG_USING_PCF8574 is not set */
/* PKG_USING_KENDRYTE_SDK is not set */
/* miscellaneous packages */
@@ -368,14 +387,42 @@
/* PKG_USING_CANFESTIVAL is not set */
/* PKG_USING_ZLIB is not set */
/* PKG_USING_DSTR is not set */
/* PKG_USING_TINYFRAME is not set */
/* sample package */
/* PKG_USING_SAMPLES is not set */
/* samples: kernel and components samples */
/* PKG_USING_KERNEL_SAMPLES is not set */
/* PKG_USING_FILESYSTEM_SAMPLES is not set */
/* PKG_USING_NETWORK_SAMPLES is not set */
/* PKG_USING_PERIPHERAL_SAMPLES is not set */
/* example package: hello */
/* PKG_USING_HELLO is not set */
/* Privated Packages of RealThread */
/* PKG_USING_CODEC is not set */
/* PKG_USING_PLAYER is not set */
/* PKG_USING_PERSIMMON_SRC is not set */
/* PKG_USING_JS_PERSIMMON is not set */
/* PKG_USING_JERRYSCRIPT_WIN32 is not set */
/* Network Utilities */
/* PKG_USING_MDNS is not set */
/* PKG_USING_UPNP is not set */
/* PKG_USING_WICED is not set */
/* PKG_USING_CLOUDSDK is not set */
/* PKG_USING_COREMARK is not set */
/* PKG_USING_POWER_MANAGER is not set */
/* PKG_USING_RT_OTA is not set */
/* PKG_USING_RDBD_SRC is not set */
/* PKG_USING_RTINSIGHT is not set */
/* PKG_USING_SMARTCONFIG is not set */
/* PKG_USING_RTX is not set */
#define SOC_VEXPRESS_A9
#define RT_USING_UART0
#define RT_USING_UART1
bsp/qemu-vexpress-a9/rtconfig.py
+1 -1
View File
@@ -2,7 +2,7 @@ import os
# toolchains options
ARCH='arm'
CPU='vexpress-a9'
CPU='cortex-a9'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
components/Kconfig
+2
View File
@@ -39,4 +39,6 @@ source "$RTT_DIR/components/utilities/Kconfig"
source "$RTT_DIR/components/CMSIS/Kconfig"
source "$RTT_DIR/components/lwp/Kconfig"
endmenu
components/lwp/Kconfig
+8
View File
@@ -0,0 +1,8 @@
config RT_USING_LWP
bool "Using light-weight process"
select RT_USING_DFS
select RT_USING_LIBC
depends on ARCH_ARM_CORTEX_M || ARCH_ARM_ARM9 || ARCH_ARM_CORTEX_A
default n
help
The lwP is a light weight process running in user mode.
components/lwp/SConscript
+20
View File
@@ -0,0 +1,20 @@
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
CPPPATH = []
support_arch = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7", "arm9", "cortex-a9"]}
platform_file = {'armcc': 'rvds.S', 'gcc': 'gcc.S', 'iar': 'iar.S'}
if rtconfig.PLATFORM in platform_file.keys(): # support platforms
if rtconfig.ARCH in support_arch.keys() and rtconfig.CPU in support_arch[rtconfig.ARCH]:
# arch/arm/cortex-m7/lwp_gcc.S
asm_path = 'arch/' + rtconfig.ARCH + '/' + rtconfig.CPU + '/*_' + platform_file[rtconfig.PLATFORM]
src = Glob('*.c') + Glob(asm_path)
CPPPATH = [cwd]
group = DefineGroup('lwP', src, depend = ['RT_USING_LWP'], CPPPATH = CPPPATH)
Return('group')
components/lwp/arch/arm/arm9/lwp_gcc.S
+81
View File
@@ -0,0 +1,81 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x13
#define Mode_MON 0x16
#define Mode_ABT 0x17
#define Mode_UDF 0x1B
#define Mode_SYS 0x1F
#define A_Bit 0x100
#define I_Bit 0x80 @; when I bit is set, IRQ is disabled
#define F_Bit 0x40 @; when F bit is set, FIQ is disabled
#define T_Bit 0x20
.cpu arm9
.syntax unified
.text
/*
* void lwp_user_entry(args, text, data);
*/
.global lwp_user_entry
.type lwp_user_entry, % function
lwp_user_entry:
mrs r9, cpsr
mov r8, r9
bic r9, #0x1f
orr r9, #Mode_USR
orr r8, #I_Bit
msr cpsr_c, r8
msr spsr, r9
/* set data address. */
mov r9, r2
movs pc, r1
/*
* void SVC_Handler(void);
*/
.global SVC_Handler
.type SVC_Handler, % function
SVC_Handler:
push {lr}
mrs lr, spsr
push {r4, r5, lr}
mrs r4, cpsr
bic r4, #I_Bit
msr cpsr_c, r4
push {r0 - r3, r12}
and r0, r7, #0xff
bl lwp_get_sys_api
cmp r0, #0 /* r0 = api */
mov r4, r0
pop {r0 - r3, r12}
beq svc_exit
ldr lr, = svc_exit
bx r4
svc_exit:
mrs r4, cpsr
orr r4, #I_Bit
msr cpsr_c, r4
pop {r4, r5, lr}
msr spsr_cxsf, lr
pop {lr}
movs pc, lr
components/lwp/arch/arm/cortex-a9/lwp_gcc.S
+70
View File
@@ -0,0 +1,70 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
*/
#define Mode_USR 0x10
#define Mode_FIQ 0x11
#define Mode_IRQ 0x12
#define Mode_SVC 0x13
#define Mode_MON 0x16
#define Mode_ABT 0x17
#define Mode_UDF 0x1B
#define Mode_SYS 0x1F
#define A_Bit 0x100
#define I_Bit 0x80 @; when I bit is set, IRQ is disabled
#define F_Bit 0x40 @; when F bit is set, FIQ is disabled
#define T_Bit 0x20
.cpu cortex-a9
.syntax unified
.text
/*
* void lwp_user_entry(args, text, data);
*/
.global lwp_user_entry
.type lwp_user_entry, % function
lwp_user_entry:
mrs r9, cpsr
bic r9, #0x1f
orr r9, #Mode_USR
cpsid i
msr spsr, r9
/* set data address. */
mov r9, r2
movs pc, r1
/*
* void SVC_Handler(void);
*/
.global SVC_Handler
.type SVC_Handler, % function
SVC_Handler:
push {lr}
mrs lr, spsr
push {r4, r5, lr}
cpsie i
push {r0 - r3, r12}
and r0, r7, #0xff
bl lwp_get_sys_api
cmp r0, #0 /* r0 = api */
mov lr, r0
pop {r0 - r3, r12}
beq svc_exit
blx lr
svc_exit:
cpsid i
pop {r4, r5, lr}
msr spsr_cxsf, lr
pop {lr}
movs pc, lr
components/lwp/arch/arm/cortex-m3/lwp_gcc.S
+124
View File
@@ -0,0 +1,124 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m3
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_sys_api
.global lwp_get_kernel_sp
.global lwp_set_kernel_sp
/*
* void lwp_user_entry(args, text, data);
*/
.global lwp_user_entry
.type lwp_user_entry, % function
lwp_user_entry:
PUSH {R0-R3} @; push text&data addr.
MOV R0, SP @; v1 = SP
BL lwp_set_kernel_sp @; lwp_set_kernel_sp(v1)
@; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 @; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} @; pop app address to R1.
@; set data address.
MOV R9, R2
@; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
/*
* void SVC_Handler(void);
*/
.global SVC_Handler
.type SVC_Handler, % function
SVC_Handler:
PUSH {LR}
@; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} @; push app SP.
@; get SVC number.
mov R0, R7
@; get kernel system API
BL lwp_get_sys_api
PUSH {R0} @; push api
@; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} @; pop api to R2.
POP {R1} @; pop app SP to R1.
stmfd r0!, {r1} @; save app SP to kernel SP
@;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
@; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} @; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} @; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] @; update LR
STR R2, [R0, #24] @; update api to PC
MSR PSP, R0 @; update SP, API is executed with kernel SP
@; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} @; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
/*
* void svc_exit(void);
*/
.global svc_exit
.type svc_exit, % function
svc_exit:
@; get user SP.
PUSH {R0} @; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] @; load pc
add r3, #32 @; exception_stack_frame size
MSR PSP, R3 @; restore app stack pointer
@; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
@; return to lwp.
ORR R1, R1, #0x01 @; only Thumb-mode.
BX R1 @; return to user app.
components/lwp/arch/arm/cortex-m3/lwp_iar.S
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;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint32_t number);
; */
IMPORT lwp_get_sys_api
IMPORT lwp_get_kernel_sp
IMPORT lwp_set_kernel_sp
;/*
; * void lwp_user_entry(args, text, data);
; */
EXPORT lwp_user_entry
lwp_user_entry:
PUSH {R0-R3} ; push text&data addr.
MOV R0, SP ; v1 = SP
BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1)
; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 ; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} ; pop app address to R1.
; set data address.
MOV R9, R2
; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
;/*
; * void SVC_Handler(void);
; */
EXPORT SVC_Handler
SVC_Handler:
PUSH {LR}
; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} ; push app SP.
; get SVC number.
mov R0, R7
; get kernel system API
BL lwp_get_sys_api
PUSH {R0} ; push api
; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} ; pop api to R2.
POP {R1} ; pop app SP to R1.
stmfd r0!, {r1} ; save app SP to kernel SP
;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] ; update LR
STR R2, [R0, #24] ; update api to PC
MSR PSP, R0 ; update SP, API is executed with kernel SP
; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} ; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
;/*
; * void svc_exit(void);
; */
EXPORT svc_exit
svc_exit:
; get user SP.
PUSH {R0} ; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] ; load pc
add r3, r3, #32 ; exception_stack_frame size
MSR PSP, R3 ; restore app stack pointer
; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
; return to lwp.
ORR R1, R1, #0x01 ; only Thumb-mode.
BX R1 ; return to user app.
END
components/lwp/arch/arm/cortex-m3/lwp_rvds.S
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;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint32_t number);
; */
IMPORT lwp_get_sys_api
IMPORT lwp_get_kernel_sp
IMPORT lwp_set_kernel_sp
;/*
; * void lwp_user_entry(args, text, data);
; */
lwp_user_entry PROC
EXPORT lwp_user_entry
PUSH {R0-R3} ; push text&data addr.
MOV R0, SP ; v1 = SP
BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1)
; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 ; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} ; pop app address to R1.
; set data address.
MOV R9, R2
; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
; never reach here!
ENDP
;/*
; * void SVC_Handler(void);
; */
SVC_Handler PROC
EXPORT SVC_Handler
PUSH {LR}
; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} ; push app SP.
; get SVC number.
mov R0, R7
; get kernel system API
BL lwp_get_sys_api
PUSH {R0} ; push api
; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} ; pop api to R2.
POP {R1} ; pop app SP to R1.
stmfd r0!, {r1} ; save app SP to kernel SP
;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] ; update LR
STR R2, [R0, #24] ; update api to PC
MSR PSP, R0 ; update SP, API is executed with kernel SP
; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} ; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
ENDP
;/*
; * void svc_exit(void);
; */
svc_exit PROC
EXPORT svc_exit
; get user SP.
PUSH {R0} ; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] ; load pc
add r3, #32 ; exception_stack_frame size
MSR PSP, R3 ; restore app stack pointer
; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
; return to lwp.
ORR R1, R1, #0x01 ; only Thumb-mode.
BX R1 ; return to user app.
ENDP
ALIGN
END
components/lwp/arch/arm/cortex-m4/lwp_gcc.S
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@@ -0,0 +1,124 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m4
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_sys_api
.global lwp_get_kernel_sp
.global lwp_set_kernel_sp
/*
* void lwp_user_entry(args, text, data);
*/
.global lwp_user_entry
.type lwp_user_entry, % function
lwp_user_entry:
PUSH {R0-R3} @; push text&data addr.
MOV R0, SP @; v1 = SP
BL lwp_set_kernel_sp @; lwp_set_kernel_sp(v1)
@; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 @; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} @; pop app address to R1.
@; set data address.
MOV R9, R2
@; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
/*
* void SVC_Handler(void);
*/
.global SVC_Handler
.type SVC_Handler, % function
SVC_Handler:
PUSH {LR}
@; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} @; push app SP.
@; get SVC number.
mov R0, R7
@; get kernel system API
BL lwp_get_sys_api
PUSH {R0} @; push api
@; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} @; pop api to R2.
POP {R1} @; pop app SP to R1.
stmfd r0!, {r1} @; save app SP to kernel SP
@;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
@; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} @; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} @; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] @; update LR
STR R2, [R0, #24] @; update api to PC
MSR PSP, R0 @; update SP, API is executed with kernel SP
@; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} @; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
/*
* void svc_exit(void);
*/
.global svc_exit
.type svc_exit, % function
svc_exit:
@; get user SP.
PUSH {R0} @; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] @; load pc
add r3, #32 @; exception_stack_frame size
MSR PSP, R3 @; restore app stack pointer
@; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
@; return to lwp.
ORR R1, R1, #0x01 @; only Thumb-mode.
BX R1 @; return to user app.
components/lwp/arch/arm/cortex-m4/lwp_iar.S
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@@ -0,0 +1,123 @@
;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint32_t number);
; */
IMPORT lwp_get_sys_api
IMPORT lwp_get_kernel_sp
IMPORT lwp_set_kernel_sp
;/*
; * void lwp_user_entry(args, text, data);
; */
EXPORT lwp_user_entry
lwp_user_entry:
PUSH {R0-R3} ; push text&data addr.
MOV R0, SP ; v1 = SP
BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1)
; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 ; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} ; pop app address to R1.
; set data address.
MOV R9, R2
; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
;/*
; * void SVC_Handler(void);
; */
EXPORT SVC_Handler
SVC_Handler:
PUSH {LR}
; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} ; push app SP.
; get SVC number.
mov R0, R7
; get kernel system API
BL lwp_get_sys_api
PUSH {R0} ; push api
; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} ; pop api to R2.
POP {R1} ; pop app SP to R1.
stmfd r0!, {r1} ; save app SP to kernel SP
;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] ; update LR
STR R2, [R0, #24] ; update api to PC
MSR PSP, R0 ; update SP, API is executed with kernel SP
; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} ; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
;/*
; * void svc_exit(void);
; */
EXPORT svc_exit
svc_exit:
; get user SP.
PUSH {R0} ; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] ; load pc
add r3, r3, #32 ; exception_stack_frame size
MSR PSP, R3 ; restore app stack pointer
; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
; return to lwp.
ORR R1, R1, #0x01 ; only Thumb-mode.
BX R1 ; return to user app.
END
components/lwp/arch/arm/cortex-m4/lwp_rvds.S
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@@ -0,0 +1,135 @@
;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint32_t number);
; */
IMPORT lwp_get_sys_api
IMPORT lwp_get_kernel_sp
IMPORT lwp_set_kernel_sp
;/*
; * void lwp_user_entry(args, text, data);
; */
lwp_user_entry PROC
EXPORT lwp_user_entry
PUSH {R0-R3} ; push text&data addr.
MOV R0, SP ; v1 = SP
BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1)
; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 ; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} ; pop app address to R1.
; set data address.
MOV R9, R2
; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
; never reach here!
ENDP
;/*
; * void SVC_Handler(void);
; */
SVC_Handler PROC
EXPORT SVC_Handler
PUSH {LR}
; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} ; push app SP.
; get SVC number.
mov R0, R7
; get kernel system API
BL lwp_get_sys_api
PUSH {R0} ; push api
; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} ; pop api to R2.
POP {R1} ; pop app SP to R1.
stmfd r0!, {r1} ; save app SP to kernel SP
;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] ; update LR
STR R2, [R0, #24] ; update api to PC
MSR PSP, R0 ; update SP, API is executed with kernel SP
; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} ; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
ENDP
;/*
; * void svc_exit(void);
; */
svc_exit PROC
EXPORT svc_exit
; get user SP.
PUSH {R0} ; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] ; load pc
add r3, #32 ; exception_stack_frame size
MSR PSP, R3 ; restore app stack pointer
; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
; return to lwp.
ORR R1, R1, #0x01 ; only Thumb-mode.
BX R1 ; return to user app.
ENDP
ALIGN
END
components/lwp/arch/arm/cortex-m7/lwp_gcc.S
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@@ -0,0 +1,124 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-10-30 heyuanjie first version
*/
.cpu cortex-m7
.syntax unified
.thumb
.text
/*
* void* lwp_get_sys_api(rt_uint32_t number);
*/
.global lwp_get_sys_api
.global lwp_get_kernel_sp
.global lwp_set_kernel_sp
/*
* void lwp_user_entry(args, text, data);
*/
.global lwp_user_entry
.type lwp_user_entry, % function
lwp_user_entry:
PUSH {R0-R3} @; push text&data addr.
MOV R0, SP @; v1 = SP
BL lwp_set_kernel_sp @; lwp_set_kernel_sp(v1)
@; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 @; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} @; pop app address to R1.
@; set data address.
MOV R9, R2
@; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
/*
* void SVC_Handler(void);
*/
.global SVC_Handler
.type SVC_Handler, % function
SVC_Handler:
PUSH {LR}
@; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} @; push app SP.
@; get SVC number.
mov R0, R7
@; get kernel system API
BL lwp_get_sys_api
PUSH {R0} @; push api
@; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} @; pop api to R2.
POP {R1} @; pop app SP to R1.
stmfd r0!, {r1} @; save app SP to kernel SP
@;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
@; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} @; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} @; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] @; update LR
STR R2, [R0, #24] @; update api to PC
MSR PSP, R0 @; update SP, API is executed with kernel SP
@; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} @; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
/*
* void svc_exit(void);
*/
.global svc_exit
.type svc_exit, % function
svc_exit:
@; get user SP.
PUSH {R0} @; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] @; load pc
add r3, #32 @; exception_stack_frame size
MSR PSP, R3 @; restore app stack pointer
@; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
@; return to lwp.
ORR R1, R1, #0x01 @; only Thumb-mode.
BX R1 @; return to user app.
components/lwp/arch/arm/cortex-m7/lwp_iar.S
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;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
SECTION .text:CODE(2)
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint32_t number);
; */
IMPORT lwp_get_sys_api
IMPORT lwp_get_kernel_sp
IMPORT lwp_set_kernel_sp
;/*
; * void lwp_user_entry(args, text, data);
; */
EXPORT lwp_user_entry
lwp_user_entry:
PUSH {R0-R3} ; push text&data addr.
MOV R0, SP ; v1 = SP
BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1)
; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 ; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} ; pop app address to R1.
; set data address.
MOV R9, R2
; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
;/*
; * void SVC_Handler(void);
; */
EXPORT SVC_Handler
SVC_Handler:
PUSH {LR}
; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} ; push app SP.
; get SVC number.
mov R0, R7
; get kernel system API
BL lwp_get_sys_api
PUSH {R0} ; push api
; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} ; pop api to R2.
POP {R1} ; pop app SP to R1.
stmfd r0!, {r1} ; save app SP to kernel SP
;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] ; update LR
STR R2, [R0, #24] ; update api to PC
MSR PSP, R0 ; update SP, API is executed with kernel SP
; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} ; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
;/*
; * void svc_exit(void);
; */
EXPORT svc_exit
svc_exit:
; get user SP.
PUSH {R0} ; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] ; load pc
add r3, r3, #32 ; exception_stack_frame size
MSR PSP, R3 ; restore app stack pointer
; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
; return to lwp.
ORR R1, R1, #0x01 ; only Thumb-mode.
BX R1 ; return to user app.
END
components/lwp/arch/arm/cortex-m7/lwp_rvds.S
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;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2018-10-30 heyuanjie first version
; */
AREA |.text|, CODE, READONLY, ALIGN=2
THUMB
REQUIRE8
PRESERVE8
;/*
; * void* lwp_get_sys_api(rt_uint32_t number);
; */
IMPORT lwp_get_sys_api
IMPORT lwp_get_kernel_sp
IMPORT lwp_set_kernel_sp
;/*
; * void lwp_user_entry(args, text, data);
; */
lwp_user_entry PROC
EXPORT lwp_user_entry
PUSH {R0-R3} ; push text&data addr.
MOV R0, SP ; v1 = SP
BL lwp_set_kernel_sp ; lwp_set_kernel_sp(v1)
; set CPU to user-thread mode.
MRS R2, CONTROL
ORR R2, R2, #0x03 ; use PSP, user-thread mode.
MSR CONTROL, R2
POP {R0-R3} ; pop app address to R1.
; set data address.
MOV R9, R2
; run app, only Thumb-mode.
ORR R1, R1, #0x01
BX R1
; never reach here!
ENDP
;/*
; * void SVC_Handler(void);
; */
SVC_Handler PROC
EXPORT SVC_Handler
PUSH {LR}
; get user SP.
TST LR, #0x4
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
PUSH {R1} ; push app SP.
; get SVC number.
mov R0, R7
; get kernel system API
BL lwp_get_sys_api
PUSH {R0} ; push api
; get kernel SP to R0.
BL lwp_get_kernel_sp
POP {R2} ; pop api to R2.
POP {R1} ; pop app SP to R1.
stmfd r0!, {r1} ; save app SP to kernel SP
;push app parm5~6 to kernel SP
STMFD R0!, {R4 - R5}
; copy R1(app SP) to R0(kernel SP).
push {r8-r11}
LDMFD R1, {R4 - R11} ; pop exception_stack_frame to r4 - r11 register
STMFD R0!, {R4 - R11} ; push exception_stack_frame to server SP.
pop {r8-r11}
LDR R3, =svc_exit
STR R3, [R0, #20] ; update LR
STR R2, [R0, #24] ; update api to PC
MSR PSP, R0 ; update SP, API is executed with kernel SP
; set to thread-privilege mode.
MRS R3, CONTROL
BIC R3, R3, #0x01
ORR R3, R3, #0x02
MSR CONTROL, R3
POP {LR} ; 0xFFFFFFED
ORR LR, LR, #0x10
BX LR
ENDP
;/*
; * void svc_exit(void);
; */
svc_exit PROC
EXPORT svc_exit
; get user SP.
PUSH {R0} ; push result to SP.
BL lwp_get_kernel_sp
ldr r3, [r0, #-4]
pop {r0}
ldr lr, [r3, #20]
ldr r1, [r3, #24] ; load pc
add r3, #32 ; exception_stack_frame size
MSR PSP, R3 ; restore app stack pointer
; restore to PSP & thread-unprivilege mode.
MRS R2, CONTROL
ORR R2, R2, #0x03
MSR CONTROL, R2
; return to lwp.
ORR R1, R1, #0x01 ; only Thumb-mode.
BX R1 ; return to user app.
ENDP
ALIGN
END
components/lwp/lwp.c
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components/lwp/lwp.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-06-29 heyuanjie first version
*/
#ifndef __LWP_H__
#define __LWP_H__
#define LWP_MAGIC 0x5A
#define LWP_TYPE_FIX_ADDR 0x01
#define LWP_TYPE_DYN_ADDR 0x02
#define LWP_ARG_MAX 8
#include <stdint.h>
#include <rtthread.h>
#include <dfs.h>
#include <lwp_memheap.h>
struct rt_lwp
{
uint8_t lwp_type;
uint8_t heap_cnt;
uint8_t reserv[2];
rt_list_t hlist; /**< headp list */
uint8_t *text_entry;
uint32_t text_size;
uint8_t *data;
uint32_t data_size;
uint32_t *kernel_sp; /**< kernel stack point */
struct dfs_fdtable fdt;
void *args;
};
struct lwp_header
{
uint8_t magic;
uint8_t compress_encrypt_algo;
uint16_t reserved;
uint32_t crc32;
};
struct lwp_chunk
{
uint32_t total_len;
char name[4];
uint32_t data_len;
uint32_t data_len_space;
};
extern struct rt_lwp *rt_lwp_self(void);
extern void rt_lwp_mem_init(struct rt_lwp *lwp);
extern void rt_lwp_mem_deinit(struct rt_lwp *lwp);
extern void *rt_lwp_mem_malloc(rt_uint32_t size);
extern void rt_lwp_mem_free(void *addr);
extern void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize);
#endif
components/lwp/lwp_mem.c
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components/lwp/lwp_mem.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-06-10 Bernard first version
*/
#ifndef __LWP_MEM_H__
#define __LWP_MEM_H__
extern void rt_lwp_mem_init(struct rt_lwp *lwp);
extern void rt_lwp_mem_deinit(struct rt_lwp *lwp);
extern void *rt_lwp_mem_malloc(rt_uint32_t size);
extern void rt_lwp_mem_free(void *addr);
extern void *rt_lwp_mem_realloc(void *rmem, rt_size_t newsize);
#endif
components/lwp/lwp_memheap.c
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components/lwp/lwp_memheap.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-06-10 Bernard first version
*/
#ifndef __LWP_MEMHEAP_H__
#define __LWP_MEMHEAP_H__
#include <stdint.h>
#include <rtthread.h>
/**
* memory item on the heap
*/
struct rt_lwp_memheap_item
{
rt_uint32_t magic; /**< magic number for memheap */
struct rt_lwp_memheap *pool_ptr; /**< point of pool */
struct rt_lwp_memheap_item *next; /**< next memheap item */
struct rt_lwp_memheap_item *prev; /**< prev memheap item */
struct rt_lwp_memheap_item *next_free; /**< next free memheap item */
struct rt_lwp_memheap_item *prev_free; /**< prev free memheap item */
};
/**
* Base structure of memory heap object
*/
struct rt_lwp_memheap
{
struct rt_object parent; /**< inherit from rt_object */
void *start_addr; /**< pool start address and size */
rt_uint32_t pool_size; /**< pool size */
rt_uint32_t available_size; /**< available size */
rt_uint32_t max_used_size; /**< maximum allocated size */
struct rt_lwp_memheap_item *block_list; /**< used block list */
struct rt_lwp_memheap_item *free_list; /**< free block list */
struct rt_lwp_memheap_item free_header; /**< free block list header */
struct rt_semaphore lock; /**< semaphore lock */
rt_list_t mlist;
};
extern rt_err_t rt_lwp_memheap_init(struct rt_lwp_memheap *memheap, const char *name, void *start_addr, rt_uint32_t size);
extern void *rt_lwp_memheap_alloc(struct rt_lwp_memheap *heap, rt_uint32_t size);
extern void rt_lwp_memheap_free(void *ptr);
extern void *rt_lwp_memheap_realloc(struct rt_lwp_memheap *heap, void *ptr, rt_size_t newsize);
extern rt_bool_t rt_lwp_memheap_is_empty(struct rt_lwp_memheap *memheap);
extern rt_bool_t rt_lwp_memheap_unavailable_size_get(void);
#endif
components/lwp/lwp_syscall.c
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components/lwp/lwp_syscall.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2006-03-18 Bernard the first version
* 2006-04-25 Bernard add rt_hw_context_switch_interrupt declaration
* 2006-09-24 Bernard add rt_hw_context_switch_to declaration
* 2012-12-29 Bernard add rt_hw_exception_install declaration
* 2017-10-17 Hichard add some micros
* 2018-12-10 Jesven fix complie error in iar and keil
*/
#ifndef __LWP_SYSCALL_H__
#define __LWP_SYSCALL_H__
#include <stdint.h>
#include <rtthread.h>
#include <dfs_posix.h>
#include <sys/time.h>
#include <sys/types.h>
typedef long suseconds_t; /* microseconds (signed) */
typedef uint32_t id_t; /* may contain pid, uid or gid */
/*
* Process priority specifications to get/setpriority.
*/
#define PRIO_MIN (-20)
#define PRIO_MAX 20
#define PRIO_PROCESS 0 /* only support lwp process */
#define PRIO_PGRP 1
#define PRIO_USER 2
#define TIMEVAL_TO_TIMESPEC(tv, ts) { \
(ts)->tv_sec = (tv)->tv_sec; \
(ts)->tv_nsec = (tv)->tv_usec * 1000; \
}
#define TIMESPEC_TO_TIMEVAL(tv, ts) { \
(tv)->tv_sec = (ts)->tv_sec; \
(tv)->tv_usec = (ts)->tv_nsec / 1000; \
}
void sys_exit(int value);
ssize_t sys_read(int fd, void *buf, size_t nbyte);
ssize_t sys_write(int fd, const void *buf, size_t nbyte);
off_t sys_lseek(int fd, off_t offset, int whence);
int sys_open(const char *name, int mode, ...);
int sys_close(int fd);
int sys_nanosleep(const struct timespec *rqtp, struct timespec *rmtp);
int sys_getpriority(int which, id_t who);
int sys_setpriority(int which, id_t who, int prio);
int sys_gettimeofday(struct timeval *tp, struct timezone *tzp);
int sys_settimeofday(const struct timeval *tv, const struct timezone *tzp);
int sys_msgget(key_t key, int msgflg);
int sys_msgsend(int msqid, const void *msgp, size_t msgsz, int msgflg);
int sys_msgrcv(int msqid, void *msgp, size_t msgsz, long msgtyp, int msgflg);
int sys_log(const char* log, int size);
#endif