mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-06-13 04:33:18 +08:00
Meco Man
GitHub
+202
@@ -1,3 +1,205 @@
|
||||
# RT-Thread v4.0.3 Change Log
|
||||
|
||||
Change log since v4.0.2
|
||||
|
||||
## Kernel
|
||||
|
||||
* Add `__RTTHREAD__` global macro definition
|
||||
* Add user heap options
|
||||
* Fix bug of rt_memheap_detach
|
||||
* Add rt_memory_info() for memheap.c
|
||||
* Add rt_object_get_length/rt_object_get_pointers APIs
|
||||
* Fix double release for thread
|
||||
* Fix thread control bug about `RT_THREAD_CTRL_CLOSE` command
|
||||
* Avoid deadlock (rt_hw_interrupt_disable and rt_enter_critical when enable smp)
|
||||
* Fix the issue of judging the ready_table of pcpu when multi-core rt_schedule_remove_thread
|
||||
* Fix the issue that the yield operation cannot release the cpu in time
|
||||
* Fix the iterator failure for softtimer list timeout check
|
||||
* Fix rt_timer_list_next_timeout multi-task safe
|
||||
* Add timer working status query function to software timer
|
||||
* Fix the software issue when the system timer thread is pending
|
||||
* Fix the timer/software timer handling issue if the timeout function starts/stops/deletes this timer.
|
||||
* Fix an issue with rt_timer_start being broken and destroying the timer list
|
||||
* Fix the bug that the linked list is still mounted when the single timer is not modified
|
||||
* Add function rt_tick_get_millisecond()
|
||||
* Fix the delay_until issue
|
||||
* Add mb mq value overflow-check code
|
||||
* Fix the rt_event_recv function, if the event met without blocking, assigning thread->event_set/event_info will goes well
|
||||
* Add the definition of the maximum value of ipc type
|
||||
* Remove the call of rt_system_object_init/rt_system_tick_init from the code.
|
||||
* Removes component configuration macro `RT_USING_FINSH` from the kernel
|
||||
* Use object_find to implement thread_find/device_find
|
||||
* The cleanup operation is executed before the current thread exits
|
||||
|
||||
## Components
|
||||
|
||||
* Fix assert in the sys_arch_mbox_fetch function when close socket
|
||||
* Add dhcp start or stop function to start or stop dhcp.
|
||||
* Change rt_data_queue_peak to rt_data_queue_peek.
|
||||
* Update elmfat to R0.14 patch 1.
|
||||
* Add SAL_INTERNET_CHECK configuration item to support turning on or off the network status check
|
||||
* Solve the issue that the do_pollfd function processing the underlying network device returns error -1
|
||||
* Fix the issue that when the network card device calls to close dhcp, the bottom layer no need to call the dhcp_stop function to close dhcp
|
||||
* Add the function of judging the network card up and down in the sal_accept function
|
||||
* Modify the spelling error of the macro definition, modify the printing error when printing the IMEI number
|
||||
* Fix the issue that the server closed the connection when web socket requests the data that comes back from the server, and the socket status is incorrectly judged at that point
|
||||
* Fix the issue of incorrect sal_getaddrinfo release when sal socket supports multiple network cards
|
||||
* Update AT socket
|
||||
* Support alloc socket dynamically with at device
|
||||
* Update AT_SW_VERSION and adjust at_socket_ops
|
||||
* Adjust where the AT socket callback function
|
||||
* Fix at_client, avoid creating the same client repeatedly and prevent working exceptions and memory leaks.
|
||||
* Fix the bug that rx_notice out of sync when the data is received after last rt_device_read() is zero
|
||||
* [FinSH] rm command supports recursive deletion of folders
|
||||
* Add clear command for FINSH
|
||||
* [posix] Implement usleep function
|
||||
* Fix the issue of pthreads compilation error when using the new version of newlib; at the same time solve the problem of pthreads under 64-bit;
|
||||
* [dlmodule] Fix crash when dlmodule exits
|
||||
* Add priority & stack_size param parsing for dlmodule
|
||||
* libc adds getline/getdelim functions
|
||||
* Change the header file included in some libc files from <rtthread.h> to <rtconfig.h> to narrow the scope of inclusion to prevent recursive compilation
|
||||
* [jffs2] error check of rt_event_recv()
|
||||
* Add rt_data_queue_deinit and fix bug of dataqueue
|
||||
* Change log in device driver framework
|
||||
* [pin] Add rt_pin_get to pin frame
|
||||
* [PM] Update RT-Thread PM2.0 framework
|
||||
* [audio] Fix compile warning, undefine var
|
||||
* [serial] Fix the crash caused when the serial port receiving buffer is full and ULOG_USING_ISR_LOG is not turned on
|
||||
* [wlan] Add raw frame send interface and Management frame filter interface
|
||||
* [Sensor] Add vendor info and sensor types for cmd
|
||||
* [Sensor] Support custom commands for rt_sensor_control
|
||||
* [sensor] Support TOF sensor class
|
||||
* [SFUD] Update the 'sf bench' command.
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||||
* [spi] Fix "response+1" causing hard fault of unaligned access to SPI memory of STM32 HAL library
|
||||
* [RTC] Optimize RTC alarm function, add alarm function for SOFT_RTC
|
||||
* [hwtimer] When getting the timer count, prevent overflow update due to the interruption
|
||||
* [dirver/i2c] i2c driver supports bus lock, STOP control
|
||||
* [usb] Fix bug in device descriptor that MAC OS enumeration failed
|
||||
* Fix the bug that USB cannot recognize composite device normally
|
||||
* Fix USB host core bugs
|
||||
* Limit >4 USB ports hubs
|
||||
* Double free intf
|
||||
* dname buffer size is too small
|
||||
* Reset child pointer after detaching instance
|
||||
|
||||
## BSP and CPU porting
|
||||
|
||||
* Add license info and code cleanup for vexpress-a9 BSP
|
||||
* Add HDSC hc32f4a0 BSP support
|
||||
* Add support for Cypress PSoC6 series products
|
||||
* Fix the lpc55 issue under Linux/GCC
|
||||
* [qemu] Fix spelling mistakes of code in drv_pl041.c
|
||||
* [loongson] Update the SPI driver and UART driver on the Loongson 2K1000 platform
|
||||
* [allwinner_tina]Fix spi driver bug
|
||||
* [smartfusion2]Support Microsemi SmartFusion2 family FPGA
|
||||
* [imxrt] Add ethernet configuration for imxrt1064-nxp-evk
|
||||
* Add support for architecture sparc-v8 and soc bm3803.
|
||||
* [libc] libc adds getline/getdelim functions (posix.1-2008)
|
||||
* Add support for c28x mcu hardware fpu
|
||||
* [at32] Add link detecting thread for ethernet driver
|
||||
* Fix gcc assembly option in rtconfig.py for imxrt1064-nxp-evk
|
||||
* [IMXRT]Fix scons --dist in IMXRT BSP
|
||||
* [ls2kdev] Initial gpio driver without irq support on ls2kdev
|
||||
* Optimize BSP dist handle process
|
||||
* [nrfx] Add the qspi_flash of nordic pdk
|
||||
* [nrf5x] Add the BSP of nrf5x, which support UART, SPI, PWM, ADC, i2c drivers and rtc device driver
|
||||
* [nrfx] Add the on-chip flash for nrf5x
|
||||
* [RISC-V:K210]Add UART1~3 support for K210
|
||||
* [Nuclei] Add Nuclei RISC-V Processor support
|
||||
* Update BSP for mini2440
|
||||
* Add soc timer cntpct
|
||||
* LPC55S69: Add NS project and TFM support on LPC55S69
|
||||
* Make MicroPython runs on Raspi3-64 BSP
|
||||
* Add rt_hw_us_delay for W60x
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||||
* [imxrt] [driver] Add usb device driver
|
||||
* Fix raspi4-32
|
||||
* Add: dma driver, bsc driver, dsi lcd/touch driver, waveshare spi lcd/touch driver, watchdog driver, hdmi driver, sdio driver, gpio interrupt
|
||||
* Fix: eth driver, spi driver, uart driver
|
||||
* Add more BSP on BSP framework:
|
||||
* At32/at32f403a-start
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||||
* At32/at32f407-start
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||||
* bluetrum/ab32vg1-ab-prougen
|
||||
* bm3803
|
||||
* cypress/psoc6-pioneerkit_modus
|
||||
* essemi/es32f0271
|
||||
* essemi/es32f369x
|
||||
* essemi/es32f0654
|
||||
* lpc55sxx/lpc55s69_nxp_evk_ns
|
||||
* ls2kdev
|
||||
* nrf5x
|
||||
* nuclei/gd32vf103_rvstar
|
||||
* nuclei/hbird_eval
|
||||
* nuvoton/nk-980iot
|
||||
* nuvoton/numaker-iot-m487
|
||||
* nuvoton/numaker-pfm-m487
|
||||
* raspi2
|
||||
* raspi3-32
|
||||
* raspi3-64
|
||||
* raspi4-32
|
||||
* raspi4-64
|
||||
* smartfusion2
|
||||
* thead-smart
|
||||
* tm4c123 BSP
|
||||
* zynqmp-r5-axu4ev
|
||||
|
||||
* Add more STM32 BSP based on new STM32 BSP framework:
|
||||
* STM32L431-BearPi
|
||||
* stm32f103-blue-pill
|
||||
* stm32f103-onenet-nbiot
|
||||
* stm32f410-st-nucleo
|
||||
* stm32f411-atk-nano
|
||||
* stm32f413-st-nucleo
|
||||
* stm32g070-st-nucleo
|
||||
* stm32h747-st-discovery
|
||||
* stm32l010-st-nucleo
|
||||
* stm32l412-st-nucleo
|
||||
* stm32l433-st-nucleo
|
||||
* stm32l496-st-nucleo
|
||||
* stm32mp157a-st-discovery
|
||||
* stm32mp157a-st-ev1
|
||||
* stm32wb55-st-nucleo
|
||||
* New STM32 BSP framework:
|
||||
* Add dcmi, ov2640 and SD Card driver for stm32h743
|
||||
* Fix bug that caused system crash by changing the run_mode in low power mode
|
||||
* Fix issue when using gcc to compile the chips of stm G4 series, but chip doesn't work
|
||||
* drv_flash_f7.c supports single bank mode
|
||||
* Add stm32f103-atk-warshipv3 sram driver
|
||||
* Update void HAL_Delay(__IO uint32_t Delay)
|
||||
* Add PWM9_CONFIG default configuration and TIM3_CONFIG default configuration
|
||||
* [stm32f103-atk-warshipv3] Add sdcard driver
|
||||
* Add English readme for stm32
|
||||
* Add dac and can driver for stm32l4 and stm32f4
|
||||
* openamp driver and add rs485 driver for stm32mp157a
|
||||
* Optimize the pin-index algorithm
|
||||
* [stm32f769-disco] Support ethernet device
|
||||
* Add C++ Support
|
||||
* Fix the clock configuration issue of STM32 hardware timer
|
||||
* Adjust the interrupt priority configuration of some peripherals of the STM32 series BSP
|
||||
* Fix stm32 f1 series rtc bug
|
||||
* Support SPI/ADC/TIME on-chip peripheral driver
|
||||
* [stm32h743-atk-apollo]Support stm32h7 uart dma
|
||||
* Add stm32h743-atk-apollo support for pcf8574 and uart2
|
||||
* Support stm32h743-atk-apollo pcf8574 and uart2(485)
|
||||
* Update bsp/stm32/stm32h743-st-nucleo
|
||||
* Fix ADC channel Configuration bug for SMT32F0/L0/H7
|
||||
* Add support for onboard AP6181
|
||||
* Fix UART DMA TX
|
||||
* Add pm support by cubemx tool for stm32l4
|
||||
* Add stm32f407-atk-explorer sram driver
|
||||
* Fix PWM timer init about pwm
|
||||
* [stm32f103-atk-warshipv3]Add sdcard driver
|
||||
* Add stm32f103-atk-warshipv3 sram driver
|
||||
|
||||
## Tools
|
||||
|
||||
* Add C++ support for eclipse target
|
||||
* Keep user's lib configuration while running --target=eclipse
|
||||
* Add Libraries when perform `scons --dist`
|
||||
* Update tools/building.py and add `tackanalysis` option
|
||||
* Improve the logic of generating `rtconfig.h` files in scons with command `scons --menuconfig`
|
||||
* Fix makeimg.py wrong on linux
|
||||
* Add Studio IDE dist feature for stm32 BSP
|
||||
|
||||
# RT-Thread v4.0.2 Change Log
|
||||
|
||||
Change log since v4.0.1
|
||||
|
||||
@@ -380,6 +380,7 @@ CONFIG_RT_USING_LIBC=y
|
||||
# CONFIG_PKG_USING_UC_COMMON is not set
|
||||
# CONFIG_PKG_USING_UC_MODBUS is not set
|
||||
# CONFIG_PKG_USING_PPOOL is not set
|
||||
# CONFIG_PKG_USING_OPENAMP is not set
|
||||
|
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#
|
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# peripheral libraries and drivers
|
||||
|
||||
@@ -60,15 +60,10 @@ SECTIONS
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} > ram1 AT > flash
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|
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.comm : {
|
||||
KEEP (*(.vector))
|
||||
EXCLUDE_FILE (*hal_drivers**.o *ab32vg1_hal**.o *components*finsh**.o *components*libc**.o *rt-thread*src**.o *kernel*src**.o *romfs.o *lib_a**.o) *(.text*)
|
||||
*idle.o (.text*)
|
||||
*ipc.o (.text*)
|
||||
*irq.o (.text*)
|
||||
*scheduler.o (.text*)
|
||||
*timer.o (.text*)
|
||||
*kservice.o (.text*)
|
||||
EXCLUDE_FILE (*romfs.o *lib_a**.o) *(.rodata*)
|
||||
KEEP(*(.vector))
|
||||
EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *romfs.o *lib_a**.o) *(.text*)
|
||||
*finsh*shell.o (.text*)
|
||||
EXCLUDE_FILE (*components*libc**.o *romfs.o *lib_a**.o) *(.rodata*)
|
||||
*(.srodata*)
|
||||
*(.rela*)
|
||||
*(.data*)
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
rtthread.siz:
|
||||
riscv64-unknown-elf-size --format=berkeley "rtthread.elf"
|
||||
sh ../pre_build.sh
|
||||
riscv32-elf-xmaker -b rtthread.xm
|
||||
riscv32-elf-xmaker -b download.xm
|
||||
|
||||
clean2:
|
||||
-$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
|
||||
-$(RM) $(OBJS) *.elf
|
||||
-@echo ' '
|
||||
|
||||
|
||||
*.elf: $(wildcard D:/Softwares/RT-ThreadStudio/workspace/ab32vg1/link.lds)
|
||||
@@ -0,0 +1,4 @@
|
||||
cp ../riscv32-elf-xmaker.exe .
|
||||
cp ../header.bin .
|
||||
cp ../rtthread.xm .
|
||||
cp ../download.xm .
|
||||
@@ -13,7 +13,7 @@
|
||||
.global rt_interrupt_from_thread
|
||||
.global rt_interrupt_to_thread
|
||||
.global rt_cur_thread_sp
|
||||
.global rt_switch_flag
|
||||
.global rt_thread_switch_interrupt_flag
|
||||
.global rt_interrupt_nest
|
||||
|
||||
/*
|
||||
@@ -77,12 +77,12 @@ enable_int_ret:
|
||||
sw x30, 108(sp)
|
||||
sw x31, 112(sp)
|
||||
|
||||
lw a5, EPC(zero) //Saves current program counter (EPC) as task program counter
|
||||
lw a5, EPC(zero) //Saves current program counter (EPC) as task program counter
|
||||
sw a5, 116(sp)
|
||||
lw a5, EPICCON(zero)
|
||||
sw a5, 120(sp)
|
||||
|
||||
sw sp, rt_cur_thread_sp, a4 //store sp in preempted tasks tcb
|
||||
sw sp, rt_cur_thread_sp, a4 //store sp in preempted tasks tcb
|
||||
.endm
|
||||
|
||||
|
||||
@@ -90,7 +90,7 @@ enable_int_ret:
|
||||
.macro restore_context
|
||||
|
||||
la a5, rt_cur_thread_sp
|
||||
lw sp, 0(a5) //get new task stack pointer
|
||||
lw sp, 0(a5) //get new task stack pointer
|
||||
|
||||
/* Load task program counter EPC*/
|
||||
lw a5, 116(sp)
|
||||
@@ -140,16 +140,16 @@ enable_int_ret:
|
||||
*/
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
sw zero, rt_interrupt_from_thread, a4 /*set from thread to 0*/
|
||||
sw a0, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
|
||||
sw zero, rt_interrupt_from_thread, a4 /*set from thread to 0*/
|
||||
sw a0, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
|
||||
|
||||
sb zero, rt_interrupt_nest, a4 /*rt_interrupt_nest = 0*/
|
||||
sb zero, rt_interrupt_nest, a4 /*rt_interrupt_nest = 0*/
|
||||
|
||||
li a5, 1
|
||||
sw a5, rt_switch_flag, a4 // rt_switch_flag = 1;
|
||||
sw a5, rt_thread_switch_interrupt_flag, a4 // rt_thread_switch_interrupt_flag = 1;
|
||||
|
||||
SWINT /*kick soft interrupt*/
|
||||
lw a5, PICCON(zero) /*enable interrupt*/
|
||||
lw a5, PICCON(zero) /*enable interrupt*/
|
||||
ori a5, a5, 1
|
||||
sw a5, PICCON(zero)
|
||||
ret
|
||||
@@ -161,10 +161,10 @@ rt_hw_context_switch_to:
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
sw a0, rt_interrupt_from_thread, a4 /*set rt_interrupt_from_thread*/
|
||||
sw a0, rt_interrupt_from_thread, a4 /*set rt_interrupt_from_thread*/
|
||||
sw a1, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
|
||||
li a5, 1
|
||||
sw a5, rt_switch_flag, a4 // rt_switch_flag = 1;
|
||||
sw a5, rt_thread_switch_interrupt_flag, a4 /*rt_thread_switch_interrupt_flag = 1*/
|
||||
SWINT /*kick soft interrupt*/
|
||||
ret
|
||||
|
||||
@@ -190,37 +190,37 @@ rt_switch_to_thread:
|
||||
*/
|
||||
.global rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
lw a5, rt_switch_flag
|
||||
lw a5, rt_thread_switch_interrupt_flag
|
||||
bnez a5, _reswitch
|
||||
li a5, 0x01
|
||||
sw a5, rt_switch_flag, a4
|
||||
sw a0, rt_interrupt_from_thread, a4 /*set rt_interrupt_from_thread*/
|
||||
sw a5, rt_thread_switch_interrupt_flag, a4
|
||||
sw a0, rt_interrupt_from_thread, a4 /*set rt_interrupt_from_thread*/
|
||||
_reswitch:
|
||||
sw a1, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
|
||||
sw a1, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
|
||||
ret
|
||||
|
||||
//软中断服务
|
||||
.global rt_soft_isr
|
||||
rt_soft_isr:
|
||||
li a5, 0x4 // PICPND = BIT(IRQ_SW_VECTOR); 清软中断Pending
|
||||
li a5, 0x4 // PICPND = BIT(IRQ_SW_VECTOR); 清软中断Pending
|
||||
sw a5, PICPND(zero)
|
||||
ret
|
||||
|
||||
.globl low_prio_irq
|
||||
low_prio_irq:
|
||||
save_context
|
||||
li a5, 1
|
||||
sb a5, rt_interrupt_nest, a4 // rt_interrupt_nest = 1;
|
||||
|
||||
lw a5, rt_interrupt_nest
|
||||
bnez a5, _low_prio_irq_exit
|
||||
|
||||
lw a5, cpu_irq_comm_hook
|
||||
jalr a5
|
||||
|
||||
lw a5, rt_switch_flag
|
||||
beqz a5, _low_prio_irq_exit // if (rt_switch_flag)
|
||||
lw a5, rt_thread_switch_interrupt_flag
|
||||
beqz a5, _low_prio_irq_exit // if (rt_thread_switch_interrupt_flag)
|
||||
jal rt_switch_to_thread
|
||||
sw zero, rt_switch_flag, a4 // rt_switch_flag = 0;
|
||||
sw zero, rt_thread_switch_interrupt_flag, a4 // rt_thread_switch_interrupt_flag = 0;
|
||||
|
||||
_low_prio_irq_exit:
|
||||
sb zero, rt_interrupt_nest, a4 // rt_interrupt_nest = 0;
|
||||
restore_context
|
||||
|
||||
|
||||
@@ -14,7 +14,6 @@
|
||||
volatile rt_ubase_t rt_interrupt_from_thread = 0;
|
||||
volatile rt_ubase_t rt_interrupt_to_thread = 0;
|
||||
volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
|
||||
volatile rt_uint32_t rt_switch_flag = 0;
|
||||
rt_uint32_t rt_cur_thread_sp = 0;
|
||||
|
||||
/**
|
||||
@@ -42,13 +41,13 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
|
||||
stk--;
|
||||
*stk = (rt_uint32_t)0x10003; /* Start address */
|
||||
stk--;
|
||||
*stk = (rt_uint32_t)tentry; /* Start address */
|
||||
stk -= 22;
|
||||
*stk = (rt_uint32_t)parameter; /* Register a0 parameter*/
|
||||
stk -= 6;
|
||||
*stk = (rt_uint32_t)tp; /* Register thread pointer */
|
||||
stk --;
|
||||
*stk = (rt_uint32_t)texit; /* Register ra texit*/
|
||||
*stk = (rt_uint32_t)tentry; /* Start address */
|
||||
stk -= 22;
|
||||
*stk = (rt_uint32_t)parameter; /* Register a0 parameter*/
|
||||
stk -= 6;
|
||||
*stk = (rt_uint32_t)tp; /* Register thread pointer */
|
||||
stk --;
|
||||
*stk = (rt_uint32_t)texit; /* Register ra texit*/
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
|
||||
@@ -131,7 +131,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
|
||||
|
||||
/* connect port to USARTx_Rx */
|
||||
gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin);
|
||||
gpio_mode_set(uart->rx_port, GPIO_MODE_INPUT, GPIO_PUPD_NONE, uart->rx_pin);
|
||||
gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->rx_pin);
|
||||
gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->rx_pin);
|
||||
|
||||
NVIC_SetPriority(uart->irqn, 0);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,42 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
@@ -0,0 +1,23 @@
|
||||
mainmenu "RT-Thread Project Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "board/Kconfig"
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,214 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file adc/adc_01_base/source/ddl_config.h
|
||||
* @brief This file contains HC32 Series Device Driver Library usage management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Yangjp First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __DDL_CONFIG_H__
|
||||
#define __DDL_CONFIG_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Chip module on-off define */
|
||||
#define DDL_ON (1U)
|
||||
#define DDL_OFF (0U)
|
||||
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the Device Driver Library.
|
||||
* Select the modules you need to use to DDL_ON.
|
||||
* @note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
* properly.
|
||||
* @note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
* Library.
|
||||
* @note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
*/
|
||||
#define DDL_ICG_ENABLE (DDL_ON)
|
||||
#define DDL_UTILITY_ENABLE (DDL_ON)
|
||||
#define DDL_PRINT_ENABLE (DDL_ON)
|
||||
|
||||
#define DDL_ADC_ENABLE (DDL_ON)
|
||||
#define DDL_AES_ENABLE (DDL_ON)
|
||||
#define DDL_CAN_ENABLE (DDL_ON)
|
||||
#define DDL_CLK_ENABLE (DDL_ON)
|
||||
#define DDL_CMP_ENABLE (DDL_ON)
|
||||
#define DDL_CRC_ENABLE (DDL_ON)
|
||||
#define DDL_CTC_ENABLE (DDL_ON)
|
||||
#define DDL_DAC_ENABLE (DDL_ON)
|
||||
#define DDL_DCU_ENABLE (DDL_ON)
|
||||
#define DDL_DMA_ENABLE (DDL_ON)
|
||||
#define DDL_DMC_ENABLE (DDL_ON)
|
||||
#define DDL_DVP_ENABLE (DDL_ON)
|
||||
#define DDL_EFM_ENABLE (DDL_ON)
|
||||
#define DDL_EMB_ENABLE (DDL_ON)
|
||||
#define DDL_ETH_ENABLE (DDL_ON)
|
||||
#define DDL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define DDL_FCM_ENABLE (DDL_ON)
|
||||
#define DDL_FMAC_ENABLE (DDL_ON)
|
||||
#define DDL_GPIO_ENABLE (DDL_ON)
|
||||
#define DDL_HASH_ENABLE (DDL_ON)
|
||||
#define DDL_HRPWM_ENABLE (DDL_ON)
|
||||
#define DDL_I2C_ENABLE (DDL_ON)
|
||||
#define DDL_I2S_ENABLE (DDL_ON)
|
||||
#define DDL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define DDL_KEYSCAN_ENABLE (DDL_ON)
|
||||
#define DDL_MAU_ENABLE (DDL_ON)
|
||||
#define DDL_MPU_ENABLE (DDL_ON)
|
||||
#define DDL_NFC_ENABLE (DDL_ON)
|
||||
#define DDL_OTS_ENABLE (DDL_ON)
|
||||
#define DDL_PWC_ENABLE (DDL_ON)
|
||||
#define DDL_QSPI_ENABLE (DDL_ON)
|
||||
#define DDL_RMU_ENABLE (DDL_ON)
|
||||
#define DDL_RTC_ENABLE (DDL_ON)
|
||||
#define DDL_SDIOC_ENABLE (DDL_ON)
|
||||
#define DDL_SMC_ENABLE (DDL_ON)
|
||||
#define DDL_SPI_ENABLE (DDL_ON)
|
||||
#define DDL_SRAM_ENABLE (DDL_ON)
|
||||
#define DDL_SWDT_ENABLE (DDL_ON)
|
||||
#define DDL_TMR0_ENABLE (DDL_ON)
|
||||
#define DDL_TMR2_ENABLE (DDL_ON)
|
||||
#define DDL_TMR4_ENABLE (DDL_ON)
|
||||
#define DDL_TMR6_ENABLE (DDL_ON)
|
||||
#define DDL_TMRA_ENABLE (DDL_ON)
|
||||
#define DDL_TRNG_ENABLE (DDL_ON)
|
||||
#define DDL_USART_ENABLE (DDL_ON)
|
||||
#define DDL_USBFS_ENABLE (DDL_OFF)
|
||||
#define DDL_USBHS_ENABLE (DDL_OFF)
|
||||
#define DDL_WDT_ENABLE (DDL_ON)
|
||||
|
||||
/* BSP on-off define */
|
||||
#define BSP_ON (1U)
|
||||
#define BSP_OFF (0U)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F4A0_LQFP176 (1U)
|
||||
#define BSP_MS_HC32F4A0_LQFP176_050_MEM (2U)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F4A0 is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to BSP_EV_HC32F4A0.
|
||||
*/
|
||||
#define BSP_EV_HC32F4A0 (BSP_EV_HC32F4A0)
|
||||
|
||||
/**
|
||||
* @brief This is the list of BSP components to be used.
|
||||
* Select the components you need to use to BSP_ON.
|
||||
*/
|
||||
#define BSP_CY62167EV30LL_ENABLE (BSP_OFF)
|
||||
#define BSP_IS42S16400J7TLI_ENABLE (BSP_OFF)
|
||||
#define BSP_IS62WV51216_ENABLE (BSP_OFF)
|
||||
#define BSP_MT29F2G08AB_ENABLE (BSP_OFF)
|
||||
#define BSP_NT35510_ENABLE (BSP_OFF)
|
||||
#define BSP_OV5640_ENABLE (BSP_OFF)
|
||||
#define BSP_S29GL064N90TFI03_ENABLE (BSP_OFF)
|
||||
#define BSP_TCA9539_ENABLE (BSP_OFF)
|
||||
#define BSP_W25QXX_ENABLE (BSP_OFF)
|
||||
#define BSP_WM8731_ENABLE (BSP_OFF)
|
||||
|
||||
/**
|
||||
* @brief Ethernet and PHY Configuration.
|
||||
* @note PHY delay these values are based on a 1 ms Systick interrupt.
|
||||
*/
|
||||
/* MAC ADDRESS */
|
||||
#define ETH_MAC_ADDR0 (2U)
|
||||
#define ETH_MAC_ADDR1 (0U)
|
||||
#define ETH_MAC_ADDR2 (0U)
|
||||
#define ETH_MAC_ADDR3 (0U)
|
||||
#define ETH_MAC_ADDR4 (0U)
|
||||
#define ETH_MAC_ADDR5 (0U)
|
||||
|
||||
/* Ethernet driver buffers size and count */
|
||||
#define ETH_TXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for receive */
|
||||
#define ETH_RXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for transmit */
|
||||
#define ETH_TXBUF_NUMBER (4UL) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_RXBUF_NUMBER (4UL) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* PHY Address*/
|
||||
#define PHY_ADDRESS (0x00U) /* RTL8201F */
|
||||
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_HW_RESET_DELAY (0x0000003FUL)
|
||||
#define PHY_RESET_DELAY (0x0000007FUL)
|
||||
#define PHY_CONFIG_DELAY (0x0000003FUL)
|
||||
#define PHY_READ_TIMEOUT (0x00000005UL)
|
||||
#define PHY_WRITE_TIMEOUT (0x00000005UL)
|
||||
|
||||
/* Common PHY Registers */
|
||||
#define PHY_BCR (0x00U) /*!< Basic Control Register */
|
||||
#define PHY_BSR (0x01U) /*!< Basic Status Register */
|
||||
|
||||
#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */
|
||||
#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */
|
||||
#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */
|
||||
|
||||
#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */
|
||||
#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */
|
||||
#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */
|
||||
#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */
|
||||
#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
*/
|
||||
#ifndef I2S_EXT_CLK_FREQ
|
||||
#define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */
|
||||
#endif /* I2S_EXT_CLK_FREQ */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DDL_CONFIG_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,319 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_common.h
|
||||
* @brief This file contains the common part of the HC32 series.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Yangjp First version
|
||||
2020-09-07 Yangjp Add the precompiled configuration of ARM compiler V6
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_COMMON_H__
|
||||
#define __HC32_COMMON_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stddef.h>
|
||||
#include <string.h>
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32_Common_Part
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HC32 Common Device Include
|
||||
*/
|
||||
#if defined(HC32F120)
|
||||
#include "hc32f120.h"
|
||||
#include "system_hc32f120.h"
|
||||
#elif defined(HC32F4A0)
|
||||
#include "hc32f4a0.h"
|
||||
#include "system_hc32f4a0.h"
|
||||
#elif defined(HC32M120)
|
||||
#include "hc32m120.h"
|
||||
#include "system_hc32m120.h"
|
||||
#elif defined(HC32M423)
|
||||
#include "hc32m423.h"
|
||||
#include "system_hc32m423.h"
|
||||
#else
|
||||
#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup HC32_Common_Global_Types HC32 Common Global Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Single precision floating point number (4 byte)
|
||||
*/
|
||||
typedef float float32_t;
|
||||
|
||||
/**
|
||||
* @brief Double precision floating point number (8 byte)
|
||||
*/
|
||||
typedef double float64_t;
|
||||
|
||||
/**
|
||||
* @brief Function pointer type to void/void function
|
||||
*/
|
||||
typedef void (*func_ptr_t)(void);
|
||||
|
||||
/**
|
||||
* @brief Function pointer type to void/uint8_t function
|
||||
*/
|
||||
typedef void (*func_ptr_arg1_t)(uint8_t);
|
||||
|
||||
/**
|
||||
* @brief Functional state
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Disable = 0U,
|
||||
Enable = 1U,
|
||||
} en_functional_state_t;
|
||||
|
||||
/* Check if it is a functional state */
|
||||
#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable))
|
||||
|
||||
/**
|
||||
* @brief Flag status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Reset = 0U,
|
||||
Set = 1U,
|
||||
} en_flag_status_t, en_int_status_t;
|
||||
|
||||
/**
|
||||
* @brief Generic error codes
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Ok = 0U, /*!< No error */
|
||||
Error = 1U, /*!< Non-specific error code */
|
||||
ErrorAddressAlignment = 2U, /*!< Address alignment does not match */
|
||||
ErrorAccessRights = 3U, /*!< Wrong mode (e.g. user/system) mode is set */
|
||||
ErrorInvalidParameter = 4U, /*!< Provided parameter is not valid */
|
||||
ErrorOperationInProgress = 5U, /*!< A conflicting or requested operation is still in progress */
|
||||
ErrorInvalidMode = 6U, /*!< Operation not allowed in current mode */
|
||||
ErrorUninitialized = 7U, /*!< Module (or part of it) was not initialized properly */
|
||||
ErrorBufferEmpty = 8U, /*!< Circular buffer can not be read because the buffer is empty */
|
||||
ErrorBufferFull = 9U, /*!< Circular buffer can not be written because the buffer is full */
|
||||
ErrorTimeout = 10U, /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */
|
||||
ErrorNotReady = 11U, /*!< A requested final state is not reached */
|
||||
OperationInProgress = 12U, /*!< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) */
|
||||
} en_result_t;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup HC32_Common_Global_Macros HC32 Common Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compiler Macro Definitions
|
||||
*/
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif /* __UNUSED */
|
||||
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __attribute__((aligned(4)))
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
|
||||
/* Usage: void __RAM_FUNC foo(void) */
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __attribute__((aligned (4)))
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __attribute__((long_call, section(".ramfunc")))
|
||||
/* Usage: void __RAM_FUNC foo(void) */
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__((section(".noinit")))
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__ICCARM__) /*!< IAR Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __weak
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN _Pragma("data_alignment=4")
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __RAM_FUNC
|
||||
#define __RAM_FUNC __ramfunc
|
||||
#endif /* __RAM_FUNC */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __no_init
|
||||
#endif /* __NO_INIT */
|
||||
#elif defined (__CC_ARM) /*!< ARM Compiler */
|
||||
#ifndef __WEAKDEF
|
||||
#define __WEAKDEF __attribute__((weak))
|
||||
#endif /* __WEAKDEF */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#ifndef __NOINLINE
|
||||
#define __NOINLINE __attribute__((noinline))
|
||||
#endif /* __NOINLINE */
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT
|
||||
#endif /* __NO_INIT */
|
||||
/* RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM. */
|
||||
#define __RAM_FUNC
|
||||
#else
|
||||
#error "unsupported compiler!!"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup Extend_Macro_Definitions Extend Macro Definitions
|
||||
* @{
|
||||
*/
|
||||
/* Decimal to BCD */
|
||||
#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U))
|
||||
|
||||
/* BCD to decimal */
|
||||
#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU))
|
||||
|
||||
/* Returns the dimension of an array */
|
||||
#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0])))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Address_Align Address Align
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADDRESS_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL)))
|
||||
#define IS_ADDRESS_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL))
|
||||
#define IS_ADDRESS_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Register_Macro_Definitions Register Macro Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RW_MEM8(addr) (*(volatile uint8_t *)(addr))
|
||||
#define RW_MEM16(addr) (*(volatile uint16_t *)(addr))
|
||||
#define RW_MEM32(addr) (*(volatile uint32_t *)(addr))
|
||||
|
||||
#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT)))
|
||||
#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT)))
|
||||
#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT)))
|
||||
|
||||
#define CLEAR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT)))))
|
||||
#define CLEAR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT)))))
|
||||
#define CLEAR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT)))))
|
||||
|
||||
#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT)))
|
||||
#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT)))
|
||||
#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT)))
|
||||
|
||||
#define CLEAR_REG8(REG) ((REG) = ((uint8_t)(0U)))
|
||||
#define CLEAR_REG16(REG) ((REG) = ((uint16_t)(0U)))
|
||||
#define CLEAR_REG32(REG) ((REG) = ((uint32_t)(0UL)))
|
||||
|
||||
#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL)))
|
||||
#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL)))
|
||||
#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL)))
|
||||
|
||||
#define READ_REG8(REG) (REG)
|
||||
#define READ_REG16(REG) (REG)
|
||||
#define READ_REG32(REG) (REG)
|
||||
|
||||
#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK)))))
|
||||
#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK)))))
|
||||
#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK)))))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_COMMON_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
@@ -0,0 +1,346 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32_ddl.h
|
||||
* @brief This file contains HC32 Series Device Driver Library file call
|
||||
* management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Yangjp First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32_DDL_H__
|
||||
#define __HC32_DDL_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Defined use Device Driver Library */
|
||||
#if !defined (USE_DDL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the Device Driver Library.
|
||||
* In this case, the application code will be based on direct access to
|
||||
* peripherals registers.
|
||||
*/
|
||||
/* #define USE_DDL_DRIVER */
|
||||
#endif /* USE_DDL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief HC32 Series Device Driver Library version number
|
||||
*/
|
||||
#define HC32_DDL_VERSION_MAIN 0x01U /*!< [31:24] main version */
|
||||
#define HC32_DDL_VERSION_SUB1 0x00U /*!< [23:16] sub1 version */
|
||||
#define HC32_DDL_VERSION_SUB2 0x04U /*!< [15:8] sub2 version */
|
||||
#define HC32_DDL_VERSION_RC 0x00U /*!< [7:0] release candidate */
|
||||
#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \
|
||||
(HC32_DDL_VERSION_SUB1 << 16) | \
|
||||
(HC32_DDL_VERSION_SUB2 << 8 ) | \
|
||||
(HC32_DDL_VERSION_RC))
|
||||
|
||||
/* Use Device Driver Library */
|
||||
#if defined (USE_DDL_DRIVER)
|
||||
|
||||
/**
|
||||
* @brief Include peripheral module's header file
|
||||
*/
|
||||
#if (DDL_ADC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_adc.h"
|
||||
#endif /* DDL_ADC_ENABLE */
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_aes.h"
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
#if (DDL_CAN_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_can.h"
|
||||
#endif /* DDL_CAN_ENABLE */
|
||||
|
||||
#if (DDL_CLK_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_clk.h"
|
||||
#endif /* DDL_CLK_ENABLE */
|
||||
|
||||
#if (DDL_CMP_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_cmp.h"
|
||||
#endif /* DDL_CMP_ENABLE */
|
||||
|
||||
#if (DDL_CRC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_crc.h"
|
||||
#endif /* DDL_CRC_ENABLE */
|
||||
|
||||
#if (DDL_CTC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_ctc.h"
|
||||
#endif /* DDL_CTC_ENABLE */
|
||||
|
||||
#if (DDL_DAC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dac.h"
|
||||
#endif /* DDL_DAC_ENABLE */
|
||||
|
||||
#if (DDL_DCU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dcu.h"
|
||||
#endif /* DDL_DCU_ENABLE */
|
||||
|
||||
#if (DDL_DMA_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dma.h"
|
||||
#endif /* DDL_DMA_ENABLE */
|
||||
|
||||
#if (DDL_DMC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dmc.h"
|
||||
#endif /* DDL_DMC_ENABLE */
|
||||
|
||||
#if (DDL_DVP_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_dvp.h"
|
||||
#endif /* DDL_DVP_ENABLE */
|
||||
|
||||
#if (DDL_EFM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_efm.h"
|
||||
#endif /* DDL_EFM_ENABLE */
|
||||
|
||||
#if (DDL_EMB_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_emb.h"
|
||||
#endif /* DDL_EMB_ENABLE */
|
||||
|
||||
#if (DDL_ETH_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_eth.h"
|
||||
#endif /* DDL_ETH_ENABLE */
|
||||
|
||||
#if (DDL_EVENT_PORT_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_event_port.h"
|
||||
#endif /* DDL_EVENT_PORT_ENABLE */
|
||||
|
||||
#if (DDL_FCM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_fcm.h"
|
||||
#endif /* DDL_FCM_ENABLE */
|
||||
|
||||
#if (DDL_FMAC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_fmac.h"
|
||||
#endif /* DDL_FMAC_ENABLE */
|
||||
|
||||
#if (DDL_GPIO_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_gpio.h"
|
||||
#endif /* DDL_GPIO_ENABLE */
|
||||
|
||||
#if (DDL_HASH_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_hash.h"
|
||||
#endif /* DDL_HASH_ENABLE */
|
||||
|
||||
#if (DDL_I2C_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_i2c.h"
|
||||
#endif /* DDL_I2C_ENABLE */
|
||||
|
||||
#if (DDL_I2S_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_i2s.h"
|
||||
#endif /* DDL_I2S_ENABLE */
|
||||
|
||||
#if (DDL_ICG_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_icg.h"
|
||||
#endif /* DDL_ICG_ENABLE */
|
||||
|
||||
#if (DDL_INTERRUPTS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_interrupts.h"
|
||||
#endif /* DDL_INTERRUPTS_ENABLE */
|
||||
|
||||
#if (DDL_KEYSCAN_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_keyscan.h"
|
||||
#endif /* DDL_KEYSCAN_ENABLE */
|
||||
|
||||
#if (DDL_MAU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_mau.h"
|
||||
#endif /* DDL_MAU_ENABLE */
|
||||
|
||||
#if (DDL_MPU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_mpu.h"
|
||||
#endif /* DDL_MPU_ENABLE */
|
||||
|
||||
#if (DDL_NFC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_nfc.h"
|
||||
#endif /* DDL_NFC_ENABLE */
|
||||
|
||||
#if (DDL_OTS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_ots.h"
|
||||
#endif /* DDL_OTS_ENABLE */
|
||||
|
||||
#if (DDL_PWC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_pwc.h"
|
||||
#endif /* DDL_PWC_ENABLE */
|
||||
|
||||
#if (DDL_QSPI_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_qspi.h"
|
||||
#endif /* DDL_QSPI_ENABLE */
|
||||
|
||||
#if (DDL_RMU_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_rmu.h"
|
||||
#endif /* DDL_RMU_ENABLE */
|
||||
|
||||
#if (DDL_RTC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_rtc.h"
|
||||
#endif /* DDL_RTC_ENABLE */
|
||||
|
||||
#if (DDL_SDIOC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_sdioc.h"
|
||||
#endif /* DDL_SDIOC_ENABLE */
|
||||
|
||||
#if (DDL_SMC_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_smc.h"
|
||||
#endif /* DDL_SMC_ENABLE */
|
||||
|
||||
#if (DDL_SPI_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_spi.h"
|
||||
#endif /* DDL_SPI_ENABLE */
|
||||
|
||||
#if (DDL_SRAM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_sram.h"
|
||||
#endif /* DDL_SRAM_ENABLE */
|
||||
|
||||
#if (DDL_SWDT_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_swdt.h"
|
||||
#endif /* DDL_SWDT_ENABLE */
|
||||
|
||||
#if (DDL_TMR0_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr0.h"
|
||||
#endif /* DDL_TMR0_ENABLE */
|
||||
|
||||
#if (DDL_TMR2_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr2.h"
|
||||
#endif /* DDL_TMR2_ENABLE */
|
||||
|
||||
#if (DDL_TMR4_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr4.h"
|
||||
#endif /* DDL_TMR4_ENABLE */
|
||||
|
||||
#if (DDL_TMR6_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmr6.h"
|
||||
#endif /* DDL_TMR6_ENABLE */
|
||||
|
||||
#if (DDL_TMRA_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_tmra.h"
|
||||
#endif /* DDL_TMRA_ENABLE */
|
||||
|
||||
#if (DDL_TRNG_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_trng.h"
|
||||
#endif /* DDL_TRNG_ENABLE */
|
||||
|
||||
#if (DDL_USART_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_usart.h"
|
||||
#endif /* DDL_USART_ENABLE */
|
||||
|
||||
#if (DDL_USBFS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_usbfs.h"
|
||||
#endif /* DDL_USBFS_ENABLE */
|
||||
|
||||
#if (DDL_USBHS_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_usbhs.h"
|
||||
#endif /* DDL_USBHS_ENABLE */
|
||||
|
||||
#if (DDL_UTILITY_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_utility.h"
|
||||
#endif /* DDL_UTILITY_ENABLE */
|
||||
|
||||
#if (DDL_WDT_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_wdt.h"
|
||||
#endif /* DDL_WDT_ENABLE */
|
||||
|
||||
#if (DDL_HRPWM_ENABLE == DDL_ON)
|
||||
#include "hc32f4a0_hrpwm.h"
|
||||
#endif /* DDL_HRPWM_ENABLE */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Include BSP board's header file
|
||||
*/
|
||||
#if (BSP_EV_HC32F4A0_LQFP176 == BSP_EV_HC32F4A0)
|
||||
#include "ev_hc32f4a0_lqfp176.h"
|
||||
#endif /* BSP_EV_HC32F4A0_LQFP176 */
|
||||
|
||||
#if (BSP_MS_HC32F4A0_LQFP176_050_MEM == BSP_EV_HC32F4A0)
|
||||
#include "ms_hc32f4a0_lqfp176_050_mem.h"
|
||||
#endif /* BSP_MS_HC32F4A0_LQFP176_050_MEM */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Include BSP device component's header file
|
||||
*/
|
||||
#if (BSP_CY62167EV30LL_ENABLE == BSP_ON)
|
||||
#include "cy62167ev30ll.h"
|
||||
#endif /* BSP_CY62167EV30LL_ENABLE */
|
||||
|
||||
#if (BSP_IS42S16400J7TLI_ENABLE == BSP_ON)
|
||||
#include "is42s16400j7tli.h"
|
||||
#endif /* BSP_IS42S16400J7TLI_ENABLE */
|
||||
|
||||
#if (BSP_IS62WV51216_ENABLE == BSP_ON)
|
||||
#include "is62wv51216.h"
|
||||
#endif /* BSP_IS62WV51216_ENABLE */
|
||||
|
||||
#if (BSP_MT29F2G08AB_ENABLE == BSP_ON)
|
||||
#include "mt29f2g08ab.h"
|
||||
#endif /* BSP_MT29F2G08AB_ENABLE */
|
||||
|
||||
#if (BSP_NT35510_ENABLE == BSP_ON)
|
||||
#include "nt35510.h"
|
||||
#endif /* BSP_NT35510_ENABLE */
|
||||
|
||||
#if (BSP_OV5640_ENABLE == BSP_ON)
|
||||
#include "ov5640.h"
|
||||
#endif /* BSP_OV5640_ENABLE */
|
||||
|
||||
#if (BSP_S29GL064N90TFI03_ENABLE == BSP_ON)
|
||||
#include "s29gl064n90tfi03.h"
|
||||
#endif /* BSP_S29GL064N90TFI03_ENABLE */
|
||||
|
||||
#if (BSP_TCA9539_ENABLE == BSP_ON)
|
||||
#include "ev_hc32f4a0_lqfp176_tca9539.h"
|
||||
#include "tca9539.h"
|
||||
#endif /* BSP_TCA9539_ENABLE */
|
||||
|
||||
#if (BSP_W25QXX_ENABLE == BSP_ON)
|
||||
#include "w25qxx.h"
|
||||
#endif /* BSP_W25QXX_ENABLE */
|
||||
|
||||
#if (BSP_WM8731_ENABLE == BSP_ON)
|
||||
#include "wm8731.h"
|
||||
#endif /* BSP_WM8731_ENABLE */
|
||||
|
||||
#endif /* USE_DDL_DRIVER */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32_DDL_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,154 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f4a0.h
|
||||
* @brief This file contains all the functions prototypes of the HC32 System.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Zhangxl First version
|
||||
2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __SYSTEM_HC32F4A0_H__
|
||||
#define __SYSTEM_HC32F4A0_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clock setup macro definition
|
||||
*/
|
||||
#define CLOCK_SETTING_NONE 0U /*!< User provides own clock setting in application */
|
||||
#define CLOCK_SETTING_CMSIS 1U
|
||||
|
||||
#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL)))
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#if !defined (HRC_16MHz_VALUE)
|
||||
#define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (HRC_20MHz_VALUE)
|
||||
#define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (MRC_VALUE)
|
||||
#define MRC_VALUE ((uint32_t)8000000UL) /*!< Internal middle speed RC freq.(8MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (LRC_VALUE)
|
||||
#define LRC_VALUE ((uint32_t)32768UL) /*!< Internal low speed RC freq.(32.768KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (RTCLRC_VALUE)
|
||||
#define RTCLRC_VALUE ((uint32_t)32768UL) /*!< Internal RTC low speed RC freq.(32.768KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (SWDTLRC_VALUE)
|
||||
#define SWDTLRC_VALUE ((uint32_t)10000UL) /*!< External low speed OSC freq.(10KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL_VALUE)
|
||||
#define XTAL_VALUE ((uint32_t)8000000UL) /*!< External high speed OSC freq.(8MHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (XTAL32_VALUE)
|
||||
#define XTAL32_VALUE ((uint32_t)32768UL) /*!< External low speed OSC freq.(32.768KHz) */
|
||||
#endif
|
||||
|
||||
#if !defined (HCLK_VALUE)
|
||||
#define HCLK_VALUE (SystemCoreClock >> ((M4_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS))
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Exported_Variable
|
||||
* @{
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */
|
||||
extern uint32_t HRC_VALUE; /*!< HRC frequency */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
extern void SystemInit(void); /*!< Initialize the system */
|
||||
extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_HC32F4A0_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,168 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file system_hc32f4a0.c
|
||||
* @brief This file provides two functions and one global variable to be called
|
||||
* from user application
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Zhangxl First version
|
||||
2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC
|
||||
2020-09-10 Zhangxl Simplify the declare
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
|
||||
/**
|
||||
* @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('define')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Variable
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< System clock frequency (Core clock) */
|
||||
__NO_INIT uint32_t SystemCoreClock;
|
||||
/*!< High speed RC frequency (HCR clock) */
|
||||
__NO_INIT uint32_t HRC_VALUE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup HC32F4A0_System_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system. Initialize the System and update
|
||||
* the SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
(*((volatile unsigned short*)(0x400543FEUL)))=0xA50BU;
|
||||
(*((volatile unsigned int*)(0x4004CCE8UL)))=0x00040000UL;
|
||||
(*((volatile unsigned short*)(0x400543FEUL)))=0xA500U;
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint8_t tmp;
|
||||
uint32_t plln;
|
||||
uint32_t pllp;
|
||||
uint32_t pllm;
|
||||
|
||||
/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
|
||||
/* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */
|
||||
/* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */
|
||||
if (1UL == (HRC_FREQ_MON() & 1UL))
|
||||
{
|
||||
HRC_VALUE = HRC_16MHz_VALUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
HRC_VALUE = HRC_20MHz_VALUE;
|
||||
}
|
||||
|
||||
tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW;
|
||||
switch(tmp)
|
||||
{
|
||||
case 0x00U: /* use internal high speed RC */
|
||||
SystemCoreClock = HRC_VALUE;
|
||||
break;
|
||||
case 0x01U: /* use internal middle speed RC */
|
||||
SystemCoreClock = MRC_VALUE;
|
||||
break;
|
||||
case 0x02U: /* use internal low speed RC */
|
||||
SystemCoreClock = LRC_VALUE;
|
||||
break;
|
||||
case 0x03U: /* use external high speed OSC */
|
||||
SystemCoreClock = XTAL_VALUE;
|
||||
break;
|
||||
case 0x04U: /* use external low speed OSC */
|
||||
SystemCoreClock = XTAL32_VALUE;
|
||||
break;
|
||||
case 0x05U: /* use PLLH */
|
||||
/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
|
||||
pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL);
|
||||
plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL);
|
||||
pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL);
|
||||
|
||||
/* use external high speed OSC as PLL source */
|
||||
if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC)
|
||||
{
|
||||
SystemCoreClock = (XTAL_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
|
||||
}
|
||||
/* use internal high RC as PLL source */
|
||||
else
|
||||
{
|
||||
SystemCoreClock = (HRC_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,283 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.3
|
||||
* @date 24. June 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,272 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,346 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.0
|
||||
* @date 08. March 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,132 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file hc32f4a0_aes.h
|
||||
* @brief This file contains all the functions prototypes of the AES driver
|
||||
* library.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2020-06-12 Heqb First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by HDSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4A0_AES_H__
|
||||
#define __HC32F4A0_AES_H__
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include "hc32_common.h"
|
||||
#include "ddl_config.h"
|
||||
|
||||
/**
|
||||
* @addtogroup HC32F4A0_DDL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup DDL_AES
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (DDL_AES_ENABLE == DDL_ON)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @defgroup AES_Global_Macros AES Global Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AES key length in bytes is 16. */
|
||||
#define AES_BLOCK_LEN (16U)
|
||||
|
||||
/**
|
||||
* @defgroup AES_STATUS AES Start or Stop
|
||||
* @{
|
||||
*/
|
||||
#define AES_START (AES_CR_START)
|
||||
#define AES_STOP (0x0UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup AES_KEY_SIZE AES Key Size
|
||||
* @{
|
||||
*/
|
||||
#define AES_KEY_SIZE_128BIT (0UL << AES_CR_KEYSIZE_POS)
|
||||
#define AES_KEY_SIZE_192BIT (1UL << AES_CR_KEYSIZE_POS)
|
||||
#define AES_KEY_SIZE_256BIT (2UL << AES_CR_KEYSIZE_POS)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @addtogroup AES_Global_Functions
|
||||
* @{
|
||||
*/
|
||||
en_result_t AES_Encrypt(uint8_t au8Plaintext[],
|
||||
uint32_t u32PlaintextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t u8KeyLength,
|
||||
uint8_t au8Ciphertext[]);
|
||||
|
||||
en_result_t AES_Decrypt(uint8_t au8Ciphertext[],
|
||||
uint32_t u32CiphertextSize,
|
||||
const uint8_t *pu8Key,
|
||||
uint8_t u8KeyLength,
|
||||
uint8_t au8Plaintext[]);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DDL_AES_ENABLE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4A0_AES_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user