[libcpu][aarch64] 使用设备树对内存进行初始化 (#8320)

bsp/qemu-virt64-aarch64/drivers/board.c

@@ -11,104 +11,22 @@
  *                           add smp ipi init
  */
 
-#include <rthw.h>
-#include <rtthread.h>
 #include <mmu.h>
-#include <gtimer.h>
-
-#ifdef RT_USING_SMART
-#include <lwp_arch.h>
-#endif
-
-#include "board.h"
+#include <board.h>
 #include <mm_aspace.h>
 #include <mm_page.h>
-#include <interrupt.h>
 #include <setup.h>
 
-#ifdef RT_USING_SMART
-struct mem_desc platform_mem_desc[] = {
-    {KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}
-};
-#else
-
-#define PAGE_POOL_SIZE (2ul << 20)
-#define PHYMEM_END (0x48000000ul)
-
-struct mem_desc platform_mem_desc[] =
-{
-    {0x40000000, PHYMEM_END - 1, 0x40000000, NORMAL_MEM},
-    // {PL031_RTC_BASE, PL031_RTC_BASE + 0x1000 - 1, PL031_RTC_BASE, DEVICE_MEM},
-    // {PL061_GPIO_BASE, PL061_GPIO_BASE + 0x1000 - 1, PL061_GPIO_BASE, DEVICE_MEM},
-    {PL011_UART0_BASE, PL011_UART0_BASE + ARCH_SECTION_SIZE - 1, PL011_UART0_BASE, DEVICE_MEM},
-    {VIRTIO_MMIO_BASE, RT_ALIGN(VIRTIO_MMIO_BASE + VIRTIO_MAX_NR * VIRTIO_MMIO_SIZE, ARCH_SECTION_SIZE) - 1, VIRTIO_MMIO_BASE, DEVICE_MEM},
-#ifdef BSP_USING_GICV2
-    {GIC_PL390_DISTRIBUTOR_PPTR, GIC_PL390_DISTRIBUTOR_PPTR + ARCH_SECTION_SIZE - 1, GIC_PL390_DISTRIBUTOR_PPTR, DEVICE_MEM},
-#endif
-#ifdef BSP_USING_GICV3
-    {GIC_PL500_DISTRIBUTOR_PPTR, GIC_PL500_DISTRIBUTOR_PPTR + 0x1000 - 1, GIC_PL500_DISTRIBUTOR_PPTR, DEVICE_MEM},
-    {GIC_PL500_REDISTRIBUTOR_PPTR, GIC_PL500_REDISTRIBUTOR_PPTR + 0xf60000 - 1, GIC_PL500_REDISTRIBUTOR_PPTR, DEVICE_MEM},
-#endif
-};
-#endif
-
-const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
-
-void idle_wfi(void)
-{
-    asm volatile ("wfi");
-}
-
-/**
- * This function will initialize board
- */
-
 extern size_t MMUTable[];
 
-#ifdef RT_USING_SMART
-rt_region_t init_page_region = {
-    PAGE_START,
-    PAGE_END,
-};
-#else
-rt_region_t init_page_region = {
-    PHYMEM_END - PAGE_POOL_SIZE,
-    PHYMEM_END,
-};
-#endif
-
 void rt_hw_board_init(void)
 {
-#ifdef RT_USING_SMART
-    rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
-#else
-    rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
-#endif
-    rt_page_init(init_page_region);
-    rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
+    rt_fdt_commit_memregion_early(&(rt_region_t)
+    {
+        .name  = "memheap",
+        .start = (rt_size_t)rt_kmem_v2p(HEAP_BEGIN),
+        .end   = (rt_size_t)rt_kmem_v2p(HEAP_END),
+    }, RT_TRUE);
 
-    /* initialize system heap */
-    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
-
-    /* initialize hardware interrupt */
-    rt_hw_interrupt_init();
-
-    rt_hw_gtimer_init();
-
-    /* support debug feature before components init */
-    rt_hw_uart_init();
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-
-#ifdef RT_USING_OFW
     rt_hw_common_setup();
-#endif
-
-    rt_components_board_init();
-
-    rt_thread_idle_sethook(idle_wfi);
-
-#ifdef RT_USING_SMP
-    /* install IPI handle */
-    rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
-#endif
 }

bsp/qemu-virt64-aarch64/drivers/board.h

@@ -18,15 +18,7 @@ extern unsigned char __bss_start;
 extern unsigned char __bss_end;
 
 #define HEAP_BEGIN  (void *)&__bss_end
-
-#ifdef RT_USING_SMART
-#define HEAP_END    (rt_size_t)(KERNEL_VADDR_START + 64 * 1024 * 1024)
-#define PAGE_START  HEAP_END + 1 * 1024 * 1024
-#define PAGE_END    ((rt_size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
-#else
 #define HEAP_END    ((void *)HEAP_BEGIN + 64 * 1024 * 1024)
-#define KERNEL_VADDR_START 0x40000000
-#endif
 
 void rt_hw_board_init(void);
 

bsp/qemu-virt64-aarch64/drivers/drv_gpio.c

@@ -305,9 +305,7 @@ int rt_hw_gpio_init(void)
     rt_spin_lock_init(&_pl061.spinlock);
 #endif
 
-#ifdef RT_USING_LWP
     pl061_gpio_base = (rt_size_t)rt_ioremap((void *)pl061_gpio_base, PL061_GPIO_SIZE);
-#endif
 
     rt_device_pin_register("gpio", &ops, RT_NULL);
     rt_hw_interrupt_install(PL061_GPIO_IRQNUM, rt_hw_gpio_isr, RT_NULL, "gpio");

bsp/qemu-virt64-aarch64/drivers/drv_rtc.c

@@ -102,9 +102,7 @@ const static struct rt_device_ops pl031_rtc_ops =
 
 int rt_hw_rtc_init(void)
 {
-#ifdef RT_USING_LWP
     pl031_rtc_base = (rt_size_t)rt_ioremap((void *)pl031_rtc_base, PL031_RTC_SIZE);
-#endif
 
     rt_memset(&rtc_device, 0, sizeof(rtc_device));
 

bsp/qemu-virt64-aarch64/drivers/drv_virtio.c

@@ -62,14 +62,12 @@ int rt_virtio_devices_init(void)
         return 0;
     }
 
-#ifdef RT_USING_LWP
     mmio_base = (rt_ubase_t)rt_ioremap((void *)mmio_base, VIRTIO_MMIO_SIZE * VIRTIO_MAX_NR);
 
     if (mmio_base == RT_NULL)
     {
         return -RT_ERROR;
     }
-#endif
 
     for (i = 0; i < VIRTIO_MAX_NR; ++i, ++irq, mmio_base += VIRTIO_MMIO_SIZE)
     {

components/mm/ioremap.c

@@ -18,8 +18,9 @@ void *rt_ioremap_start;
 size_t rt_ioremap_size;
 
 #ifdef RT_USING_SMART
-
 #include <lwp_mm.h>
+#endif
+
 #define DBG_TAG "mm.ioremap"
 #define DBG_LVL DBG_LOG
 #include <rtdbg.h>
@@ -111,23 +112,3 @@ void rt_iounmap(volatile void *vaddr)
     rt_aspace_unmap(&rt_kernel_space, (void *)vaddr);
 }
 
-#else
-void *rt_ioremap(void *paddr, size_t size)
-{
-    return paddr;
-}
-
-void *rt_ioremap_nocache(void *paddr, size_t size)
-{
-    return paddr;
-}
-
-void *rt_ioremap_cached(void *paddr, size_t size)
-{
-    return paddr;
-}
-
-void rt_iounmap(volatile void *vaddr)
-{
-}
-#endif

libcpu/aarch64/common/interrupt.c

@@ -104,7 +104,7 @@ void rt_hw_interrupt_init(void)
     rt_memset(isr_table, 0x00, sizeof(isr_table));
 
     /* initialize ARM GIC */
-#ifdef RT_USING_SMART
+#if defined(RT_USING_SMART) || defined(RT_USING_OFW)
     gic_dist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x40000);
     gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
 #ifdef BSP_USING_GICV3

libcpu/aarch64/common/mmu.c

@@ -15,13 +15,15 @@
 #include <stdint.h>
 #include <string.h>
 
+#define __MMU_INTERNAL
+
 #include "mm_aspace.h"
 #include "mm_page.h"
 #include "mmu.h"
 #include "tlb.h"
 
-#ifdef RT_USING_SMART
 #include "ioremap.h"
+#ifdef RT_USING_SMART
 #include <lwp_mm.h>
 #endif
 
@@ -45,6 +47,10 @@
 #define MMU_TBL_PAGE_4k_LEVEL  3
 #define MMU_TBL_LEVEL_NR       4
 
+#ifndef KERNEL_VADDR_START
+#define KERNEL_VADDR_START ARCH_TEXT_OFFSET
+#endif
+
 volatile unsigned long MMUTable[512] __attribute__((aligned(4 * 1024)));
 
 struct mmu_level_info
@@ -423,21 +429,13 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
     rt_page_cleanup();
 }
 
-#ifdef RT_USING_SMART
 static void _init_region(void *vaddr, size_t size)
 {
     rt_ioremap_start = vaddr;
     rt_ioremap_size = size;
     rt_mpr_start = (char *)rt_ioremap_start - rt_mpr_size;
 }
-#else
 
-#define RTOS_VEND (0xfffffffff000UL)
-static inline void _init_region(void *vaddr, size_t size)
-{
-    rt_mpr_start = (void *)(RTOS_VEND - rt_mpr_size);
-}
-#endif
 
 /**
  * This function will initialize rt_mmu_info structure.
@@ -476,12 +474,8 @@ int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, size_t size,
         return -1;
     }
 
-#ifdef RT_USING_SMART
     rt_aspace_init(aspace, (void *)KERNEL_VADDR_START, 0 - KERNEL_VADDR_START,
                    vtable);
-#else
-    rt_aspace_init(aspace, (void *)0x1000, RTOS_VEND - 0x1000ul, vtable);
-#endif
 
     _init_region(v_address, size);
 
@@ -497,10 +491,14 @@ int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, size_t size,
 void mmu_tcr_init(void)
 {
     unsigned long val64;
+    unsigned long pa_range;
 
     val64 = 0x00447fUL;
     __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n" ::"r"(val64));
 
+    __asm__ volatile ("mrs %0, ID_AA64MMFR0_EL1":"=r"(val64));
+    pa_range = val64 & 0xf; /* PARange */
+
     /* TCR_EL1 */
     val64 = (16UL << 0)      /* t0sz 48bit */
             | (0x0UL << 6)   /* reserved */
@@ -516,7 +514,7 @@ void mmu_tcr_init(void)
             | (0x3UL << 26)  /* t1 outer wb cacheable */
             | (0x2UL << 28)  /* t1 outer shareable */
             | (0x2UL << 30)  /* t1 4k */
-            | (0x1UL << 32)  /* 001b 64GB PA */
+            | (pa_range << 32)  /* PA range */
             | (0x0UL << 35)  /* reserved */
             | (0x1UL << 36)  /* as: 0:8bit 1:16bit */
             | (0x0UL << 37)  /* tbi0 */
@@ -530,17 +528,21 @@ struct page_table
 };
 
 /*  */
-static struct page_table __init_page_array[6] rt_align(0x1000);
-static unsigned long __page_off = 2UL; /* 0, 1 for ttbr0, ttrb1 */
+static struct page_table* __init_page_array;
+static unsigned long __page_off = 0UL;
 unsigned long get_ttbrn_base(void)
 {
     return (unsigned long) __init_page_array;
 }
 
+void set_free_page(void *page_array)
+{
+    __init_page_array = page_array;
+}
+
 unsigned long get_free_page(void)
 {
-    __page_off++;
-    return (unsigned long) (__init_page_array[__page_off - 1].page);
+    return (unsigned long) (__init_page_array[__page_off++].page);
 }
 
 static int _map_single_page_2M(unsigned long *lv0_tbl, unsigned long va,
@@ -594,6 +596,7 @@ static int _map_single_page_2M(unsigned long *lv0_tbl, unsigned long va,
 void *rt_ioremap_early(void *paddr, size_t size)
 {
     size_t count;
+    rt_ubase_t base;
     static void *tbl = RT_NULL;
 
     if (!size)
@@ -607,10 +610,16 @@ void *rt_ioremap_early(void *paddr, size_t size)
     }
 
     count = (size + ARCH_SECTION_MASK) >> ARCH_SECTION_SHIFT;
+    base = (rt_ubase_t)paddr & (~ARCH_SECTION_MASK);
 
     while (count --> 0)
     {
-        _map_single_page_2M(tbl, (unsigned long)paddr, (unsigned long)paddr, MMU_MAP_K_DEVICE);
+        if (_map_single_page_2M(tbl, base, base, MMU_MAP_K_DEVICE))
+        {
+            return RT_NULL;
+        }
+
+        base += ARCH_SECTION_SIZE;
     }
 
     return paddr;

libcpu/aarch64/common/mmu.h

@@ -11,6 +11,8 @@
 #ifndef __MMU_H_
 #define __MMU_H_
 
+#ifndef __ASSEMBLY__
+
 #include <rtthread.h>
 #include <mm_aspace.h>
 
@@ -30,6 +32,8 @@ struct mem_desc
     struct rt_varea varea;
 };
 
+#endif /* !__ASSEMBLY__ */
+
 #define RT_HW_MMU_PROT_READ 1
 #define RT_HW_MMU_PROT_WRITE 2
 #define RT_HW_MMU_PROT_EXECUTE 4
@@ -85,6 +89,8 @@ struct mem_desc
 
 #define ARCH_MAP_FAILED ((void *)0x1ffffffffffff)
 
+#ifndef __ASSEMBLY__
+
 struct rt_aspace;
 
 void rt_hw_mmu_ktbl_set(unsigned long tbl);
@@ -93,8 +99,7 @@ void rt_hw_mem_setup_early(unsigned long *tbl0, unsigned long *tbl1,
 void rt_hw_mmu_setup(struct rt_aspace *aspace, struct mem_desc *mdesc,
                      int desc_nr);
 
-int rt_hw_mmu_map_init(struct rt_aspace *aspace, void *v_address,
-                       rt_size_t size, rt_size_t *vtable, rt_size_t pv_off);
+int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, size_t size, size_t *vtable, size_t pv_off);
 void *rt_hw_mmu_map(struct rt_aspace *aspace, void *v_addr, void *p_addr,
                     size_t size, size_t attr);
 void rt_hw_mmu_unmap(struct rt_aspace *aspace, void *v_addr, size_t size);
@@ -204,4 +209,6 @@ rt_inline rt_bool_t rt_hw_mmu_attr_test_perm(size_t attr, rt_base_t prot)
 int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
                       enum rt_mmu_cntl cmd);
 
+#endif /* !__ASSEMBLY__ */
+
 #endif