更新MCXA153-SDK-V2.16.000

2026-11-09 20:45:41 +08:00 · 2024-07-31 22:34:46 +08:00
1 parent 4c5b203c0b
commit b06843b91c
@@ -4,11 +4,11 @@
 /*            MCXA153                                                        */
 /*  @version: 1.0                                                            */
 /*  @date:    2022-3-29                                                      */
-/*  @build:   b230804                                                        */
+/*  @build:   b240401                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2023 NXP                                                   */
+/* Copyright 2016-2024 NXP                                                   */
 /* SPDX-License-Identifier: BSD-3-Clause                                     */
 /*****************************************************************************/
 /* Version: GCC for ARM Embedded Processors                                  */
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_AOI_H_
-#define _FSL_AOI_H_
+#ifndef FSL_AOI_H_
+#define FSL_AOI_H_

 #include "fsl_common.h"

@@ -23,9 +23,9 @@
 #endif

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 #define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
-/*@}*/
+/*! @} */

 /*!
 * @brief AOI input configurations.
@@ -109,7 +109,7 @@ void AOI_Init(AOI_Type *base);
 */
 void AOI_Deinit(AOI_Type *base);

-/*@}*/
+/*! @} */

 /*!
 * @name  AOI Get Set Operation
@@ -179,8 +179,8 @@ void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_
 }
 #endif /* __cplusplus*/

-/*@}*/
+/*! @} */

 /*!* @} */

-#endif /* _FSL_AOI_H_*/
+#endif /* FSL_AOI_H_*/
@@ -283,8 +283,8 @@ status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask)
    VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK;
    VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK;

-    /* enable clk_16k0 and clk_16k1. */
-    VBAT0->FROCLKE = VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask) & VBAT_FROCLKE_CLKE_MASK);
+    /* enable clk_16k output clock to corresponding modules according to the enable_mask. */
+    VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask));

    return kStatus_Success;
 }
@@ -347,6 +347,47 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq)
    return kStatus_Success;
 }

+/*!
+ * @brief   Initialize the external reference clock to given frequency.
+ * param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)
+{
+    
+    if (iFreq > 50000000U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If configure register is locked, return error. */
+    if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    /* De-initializes the SCG SOSC */
+    SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
+
+    /* Select SOSC source (external reference clock)*/
+    SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK;
+
+    /* Unlock SOSCCSR */
+    SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
+
+    /* Enable SOSC clock monitor and Enable SOSC */
+    SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
+
+    /* Wait for SOSC clock to be valid. */
+    while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
+    {
+    }
+
+    s_Ext_Clk_Freq = iFreq;
+
+    return kStatus_Success;
+}
+
 /* Get IP Clk */
 /*! brief  Return Frequency of selected clock
 *  return Frequency of selected clock
@@ -550,9 +591,9 @@ uint32_t CLOCK_GetCoreSysClkFreq(void)
    return CLOCK_GetMainClk() / ((SYSCON->AHBCLKDIV & 0xFFU) + 1U);
 }

-/* Get LPI2C Clk */
-/*! brief  Return Frequency of CTimer functional Clock
- *  return Frequency of CTimer functional Clock
+/* Get I3C Clk */
+/*! brief  Return Frequency of I3C Clock
+ *  return Frequency of I3C Clock
 */
 uint32_t CLOCK_GetI3CFClkFreq(void)
 {
@@ -630,8 +671,8 @@ uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
 }

 /* Get LPI2C Clk */
-/*! brief  Return Frequency of CTimer functional Clock
- *  return Frequency of CTimer functional Clock
+/*! brief  Return Frequency of LPI2C functional Clock
+ *  return Frequency of LPI2C functional Clock
 */
 uint32_t CLOCK_GetLpi2cClkFreq(void)
 {
@@ -696,6 +696,13 @@ status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask);
 */
 status_t CLOCK_SetupExtClocking(uint32_t iFreq);

+/**
+ * @brief   Initialize the external reference clock to given frequency.
+ * @param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtRefClocking(uint32_t iFreq);
+
 /*! @brief  Return Frequency of selected clock
 *  @return Frequency of selected clock
 */
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 ~ 2023 NXP
+ * Copyright 2022-2024 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -18,14 +18,7 @@
 /*******************************************************************************
 * Prototypes
 ******************************************************************************/
-#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
-#define CMC_SRAMDIS_RESERVED_MASK                                                                                   \
-    (~(kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 | kCMC_RAMD1 |       \
-       kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 | kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | \
-       kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ | kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI))

-#define CMC_SRAMRET_RESERVED_MASK (CMC_SRAMDIS_RESERVED_MASK)
-#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
 /*******************************************************************************
 * Variables
 ******************************************************************************/
@@ -127,10 +120,11 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
 */
 void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
 {
-    uint32_t reg = base->SRAMDIS[0];
+    uint32_t reg       = base->SRAMDIS[0];
+    uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);

-    reg &= ~(CMC_SRAMDIS_DIS_MASK | CMC_SRAMDIS_RESERVED_MASK);
-    reg |= CMC_SRAMDIS_DIS(mask);
+    reg &= ~((uint32_t)kCMC_AllSramArrays);
+    reg |= CMC_SRAMDIS_DIS(maskToSet);
    base->SRAMDIS[0] = reg;
 }

@@ -145,14 +139,36 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
 */
 void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
 {
-    uint32_t reg = base->SRAMRET[0];
+    uint32_t reg       = base->SRAMRET[0];
+    uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);

-    reg &= ~(CMC_SRAMRET_RET_MASK | CMC_SRAMRET_RESERVED_MASK);
-    reg |= CMC_SRAMRET_RET(mask);
+    reg &= ~((uint32_t)kCMC_AllSramArrays);
+    reg |= CMC_SRAMRET_RET(maskToSet);
    base->SRAMRET[0] = reg;
 }
 #endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */

+#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
+/*!
+ * brief Configs the low power mode of the on-chip flash memory.
+ *
+ * This function configs the low power mode of the on-chip flash memory.
+ *
+ * param base CMC peripheral base address.
+ * param doze true: Flash is disabled while core is sleeping
+ *             false: No effect.
+ * param disable true: Flash memory is placed in low power state.
+ *                false: No effect.
+ */
+void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable)
+{
+    uint32_t reg = 0UL;
+
+    reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) |
+           (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U));
+    base->FLASHCR = reg;
+}
+#else
 /*!
 * brief Configs the low power mode of the on-chip flash memory.
 *
@@ -178,6 +194,7 @@ void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable)
           (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U));
    base->FLASHCR = reg;
 }
+#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */

 /*!
 * brief Prepares to enter stop modes.
@@ -274,7 +291,7 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
        CMC_SetMAINPowerMode(base, config->main_domain);
 #if (CMC_PMCTRL_COUNT > 1U)
        CMC_SetWAKEPowerMode(base, config->wake_domain);
-#endif /* (CMC_PMCTRL_COUNT > 1U) */
+#endif  /* (CMC_PMCTRL_COUNT > 1U) */

        /* Before execute WFI instruction read back the last register to
         * ensure all registers writes have completed. */
@@ -6,8 +6,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_COMMON_H_
-#define _FSL_COMMON_H_
+#ifndef FSL_COMMON_H_
+#define FSL_COMMON_H_

 #include <assert.h>
 #include <stdbool.h>
@@ -57,12 +57,13 @@
 #define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief common driver version. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
-/*@}*/
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
+/*! @} */

-/* Debug console type definition. */
+/*! @name Debug console type definition. */
+/*! @{ */
 #define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */
 #define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */
 #define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */
@@ -74,6 +75,7 @@
 #define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */
 #define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */
 #define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */
+/*! @} */

 /*! @brief Status group numbers. */
 enum _status_groups
@@ -156,6 +158,9 @@ enum _status_groups
    kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */
    kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */
    kStatusGroup_VBAT                  = 107, /*!< Group number for VBAT status codes */
+    kStatusGroup_XSPI                  = 108, /*!< Group number for XSPI status codes */
+    kStatusGroup_PNGDEC                = 109, /*!< Group number for PNGDEC status codes */
+    kStatusGroup_JPEGDEC               = 110, /*!< Group number for JPEGDEC status codes */

    kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */
    kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */
@@ -189,7 +194,7 @@ enum _status_groups
    kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */
    kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */
    kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */
-    kStatusGroup_SNT            = 157, /*!< Group number for SNT status codes. */
+    kStatusGroup_ELEMU          = 157, /*!< Group number for ELEMU status codes. */
    kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
    kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
    kStatusGroup_IPED           = 160, /*!< Group number for IPED status codes. */
@@ -224,48 +229,66 @@ enum
 /*! @brief Type used for all status and error return values. */
 typedef int32_t status_t;

+#ifdef __ZEPHYR__
+#include <zephyr/sys/util.h>
+#else
 /*!
 * @name Min/max macros
 * @{
 */
 #if !defined(MIN)
+/*! Computes the minimum of \a a and \a b. */
 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
 #endif

 #if !defined(MAX)
+/*! Computes the maximum of \a a and \a b. */
 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
 #endif
-/* @} */
+/*! @} */

 /*! @brief Computes the number of elements in an array. */
 #if !defined(ARRAY_SIZE)
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #endif
+#endif /* __ZEPHYR__ */

 /*! @name UINT16_MAX/UINT32_MAX value */
-/* @{ */
+/*! @{ */
 #if !defined(UINT16_MAX)
+/*! Max value of uint16_t type. */
 #define UINT16_MAX ((uint16_t)-1)
 #endif

 #if !defined(UINT32_MAX)
+/*! Max value of uint32_t type. */
 #define UINT32_MAX ((uint32_t)-1)
 #endif
-/* @} */
+/*! @} */

-/*! @name Suppress fallthrough warning macro */
-/* For switch case code block, if case section ends without "break;" statement, there wil be
- fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
- To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
- case section which misses "break;"statement.
+/*! Macro to get upper 32 bits of a 64-bit value */
+#if !defined(UINT64_H)
+#define UINT64_H(X)        ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL))
+#endif
+
+/*! Macro to get lower 32 bits of a 64-bit value */
+#if !defined(UINT64_L)
+#define UINT64_L(X)        ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL))
+#endif
+
+/*!
+ * @def SUPPRESS_FALL_THROUGH_WARNING()
+ *
+ * For switch case code block, if case section ends without "break;" statement, there wil be
+ * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ * case section which misses "break;"statement.
 */
-/* @{ */
 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)
 #define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
 #else
 #define SUPPRESS_FALL_THROUGH_WARNING()
 #endif
-/* @} */

 /*******************************************************************************
 * API
@@ -319,4 +342,4 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
 #include "fsl_common_arm.h"
 #endif

-#endif /* _FSL_COMMON_H_ */
+#endif /* FSL_COMMON_H_ */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2023 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -25,11 +25,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
    extern uint32_t Image$$VECTOR_ROM$$Base[];
    extern uint32_t Image$$VECTOR_RAM$$Base[];
-    extern uint32_t Image$$RW_m_data$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];

 #define __VECTOR_TABLE          Image$$VECTOR_ROM$$Base
 #define __VECTOR_RAM            Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
 #elif defined(__ICCARM__)
    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
    extern uint32_t __VECTOR_TABLE[];
@@ -159,11 +159,11 @@ static void DelayLoop(uint32_t count)
 {
    __ASM volatile("    MOV    X0, %0" : : "r"(count));
    __ASM volatile(
-        "loop:                          \n"
+        "loop%=:                        \n"
        "    SUB    X0, X0, #1          \n"
        "    CMP    X0, #0              \n"

-        "    BNE    loop                \n"
+        "    BNE    loop%=              \n"
        :
        :
        : "r0");
@@ -176,7 +176,7 @@ static void DelayLoop(uint32_t count)
 {
    __ASM volatile("    MOV    R0, %0" : : "r"(count));
    __ASM volatile(
-        "loop:                          \n"
+        "loop%=:                        \n"
 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)
        "    SUB    R0, R0, #1          \n"
 #else
@@ -184,7 +184,7 @@ static void DelayLoop(uint32_t count)
 #endif
        "    CMP    R0, #0              \n"

-        "    BNE    loop                \n"
+        "    BNE    loop%=              \n"
        :
        :
        : "r0");
@@ -232,13 +232,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
        {
        }
 #else
+#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55))
+        /*
+         * Cortex-A53/A55 execution throughput:
+         *  - SUB/CMP: 2 instructions per cycle
+         *  - BNE:     1 instruction per cycle
+         * So, each loop takes 2 CPU cycles.
+         */
+        count = count / 2U;
+#elif (__CORTEX_M == 7)
        /* Divide value may be different in various environment to ensure delay is precise.
         * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
         * two instructions in one period, through test here set divide 1.5. Other M cores use
         * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
         * not matter because other instructions outside while loop is enough to fill the time.
         */
-#if (__CORTEX_M == 7)
        count = count / 3U * 2U;
 #else
        count = count / 4U;
@@ -6,8 +6,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_CRC_H_
-#define _FSL_CRC_H_
+#ifndef FSL_CRC_H_
+#define FSL_CRC_H_

 #include "fsl_common.h"

@@ -21,7 +21,7 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief CRC driver version. Version 2.0.4.
 *
 * Current version: 2.0.4
@@ -30,7 +30,7 @@
 *
 * - Version 2.0.4
 *   - Release peripheral from reset if necessary in init function.
- *
+ * 
 * - Version 2.0.3
 *   - Fix MISRA issues
 *
@@ -41,7 +41,7 @@
 *   - move DATA and DATALL macro definition from header file to source file
 */
 #define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
-/*@}*/
+/*! @} */

 #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
 /*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
@@ -178,4 +178,4 @@ uint16_t CRC_Get16bitResult(CRC_Type *base);
 *@}
 */

-#endif /* _FSL_CRC_H_ */
+#endif /* FSL_CRC_H_ */
@@ -575,3 +575,30 @@ void CTIMER4_DriverIRQHandler(void)
    SDK_ISR_EXIT_BARRIER;
 }
 #endif
+
+#if defined(CTIMER5)
+void CTIMER5_DriverIRQHandler(void);
+void CTIMER5_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(5);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CTIMER6)
+void CTIMER6_DriverIRQHandler(void);
+void CTIMER6_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(6);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CTIMER7)
+void CTIMER7_DriverIRQHandler(void);
+void CTIMER7_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(7);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_CTIMER_H_
-#define _FSL_CTIMER_H_
+#ifndef FSL_CTIMER_H_
+#define FSL_CTIMER_H_

 #include "fsl_common.h"

@@ -22,9 +22,9 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 #define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
-/*@}*/
+/*! @} */

 /*! @brief List of Timer capture channels */
 typedef enum _ctimer_capture_channel
@@ -679,4 +679,4 @@ static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match

 /*! @}*/

-#endif /* _FSL_CTIMER_H_ */
+#endif /* FSL_CTIMER_H_ */
@@ -6,8 +6,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_EIM_H_
-#define _FSL_EIM_H_
+#ifndef FSL_EIM_H_
+#define FSL_EIM_H_

 #include "fsl_common.h"

@@ -21,10 +21,10 @@
 *****************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Driver version. */
 #define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
-/*@}*/
+/*! @} */

 /*******************************************************************************
 * APIs
@@ -47,7 +47,7 @@ void EIM_Init(EIM_Type *base);
 */
 void EIM_Deinit(EIM_Type *base);

-/* @} */
+/*! @} */

 /*!
 * @name functional
@@ -93,7 +93,7 @@ void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)
    /* Initialize Double-set registers */
    EQDC_ClearBufferedRegisterLoadUpdateMode(base);
    EQDC_ClearEqdcLdok(base);
-
+    
    /* Counter value. */
    EQDC_SetPositionCounterValue(base, psConfig->positionCounterValue);

@@ -117,6 +117,9 @@ void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)
    /* Watchdog. */
    EQDC_SetWatchdogTimeout(base, psConfig->watchdogTimeoutValue);

+    /* Clear EQDC_REV */
+    base->REV = 0U;
+
    /* EQDC_IMR. */
    base->IMR = EQDC_IMR_FPHA(psConfig->filterPhaseA) | EQDC_IMR_FPHB(psConfig->filterPhaseB) |
                EQDC_IMR_FIND_PRE(psConfig->filterIndPre) | EQDC_IMR_FHOM_ENA(psConfig->filterHomEna);
@@ -200,7 +203,7 @@ void EQDC_Deinit(EQDC_Type *base)
 *    psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
 *    psConfig->filterSamplePeriod                  = 0U;
 *    psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
- *    psConfig->positionCompareValue[0]         = 0xFFFFFFFFU;
+ *    psConfig->positionCompareValue[0]  	    = 0xFFFFFFFFU;
 *    psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
 *    psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
 *    psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
@@ -295,4 +298,4 @@ void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)
            assert(false);
            break;
    }
-}
+}
@@ -4,8 +4,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_EQDC_H_
-#define _FSL_EQDC_H_
+#ifndef FSL_EQDC_H_
+#define FSL_EQDC_H_

 #include "fsl_common.h"

@@ -17,7 +17,7 @@
 /*******************************************************************************
 * Definitions
 ******************************************************************************/
-#define FSL_EQDC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+#define FSL_EQDC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))

 /*! @brief W1C bits in EQDC CTRL registers. */
 #define EQDC_CTRL_W1C_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK)
@@ -31,9 +31,14 @@
 #define EQDC_CTRL_INT_EN (EQDC_CTRL_HIE_MASK | EQDC_CTRL_XIE_MASK | EQDC_CTRL_WDIE_MASK)

 /*! @brief Interrupt enable bits in EQDC INTCTRL registers. */
+#if (defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
+#define EQDC_INTCTRL_INT_EN                                                                                \
+    (EQDC_INTCTRL_SABIE_MASK | EQDC_INTCTRL_DIRIE_MASK | EQDC_INTCTRL_RUIE_MASK | EQDC_INTCTRL_ROIE_MASK)
+#else
 #define EQDC_INTCTRL_INT_EN                                                                                \
    (EQDC_INTCTRL_SABIE_MASK | EQDC_INTCTRL_DIRIE_MASK | EQDC_INTCTRL_RUIE_MASK | EQDC_INTCTRL_ROIE_MASK | \
     EQDC_INTCTRL_CMP0IE_MASK | EQDC_INTCTRL_CMP1IE_MASK | EQDC_INTCTRL_CMP2IE_MASK | EQDC_INTCTRL_CMP3IE_MASK)
+#endif

 /*! @brief Interrupt flag bits in EQDC CTRL registers. */
 #define EQDC_CTRL_INT_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK)
@@ -43,10 +48,12 @@
    (EQDC_INTCTRL_SABIRQ_MASK | EQDC_INTCTRL_DIRIRQ_MASK | EQDC_INTCTRL_RUIRQ_MASK | EQDC_INTCTRL_ROIRQ_MASK | \
     EQDC_INTCTRL_CMP0IRQ_MASK | EQDC_INTCTRL_CMP1IRQ_MASK | EQDC_INTCTRL_CMP2IRQ_MASK | EQDC_INTCTRL_CMP3IRQ_MASK)

+#if !(defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
 #define kEQDC_PositionCompare0InerruptEnable kEQDC_PositionCompare0InterruptEnable
 #define kEQDC_PositionCompare1InerruptEnable kEQDC_PositionCompare1InterruptEnable
 #define kEQDC_PositionCompare2InerruptEnable kEQDC_PositionCompare2InterruptEnable
 #define kEQDC_PositionCompare3InerruptEnable kEQDC_PositionCompare3InterruptEnable
+#endif

 /*!
 * @brief EQDC status flags, these flags indicate the counter's events.
@@ -134,6 +141,7 @@ enum _eqdc_interrupt_enable
    kEQDC_PositionRollUnderInterruptEnable = (uint32_t)EQDC_INTCTRL_RUIE_MASK
                                             << 16U, /*!< Roll-under interrupt enable. */

+#if !(defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
    kEQDC_PositionCompare0InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP0IE_MASK
                                           << 16U, /*!< Position compare 0 interrupt enable. */
    kEQDC_PositionCompare1InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP1IE_MASK
@@ -142,13 +150,21 @@ enum _eqdc_interrupt_enable
                                           << 16U, /*!< Position compare 2 interrupt enable. */
    kEQDC_PositionCompare3InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP3IE_MASK
                                           << 16U, /*!< Position compare 3 interrupt enable. */
+#endif

+#if (defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
+    kEQDC_AllInterruptEnable = kEQDC_HomeEnableTransitionInterruptEnable | kEQDC_IndexPresetPulseInterruptEnable |
+                               kEQDC_WatchdogTimeoutInterruptEnable | kEQDC_SimultPhaseChangeInterruptEnable |
+                               kEQDC_CountDirectionChangeInterruptEnable | kEQDC_PositionRollOverInterruptEnable |
+                               kEQDC_PositionRollUnderInterruptEnable
+#else
    kEQDC_AllInterruptEnable = kEQDC_HomeEnableTransitionInterruptEnable | kEQDC_IndexPresetPulseInterruptEnable |
                               kEQDC_WatchdogTimeoutInterruptEnable | kEQDC_SimultPhaseChangeInterruptEnable |
                               kEQDC_CountDirectionChangeInterruptEnable | kEQDC_PositionRollOverInterruptEnable |
                               kEQDC_PositionRollUnderInterruptEnable | kEQDC_PositionCompare0InterruptEnable |
                               kEQDC_PositionCompare1InterruptEnable | kEQDC_PositionCompare2InterruptEnable |
                               kEQDC_PositionCompare3InterruptEnable
+#endif
 };

 /*!
@@ -464,7 +480,7 @@ void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig);
    psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
    psConfig->filterSamplePeriod                  = 0U;
    psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
-    psConfig->positionCompareValue[0]             = 0xFFFFFFFFU;
+    psConfig->positionCompareValue[0]  	          = 0xFFFFFFFFU;
    psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
    psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
    psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
@@ -1192,4 +1208,4 @@ static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base)
 /*!
 * @}
 */
-#endif /* _FSL_EQDC_H_ */
+#endif /* FSL_EQDC_H_ */
@@ -6,8 +6,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_ERM_H_
-#define _FSL_ERM_H_
+#ifndef FSL_ERM_H_
+#define FSL_ERM_H_

 #include "fsl_common.h"

@@ -21,10 +21,10 @@
 *****************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Driver version. */
 #define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
-/*@}*/
+/*! @} */

 /*!
 * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.
@@ -78,7 +78,7 @@ void ERM_Init(ERM_Type *base);
 */
 void ERM_Deinit(ERM_Type *base);

-/* @} */
+/*! @} */

 /*!
 * @name Interrupt
@@ -177,7 +177,7 @@ static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t
 #endif
 }

-/* @} */
+/*! @} */

 /*!
 * @name functional
@@ -4,8 +4,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_FREQME_
-#define _FSL_FREQME_
+#ifndef FSL_FREQME_H_
+#define FSL_FREQME_H_

 #include "fsl_common.h"

@@ -19,10 +19,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FREQME driver version 2.1.2. */
 #define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
-/*@}*/
+/*! @} */

 /*!
 * @brief The enumeration of interrupt status flags.
@@ -438,4 +438,4 @@ static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks)
 /*!
 * @}
 */
-#endif /* __FSL_FREQME_H__ */
+#endif /* FSL_FREQME_H_ */
@@ -46,9 +46,8 @@ static inline void Glikey_Internal_Set_WR_1(GLIKEY_Type *base, uint32_t value);

 __WEAK void GLIKEY0_DriverIRQHandler(void)
 {
-    // GLIKEY generates IRQ until corresponding bit in STATUS is cleared by calling
-    // GLIKEY_ClearStatusFlags();
-    //
+    GLIKEY generates IRQ until corresponding bit in STATUS is cleared by calling
+    GLIKEY_ClearStatusFlags();
 }
 */

@@ -81,7 +80,7 @@ uint32_t GLIKEY_GetStatus(GLIKEY_Type *base)

 status_t GLIKEY_IsLocked(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked == retCode)
    {
        return kStatus_GLIKEY_NotLocked;
@@ -104,16 +103,18 @@ status_t GLIKEY_CheckLock(GLIKEY_Type *base)
    return kStatus_GLIKEY_NotLocked;
 }

+#if defined(GLIKEY_VERSION_FSM_CONFIG)
 status_t GLIKEY_GetVersion(GLIKEY_Type *base, uint32_t *result)
 {
    *result = ((GLIKEY_Type *)base)->VERSION;

    return kStatus_Success;
 }
+#endif

 status_t GLIKEY_SyncReset(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -127,7 +128,7 @@ status_t GLIKEY_SyncReset(GLIKEY_Type *base)

 status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -147,7 +148,7 @@ status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value)

 status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -160,7 +161,7 @@ status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)

 status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -174,7 +175,7 @@ status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)
 status_t GLIKEY_Lock(GLIKEY_Type *base)
 {
    /* Check if SFR_LOCK is locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode) /* Glikey is not locked -> lock */
    {
        uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1;
@@ -216,7 +217,7 @@ status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index)
 status_t GLIKEY_LockIndex(GLIKEY_Type *base)
 {
    /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -239,7 +240,7 @@ status_t GLIKEY_LockIndex(GLIKEY_Type *base)
 status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
 {
    /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -262,7 +263,7 @@ status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
    ctrl0 |= GLIKEY_CTRL_0_WRITE_INDEX(index);

    /* Start the enable process by writting 0x01 to CTRL0.WR_EN_0 */
-    ctrl0 = ctrl0 | (0x01u << GLIKEY_CTRL_0_WR_EN_0_SHIFT);
+    ctrl0 = ctrl0 | ((uint32_t)0x01u << GLIKEY_CTRL_0_WR_EN_0_SHIFT);

    /* Write to CTRL0 (new index and WR_EN_0 = 0x01) */
    ((GLIKEY_Type *)base)->CTRL_0 = ctrl0;
@@ -271,7 +272,7 @@ status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
    uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1;
    /* Clear CTRL1.WR_EN_1 */
    ctrl1 &= ~GLIKEY_CTRL_1_WR_EN_1_MASK;
-    //((GLIKEY_Type*)base)->CTRL_1 = ctrl1;
+    ((GLIKEY_Type*)base)->CTRL_1 = ctrl1;

    return kStatus_Success;
 }
@@ -279,7 +280,7 @@ status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
 status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)
 {
    /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -317,7 +318,7 @@ status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)
 status_t GLIKEY_EndOperation(GLIKEY_Type *base)
 {
    /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -341,7 +342,8 @@ status_t GLIKEY_EndOperation(GLIKEY_Type *base)
                return kStatus_GLIKEY_Locked;
            }

-            return kStatus_Success;
+            retCode = kStatus_Success;
+            break;
        }

        case GLIKEY_FSM_SSR_RESET:
@@ -352,19 +354,23 @@ status_t GLIKEY_EndOperation(GLIKEY_Type *base)
            Glikey_Internal_Set_WR_0(base, WR_0_INIT);
            Glikey_Internal_Set_WR_1(base, WR_1_INIT);

-            return kStatus_Success;
+            retCode = kStatus_Success;
+            break;
        }

        default:
            /* Disabled error */
-            return kStatus_GLIKEY_DisabledError;
+            retCode = kStatus_GLIKEY_DisabledError;
+            break;
    }
+
+    return retCode;
 }

 status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index)
 {
    /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
    if (kStatus_GLIKEY_NotLocked != retCode)
    {
        return retCode;
@@ -73,7 +73,6 @@ enum
 /*******************************************************************************
 * API
 *******************************************************************************/
-extern void GLIKEY0_IRQHandler(void);

 #if defined(__cplusplus)
 extern "C" {
@@ -28,6 +28,10 @@
    defined(FSL_FEATURE_SOC_PORT_COUNT)
 static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
 static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#else
+#if defined(GPIO_RESETS_ARRAY)
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#endif
 #endif

 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
@@ -6,8 +6,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_GPIO_H_
-#define _FSL_GPIO_H_
+#ifndef FSL_GPIO_H_
+#define FSL_GPIO_H_

 #include "fsl_common.h"

@@ -21,10 +21,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief GPIO driver version. */
 #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
-/*@}*/
+/*! @} */

 #if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
 #define GPIO_FIT_REG(value) \
@@ -147,7 +147,7 @@ extern "C" {
 */

 /*! @name GPIO Configuration */
-/*@{*/
+/*! @{ */

 /*!
 * @brief Initializes a GPIO pin used by the board.
@@ -312,10 +312,10 @@ static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
 }
 #endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */

-/*@}*/
+/*! @} */

 /*! @name GPIO Output Operations */
-/*@{*/
+/*! @{ */

 /*!
 * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
@@ -394,10 +394,10 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
 #endif
 }

-/*@}*/
+/*! @} */

 /*! @name GPIO Input Operations */
-/*@{*/
+/*! @{ */

 /*!
 * @brief Reads the current input value of the GPIO port.
@@ -413,10 +413,10 @@ static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
    return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
 }

-/*@}*/
+/*! @} */

 /*! @name GPIO Interrupt */
-/*@{*/
+/*! @{ */
 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
    defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
@@ -604,7 +604,7 @@ static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t
 void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
 #endif

-/*@}*/
+/*! @} */
 /*! @} */

 /*!
@@ -623,7 +623,7 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut
 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT

 /*! @name FGPIO Configuration */
-/*@{*/
+/*! @{ */

 #if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
 /*!
@@ -664,10 +664,10 @@ void FGPIO_PortInit(FGPIO_Type *base);
 */
 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);

-/*@}*/
+/*! @} */

 /*! @name FGPIO Output Operations */
-/*@{*/
+/*! @{ */

 /*!
 * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
@@ -722,10 +722,10 @@ static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
 {
    base->PTOR = mask;
 }
-/*@}*/
+/*! @} */

 /*! @name FGPIO Input Operations */
-/*@{*/
+/*! @{ */

 /*!
 * @brief Reads the current input value of the FGPIO port.
@@ -740,10 +740,10 @@ static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
 {
    return (((base->PDIR) >> pin) & 0x01U);
 }
-/*@}*/
+/*! @} */

 /*! @name FGPIO Interrupt */
-/*@{*/
+/*! @{ */
 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
    defined(FSL_FEATURE_SOC_PORT_COUNT)

@@ -784,7 +784,7 @@ void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
 void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
 #endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */

-/*@}*/
+/*! @} */

 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */

@@ -796,4 +796,4 @@ void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attrib
 * @}
 */

-#endif /* _FSL_GPIO_H_*/
+#endif /* FSL_GPIO_H_*/
@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_I3C_EDMA_H_
-#define _FSL_I3C_EDMA_H_
+#ifndef FSL_I3C_EDMA_H_
+#define FSL_I3C_EDMA_H_

 #include "fsl_i3c.h"
 #include "fsl_edma.h"
@@ -14,10 +14,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief I3C EDMA driver version. */
-#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
-/*@}*/
+#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 9))
+/*! @} */

 /*!
 * @addtogroup i3c_master_edma_driver
@@ -125,7 +125,7 @@ extern "C" {
 */

 /*! @name Master DMA */
-/*@{*/
+/*! @{ */

 /*!
 * @brief Create a new handle for the I3C master DMA APIs.
@@ -193,10 +193,10 @@ void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handl
 * @note This function does not need to be called unless you are reimplementing the
 *  nonblocking API's interrupt handler routines to add special functionality.
 * @param base The I3C peripheral base address.
- * @param handle Pointer to the I3C master DMA driver handle.
+ * @param i3cHandle Pointer to the I3C master DMA driver handle.
 */
 void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
-/*@}*/
+/*! @} */

 /*! @} */

@@ -206,7 +206,7 @@ void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
 */

 /*! @name Slave DMA */
-/*@{*/
+/*! @{ */
 /*!
 * @brief Create a new handle for the I3C slave DMA APIs.
 *
@@ -266,14 +266,14 @@ void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)
 * @note This function does not need to be called unless you are reimplementing the
 *  nonblocking API's interrupt handler routines to add special functionality.
 * @param base The I3C peripheral base address.
- * @param handle Pointer to the I3C slave DMA driver handle.
+ * @param i3cHandle Pointer to the I3C slave DMA driver handle.
 */
 void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
-/*@}*/
+/*! @} */

 /*! @} */
 #if defined(__cplusplus)
 }
 #endif

-#endif /* _FSL_I3C_EDMA_H_ */
+#endif /* FSL_I3C_EDMA_H_ */
@@ -6,8 +6,8 @@
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_INPUTMUX_H_
-#define _FSL_INPUTMUX_H_
+#ifndef FSL_INPUTMUX_H_
+#define FSL_INPUTMUX_H_

 #include "fsl_inputmux_connections.h"
 #include "fsl_common.h"
@@ -25,10 +25,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Group interrupt driver version for SDK */
 #define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
-/*@}*/
+/*! @} */

 /*******************************************************************************
 * API
@@ -98,6 +98,6 @@ void INPUTMUX_Deinit(INPUTMUX_Type *base);
 }
 #endif

-/*@}*/
+/*! @} */

-#endif /* _FSL_INPUTMUX_H_ */
+#endif /* FSL_INPUTMUX_H_ */
@@ -62,6 +62,8 @@
 #define LPSPI0_TRIG_REG           0x5E0U
 #define LPSPI1_TRIG_REG           0x600U
 #define LPUART0_TRIG_REG          0x620U
+#define LPUART1_TRIG_REG          0x640U
+#define LPUART2_TRIG_REG          0x660U

 #define PMUX_SHIFT 20U

@@ -1300,6 +1302,74 @@ typedef enum _inputmux_connection_t
    kINPUTMUX_Gpio3PinEventTrig0ToLpuart0Trigger      = 32U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_WuuToLpuart0Trigger                     = 34U + (LPUART0_TRIG_REG << PMUX_SHIFT),
    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart0Trigger = 35U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART1 trigger input connections. */
+    kINPUTMUX_ArmTxevToLpuart1Trigger                 = 1U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToLpuart1Trigger                = 2U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart1Trigger                = 3U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart1Trigger                = 4U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart1Trigger                = 5U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart1Trigger                 = 6U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart1Trigger                 = 7U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart1Trigger               = 9U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart1Trigger               = 10U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart1Trigger               = 11U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart1Trigger               = 12U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart1Trigger               = 13U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart1Trigger               = 14U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart1Trigger                  = 15U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart1Trigger                 = 17U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart1Trigger                 = 18U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart1Trigger                 = 19U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart1Trigger                 = 20U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart1Trigger                 = 21U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart1Trigger                 = 22U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart1Trigger                 = 23U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart1Trigger                 = 24U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart1Trigger                 = 25U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart1Trigger                 = 26U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart1Trigger                = 27U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart1Trigger                = 28U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart1Trigger      = 29U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart1Trigger      = 30U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart1Trigger      = 31U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart1Trigger      = 32U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart1Trigger                     = 34U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart1Trigger = 35U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART2 trigger input connections. */
+    kINPUTMUX_ArmTxevToLpuart2Trigger                 = 1U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToLpuart2Trigger                = 2U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart2Trigger                = 3U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart2Trigger                = 4U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart2Trigger                = 5U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart2Trigger                 = 6U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart2Trigger                 = 7U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart2Trigger               = 9U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart2Trigger               = 10U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart2Trigger               = 11U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart2Trigger               = 12U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart2Trigger               = 13U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart2Trigger               = 14U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart2Trigger                  = 15U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart2Trigger                 = 17U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart2Trigger                 = 18U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart2Trigger                 = 19U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart2Trigger                 = 20U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart2Trigger                 = 21U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart2Trigger                 = 22U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart2Trigger                 = 23U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart2Trigger                 = 24U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart2Trigger                 = 25U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart2Trigger                 = 26U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart2Trigger                = 27U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart2Trigger                = 28U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart2Trigger      = 29U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart2Trigger      = 30U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart2Trigger      = 31U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart2Trigger      = 32U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart2Trigger                     = 34U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart2Trigger = 35U + (LPUART2_TRIG_REG << PMUX_SHIFT),
 } inputmux_connection_t;

 /*@}*/
@@ -29,18 +29,18 @@
 #define ADC_CMDL_CHANNEL_MODE(x) \
    (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CHANNEL_MODE_SHIFT)) & ADC_CMDL_CHANNEL_MODE_MASK)

-#define GET_ADC_CFG_TPRICTRL_VALUE(val) (val & 0x3U)
+#define GET_ADC_CFG_TPRICTRL_VALUE(val) (((uint32_t)val) & 0x3U)

 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES
-#define GET_ADC_CFG_TRES_VALUE(val) ((val & 0x4U) >> 2U)
+#define GET_ADC_CFG_TRES_VALUE(val) ((((uint32_t)val) & 0x4U) >> 2U)
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */

 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES
-#define GET_ADC_CFG_TCMDRES_VALUE(val) ((val & 0x8U) >> 3U)
+#define GET_ADC_CFG_TCMDRES_VALUE(val) ((((uint32_t)val) & 0x8U) >> 3U)
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */

 #if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI
-#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((val & 0x10U) >> 4U)
+#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((((uint32_t)val) & 0x10U) >> 4U)
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */

 #if defined(LPADC_RSTS)
@@ -161,7 +161,6 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
    (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

-
 #if defined(LPADC_RESETS_ARRAY)
    RESET_ReleasePeripheralReset(s_lpadcResets[LPADC_GetInstance(base)]);
 #endif
@@ -220,15 +219,15 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
    tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy));

 #if (defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES)
-    tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE((uint8_t)(config->triggerPriorityPolicy)));
+    tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE(config->triggerPriorityPolicy));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */

 #if (defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES)
-    tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE((uint8_t)(config->triggerPriorityPolicy)));
+    tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE(config->triggerPriorityPolicy));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */

 #if (defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI)
-    tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE((uint8_t)(config->triggerPriorityPolicy)));
+    tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE(config->triggerPriorityPolicy));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */

    base->CFG = tmp32;
@@ -342,10 +341,11 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in

    uint32_t tmp32 = 0U;

-    while (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
+    tmp32 = base->RESFIFO[index];
+
+    if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
    {
-        /* while loop until FIFO is not empty */
-        tmp32 = base->RESFIFO[index];
+        return false; /* FIFO is empty. Discard any read from RESFIFO. */
    }

    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
@@ -355,6 +355,31 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in

    return true;
 }
+/*!
+ * brief Get the result in conversion FIFOn using blocking method.
+ *
+ * param base LPADC peripheral base address.
+ * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
+ * param index Result FIFO index.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index)
+{
+    assert(result != NULL); /* Check if the input pointer is available. */
+
+    uint32_t tmp32 = 0U;
+
+    tmp32 = base->RESFIFO[index];
+
+    while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
+    {
+        tmp32 = base->RESFIFO[index];
+    }
+
+    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
+    result->loopCountIndex  = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
+    result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
+    result->convValue       = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
+}
 #else
 /*!
 * brief Get the result in conversion FIFO.
@@ -370,10 +395,11 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)

    uint32_t tmp32 = 0U;

-    while (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
+    tmp32 = base->RESFIFO;
+
+    if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
    {
-        /* while loop until FIFO is not empty */
-        tmp32 = base->RESFIFO;
+        return false; /* FIFO is empty. Discard any read from RESFIFO. */
    }

    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
@@ -383,6 +409,30 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)

    return true;
 }
+/*!
+ * @brief Get the result in conversion FIFO using blocking method.
+ *
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result)
+{
+    assert(result != NULL); /* Check if the input pointer is available. */
+
+    uint32_t tmp32 = 0U;
+
+    tmp32 = base->RESFIFO;
+
+    while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
+    {
+        tmp32 = base->RESFIFO;
+    }
+
+    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
+    result->loopCountIndex  = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
+    result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
+    result->convValue       = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
+}
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */

 /*!
@@ -453,6 +503,9 @@ void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
 /*!
 * brief Configure conversion command.
 *
+ * note The number of compare value register on different chips is different, that is mean in some chips, some
+ * command buffers do not have the compare functionality.
+ *
 * param base LPADC peripheral base address.
 * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
 * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
@@ -483,7 +536,6 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
    assert(((config->sampleChannelMode >= kLPADC_SampleChannelDiffBothSideAB) &&
            (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) ||
           (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSideAB));
-    tmp32 |= ADC_CMDL_CHANNEL_MODE(config->sampleChannelMode);
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */

 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
@@ -491,8 +543,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
            (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) ||
           ((config->sampleChannelMode == kLPADC_SampleChannelDualSingleEndBothSide) &&
            (((base->VERID) & ADC_VERID_NUM_SEC_MASK) != 0U)) ||
-           (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSide));
-    tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode);
+           (config->sampleChannelMode < kLPADC_SampleChannelDualSingleEndBothSide));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
 #endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */

@@ -533,13 +584,15 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_

    /* Hardware compare settings.
     * Not all Command Buffers have an associated Compare Value register. The compare function is only available on
-     * Command Buffers that have a corresponding Compare Value register.
+     * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be
+     * made before setting the CV register.
     */
-    if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode)
+
+    if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT))
    {
        /* Set CV register. */
-        base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh)   /* Compare value high. */
-                              | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */
+        base->CV[commandId] = (ADC_CV_CVH(config->hardwareCompareValueHigh)    /* Compare value high. */
+                               | ADC_CV_CVL(config->hardwareCompareValueLow)); /* Compare value low. */
    }
 }

@@ -764,8 +817,8 @@ void LPADC_FinishAutoCalibration(ADC_Type *base)
    }

 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
-    GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
-    GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
+    GCCa = (int32_t)(base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
+    GCCb = (int32_t)(base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
    if (0U != ((base->GCC[0]) & 0x8000U))
    {
        GCCa         = GCCa - 0x10000;
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_LPADC_H_
-#define _FSL_LPADC_H_
+#ifndef FSL_LPADC_H_
+#define FSL_LPADC_H_

 #include "fsl_common.h"

@@ -22,10 +22,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
-/*! @brief LPADC driver version 2.7.2. */
-#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 7, 2))
-/*@}*/
+/*! @{ */
+/*! @brief LPADC driver version 2.8.4. */
+#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 8, 4))
+/*! @} */

 #if (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1))
 #define ADC_OFSTRIM_OFSTRIM_MAX  (ADC_OFSTRIM_OFSTRIM_MASK >> ADC_OFSTRIM_OFSTRIM_SHIFT)
@@ -290,8 +290,8 @@ typedef enum _lpadc_sample_channel_mode
    kLPADC_SampleChannelDiffBothSideBA = 0x3U, /*!< Differential mode, the ADC result is (CHnB-CHnA). */
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
-    kLPADC_SampleChannelDualSingleEndBothSide = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */
-    kLPADC_SampleChannelDiffBothSide          = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side
+    kLPADC_SampleChannelDiffBothSide          = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */
+    kLPADC_SampleChannelDualSingleEndBothSide = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side
                                                            channels are converted independently. */
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
 #endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
@@ -816,7 +816,7 @@ static inline void LPADC_DoResetConfig(ADC_Type *base)
    base->CTRL &= ~ADC_CTRL_RST_MASK;
 }

-/* @} */
+/*! @} */

 /*!
 * @name Status
@@ -876,7 +876,7 @@ static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)
 }
 #endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) */

-/* @} */
+/*! @} */

 /*!
 * @name Interrupts
@@ -976,7 +976,7 @@ static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
    }
 }
 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */
-/* @} */
+/*! @} */

 /*!
 * @name Trigger and conversion with FIFO.
@@ -997,15 +997,24 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index)
 }

 /*!
- * brief Get the result in conversion FIFOn.
+ * @brief Get the result in conversion FIFOn.
 *
- * param base LPADC peripheral base address.
- * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
- * param index Result FIFO index.
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
+ * @param index Result FIFO index.
 *
- * return Status whether FIFOn entry is valid.
+ * @return Status whether FIFOn entry is valid.
 */
 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
+
+/*!
+ * @brief Get the result in conversion FIFOn using blocking method.
+ *
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
+ * @param index Result FIFO index.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
 #else  /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */
 /*!
 * @brief Get the count of result kept in conversion FIFO.
@@ -1027,6 +1036,14 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
 * @return Status whether FIFO entry is valid.
 */
 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result);
+
+/*!
+ * @brief Get the result in conversion FIFO using blocking method.
+ *
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result);
 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */

 /*!
@@ -1094,6 +1111,9 @@ static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, u

 /*!
 * @brief Configure conversion command.
+
+ * @note The number of compare value register on different chips is different, that is mean in some chips, some
+ * command buffers do not have the compare functionality.
 *
 * @param base LPADC peripheral base address.
 * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
@@ -1186,8 +1206,6 @@ void LPADC_DoAutoCalibration(ADC_Type *base);
 */
 static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value)
 {
-    assert((value >= -512) && (value <= 511));
-
    base->OFSTRIM = ADC_OFSTRIM_OFSTRIM(value);
 }

@@ -1224,9 +1242,6 @@ static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue)
 */
 static inline void LPADC_SetOffsetValue(ADC_Type *base, int32_t valueA, int32_t valueB)
 {
-    assert((valueA >= -16) && (valueA <= 15));
-    assert((valueB >= -16) && (valueB <= 15));
-
    base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB);
 }

@@ -1503,7 +1518,7 @@ static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable)
 }
 #endif /* (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) */

-/* @} */
+/*! @} */

 #if defined(__cplusplus)
 }
@@ -1511,4 +1526,4 @@ static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable)
 /*!
 * @}
 */
-#endif /* _FSL_LPADC_H_ */
+#endif /* FSL_LPADC_H_ */
@@ -116,15 +116,23 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config)

    /* Configure. */
    LPCMP_Enable(base, false);
+
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
    /* CCR0 register. */
-    if (config->enableStopMode)
+#if defined(FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn)
+    if (1U == FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(base))
+#endif /* FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn */
    {
-        base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK;
-    }
-    else
-    {
-        base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK;
+        if (config->enableStopMode)
+        {
+            base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK;
+        }
+        else
+        {
+            base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK;
+        }
    }
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */

    /* CCR1 register. */
    tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK
@@ -202,8 +210,9 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config)
 {
    /* Initializes the configure structure to zero. */
    (void)memset(config, 0, sizeof(*config));
-
-    config->enableStopMode      = false;
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
+    config->enableStopMode = false;
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
    config->enableOutputPin     = false;
    config->useUnfilteredOutput = false;
    config->enableInvertOutput  = false;
@@ -1,14 +1,14 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2020, 2023 NXP
+ * Copyright 2016-2020, 2023-2024 NXP
 * All rights reserved.
 *
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_LPCMP_H_
-#define _FSL_LPCMP_H_
+#ifndef FSL_LPCMP_H_
+#define FSL_LPCMP_H_

 #include "fsl_common.h"

@@ -22,8 +22,8 @@
 ******************************************************************************/
 /*! @name Driver version */
 /*! @{ */
-/*! @brief LPCMP driver version 2.1.1. */
-#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @brief LPCMP driver version 2.1.3. */
+#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
 /*! @} */

 #define LPCMP_CCR1_COUTA_CFG_MASK  (LPCMP_CCR1_COUTA_OWEN_MASK | LPCMP_CCR1_COUTA_OW_MASK)
@@ -196,7 +196,10 @@ typedef struct _lpcmp_dac_config
 */
 typedef struct _lpcmp_config
 {
-    bool enableStopMode;      /*!< Decide whether to enable the comparator when in STOP modes. */
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
+    bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
+
    bool enableOutputPin;     /*!< Decide whether to enable the comparator is available in selected pin. */
    bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */
    bool enableInvertOutput;  /*!< Decide whether to inverts the comparator output. */
@@ -235,9 +238,12 @@ typedef struct _lpcmp_roundrobin_config
    uint8_t sampleTimeThreshhold; /*!< Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are
                                       "1",the final result is "1", otherwise the final result is "0", note that the
                                       sampleTimeThreshhold must not be larger than channelSampleNumbers. */
-    lpcmp_roundrobin_clock_source_t roundrobinClockSource;    /*!< Decide which clock source to choose in round robin mode. */
-    lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource;  /*!< Decide which trigger source to choose in round robin mode. */
-    lpcmp_roundrobin_fixedmuxport_t fixedMuxPort;           /*!< Decide which mux port to choose as fixed channel in round robin mode. */
+    lpcmp_roundrobin_clock_source_t roundrobinClockSource;     /*!< Decide which clock source to
+                                                        choose in round robin mode. */
+    lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource; /*!< Decide which trigger source to
+                                                        choose in round robin mode. */
+    lpcmp_roundrobin_fixedmuxport_t fixedMuxPort;              /*!< Decide which mux port to choose as
+                                                        fixed channel in round robin mode. */
    uint8_t fixedChannel;       /*!< Indicate which channel of the fixed mux port is used in round robin mode. */
    uint8_t checkerChannelMask; /*!< Indicate which channel of the non-fixed mux port to check its voltage value in
                                     round robin mode, for example, if checkerChannelMask set to 0x11U means select
@@ -576,4 +582,4 @@ static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base)

 /*! @} */

-#endif /* _FSL_LPCMP_H_ */
+#endif /* FSL_LPCMP_H_ */
@@ -39,7 +39,7 @@
 #define LPI2C_RESETS_ARRAY LPI2C_RSTS
 #endif

-/* ! @brief LPI2C master fifo commands. */
+/*! @brief LPI2C master fifo commands. */
 enum
 {
    kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */
@@ -70,16 +70,16 @@ enum
    kWaitForCompletionState,
 };

-/*
- * <! Structure definition for variables that passed as parameters in LPI2C_RunTransferStateMachine.
+/*!
+ * @brief Structure definition for variables that passed as parameters in LPI2C_RunTransferStateMachine.
 * The structure is private.
 */
 typedef struct _lpi2c_state_machine_param
 {
-    bool state_complete;
-    size_t rxCount;
-    size_t txCount;
-    uint32_t status;
+    bool state_complete; /*!< status of complete */
+    size_t rxCount;      /*!< rx count */
+    size_t txCount;      /*!< tx count */
+    uint32_t status;     /*!< machine status */
 } lpi2c_state_machine_param_t;

 /*! @brief Typedef for slave interrupt handler. */
@@ -274,16 +274,15 @@ static uint32_t LPI2C_GetCyclesForWidth(
 }

 /*!
- * @brief Convert provided flags to status code, and clear any errors if present.
- * @param base The LPI2C peripheral base address.
- * @param status Current status flags value that will be checked.
- * @retval #kStatus_Success
- * @retval #kStatus_LPI2C_PinLowTimeout
- * @retval #kStatus_LPI2C_ArbitrationLost
- * @retval #kStatus_LPI2C_Nak
- * @retval #kStatus_LPI2C_FifoError
+ * brief Convert provided flags to status code, and clear any errors if present.
+ * param base The LPI2C peripheral base address.
+ * param status Current status flags value that will be checked.
+ * retval #kStatus_Success
+ * retval #kStatus_LPI2C_PinLowTimeout
+ * retval #kStatus_LPI2C_ArbitrationLost
+ * retval #kStatus_LPI2C_Nak
+ * retval #kStatus_LPI2C_FifoError
 */
-/* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
 {
    status_t result = kStatus_Success;
@@ -323,8 +322,16 @@ status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
        /* Clear the flags. */
        LPI2C_MasterClearStatusFlags(base, status);

-        /* Reset fifos. These flags clear automatically. */
-        base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
+        if (((base->MCFGR1 & LPI2C_MCFGR1_IGNACK_MASK) != 0x00U) && (result == kStatus_LPI2C_Nak))
+        {
+            /* ERR051119: If IGNACK was set and nak detect , we will ignore the Nak status */
+            result = kStatus_Success;
+        }
+        else
+        {
+            /* Reset fifos. These flags clear automatically.*/
+            base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
+        }
    }
    else
    {
@@ -382,13 +389,13 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base)
 }

 /*!
- * @brief Make sure the bus isn't already busy.
+ * brief Make sure the bus isn't already busy.
 *
 * A busy bus is allowed if we are the one driving it.
 *
- * @param base The LPI2C peripheral base address.
- * @retval #kStatus_Success
- * @retval #kStatus_LPI2C_Busy
+ * param base The LPI2C peripheral base address.
+ * retval #kStatus_Success
+ * retval #kStatus_LPI2C_Busy
 */
 /* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)
@@ -547,7 +554,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
        /* Calculate bus idle timeout value. The value is equal to BUSIDLE cycles of functional clock divided by
           prescaler. And set BUSIDLE to 0 disables the fileter, so the min value is 1. */
        cycles       = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, 1U,
-                                         (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
+                                               (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
        base->MCFGR2 = (base->MCFGR2 & (~LPI2C_MCFGR2_BUSIDLE_MASK)) | LPI2C_MCFGR2_BUSIDLE(cycles);
    }
    if (0U != masterConfig->pinLowTimeout_ns)
@@ -555,7 +562,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
        /* Calculate bus pin low timeout value. The value is equal to PINLOW cycles of functional clock divided by
           prescaler. And set PINLOW to 0 disables the fileter, so the min value is 1. */
        cycles       = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256U, 1U,
-                                         (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
+                                               (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
        base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles);
    }

@@ -1115,6 +1122,15 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t
                }
            }
        }
+
+        /* Transmit fail */
+        if (kStatus_Success != result)
+        {
+            if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U)
+            {
+                (void)LPI2C_MasterStop(base);
+            }
+        }
    }

    return result;
@@ -1665,8 +1681,6 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h
 *
 * param base The LPI2C peripheral base address.
 * param handle Pointer to the LPI2C master driver handle.
- * retval #kStatus_Success A transaction was successfully aborted.
- * retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress.
 */
 void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)
 {
@@ -2296,8 +2310,6 @@ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *han
 * note This API could be called at any time to stop slave for handling the bus events.
 * param base The LPI2C peripheral base address.
 * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
- * retval #kStatus_Success
- * retval #kStatus_LPI2C_Idle
 */
 void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
 {
@@ -2355,9 +2367,9 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle
            if (0U !=
                (flags & (((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag) | ((uint32_t)kLPI2C_SlaveStopDetectFlag))))
            {
-                xfer->event = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ?
-                                  kLPI2C_SlaveRepeatedStartEvent :
-                                  kLPI2C_SlaveCompletionEvent;
+                xfer->event            = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ?
+                                             kLPI2C_SlaveRepeatedStartEvent :
+                                             kLPI2C_SlaveCompletionEvent;
                xfer->receivedAddress  = 0U;
                xfer->completionStatus = kStatus_Success;
                xfer->transferredCount = handle->transferredCount;
@@ -2567,6 +2579,24 @@ void LPI2C6_DriverIRQHandler(void)
 }
 #endif

+#if defined(LPI2C7)
+/* Implementation of LPI2C7 handler named in startup code. */
+void LPI2C7_DriverIRQHandler(void);
+void LPI2C7_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(LPI2C7, 7U);
+}
+#endif
+
+#if defined(LPI2C8)
+/* Implementation of LPI2C8 handler named in startup code. */
+void LPI2C8_DriverIRQHandler(void);
+void LPI2C8_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(LPI2C8, 8U);
+}
+#endif
+
 #if defined(CM4_0__LPI2C)
 /* Implementation of CM4_0__LPI2C handler named in startup code. */
 void M4_0_LPI2C_DriverIRQHandler(void);
@@ -30,8 +30,8 @@
 #define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma"
 #endif

-/* @brief Mask to align an address to 32 bytes. */
-#define ALIGN_32_MASK (0x1fU)
+/* @brief Mask to align an address to edma_tcd_t size. */
+#define ALIGN_TCD_SIZE_MASK (sizeof(edma_tcd_t) - 1U)

 /* ! @brief LPI2C master fifo commands. */
 enum _lpi2c_master_fifo_cmd
@@ -313,7 +313,7 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
    }

    /* Get a 32-byte aligned TCD pointer. */
-    edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK));
+    edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_TCD_SIZE_MASK));

    bool hasSendData    = (transfer->direction == kLPI2C_Write) && (transfer->dataSize != 0U);
    bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize != 0U);
@@ -339,10 +339,17 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,

        if (commandCount != 0U)
        {
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            /* Create a software TCD, which will be chained after the commands. */
+            EDMA_TcdResetExt(handle->tx->base, tcd);
+            EDMA_TcdSetTransferConfigExt(handle->tx->base, tcd, &transferConfig, NULL);
+            EDMA_TcdEnableInterruptsExt(handle->tx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#else
            /* Create a software TCD, which will be chained after the commands. */
            EDMA_TcdReset(tcd);
            EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
            EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#endif
            linkTcd = tcd;
        }
        else
@@ -380,9 +387,15 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
               enabling rx dma and disabling tx dma, which will be chained onto the commands transfer,
               and create another software TCD of transfering data and chain it onto the last TCD.
               Notice that in this situation assume tx/rx uses same channel */
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->rx->base, tcd);
+            EDMA_TcdSetTransferConfigExt(handle->rx->base, tcd, &transferConfig, NULL);
+            EDMA_TcdEnableInterruptsExt(handle->rx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#else
            EDMA_TcdReset(tcd);
            EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
            EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#endif

            transferConfig.srcAddr          = (uint32_t)&lpi2c_edma_RecSetting;
            transferConfig.destAddr         = (uint32_t) & (base->MDER);
@@ -393,10 +406,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
            transferConfig.minorLoopBytes   = sizeof(uint8_t);
            transferConfig.majorLoopCounts  = 1;

-            edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_32_MASK));
-
+            edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_TCD_SIZE_MASK));
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->rx->base, tcdSetRxClearTxDMA);
+            EDMA_TcdSetTransferConfigExt(handle->rx->base, tcdSetRxClearTxDMA, &transferConfig, tcd);
+#else
            EDMA_TcdReset(tcdSetRxClearTxDMA);
            EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd);
+#endif
            linkTcd = tcdSetRxClearTxDMA;
        }
    }
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_LPI2C_EDMA_H_
-#define _FSL_LPI2C_EDMA_H_
+#ifndef FSL_LPI2C_EDMA_H_
+#define FSL_LPI2C_EDMA_H_

 #include "fsl_lpi2c.h"
 #include "fsl_edma.h"
@@ -15,11 +15,13 @@
 * Definitions
 ******************************************************************************/

-/*! @name Driver version */
-/*@{*/
+/*!
+ * @name Driver version
+ * @{
+ */
 /*! @brief LPI2C EDMA driver version. */
-#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
+#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
+/*! @} */

 /*!
 * @addtogroup lpi2c_master_edma_driver
@@ -27,6 +29,7 @@
 */

 /* Forward declaration of the transfer descriptor and handle typedefs. */
+/*! @brief LPI2C master EDMA handle of the transfer. */
 typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t;

 /*!
@@ -79,8 +82,10 @@ extern "C" {
 * @{
 */

-/*! @name Master DMA */
-/*@{*/
+/*!
+ * @name Master DMA
+ * @{
+ */

 /*!
 * @brief Create a new handle for the LPI2C master DMA APIs.
@@ -147,7 +152,7 @@ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_ha
 */
 status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle);

-/*@}*/
+/*! @} */

 /*! @} */

@@ -155,4 +160,4 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl
 }
 #endif

-#endif /* _FSL_LPI2C_EDMA_H_ */
+#endif /* FSL_LPI2C_EDMA_H_ */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2022, 2024 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -59,7 +59,7 @@ typedef struct _lpspi_transfer_blocking_param
    bool isPcsContinuous;
    uint8_t bytesEachWrite;
    uint8_t bytesEachRead;    
-    uint8_t *txData;
+    const uint8_t *txData;
    uint8_t *rxData;
    uint32_t rxRemainingByteCount;
 } lpspi_transfer_blocking_param_t;
@@ -94,7 +94,7 @@ static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base,
 * @brief Combine the write data for 1 byte to 4 bytes.
 * This is not a public API.
 */
-static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap);
+static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap);

 /*!
 * @brief Separate the read data for 1 byte to 4 bytes.
@@ -294,9 +294,17 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi

 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

-#if defined(ZQ_RESETS_ARRAY)
+#if defined(LPSPI_RESETS_ARRAY)
    RESET_ReleasePeripheralReset(s_lpspiResets[LPSPI_GetInstance(base)]);
 #endif
+    /* if register exist,software manual reset the register to default and clear FIFO */
+    base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK;
+    base->IER = 0U;
+    base->CR  = 0U;
+    
+    /* Disable LPSPI first */
+    LPSPI_Enable(base, false);
+
    /* Set LPSPI to master */
    LPSPI_SetMasterSlaveMode(base, kLPSPI_Master);

@@ -307,7 +315,11 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi
    base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK |
                                   LPSPI_CFGR1_SAMPLE_MASK)) |
                  LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) |
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+                  LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc) |
+#endif
                  LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay);
+
    if ((masterConfig->pinCfg == kLPSPI_SdiInSdiOut) || (masterConfig->pinCfg == kLPSPI_SdoInSdoOut))
    {
        base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
@@ -358,6 +370,9 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
    masterConfig->cpol         = kLPSPI_ClockPolarityActiveHigh;
    masterConfig->cpha         = kLPSPI_ClockPhaseFirstEdge;
    masterConfig->direction    = kLPSPI_MsbFirst;
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+    masterConfig->pcsFunc            = kLPSPI_PcsAsCs; 
+#endif

    masterConfig->pcsToSckDelayInNanoSec        = (1000000000U / masterConfig->baudRate) / 2U;
    masterConfig->lastSckToPcsDelayInNanoSec    = (1000000000U / masterConfig->baudRate) / 2U;
@@ -953,7 +968,7 @@ static bool LPSPI_MasterTransferWriteAllTxData(LPSPI_Type *base,
        /*Wait until TX FIFO is not full*/
 #if SPI_RETRY_TIMES
        uint32_t waitTimes = SPI_RETRY_TIMES;
-        while (LPSPI_GetTxFifoCount(base) == fifo_size) && ((--waitTimes) != 0U))
+        while ((LPSPI_GetTxFifoCount(base) == fifo_size) && ((--waitTimes) != 0U))
 #else
        while (LPSPI_GetTxFifoCount(base) == fifo_size)
 #endif
@@ -1179,6 +1194,9 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf

    /* Variables */
    uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+    uint32_t width    = (transfer->configFlags & LPSPI_MASTER_WIDTH_MASK) >> LPSPI_MASTER_WIDTH_SHIFT;
+#endif
    uint32_t temp     = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
    lpspi_transfer_blocking_param_t stateParams;
    (void)memset(&stateParams, 0, sizeof(stateParams));
@@ -1206,8 +1224,10 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
    /* Configure transfer control register. */
    base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK |
                               LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+                LPSPI_TCR_WIDTH(width) |
+#endif
                LPSPI_TCR_PCS(whichPcs);
-
    /*TCR is also shared the FIFO, so wait for TCR written.*/
    /*
     * $Branch Coverage Justification$
@@ -1337,6 +1357,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t

    /* Variables */
    bool isRxMask = false;
+    handle->isTxMask = false;
    uint8_t txWatermark;
    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
    uint32_t tmpTimes;
@@ -1457,7 +1478,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
        handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame;
        if (!LPSPI_WaitTxFifoEmpty(base))
        {
-            return false;
+            return kStatus_LPSPI_Timeout;
        }
    }
    else
@@ -2214,6 +2235,8 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle
            handle->state = (uint8_t)kLPSPI_Error;
        }
        handle->errorCount++;
+        /* ERR051588: Clear FIFO after underrun occurs */   
+        LPSPI_FlushFifo(base, true, false);
    }
    /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */
    /*
@@ -2237,7 +2260,7 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle
    }
 }

-static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap)
+static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap)
 {
    assert(txData != NULL);

@@ -2501,6 +2524,15 @@ void LPSPI5_DriverIRQHandler(void)
 }
 #endif

+#if defined(LPSPI6)
+void LPSPI6_DriverIRQHandler(void);
+void LPSPI6_DriverIRQHandler(void)
+{
+    assert(s_lpspiHandle[6] != NULL);
+    LPSPI_CommonIRQHandler(LPSPI6, s_lpspiHandle[6]);
+}
+#endif
+
 #if defined(DMA__LPSPI0)
 void DMA_SPI0_INT_DriverIRQHandler(void);
 void DMA_SPI0_INT_DriverIRQHandler(void)
@@ -1,12 +1,12 @@
 /*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2023, 2024 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_LPSPI_H_
-#define _FSL_LPSPI_H_
+#ifndef FSL_LPSPI_H_
+#define FSL_LPSPI_H_

 #include "fsl_common.h"

@@ -20,10 +20,10 @@
 *********************************************************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPSPI driver version. */
-#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
-/*@}*/
+#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 6, 8))
+/*! @} */

 #ifndef LPSPI_DUMMY_DATA
 /*! @brief LPSPI dummy data if no Tx data.*/
@@ -179,6 +179,15 @@ typedef enum _lpspi_data_out_config
    kLpspiDataOutTristate = 1U  /*!< Data out is tristated when chip select is de-asserted */
 } lpspi_data_out_config_t;

+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+/*! @brief LPSPI cs function configuration. */
+typedef enum _lpspi_pcs_function_config
+{
+    kLPSPI_PcsAsCs = 0U,        /*!< PCS pin select as cs function */
+    kLPSPI_PcsAsData = 1U,      /*!< PCS pin select as date function */
+} lpspi_pcs_function_config_t;
+#endif
+
 /*! @brief LPSPI transfer width configuration. */
 typedef enum _lpspi_transfer_width
 {
@@ -197,6 +206,10 @@ typedef enum _lpspi_delay_type

 #define LPSPI_MASTER_PCS_SHIFT (4U)    /*!< LPSPI master PCS shift macro , internal used. */
 #define LPSPI_MASTER_PCS_MASK  (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+#define LPSPI_MASTER_WIDTH_SHIFT (16U)      /*!< LPSPI master width shift macro, internal used */
+#define LPSPI_MASTER_WIDTH_MASK  (0x30000U) /*!< LPSPI master width shift mask, internal used */
+#endif

 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */
 enum _lpspi_transfer_config_flag_for_master
@@ -205,6 +218,11 @@ enum _lpspi_transfer_config_flag_for_master
    kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */
    kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */
    kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+    kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */
+    kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */
+    kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */
+#endif

    kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */

@@ -278,7 +296,10 @@ typedef struct _lpspi_master_config

    lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
                                *during single bit transfers.*/
-
+    
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+    lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/
+#endif
    lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
                                            * between accesses (LPSPI_PCS is negated). */
    bool enableInputDelay; /*!< Enable master to sample the input data on a delayed SCK. This can help improve slave
@@ -342,7 +363,7 @@ typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
 /*! @brief LPSPI master/slave transfer structure.*/
 typedef struct _lpspi_transfer
 {
-    uint8_t *txData;          /*!< Send buffer. */
+    const uint8_t *txData;    /*!< Send buffer. */
    uint8_t *rxData;          /*!< Receive buffer. */
    volatile size_t dataSize; /*!< Transfer bytes. */

@@ -368,7 +389,7 @@ struct _lpspi_master_handle
    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */

-    uint8_t *volatile txData;             /*!< Send buffer. */
+    const uint8_t *volatile txData;            /*!< Send buffer. */
    uint8_t *volatile rxData;             /*!< Receive buffer. */
    volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
    volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -398,7 +419,7 @@ struct _lpspi_slave_handle
    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */

-    uint8_t *volatile txData; /*!< Send buffer. */
+    const uint8_t *volatile txData;           /*!< Send buffer. */
    uint8_t *volatile rxData; /*!< Receive buffer. */

    volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
@@ -514,6 +535,7 @@ static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
    {
        base->CR &= ~LPSPI_CR_MEN_MASK;
    }
+#if defined(FSL_FEATURE_LPSPI_HAS_ERRATA_051472) && FSL_FEATURE_LPSPI_HAS_ERRATA_051472
    /* ERRATA051472: The SR[REF] would assert if software disables the LPSPI module 
       after receiving some data and then enabled the LPSPI again without performing a software reset.
       Clear SR[REF] flag after LPSPI module enabled*/
@@ -521,6 +543,7 @@ static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
    {
        base->SR = (uint32_t)kLPSPI_ReceiveErrorFlag;
    }
+#endif
 }

 /*!
@@ -1205,4 +1228,4 @@ bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base);

 /*! @}*/

-#endif /*_FSL_LPSPI_H_*/
+#endif /*FSL_LPSPI_H_*/
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_LPSPI_EDMA_H_
-#define _FSL_LPSPI_EDMA_H_
+#ifndef FSL_LPSPI_EDMA_H_
+#define FSL_LPSPI_EDMA_H_

 #include "fsl_lpspi.h"
 #include "fsl_edma.h"
@@ -20,10 +20,13 @@
 * Definitions
 **********************************************************************************************************************/
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPSPI EDMA driver version. */
-#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
+#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4))
+
+/*! @brief DMA max transfer size */
+#define DMA_MAX_TRANSFER_COUNT 0x7FFFU
+/*! @} */

 /*!
 * @brief Forward declaration of the _lpspi_master_edma_handle typedefs.
@@ -63,89 +66,98 @@ typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base,
 /*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */
 struct _lpspi_master_edma_handle
 {
-    volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */
+    volatile bool isPcsContinuous;            /*!< Is PCS continuous in transfer. */

-    volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
+    volatile bool isByteSwap;                 /*!< A flag that whether should byte swap. */

-    volatile uint8_t fifoSize; /*!< FIFO dataSize. */
+    volatile uint8_t fifoSize;                /*!< FIFO dataSize. */

-    volatile uint8_t rxWatermark; /*!< Rx watermark. */
+    volatile uint8_t rxWatermark;             /*!< Rx watermark. */

-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
+    volatile uint8_t bytesEachWrite;          /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;           /*!< Bytes for each read RDR. */

-    volatile uint8_t bytesLastRead;    /*!< Bytes for last read RDR. */
-    volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */
+    volatile uint8_t bytesLastRead;           /*!< Bytes for last read RDR. */
+    volatile bool isThereExtraRxBytes;        /*!< Is there extra RX byte. */

-    uint8_t *volatile txData;             /*!< Send buffer. */
-    uint8_t *volatile rxData;             /*!< Receive buffer. */
-    volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
-    volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
+    const uint8_t *volatile txData;           /*!< Send buffer. */
+    uint8_t *volatile rxData;                 /*!< Receive buffer. */
+    volatile size_t txRemainingByteCount;     /*!< Number of bytes remaining to send.*/
+    volatile size_t rxRemainingByteCount;     /*!< Number of bytes remaining to receive.*/

    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times. */

-    uint32_t totalByteCount; /*!< Number of transfer bytes*/
+    uint32_t totalByteCount;                  /*!< Number of transfer bytes*/

-    uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
-    uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
+    edma_tcd_t *lastTimeTCD;                  /*!< Pointer to the lastTime TCD*/
+    bool isMultiDMATransmit;                  /*!< Is there multi DMA transmit*/
+    volatile uint8_t dmaTransmitTime;         /*!< DMA Transfer times. */
+    uint32_t lastTimeDataBytes;               /*!< DMA transmit last Time data Bytes */

-    uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/
+    uint32_t dataBytesEveryTime;             /*!< Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT */

-    volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
+    edma_transfer_config_t transferConfigRx; /*!< Config of DMA rx channel.*/
+    edma_transfer_config_t transferConfigTx; /*!< Config of DMA tx channel.*/
+    uint32_t txBuffIfNull;                   /*!< Used if there is not txData for DMA purpose.*/
+    uint32_t rxBuffIfNull;                   /*!< Used if there is not rxData for DMA purpose.*/

-    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+    uint32_t transmitCommand;                /*!< Used to write TCR for DMA purpose.*/
+
+    volatile uint8_t state;                  /*!< LPSPI transfer state , _lpspi_transfer_state.*/
+
+    uint8_t nbytes;                          /*!< eDMA minor byte transfer count initially configured. */

    lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */
    void *userData;                                 /*!< Callback user data. */

-    edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
-    edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg buff*/
+    edma_handle_t *edmaRxRegToRxDataHandle;         /*!<edma_handle_t handle point used for RxReg to RxData buff*/
+    edma_handle_t *edmaTxDataToTxRegHandle;         /*!<edma_handle_t handle point used for TxData to TxReg buff*/

-    edma_tcd_t lpspiSoftwareTCD[3]; /*!<SoftwareTCD, internal used*/
+    edma_tcd_t lpspiSoftwareTCD[3];                 /*!<SoftwareTCD, internal used*/
 };

 /*! @brief LPSPI slave eDMA transfer handle structure used for transactional API.*/
 struct _lpspi_slave_edma_handle
 {
-    volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
+    volatile bool isByteSwap;                      /*!< A flag that whether should byte swap. */

-    volatile uint8_t fifoSize; /*!< FIFO dataSize. */
+    volatile uint8_t fifoSize;                     /*!< FIFO dataSize. */

-    volatile uint8_t rxWatermark; /*!< Rx watermark. */
+    volatile uint8_t rxWatermark;                  /*!< Rx watermark. */

-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
+    volatile uint8_t bytesEachWrite;               /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;                /*!< Bytes for each read RDR. */

-    volatile uint8_t bytesLastRead;    /*!< Bytes for last read RDR. */
-    volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */
+    volatile uint8_t bytesLastRead;                /*!< Bytes for last read RDR. */
+    volatile bool isThereExtraRxBytes;             /*!< Is there extra RX byte. */

-    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+    uint8_t nbytes;                                /*!< eDMA minor byte transfer count initially configured. */

-    uint8_t *volatile txData;             /*!< Send buffer. */
-    uint8_t *volatile rxData;             /*!< Receive buffer. */
-    volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
-    volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
+    const uint8_t *volatile txData;                /*!< Send buffer. */
+    uint8_t *volatile rxData;                      /*!< Receive buffer. */
+    volatile size_t txRemainingByteCount;          /*!< Number of bytes remaining to send.*/
+    volatile size_t rxRemainingByteCount;          /*!< Number of bytes remaining to receive.*/

-    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
-    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times. */
+    volatile uint32_t writeRegRemainingTimes;      /*!< Write TDR register remaining times. */
+    volatile uint32_t readRegRemainingTimes;       /*!< Read RDR register remaining times. */

-    uint32_t totalByteCount; /*!< Number of transfer bytes*/
+    uint32_t totalByteCount;                       /*!< Number of transfer bytes*/

-    uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
-    uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
+    uint32_t txBuffIfNull;                         /*!< Used if there is not txData for DMA purpose.*/
+    uint32_t rxBuffIfNull;                         /*!< Used if there is not rxData for DMA purpose.*/

-    volatile uint8_t state; /*!< LPSPI transfer state.*/
+    volatile uint8_t state;                        /*!< LPSPI transfer state.*/

-    uint32_t errorCount; /*!< Error count for slave transfer.*/
+    uint32_t errorCount;                           /*!< Error count for slave transfer.*/

    lpspi_slave_edma_transfer_callback_t callback; /*!< Completion callback. */
    void *userData;                                /*!< Callback user data. */

-    edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
-    edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg*/
+    edma_handle_t *edmaRxRegToRxDataHandle;        /*!<edma_handle_t handle point used for RxReg to RxData buff*/
+    edma_handle_t *edmaTxDataToTxRegHandle;        /*!<edma_handle_t handle point used for TxData to TxReg*/

-    edma_tcd_t lpspiSoftwareTCD[2]; /*!<SoftwareTCD, internal used*/
+    edma_tcd_t lpspiSoftwareTCD[2];                /*!<SoftwareTCD, internal used*/
 };

 /***********************************************************************************************************************
@@ -205,7 +217,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 /*!
 * @brief LPSPI master config transfer parameter while using eDMA.
 *
- * This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite. 
+ * This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.
 *
 * @param base LPSPI peripheral base address.
 * @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
@@ -214,7 +226,9 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 * @retval kStatus_Success          Execution successfully.
 * @retval kStatus_LPSPI_Busy       The LPSPI device is busy.
 */
-status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags);
+status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base,
+                                             lpspi_master_edma_handle_t *handle,
+                                             uint32_t configFlags);

 /*!
 * @brief LPSPI master transfer data using eDMA without configs.
@@ -223,7 +237,7 @@ status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma
 * is transferred, the callback function is called.
 *
 * Note:
- * This API is only for transfer through DMA without configuration. 
+ * This API is only for transfer through DMA without configuration.
 * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once.
 * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
 * For bytesPerFrame greater than 4:
@@ -336,4 +350,4 @@ status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_hand

 /*! @}*/

-#endif /*_FSL_LPSPI_EDMA_H_*/
+#endif /*FSL_LPSPI_EDMA_H_*/
@@ -165,9 +165,19 @@ void LPTMR_GetDefaultConfig(lptmr_config_t *config)
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
    config->prescalerClockSource = kLPTMR_PrescalerClock_1;
-#else
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
    config->prescalerClockSource = kLPTMR_PrescalerClock_0;
-#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_2;
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_3;
+#else
+#error No valid source
+#endif
+
    /* Divide the prescaler clock by 2 */
    config->value = kLPTMR_Prescale_Glitch_0;
 }
@@ -1,12 +1,12 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2023 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_LPTMR_H_
-#define _FSL_LPTMR_H_
+#ifndef FSL_LPTMR_H_
+#define FSL_LPTMR_H_

 #include "fsl_common.h"

@@ -20,9 +20,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
-#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
-/*@}*/
+/*! @{ */
+/*! Driver Version */
+#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @} */

 /*! @brief LPTMR pin selection used in pulse counter mode.*/
 typedef enum _lptmr_pin_select
@@ -74,12 +75,21 @@ typedef enum _lptmr_prescaler_glitch_value
 */
 typedef enum _lptmr_prescaler_clock_select
 {
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
    kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
+#endif
+
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
    kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
 #endif                              /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
+
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
    kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
+#endif
+
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
    kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
@@ -371,4 +381,4 @@ static inline void LPTMR_StopTimer(LPTMR_Type *base)

 /*! @}*/

-#endif /* _FSL_LPTMR_H_ */
+#endif /* FSL_LPTMR_H_ */
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_LPUART_EDMA_H_
-#define _FSL_LPUART_EDMA_H_
+#ifndef FSL_LPUART_EDMA_H_
+#define FSL_LPUART_EDMA_H_

 #include "fsl_lpuart.h"
 #include "fsl_edma.h"
@@ -21,10 +21,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPUART EDMA driver version. */
 #define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
-/*@}*/
+/*! @} */

 /* Forward declaration of the handle typedef. */
 typedef struct _lpuart_edma_handle lpuart_edma_handle_t;
@@ -178,7 +178,7 @@ status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handl
 */
 void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle);

-/*@}*/
+/*! @} */

 #if defined(__cplusplus)
 }
@@ -186,4 +186,4 @@ void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle);

 /*! @}*/

-#endif /* _FSL_LPUART_EDMA_H_ */
+#endif /* FSL_LPUART_EDMA_H_ */
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2021 NXP
+ * Copyright 2018-2021, 2023 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -375,20 +375,10 @@ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb)
    }
 }

-#if defined(OSTIMER0)
 void OS_EVENT_DriverIRQHandler(void);
 void OS_EVENT_DriverIRQHandler(void)
 {
-    s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]);
+    s_ostimerIsr(s_ostimerBases[0], s_ostimerHandle[0]);
    SDK_ISR_EXIT_BARRIER;
 }
-#endif

-#if defined(OSTIMER)
-void OS_EVENT_DriverIRQHandler(void);
-void OS_EVENT_DriverIRQHandler(void)
-{
-    s_ostimerIsr(OSTIMER, s_ostimerHandle[0]);
-    SDK_ISR_EXIT_BARRIER;
-}
-#endif
@@ -4,8 +4,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_OSTIMER_H_
-#define _FSL_OSTIMER_H_
+#ifndef FSL_OSTIMER_H_
+#define FSL_OSTIMER_H_

 #include "fsl_common.h"

@@ -21,10 +21,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief OSTIMER driver version. */
-#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
-/*@}*/
+#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*! @} */

 /*!
 * @brief OSTIMER status flags.
@@ -149,7 +149,7 @@ status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callb
 * value to gray code.
 *
 * @param base   OSTIMER peripheral base address.
- * @param count  OSTIMER timer match value (Value is gray-code format).
+ * @param value  OSTIMER timer match value (Value is gray-code format).
 */
 static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value)
 {
@@ -262,7 +262,7 @@ uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base);
 * @return       none
 */
 void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb);
-/* @} */
+/*! @} */

 #if defined(__cplusplus)
 }
@@ -270,4 +270,4 @@ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb);

 /*! @}*/

-#endif /* _FSL_OSTIMER_H_ */
+#endif /* FSL_OSTIMER_H_ */
@@ -1,12 +1,12 @@
 /*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2022, 2024 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_PORT_H_
-#define _FSL_PORT_H_
+#ifndef FSL_PORT_H_
+#define FSL_PORT_H_

 #include "fsl_common.h"

@@ -25,10 +25,10 @@
 #endif

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief PORT driver version. */
-#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*! @} */

 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
 /*! @brief Internal resistor pull feature selection */
@@ -125,8 +125,12 @@ enum _port_lock_register
 /*! @brief Pin mux selection */
 typedef enum _port_mux
 {
+#if defined(FSL_FEATURE_PORT_PCR_MUX_GPIO) && (FSL_FEATURE_PORT_PCR_MUX_GPIO == 0)
+    kPORT_MuxAsGpio           = 0U,  /*!< Corresponding pin is configured as GPIO. */
+#else
    kPORT_PinDisabledOrAnalog = 0U,  /*!< Corresponding pin is disabled, but is used as an analog pin. */
    kPORT_MuxAsGpio           = 1U,  /*!< Corresponding pin is configured as GPIO. */
+#endif
    kPORT_MuxAlt0             = 0U,  /*!< Chip-specific */
    kPORT_MuxAlt1             = 1U,  /*!< Chip-specific */
    kPORT_MuxAlt2             = 2U,  /*!< Chip-specific */
@@ -295,9 +299,10 @@ typedef enum _port_voltage_range
 extern "C" {
 #endif

-#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
 /*! @name Configuration */
-/*@{*/
+/*! @{ */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH

 #if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
 /*!
@@ -497,10 +502,10 @@ static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digit
 }

 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
-/*@}*/
+/*! @} */

 /*! @name Interrupt */
-/*@{*/
+/*! @{ */

 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
 /*!
@@ -668,7 +673,7 @@ static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
 }
 #endif /* FSL_FEATURE_PORT_SUPPORT_EFT */

-/*@}*/
+/*! @} */

 #if defined(__cplusplus)
 }
@@ -676,4 +681,4 @@ static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)

 /*! @}*/

-#endif /* _FSL_PORT_H_ */
+#endif /* FSL_PORT_H_ */
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_PWM_H_
-#define _FSL_PWM_H_
+#ifndef FSL_PWM_H_
+#define FSL_PWM_H_

 #include "fsl_common.h"

@@ -19,9 +19,9 @@
 * Definitions
 ******************************************************************************/
 /*! @name Driver version */
-/*@{*/
-#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 7, 1)) /*!< Version 2.7.1 */
-/*@}*/
+/*! @{ */
+#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) /*!< Version 2.8.4 */
+/*! @} */

 /*! Number of bits per submodule for software output control */
 #define PWM_SUBMODULE_SWCONTROL_WIDTH 2
@@ -508,7 +508,9 @@ void PWM_GetDefaultConfig(pwm_config_t *config);
 *                    Array size should not be more than 2 as each submodule has 2 pins to output PWM
 * @param mode        PWM operation mode, options available in enumeration ::pwm_mode_t
 * @param pwmFreq_Hz  PWM signal frequency in Hz
- * @param srcClock_Hz PWM main counter clock in Hz.
+ * @param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from
+ *                    submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0
+ *                    prescaler value instead of submodule0 source clock.
 *
 * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise
 */
@@ -521,14 +523,14 @@ status_t PWM_SetupPwm(PWM_Type *base,
                      uint32_t srcClock_Hz);

 /*!
- * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle..
+ * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle.
 *
 * @param base        PWM peripheral base address
 * @param subModule   PWM submodule to configure
 * @param pwmChannel  PWM channel to configure
 * @param pwmFreq_Hz  PWM signal frequency in Hz
 * @param srcClock_Hz PWM main counter clock in Hz.
- * @param shiftvalue  Phase shift value
+ * @param shiftvalue  Phase shift value, range in 0 ~ 50
 * @param doSync      true: Set LDOK bit for the submodule list;
 *                    false: LDOK bit don't set, need to call PWM_SetPwmLdok to sync update.
 *
@@ -581,6 +583,36 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base,
 void PWM_UpdatePwmDutycycleHighAccuracy(
    PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle);

+/*!
+ * @brief Update the PWM signal's period and dutycycle for a PWM submodule.
+ *
+ * The function updates PWM signal period generated by a specific submodule according to the parameters
+ * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle
+ * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by  
+ * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function 
+ * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register
+ * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time 
+ * period specified by the user. PWM signal will not be generated if its period is less than dead time duration.
+ *
+ * @param base        PWM peripheral base address
+ * @param subModule   PWM submodule to configure
+ * @param pwmSignal   Signal (PWM A or PWM B) to update
+ * @param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t
+ * @param pulseCnt    New PWM period, value should be between 0 to 65535
+ *                    0=minimum PWM period...
+ *                    65535=maximum PWM period
+ * @param dutyCycle   New PWM pulse width of channel, value should be between 0 to 65535
+ *                    0=inactive signal(0% duty cycle)...
+ *                    65535=active signal (100% duty cycle)
+ *                    You can keep original duty cycle or update new duty cycle
+ */
+void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base,
+                                         pwm_submodule_t subModule,
+                                         pwm_channels_t pwmSignal,
+                                         pwm_mode_t currPwmMode,
+                                         uint16_t pulseCnt,
+                                         uint16_t dutyCycle);
+
 /*! @}*/

 /*!
@@ -1337,4 +1369,4 @@ static inline void PWM_SetFilterSamplePeriod(PWM_Type *base,

 /*! @}*/

-#endif /* _FSL_PWM_H_ */
+#endif /* FSL_PWM_H_ */
@@ -68,6 +68,10 @@ void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
        MRCC0->MRCC_GLB_RST1_SET = bitMask;
        pResetCtrl               = &(MRCC0->MRCC_GLB_RST1);
    }
+    else
+    {
+     /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */
+    } 
    /* wait until it reads 0b1 */
    while (0u == ((*pResetCtrl) & bitMask))
    {
@@ -109,6 +113,10 @@ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
        MRCC0->MRCC_GLB_RST1_CLR = bitMask;
        pResetCtrl               = &(MRCC0->MRCC_GLB_RST1);
    }
+    else
+    {
+     /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */
+    } 
    /* wait until it reads 0b0 */
    while (bitMask == ((*pResetCtrl) & bitMask))
    {
@@ -119,7 +119,7 @@ typedef enum _SYSCON_RSTn
    } /* Reset bits for LPUART peripheral */
 #define LPSPI_RSTS                                     \
    {                                                  \
-        kLPSPI0_RST_SHIFT_RSTn, kLPSPI0_RST_SHIFT_RSTn \
+        kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn \
    } /* Reset bits for LPSPI peripheral */
 #define LPI2C_RSTS             \
    {                          \
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_TRDC_SOC_H_
+#define _FSL_TRDC_SOC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup trdc_soc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+ /* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.trdc_soc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_TRDC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK      0x000003FFUL
+#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK  0x001F0000UL
+#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT 16U
+#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x)  (((uint32_t)(x) & 0xFUL) << 8U)
+#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) (((uint32_t)(x) & 0x1UL) << 16U)
+
+/*!@brief TRDC feature */
+#define FSL_FEATURE_TRDC_DOMAIN_COUNT 1
+
+/*!@brief TRDC base address convert macro */
+#define TRDC_MBC_COUNT 1
+#define TRDC_MBC_OFFSET(x)  0x0000 /* MBC register offset in TRDC_Type structure. */
+#define TRDC_MBC_ARRAY_STEP 0U     /* Offset between two MBC control block, useless if there is only one. */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_TRDC_SOC_H_ */
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_UTICK_H_
-#define _FSL_UTICK_H_
+#ifndef FSL_UTICK_H_
+#define FSL_UTICK_H_

 #include "fsl_common.h"
 /*!
@@ -21,10 +21,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief UTICK driver version 2.0.5. */
 #define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
-/*@}*/
+/*! @} */

 /*! @brief UTICK timer operational mode. */
 typedef enum _utick_mode
@@ -107,7 +107,7 @@ void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_ca
 */
 void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);

-/* @} */
+/*! @} */

 #if defined(__cplusplus)
 }
@@ -115,4 +115,4 @@ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);

 /*! @}*/

-#endif /* _FSL_UTICK_H_ */
+#endif /* FSL_UTICK_H_ */
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -78,7 +78,7 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base,

    if (operateMode == kVBAT_Osc32kEnabledToLowPowerBackupMode)
    {
-        if ((extalCap & 0x1U) != 0U)
+        if (((uint8_t)extalCap & 0x1U) != 0U)
        {
            return kStatus_VBAT_WrongCapacitanceValue;
        }
@@ -91,11 +91,11 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base,
        base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) |
                         (VBAT_OSCCTLA_XTAL_CAP_SEL(xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(extalCap)));
        base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) |
-                         VBAT_OSCCTLA_XTAL_CAP_SEL(~xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~extalCap));
+                         VBAT_OSCCTLA_XTAL_CAP_SEL(~(uint32_t)xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~(uint32_t)extalCap));
    }

    base->OSCCTLA = (((base->OSCCTLA & ~VBAT_OSCCTLA_MODE_EN_MASK)) | VBAT_OSCCTLA_MODE_EN(operateMode));
-    base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN((uint8_t)~operateMode));
+    base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN(~(uint32_t)operateMode));

    return kStatus_Success;
 }
@@ -1,12 +1,12 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

-#ifndef _FSL_VBAT_H_
-#define _FSL_VBAT_H_
+#ifndef FSL_VBAT_H_
+#define FSL_VBAT_H_

 #include "fsl_common.h"

@@ -21,10 +21,16 @@

 /*! @name Driver version */
 /*@{*/
-/*! @brief VBAT driver version 2.2.0. */
-#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @brief VBAT driver version 2.3.1. */
+#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
 /*@}*/

+#if !defined(VBAT_LDORAMC_RET_MASK)
+#define VBAT_LDORAMC_RET_MASK   (0xF00U)
+#define VBAT_LDORAMC_RET_SHIFT  (8U) 
+#define VBAT_LDORAMC_RET(x)     (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK)
+#endif 
+
 /*!
 * @brief The enumeration of VBAT module status.
 */
@@ -527,7 +533,7 @@ static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable)

        /* Polling status register to check clock is ready. */
        while ((base->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0UL)
-            ;
+        {}
    }
    else
    {
@@ -561,6 +567,7 @@ static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass)
    }
 }

+#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) 
 /*!
 * @brief Adjust 32k crystal oscillator amplifier gain.
 *
@@ -575,6 +582,20 @@ static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_
    base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) |
                     (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(~fine)));
 }
+#else
+/*!
+ * @brief Adjust 32k crystal oscillator amplifier gain.
+ *
+ * @param base VBAT peripheral base address.
+ * @param coarse Specify amplifier coarse trim value.
+ */
+static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse)
+{
+    base->OSCCTLA = (base->OSCCTLA & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse));
+    base->OSCCTLB = (base->OSCCTLB & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~(uint32_t)coarse));        
+}
+
+#endif /*  */

 /*!
 * @brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin.
@@ -602,7 +623,7 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base,
 static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime)
 {
    base->OSCCFGA = ((base->OSCCFGA & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(startupTime));
-    base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~startupTime));
+    base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~((uint32_t)startupTime)));
 }

 /*!
@@ -614,7 +635,7 @@ static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32
 static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue)
 {
    base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(comparatorTrimValue));
-    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~comparatorTrimValue));
+    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~((uint32_t)comparatorTrimValue)));
 }

 /*!
@@ -626,7 +647,7 @@ static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base,
 static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue)
 {
    base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(delayTrimValue));
-    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~delayTrimValue));
+    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~((uint32_t)delayTrimValue)));
 }

 /*!
@@ -638,7 +659,7 @@ static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8
 static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue)
 {
    base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(capacitorTrimValue));
-    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~capacitorTrimValue));
+    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~((uint32_t)capacitorTrimValue)));
 }

 /*!
@@ -835,7 +856,7 @@ static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base)
 */
 static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)
 {
-    base->LDORAMC |= VBAT_LDORAMC_RET(sramMask);
+    base->LDORAMC |= (uint32_t)VBAT_LDORAMC_RET(sramMask);
 }

 /*!
@@ -846,7 +867,7 @@ static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sr
 */
 static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)
 {
-    base->LDORAMC &= ~VBAT_LDORAMC_RET(sramMask);
+    base->LDORAMC &= ~(uint32_t)VBAT_LDORAMC_RET(sramMask);
 }

 /*!
@@ -951,7 +972,7 @@ static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_i
 */
 static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base)
 {
-    return (base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK);
+    return (vbat_internal_module_supply_t)(uint8_t)(base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK);
 }

 /*!
@@ -1362,4 +1383,4 @@ static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert)
 /*!
 * @}
 */
-#endif /* __FSL_VBAT_H__ */
+#endif /* FSL_VBAT_H__ */
@@ -4,8 +4,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_WAKETIMER_H_
-#define _FSL_WAKETIMER_H_
+#ifndef FSL_WAKETIMER_H_
+#define FSL_WAKETIMER_H_

 #include "fsl_common.h"

@@ -21,10 +21,10 @@
 ******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief WAKETIMER driver version. */
 #define FSL_WAKETIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
-/*@}*/
+/*! @} */

 /*!
 * @brief WAKETIMER status flags.
@@ -209,4 +209,4 @@ uint32_t WAKETIMER_GetCurrentTimerValue(WAKETIMER_Type *base);

 /*! @}*/

-#endif /* _FSL_WAKETIMER_H_ */
+#endif /* FSL_WAKETIMER_H_ */
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019-2023 NXP.
+ * Copyright 2019-2024 NXP.
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -118,6 +118,26 @@ void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu
    }
 }

+/*!
+ * brief Disable and clear external wakeup pin settings.
+ * 
+ * param base MUU peripheral base address.
+ * param pinIndex The index of the external input pin.
+ */
+void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex)
+{
+    if (pinIndex <= 15U)
+    {
+        base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex));
+        base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex));
+    }
+    else
+    {
+        base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL)));
+        base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL)));
+    }
+}
+
 /*!
 * brief Config Internal modules' event as the wake up soures.
 *
@@ -1,11 +1,11 @@
 /*
- * Copyright 2019-2023 NXP.
+ * Copyright 2019-2024 NXP.
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_WUU_H_
-#define _FSL_WUU_H_
+#ifndef FSL_WUU_H_
+#define FSL_WUU_H_

 #include "fsl_common.h"

@@ -17,10 +17,10 @@
 *******************************************************************************/

 /*! @name Driver version */
-/*@{*/
-/*! @brief Defines WUU driver version 2.3.0. */
-#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
-/*@}*/
+/*! @{ */
+/*! @brief Defines WUU driver version 2.4.0. */
+#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
+/*! @} */

 /*!
 * @brief External WakeUp pin edge detection enumeration.
@@ -135,6 +135,14 @@ extern "C" {
 */
 void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config);

+/*!
+ * @brief Disable and clear external wakeup pin settings.
+ * 
+ * @param base MUU peripheral base address.
+ * @param pinIndex The index of the external input pin.
+ */
+void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex);
+
 /*!
 * @brief Gets External Wakeup pin flags.
 *
@@ -160,7 +168,7 @@ static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask
 {
    base->PF = mask;
 }
-/* @} */
+/*! @} */

 /*!
 * @name Internal Wakeup Module control APIs.
@@ -215,7 +223,7 @@ static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t modu
 }
 #endif /* FSL_FEATURE_WUU_HAS_MF */

-/* @} */
+/*! @} */

 /*!
 * @name Pin Filter Control APIs
@@ -275,7 +283,7 @@ bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex);
 * param pinIndex A pin index, which starts from 0.
 */
 void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex);
-/* @} */
+/*! @} */

 #if defined(__cplusplus)
 }
@@ -283,4 +291,4 @@ void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex);

 /*! @} */

-#endif /*_FSL_WUU_H_*/
+#endif /*FSL_WUU_H_*/
@@ -5,8 +5,8 @@
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
-#ifndef _FSL_WWDT_H_
-#define _FSL_WWDT_H_
+#ifndef FSL_WWDT_H_
+#define FSL_WWDT_H_

 #include "fsl_common.h"

@@ -22,16 +22,16 @@
 *******************************************************************************/

 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Defines WWDT driver version. */
 #define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9))
-/*@}*/
+/*! @} */

 /*! @name Refresh sequence */
-/*@{*/
+/*! @{ */
 #define WWDT_FIRST_WORD_OF_REFRESH  (0xAAU) /*!< First word of refresh sequence */
 #define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */
-/*@}*/
+/*! @} */

 /*! @brief Describes WWDT configuration structure. */
 typedef struct _wwdt_config
@@ -126,7 +126,7 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config);
 */
 void WWDT_Deinit(WWDT_Type *base);

-/* @} */
+/*! @} */

 /*!
 * @name WWDT Functional Operation
@@ -265,7 +265,7 @@ static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)
 */
 void WWDT_Refresh(WWDT_Type *base);

-/*@}*/
+/*! @} */

 #if defined(__cplusplus)
 }
@@ -273,4 +273,4 @@ void WWDT_Refresh(WWDT_Type *base);

 /*! @}*/

-#endif /* _FSL_WWDT_H_ */
+#endif /* FSL_WWDT_H_ */
@@ -1,6 +1,6 @@
 /*
 * Copyright 2014-2016 Freescale Semiconductor, Inc.
- * Copyright 2016-2023 NXP
+ * Copyright 2016-2024 NXP
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
@@ -13,7 +13,8 @@
 *
 * The CPU macro should be declared in the project or makefile.
 */
-#if (defined(CPU_MCXA153VFM) || defined(CPU_MCXA153VFT) || defined(CPU_MCXA153VLH))
+#if (defined(CPU_MCXA153VFM) || defined(CPU_MCXA153VFT) || defined(CPU_MCXA153VLF) || \
+    defined(CPU_MCXA153VLH))

 #define MCXA153_SERIES

@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            GNU C Compiler
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            GNU C Compiler
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -4,11 +4,11 @@
 /*            MCXA153                                                        */
 /*  @version: 1.0                                                            */
 /*  @date:    2022-3-29                                                      */
-/*  @build:   b231018                                                        */
+/*  @build:   b240401                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2023 NXP                                                   */
+/* Copyright 2016-2024 NXP                                                   */
 /* SPDX-License-Identifier: BSD-3-Clause                                     */
 /*****************************************************************************/
 /* Version: GCC for ARM Embedded Processors                                  */
@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -4,11 +4,11 @@
 ;            MCXA153
 ;  @version: 1.0
 ;  @date:    2022-3-29
-;  @build:   b230804
+;  @build:   b240401
 ; -------------------------------------------------------------------------
 ;
 ; Copyright 1997-2016 Freescale Semiconductor, Inc.
-; Copyright 2016-2023 NXP
+; Copyright 2016-2024 NXP
 ; SPDX-License-Identifier: BSD-3-Clause
 ;
 ; The modules in this file are included in the libraries, and may be replaced
@@ -2,6 +2,7 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compilers:           GNU C Compiler
@@ -11,7 +12,7 @@
 **
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230725
+**     Build:               b240403
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
@@ -19,7 +20,7 @@
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -79,8 +80,34 @@ __attribute__ ((weak)) void SystemInit (void) {
    /* Enable the LPCAC */
    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK;
    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
-    /* Disable AGDET RESET */
-    SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_RE_MASK;
+
+    /* Enable flash RWX when FLASH_ACL in IFR0 is invalid */
+    if ((*((volatile const uint32_t *)(0x1000000)) == 0xFFFFFFFFU) ||
+        ((*((volatile const uint32_t *)(0x1000000)) == 0x59630000U) &&
+         (*((volatile const uint32_t *)(0x1000040)) == 0xFFFFFFFFU) &&
+         (*((volatile const uint32_t *)(0x1000044)) == 0xFFFFFFFFU)))
+    {
+        /* Enable MBC register written with GLIKEY index15 */
+        GLIKEY0->CTRL_0 = 0x00060000U;
+        GLIKEY0->CTRL_0 = 0x0002000FU;
+        GLIKEY0->CTRL_0 = 0x0001000FU;
+        GLIKEY0->CTRL_1 = 0x00290000U;
+        GLIKEY0->CTRL_0 = 0x0002000FU;
+        GLIKEY0->CTRL_1 = 0x00280000U;
+        GLIKEY0->CTRL_0 = 0x0000000FU;
+
+        /* Enable RWX for GLBAC0 */
+        MBC0->MBC_INDEX[0].MBC_MEMN_GLBAC[0] = 0x7700U;
+
+        /* Use GLBAC0 for all flash block */
+        for (uint8_t i = 0; i < 2U; i++)
+        {
+            MBC0->MBC_INDEX[0].MBC_DOM0_MEM0_BLK_CFG_W[i] = 0x00000000U;
+        }
+
+        /* Disable MBC register written */
+        GLIKEY0->CTRL_0 = 0x0002000FU;
+    }
  SystemInitHook();
 }

@@ -2,6 +2,7 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compilers:           GNU C Compiler
@@ -11,7 +12,7 @@
 **
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230725
+**     Build:               b240403
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
@@ -19,7 +20,7 @@
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com