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Merge pull request #1468 from misonyo/gd32303-github

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[bsp][gd32303e-eval]add gcc support
This commit is contained in:
Bernard Xiong authored and GitHub committed 2018-05-24 11:44:10 +08:00
2 parents b0a91ad136 8d0328c784
commit b030e6773d
16 files changed
+3346 -234
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bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S
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bsp/gd32303e-eval/Libraries/SConscript
+1 -4
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@@ -11,10 +11,7 @@ src += [cwd + '/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
print('=================================================')
print('Not support gcc yet !')
print('=================================================')
exit(0)
src += [cwd + '/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s']
elif rtconfig.CROSS_TOOL == 'iar':
bsp/gd32303e-eval/README.md
+2 -1
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@@ -15,12 +15,13 @@
## 2. 编译说明
GD32303E-EVAL板级包支持MDK5和IAR。
GD32303E-EVAL板级包支持MDK5、IAR开发环境和GCC编译器，以下是具体版本信息：
| IDE/编译器 | 已测试版本 |
| -- | -- |
| MDK5 | MDK5.25 |
| IAR | IAR8.20 |
| GCC | GCC 5.4.1 20160919 (release) |
## 3. 烧写及执行
bsp/gd32303e-eval/RTE/_rt-thread_gd32f30x/RTE_Components.h
+20
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@@ -0,0 +1,20 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'project'
* Target: 'rt-thread_gd32f30x'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "gd32f30x.h"
#endif /* RTE_COMPONENTS_H */
bsp/gd32303e-eval/applications/main.c
+2 -2
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@@ -16,9 +16,9 @@
int main(void)
{
/* user app entry */
/* user app entry */
return 0;
return 0;
}
bsp/gd32303e-eval/cconfig.h
+18
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@@ -0,0 +1,18 @@
#ifndef CCONFIG_H__
#define CCONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* compiler configure file for RT-Thread in GCC*/
#define HAVE_NEWLIB_H 1
#define LIBC_VERSION "newlib 2.4.0"
#define HAVE_SYS_SIGNAL_H 1
#define HAVE_SYS_SELECT_H 1
#define HAVE_PTHREAD_H 1
#define HAVE_FDSET 1
#define HAVE_SIGACTION 1
#define GCC_VERSION "5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]"
#define STDC "2011"
#endif
bsp/gd32303e-eval/drivers/board.c
+11 -12
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@@ -23,12 +23,12 @@
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler */
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while (1)
{
}
/* USER CODE END Error_Handler */
}
/** System Clock Configuration
@@ -54,13 +54,12 @@ void SysTick_Handler(void)
rt_interrupt_leave();
}
/**
* This function will initial GD32 board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
@@ -69,17 +68,17 @@ void rt_hw_board_init()
/* Set the Vector Table base location at 0x08000000 */
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
#endif
SystemClock_Config();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(CONSOLE_DEVICE);
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif
bsp/gd32303e-eval/drivers/board.h
-27
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@@ -42,33 +42,6 @@ extern int __bss_end;
#define HEAP_END GD32_SRAM_END
// <o> Console on USART:
// <127=> no console
// <0=>USART 0 <1=>USART 1 <2=>USART 2 <3=> USART 3
// <4=>USART 4
// <i>Default: 0
#define GD32_CONSOLE_USART 0
void rt_hw_board_init(void);
#if GD32_CONSOLE_USART == 127
#define CONSOLE_DEVICE "no"
#elif GD32_CONSOLE_USART == 0
#define CONSOLE_DEVICE "uart0"
#elif GD32_CONSOLE_USART == 1
#define CONSOLE_DEVICE "uart1"
#elif GD32_CONSOLE_USART == 2
#define CONSOLE_DEVICE "uart2"
#elif GD32_CONSOLE_USART == 3
#define CONSOLE_DEVICE "uart3"
#elif GD32_CONSOLE_USART == 4
#define CONSOLE_DEVICE "uart4"
#endif
#define FINSH_DEVICE_NAME CONSOLE_DEVICE
void Error_Handler(void);
#endif
//*** <<< end of configuration section >>> ***
bsp/gd32303e-eval/drivers/drv_gpio.c
+2 -2
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@@ -459,7 +459,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
return RT_EINVAL;
}
rcu_periph_clock_enable(RCU_AF);
rcu_periph_clock_enable(RCU_AF);
/* enable and set interrupt priority */
nvic_irq_enable(irqmap->irqno, 5U, 0U);
@@ -522,7 +522,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
{
pin_irq_hdr(exti_line);
exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
}
}
void EXTI0_IRQHandler(void)
bsp/gd32303e-eval/drivers/drv_i2c.c
+149 -149
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bsp/gd32303e-eval/drivers/drv_spi.c
+10 -10
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@@ -29,7 +29,7 @@
#ifdef DEBUG
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
#else
#define DEBUG_PRINTF(...)
#define DEBUG_PRINTF(...)
#endif
/* private rt-thread spi ops function */
@@ -48,8 +48,8 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
if(configuration->data_width <= 8)
{
@@ -127,10 +127,10 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
break;
case RT_SPI_MODE_1:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
break;
break;
case RT_SPI_MODE_2:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
break;
break;
case RT_SPI_MODE_3:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
break;
@@ -260,9 +260,9 @@ int gd32_hw_spi_init(void)
#ifdef RT_USING_SPI0
static struct rt_spi_bus spi_bus0;
spi_bus0.parent.user_data = (void *)SPI0;
result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops);
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_SPI0);
/* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */
@@ -274,8 +274,8 @@ int gd32_hw_spi_init(void)
static struct rt_spi_bus spi_bus1;
spi_bus1.parent.user_data = (void *)SPI1;
result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops);
result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops);
rcu_periph_clock_enable(RCU_SPI1);
rcu_periph_clock_enable(RCU_GPIOB);
@@ -291,7 +291,7 @@ int gd32_hw_spi_init(void)
rcu_periph_clock_enable(RCU_SPI2);
rcu_periph_clock_enable(RCU_GPIOB);
/* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */
gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5);
gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4);
bsp/gd32303e-eval/drivers/drv_usart.c
+22 -23
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@@ -36,17 +36,17 @@
// Todo: compress uart info
struct gd32_uart
{
uint32_t uart_periph;
IRQn_Type irqn;
rcu_periph_enum per_clk;
rcu_periph_enum tx_gpio_clk;
rcu_periph_enum rx_gpio_clk;
uint32_t tx_port;
uint16_t tx_pin;
uint32_t rx_port;
uint16_t rx_pin;
uint32_t uart_periph;
IRQn_Type irqn;
rcu_periph_enum per_clk;
rcu_periph_enum tx_gpio_clk;
rcu_periph_enum rx_gpio_clk;
uint32_t tx_port;
uint16_t tx_pin;
uint32_t rx_port;
uint16_t rx_pin;
struct rt_serial_device * serial;
struct rt_serial_device * serial;
char *device_name;
};
@@ -137,8 +137,8 @@ static const struct gd32_uart uarts[] = {
USART0, // uart peripheral index
USART0_IRQn, // uart iqrn
RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
GPIOA, GPIO_PIN_9, // tx port, tx pin
GPIOA, GPIO_PIN_10, // rx port, rx pin
GPIOA, GPIO_PIN_9, // tx port, tx pin
GPIOA, GPIO_PIN_10, // rx port, rx pin
&serial0,
"uart0",
},
@@ -149,8 +149,8 @@ static const struct gd32_uart uarts[] = {
USART1, // uart peripheral index
USART1_IRQn, // uart iqrn
RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock
GPIOA, GPIO_PIN_2, // tx port, tx pin
GPIOA, GPIO_PIN_3, // rx port, rx pin
GPIOA, GPIO_PIN_2, // tx port, tx pin
GPIOA, GPIO_PIN_3, // rx port, rx pin
&serial1,
"uart1",
},
@@ -161,8 +161,8 @@ static const struct gd32_uart uarts[] = {
USART2, // uart peripheral index
USART2_IRQn, // uart iqrn
RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock
GPIOB, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOB, GPIO_PIN_11, // rx port, rx alternate, rx pin
GPIOB, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOB, GPIO_PIN_11, // rx port, rx alternate, rx pin
&serial2,
"uart2",
},
@@ -173,8 +173,8 @@ static const struct gd32_uart uarts[] = {
UART3, // uart peripheral index
UART3_IRQn, // uart iqrn
RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock
GPIOC, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOC, GPIO_PIN_11, // rx port, rx alternate, rx pin
GPIOC, GPIO_PIN_10, // tx port, tx alternate, tx pin
GPIOC, GPIO_PIN_11, // rx port, rx alternate, rx pin
&serial3,
"uart3",
},
@@ -185,8 +185,8 @@ static const struct gd32_uart uarts[] = {
UART4, // uart peripheral index
UART4_IRQn, // uart iqrn
RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock
GPIOC, GPIO_PIN_12, // tx port, tx alternate, tx pin
GPIOD, GPIO_PIN_2, // rx port, rx alternate, rx pin
GPIOC, GPIO_PIN_12, // tx port, tx alternate, tx pin
GPIOD, GPIO_PIN_2, // rx port, rx alternate, rx pin
&serial4,
"uart4",
},
@@ -296,7 +296,6 @@ static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg
/* enable interrupt */
usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE);
break;
}
return RT_EOK;
@@ -355,14 +354,14 @@ static const struct rt_uart_ops gd32_uart_ops =
gd32_configure,
gd32_control,
gd32_putc,
gd32_getc,
gd32_getc
};
int gd32_hw_usart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
int i;
for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
{
uarts[i].serial->ops = &gd32_uart_ops;
bsp/gd32303e-eval/gd32_rom.ld
+1 -1
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@@ -1,5 +1,5 @@
/*
* linker script for GD32F4xx with GNU ld
* linker script for GD32F30x with GNU ld
* bernard.xiong 2009-10-14
*/
bsp/gd32303e-eval/project.ewd
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bsp/gd32303e-eval/project.uvoptx
+1 -1
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@@ -196,7 +196,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
bsp/gd32303e-eval/rtconfig.py
+2 -2
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@@ -11,8 +11,8 @@ if os.getenv('RTT_CC'):
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'D:/ArdaArmTools/GNUARM_4.9_2015q1/bin'
PLATFORM = 'gcc'
EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'