Merge pull request #4107 from Wang-Huachen/master

[bsp] 添加对zynqmp-r5核心的支持和zynqmp-r5-axu4ev开发板的bsp
2026-11-08 14:43:04 +08:00 · 2020-12-07 14:02:58 +08:00
commit af72becc8c
@@ -403,6 +403,10 @@ jobs:
           RTT_BSP: "zynq7000"
           RTT_TOOL_CHAIN: "sourcery-arm"

+         - action-version: "1.0"
+           RTT_BSP: "zynqmp-r5-axu4ev"
+           RTT_TOOL_CHAIN: "sourcery-arm"
+
         - action-version: "1.0"
           RTT_BSP: "frdm-k64f"
           RTT_TOOL_CHAIN: "sourcery-arm"
@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ZYNQMP_R5
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "$BSP_DIR/drivers/Kconfig"
@@ -0,0 +1,112 @@
+# AXU4EV-E BSP (Board Support Package) Execution Instruction
+
+[中文页](README_zh.md) |
+
+## **Introduction**
+
+This document records the execution instruction of the BSP (board support package) for the AXU4EV-E development board.
+
+The document is covered in three parts:
+
+- AXU4EV-E Board Resources Introduction
+- Quickly Get Started
+- Advanced Features
+- BSP Migration
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## AXU4EV-E Resources Introduction
+
+ALINX AXU4EV-E: Xilinx Zynq UltraScale+ MPSOC XCZU4EV-1SFVC784I Ethernet FPGA development board, the SoM Core board is the smallest system, mainly composed of XCZU4EV-1SFVC784I + 5 DDR4 + eMMC + 1 QSPI FLASH. The Carrier board expands a wealth of peripheral interfaces for the core board, including 1 SATA M.2 interface, 1 DP output interface, 4 USB3.0 interfaces, 2 Gigabit Ethernet interfaces, 2 UART interfaces, 1 SD card interface, 2*40-pin Expansion Connectors for Modules, 2 CAN bus interfaces, 2 RS485 interfaces, 1 MIPI interface, Keys and LEDs. High-speed data exchange and transmission, data storage, pre-verification and post-application of data processing, video transmission processing, deep learning, artificial intelligence and industrial control, is a professional ZYNQ development platform. suitable for students, engineers and other groups engaged in the development of MPSoCs.
+
+For more details about this board, please refer to [Alinx Electronic Technology (Shanghai) Co.,Ltd.](http://www.alinx.com/en/)。
+
+## **Peripheral Condition**
+
+Each peripheral supporting condition for this BSP is as follows:
+
+| **Core**      | **Support** | **Remark**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| R5-CPU0   |     Support     | The R5-CPU0 is running the system |
+| **On-board Peripherals**      | **Support** | **Remark**                              |
+| None |          |  |
+| **On-chip Peripherals**      | **Support** | **Remark**                              |
+| GPIO              |     Support     |  |
+| UART              |     Support     | UART0                            |
+| TIMER     |     Support     |     TTC0 provides system clock         |
+| EMMC | Support | SD0 Controller |
+
+## Execution Instruction
+
+### Quickly Get Started
+
+This BSP only support the GCC development environment. Here's an example to introduce how to run the system.
+
+#### Compile and Download
+
+1. Open the env tool under BSP. Enter `scons` to compile.
+
+2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
+
+3. Use Xilinx Vitis to generate fsbl, and then create "Debug Configuration", select the `rtthread-zynqmp-r5.elf` file as the application.
+
+4. Use the debugger to connect the PC and the development board. Set the dial switch to JTAG to start. Then connect the power supply. Click start debugging or running.
+
+   Since the compiler has debugging information by default (see rtconfig.py In BUILD, so when debugging in Xilinx Vitis, you can also open source files to set breakpoints for debugging.
+
+#### Software Solidification
+
+1. Open the env tool under BSP. Enter `scons` to compile.
+
+2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
+
+3. Use Xilinx Vitis or Xilinx SDK to generate fsbl, and then use the bootgen tool provided by Xilinx to make fsbl BOOT.bin Documents.
+
+   For example, use the command line:
+
+   ```
+    bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on
+   ```
+   
+   And the outpu.bif file could be：
+   ```
+   //arch = zynqmp; split = false; format = BIN
+   the_ROM_image:
+   {
+        [bootloader, destination_cpu = r5-0]./fsbl.elf
+        [destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf
+   }
+   ```
+   
+4. According to the document provided by Alinx, put BOOT.bin into SD card or burn to QSPI flash, set the startup mode through dial switch, and then connect the power supply to start.
+
+
+#### Running Results
+
+Once the project is successfully downloaded, the system runs automatically.
+
+Connect the serial port of the board to PC, communicate with it via a serial terminal tool (115200bps, 8N1). Restart the board and the startup information of RT-Thread will be observed:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Nov 27 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh />
+```
+
+### **Advanced Features**
+
+This BSP enables EMMC driver and DFS file system by default. If you need to use a file system, you can format and mount it by yourself.
+
+## BSP Migration
+
+If you need to ported the BSP to another development board of Xilinx Zynq UltraScale+ MPSOC development platform, it is also convenient. The main modifications are as follows:
+
+1. Memory: `psu_r5_ddr_0_MEM_0` in `zynqmp-r5.ld` (if DDR memory is less than 2G)
+2. Main Frequency: `XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ` in `zynqmp-r5.h`
+3. Pin and Frequency of Serial Port: `rxmio`, `txmio` and `XPAR_PSU_UART_0_UART_CLK_FREQ_HZ` in `drv_uart.c`
+4. Timer Frequency: `XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` in `drv_timer.c`
+5. SD Controller: Block device driver initialization in `drv_sdcard.c`
+
+The parameter macro definition in `xparameters.h` does not need to be modified manually. You can directly copy the `xparameters.h` file of the development board generated in Xilinx Vitis.
@@ -0,0 +1,133 @@
+# AXU4EV-E 开发板 BSP 说明
+
+## 简介
+
+本文档是为 AXU4EV-E 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+AXU4EV-E 开发板是 芯驿电子科技（上海）有限公司 推出的一款基于 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板。这款 MPSoCs 开发平台采用核心板加扩展板的模式，方便用户对核心板的二次开发利用。核心板使用 XILINX Zynq UltraScale+ EV 芯片 ZU4EV 的解决方案，它采用Processing System(PS)+Programmable Logic(PL)技术将四核ARM Cortex-A53 和FPGA 可编程逻辑集成在一颗芯片上。另外核心板上 PS 端带有 4 片共 4GB 高速 DDR4 SDRAM 芯片，1 片 8GB的 eMMC 存储芯片和 1 片 256Mb 的 QSPI FLASH 芯片；核心板上 PL 端带有 1 片 1GB 的DDR4 SDRAM 芯片 。
+
+开发板更多详细信息请参考[芯驿电子科技（上海）有限公司](http://www.alinx.cn/)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **核心**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| R5-CPU0   |     支持     | 运行系统的为R5核的CPU0 |
+| **板载外设**      | **支持情况** | **备注**                              |
+| 无 |          |  |
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     |  |
+| UART              |     支持     | UART0                            |
+| TIMER     |     支持     |     TTC0提供系统时钟         |
+| EMMC | 支持 | SD0控制器 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为仅支持 GCC 开发环境，下面介绍如何将系统运行起来。
+
+#### 编译下载
+
+1. 在 bsp 下打开 env 工具，输入`scons`进行编译。
+
+2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。
+
+3. 使用 Xilinx Vitis 产生 FSBL，然后创建 “Debug Configuration”，Application 选择`rtthread-zynqmp-r5.elf` 文件。
+
+4. 使用调试器连接 PC 和开发板，通过拨码开关设置为 JTAG 启动，然后连接电源，点击开始调试或运行即可。
+
+   由于编译时默认带有调试信息（见 rtconfig.py 中 BUILD），所以在 Xilinx Vitis 中调试时同样可以打开源文件设断点进行调试。
+
+#### 固化程序
+
+1. 在 bsp 下打开 env 工具，输入`scons`进行编译。
+
+2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。
+
+3. 使用 Xilinx Vitis 或 Xilinx SDK 产生 FSBL，然后使用 Xilinx 提供的 bootgen 工具制作 BOOT.bin 文件。
+
+   例如使用命令行方式：
+
+   ```
+    bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on
+   ```
+   
+   其中 output.bif 文件可以是：
+   ```
+   //arch = zynqmp; split = false; format = BIN
+   the_ROM_image:
+   {
+        [bootloader, destination_cpu = r5-0]./fsbl.elf
+        [destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf
+   }
+   ```
+   
+4. 根据 ALINX 提供的文档将 BOOT.bin 放进SD卡或烧录到 QSPI FLASH 中，通过拨码开关设置启动方式，然后连接电源即可启动。
+
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Nov 27 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh />
+```
+
+### 进阶使用
+
+此 BSP 默认开启了 EMMC 驱动和 DFS 文件系统，如果需要使用文件系统可以自行格式化并挂载。
+
+
+## 板级移植
+
+如果需要将BSP移植到其他 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板上也比较方便，主要修改的地方有以下几点：
+
+1. 内存： 如果 DDR memory 小于 2G，需要修改`zynqmp-r5.ld`链接文件中的`psu_r5_ddr_0_MEM_0` 
+2. 主频： `xparameters.h`中的`XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ`
+3. 串口引脚和频率：`drv_uart.c`中的`rxmio`, `txmio` 和`xparameters.h`中的`XPAR_PSU_UART_0_UART_CLK_FREQ_HZ`
+4. 定时器频率：`xparameters.h`中的`XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` 
+5. SD控制器：`drv_sdcard.c`中的块设备驱动初始化
+
+以上需要修改的`xparameters.h`中的参数宏定义不需要手动修改，可以直接将Xilinx Vitis中产生的开发板的`xparameters.h`文件复制过来即可。
+
+
+
+## 注意事项
+
+- 无
+
+## 联系人信息
+
+维护人:
+
+-  [王华辰](https://github.com/Wang-Huachen/)
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-zynqmp-r5.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,18 @@
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN    40
+int main(void)
+{
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;
+}
@@ -0,0 +1,35 @@
+menu "Hardware Drivers Config"
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default y
+        endif
+
+    menuconfig BSP_USING_SDIO
+        bool "Enable SDIO"
+        default y
+        if BSP_USING_SDIO
+            config BSP_USING_SD0
+                bool "Enable SD0 EMMC"
+                default y
+        endif
+
+    endmenu
+
+    menu "Board extended module Drivers"
+
+    endmenu
+
+endmenu
+
@@ -0,0 +1,26 @@
+from building import *
+
+cwd  = GetCurrentDir()
+src  = Glob('*.c')
+list = os.listdir(cwd)
+CPPPATH = [cwd]
+objs = []
+
+if not GetDepend('BSP_USING_UART'):
+    SrcRemove(src, ['drv_uart.c'])
+
+if not GetDepend('BSP_USING_SDIO'):
+    SrcRemove(src, ['drv_sdcard.c'])
+
+if not GetDepend('RT_USING_PIN'):
+    SrcRemove(src, ['drv_gpio.c'])
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+objs = objs + group
+
+Return('objs')
@@ -0,0 +1,17 @@
+from building import *
+
+cwd  = GetCurrentDir()
+src  = Glob('*.c')
+CPPPATH = [cwd]
+objs = []
+
+group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH)
+
+if GetDepend('BSP_USING_SDIO'):
+    objs = objs + SConscript('sdps_v3_9/SConscript')
+if GetDepend('RT_USING_PIN'):
+    objs = objs + SConscript('gpiops_v3_7/SConscript')
+
+objs = objs + group
+
+Return('objs')
@@ -0,0 +1,15 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+CPPPATH = [cwd]
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('*.c')
+path = cwd
+
+group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,31 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2020.1
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT 
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PSU_GPIO_0_DEVICE_ID,
+		XPAR_PSU_GPIO_0_BASEADDR
+	}
+};
+
+
@@ -0,0 +1,146 @@
+/******************************************************************************
+* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_7
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* 3.5   sne  03/14/19 Added versal support.
+* </pre>
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET  0x03FFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU  /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU  /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
+/* @} */
+#define XGPIOPS_PS_GPIO_BASEADDR     0xFF0B0000U     /* Flag for Base Address for PS_GPIO in Versal */
+#define XGPIOPS_ZERO    0U  /* Flag for 0 Value */
+#define XGPIOPS_ONE     1U  /* Flag for 1 Value */
+#define XGPIOPS_TWO     2U  /* Flag for 2 Value */
+#define XGPIOPS_THREE   3U  /* Flag for 3 Value */
+#define XGPIOPS_FOUR    4U  /* Flag for 4 Value */
+#define XGPIOPS_SIX     6U  /* Flag for 6 Value */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
@@ -0,0 +1,112 @@
+/******************************************************************************
+* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_7
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5   sne  03/01/19 Fixes violations according to MISRAC-2012
+*                     in safety mode and modified the code such as
+*                     Use of mixed mode arithmetic,Declared the pointer param
+*                     as Pointer to const,Casting operation to a pointer,
+*                     Literal value requires a U suffix.
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrEnabled;
+	u32 CurrentIntrType = 0U;
+	u32 CurrentIntrPolarity = 0U;
+	u32 CurrentIntrOnAny = 0U;
+	u32 IntrType = 0U;
+	u32 IntrPolarity = 0U;
+	u32 IntrOnAny = 0U;
+	u32 IntrTestValue = 0x22U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable the Interrupts for Bank 0 . */
+	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	/*
+	 * Get the Current Interrupt properties for Bank 0.
+	 * Set them to a known value, read it back and compare.
+	 */
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+			     IntrTestValue, IntrTestValue);
+
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+			     &IntrPolarity, &IntrOnAny);
+
+	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+	    (IntrOnAny != IntrTestValue)) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the contents of all the interrupt registers modified in this
+	 * test.
+	 */
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+			     CurrentIntrPolarity, CurrentIntrOnAny);
+
+	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	return Status;
+}
+/** @} */
@@ -0,0 +1,75 @@
+/******************************************************************************
+* Copyright (C) 2010 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_7
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+	XGpioPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpioPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
@@ -0,0 +1,15 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+CPPPATH = [cwd]
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('*.c')
+path = cwd
+
+group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,115 @@
+/******************************************************************************
+* Copyright (C) 2013 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xsdps_include.h
+* @addtogroup sdps_v3_9
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 3.9   mn     03/03/20 Restructured the code for more readability and modularity
+*       mn     03/16/20 Move XSdPs_Select_Card API to User APIs
+*
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SDPS_INCLUDE_H_
+#define SDPS_INCLUDE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xsdps.h"
+#if defined (__aarch64__)
+#include "xil_smc.h"
+#endif
+
+/** @cond INTERNAL */
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+s32 XSdPs_SetupTransfer(XSdPs *InstancePtr);
+s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+s32 XSdPs_DllReset(XSdPs *InstancePtr);
+s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst);
+void XSdPs_ConfigTapDelay(XSdPs *InstancePtr);
+s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value);
+s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr);
+s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt);
+void XSdPs_SetExecTuning(XSdPs *InstancePtr);
+s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr);
+s32 XSdPs_CardReset(XSdPs *InstancePtr);
+s32 XSdPs_CardIfCond(XSdPs *InstancePtr);
+s32 XSdPs_CardOpCond(XSdPs *InstancePtr);
+s32 XSdPs_GetCardId(XSdPs *InstancePtr);
+s32 XSdPs_GetCsd(XSdPs *InstancePtr);
+s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr);
+s32 XSdPs_SdModeInit(XSdPs *InstancePtr);
+s32 XSdPs_SdCardEnum(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr);
+s32 XSdPs_MmcModeInit(XSdPs *InstancePtr);
+s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr);
+s32 XSdPs_ResetConfig(XSdPs *InstancePtr);
+void XSdPs_HostConfig(XSdPs *InstancePtr);
+s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value);
+void XSdPs_DisableBusPower(XSdPs *InstancePtr);
+void XSdPs_EnableBusPower(XSdPs *InstancePtr);
+s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value);
+s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr);
+s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr);
+s32 XSdPs_AutoTuning(XSdPs *InstancePtr);
+s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq);
+u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg);
+s32 XSdps_CheckTransferDone(XSdPs *InstancePtr);
+s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg);
+void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff);
+void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff);
+s32 XSdPs_DoDmaTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+s32 XSdPs_DoCmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+s32 XSdPs_SetVoltage18(XSdPs *InstancePtr);
+s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd);
+void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd);
+s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd);
+void XSdPs_ConfigPower(XSdPs *InstancePtr);
+void XSdPs_ConfigDma(XSdPs *InstancePtr);
+void XSdPs_ConfigInterrupt(XSdPs *InstancePtr);
+
+#if EL1_NONSECURE && defined (__aarch64__)
+void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val);
+#endif
+/** @endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,49 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2020.1
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT 
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PSU_SD_0_DEVICE_ID,
+		XPAR_PSU_SD_0_BASEADDR,
+		XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
+		XPAR_PSU_SD_0_HAS_CD,
+		XPAR_PSU_SD_0_HAS_WP,
+		XPAR_PSU_SD_0_BUS_WIDTH,
+		XPAR_PSU_SD_0_MIO_BANK,
+		XPAR_PSU_SD_0_HAS_EMIO,
+		XPAR_PSU_SD_0_IS_CACHE_COHERENT
+	},
+	{
+		XPAR_PSU_SD_1_DEVICE_ID,
+		XPAR_PSU_SD_1_BASEADDR,
+		XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
+		XPAR_PSU_SD_1_HAS_CD,
+		XPAR_PSU_SD_1_HAS_WP,
+		XPAR_PSU_SD_1_BUS_WIDTH,
+		XPAR_PSU_SD_1_MIO_BANK,
+		XPAR_PSU_SD_1_HAS_EMIO,
+		XPAR_PSU_SD_1_IS_CACHE_COHERENT
+	}
+};
+
+
@@ -0,0 +1,75 @@
+/******************************************************************************
+* Copyright (C) 2013 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v3_9
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 3.7   aru    03/12/19 Modified the code according to MISRAC-2012.
+*
+* </pre>
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* @brief
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
@@ -0,0 +1,31 @@
+#ifndef XLI_SLEEP_H
+#define XLI_SLEEP_H
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void usleep(unsigned long useconds)
+{
+	rt_uint32_t milliseconds = useconds/1000;
+	useconds = useconds%1000;
+	if (milliseconds) rt_thread_mdelay(milliseconds);
+	if (useconds) rt_hw_us_delay(useconds);
+}
+
+static inline void sleep(unsigned int seconds)
+{
+	rt_thread_delay(seconds);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,21 @@
+#ifndef XIL_ASSERT_H /* prevent circular inclusions */
+#define XIL_ASSERT_H /* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#define Xil_AssertNonvoid(Expression) RT_ASSERT(Expression)
+#define Xil_AssertVoid(Expression)    RT_ASSERT(Expression)
+#define Xil_AssertVoidAlways()        RT_ASSERT(0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
@@ -0,0 +1,18 @@
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define Xil_DCacheFlushRange(addr, size)  rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)(addr), (size))
+#define Xil_DCacheInvalidateRange(addr, size)  rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void*)(addr), (size))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup r5_cache_apis".
+*/
@@ -0,0 +1,16 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define xil_printf rt_kprintf
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
@@ -0,0 +1,96 @@
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include <rtdef.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
+
+typedef rt_uint8_t u8;
+typedef rt_uint16_t u16;
+typedef rt_uint32_t u32;
+
+typedef char char8;
+typedef rt_int8_t s8;
+typedef rt_int16_t s16;
+typedef rt_int32_t s32;
+typedef rt_int64_t s64;
+typedef rt_uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
@@ -0,0 +1,64 @@
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (versal)
+#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
+#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
+#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
+									XPAR_PMC_TAP_VERSION_OFFSET)
+#else
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
+									XPAR_CSU_VER_OFFSET)
+#endif
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+#define XPLAT_VERSAL 0x6U
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+#define XPLAT_INFO_MASK (0xF)
+
+#if defined (versal)
+#define XPS_VERSION_INFO_MASK 0xFF00U
+#define XPS_VERSION_INFO_SHIFT 0x8U
+#define XPLAT_INFO_SHIFT 0x18U
+#else
+#define XPS_VERSION_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_SHIFT 0x0U
+#define XPLAT_INFO_SHIFT 0xCU
+#endif
+
+static INLINE u32 XGetPlatform_Info()
+{
+#if defined (versal)
+	return XPLAT_VERSAL;
+#elif defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+	return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+	return XPLAT_MICROBLAZE;
+#else
+	return XPLAT_ZYNQ;
+#endif
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-11-24     WangHuachen  the first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+#include <dfs_fs.h>
+
+#include "board.h"
+#include "drv_timer.h"
+
+#define ITERS_PER_USEC  (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000)
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    __asm__ __volatile__ (
+        "push {r0,r1,r3} \n"
+        "mov r0, %[usec] \n"
+        "mov r1, %[iter] \n"
+        "1: \n"
+        "mov r3, r1 \n"
+        "2: \n"
+        "subs r3, r3, #0x1\n"
+        "bne 2b \n"
+        "subs r0, r0, #0x1 \n"
+        "bne 1b \n"
+        "pop {r0,r1,r3} \n"
+        ::[iter] "r" (ITERS_PER_USEC), [usec] "r" (us)
+        );
+}
+
+#ifdef RT_USING_CONSOLE
+
+#include "drv_uart.h"
+void rt_hw_serial_putc(const char c)
+{
+    UART_Registers *uart = (UART_Registers *)XPAR_PSU_UART_0_BASEADDR;
+    if (c == '\n')
+        rt_hw_serial_putc('\r');
+
+    while ((uart->SR) & UART_SR_TXFULL);
+    uart->FIFO = c;
+}
+void rt_hw_console_output(const char *str)
+{
+    while (*str)
+    {
+        rt_hw_serial_putc(*str++);
+    }
+}
+#endif
+
+/**
+ * This function will initialize beaglebone board
+ */
+void rt_hw_board_init(void)
+{
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
+    /* initialize system heap */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
@@ -0,0 +1,18 @@
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "zynqmp-r5.h"
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      ((void*)&__bss_end)
+#endif
+
+#define HEAP_END        (void*)(0x80000000)
+
+void rt_hw_board_init();
+
+#endif
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-11-27     WangHuachen  the first version
+ */
+
+#include <rtdevice.h>
+#include <rthw.h>
+#include "drv_gpio.h"
+#include "xgpiops.h"
+
+#define DBG_TAG "drv.gpio"
+#define DBG_LVL DBG_INFO
+#include "rtdbg.h"
+
+#define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
+static XGpioPs Gpio; /* The driver instance for GPIO Device. */
+
+void xgpiops_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+    case PIN_MODE_OUTPUT_OD:
+        XGpioPs_SetDirectionPin(&Gpio, pin, 1);
+        XGpioPs_SetOutputEnablePin(&Gpio, pin, 1);
+        break;
+    case PIN_MODE_INPUT:
+    case PIN_MODE_INPUT_PULLUP:
+    case PIN_MODE_INPUT_PULLDOWN:
+        XGpioPs_SetDirectionPin(&Gpio, pin, 0);
+        break;
+    default:
+        break;
+    }
+}
+
+void xgpiops_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    if (pin >= Gpio.MaxPinNum)
+        return;
+
+    XGpioPs_WritePin(&Gpio, pin, (value == PIN_HIGH)?1:0);
+}
+
+int xgpiops_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    if (pin >= Gpio.MaxPinNum)
+        return 0;
+
+    int DataRead = XGpioPs_ReadPin(&Gpio, pin);
+    return DataRead?PIN_HIGH:PIN_LOW;
+}
+
+const static struct rt_pin_ops _xgpiops_pin_ops =
+    {
+        xgpiops_pin_mode,
+        xgpiops_pin_write,
+        xgpiops_pin_read,
+        RT_NULL,
+        RT_NULL,
+        RT_NULL,
+        RT_NULL,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+    XGpioPs_Config *ConfigPtr;
+    /* Initialize the GPIO driver. */
+    ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
+
+    if (XGpioPs_CfgInitialize(&Gpio, ConfigPtr,
+                              ConfigPtr->BaseAddr) == XST_SUCCESS)
+    {
+        result = rt_device_pin_register("pin", &_xgpiops_pin_ops, RT_NULL);
+        return result;
+    }
+    return -RT_ERROR;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
@@ -0,0 +1,13 @@
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,13 @@
+#ifndef __DRV_SDCARD_H__
+#define __DRV_SDCARD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-03-19     WangHuachen  the first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+#include <stdint.h>
+
+#include "drv_timer.h"
+
+#define TTC0_0_BASEADDR     XPAR_PSU_TTC_0_BASEADDR
+#define TTC0_0_CLK_FREQ_HZ  XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
+
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    rt_tick_increase();
+    /* clear interrupt */
+    TTC_ISR(TTC0_0_BASEADDR);
+}
+
+static int rt_hw_timer_init(void)
+{
+    /* Stop timer */
+    TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_DIS_MASK;
+
+    /* Initialize TTC */
+    TTC_CNT_CNTRL(TTC0_0_BASEADDR) = TTC_CNT_CNTRL_RESET_VALUE;
+    TTC_CLK_CNTRL(TTC0_0_BASEADDR) = 0x00;
+    TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = 0x00;
+    TTC_MATCH_0(TTC0_0_BASEADDR) = 0x00;
+    TTC_MATCH_1(TTC0_0_BASEADDR) = 0x00;
+    TTC_MATCH_2(TTC0_0_BASEADDR) = 0x00;
+    TTC_IER(TTC0_0_BASEADDR) = 0x00;
+    TTC_ISR(TTC0_0_BASEADDR) = 0x00;
+
+    /* Reset counter */
+    TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_RST_MASK;
+
+    /* Interval mode select */
+    TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_INT_MASK;
+    /* Setup interval */
+    TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = TTC0_0_CLK_FREQ_HZ / RT_TICK_PER_SECOND;
+    /* Clear all of the prescaler control bits in the register */
+    TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK | 
+                                            TTC_CLK_CNTRL_PS_EN_MASK);
+    /* We do not need a prescaler*/
+    
+    /* Register the ticker handler with the GIC */
+    rt_hw_interrupt_install(XPAR_XTTCPS_0_INTR, rt_hw_timer_isr, RT_NULL, "tick");
+    /* Enable TTC interrupts in the GIC */
+    rt_hw_interrupt_umask(XPAR_XTTCPS_0_INTR);
+    /* Enable interval interrupt */
+    TTC_IER(TTC0_0_BASEADDR) |= TTC_IXR_INTERVAL_MASK;
+    /* Start timer */
+    TTC_CNT_CNTRL(TTC0_0_BASEADDR) &=~ TTC_CNT_CNTRL_DIS_MASK;
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
@@ -0,0 +1,48 @@
+#ifndef __DRV_TIMER_H__
+#define __DRV_TIMER_H__
+
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define TTC_CLK_CNTRL(hw_base)      __REG32(hw_base + 0x00)
+#define TTC_CLK_CNTRL_PS_EN_MASK        0x00000001      /**< Prescale enable */
+#define TTC_CLK_CNTRL_PS_VAL_MASK       0x0000001E      /**< Prescale value */
+#define TTC_CLK_CNTRL_PS_VAL_SHIFT      1               /**< Prescale shift */
+#define TTC_CLK_CNTRL_PS_DISABLE        16              /**< Prescale disable */
+#define TTC_CLK_CNTRL_SRC_MASK          0x00000020      /**< Clock source */
+#define TTC_CLK_CNTRL_EXT_EDGE_MASK     0x00000040      /**< External Clock edge */
+
+#define TTC_CNT_CNTRL(hw_base) __REG32(hw_base + 0x0C)
+#define TTC_CNT_CNTRL_DIS_MASK      0x00000001      /**< Disable the counter */
+#define TTC_CNT_CNTRL_INT_MASK      0x00000002      /**< interval mode */
+#define TTC_CNT_CNTRL_DECR_MASK     0x00000004      /**< Decrement mode */
+#define TTC_CNT_CNTRL_MATCH_MASK    0x00000008      /**< Match mode */
+#define TTC_CNT_CNTRL_RST_MASK      0x00000010      /**< Reset counter */
+#define TTC_CNT_CNTRL_EN_WAVE_MASK  0x00000020      /**< Enable waveform */
+#define TTC_CNT_CNTRL_POL_WAVE_MASK 0x00000040      /**< Waveform polarity */
+#define TTC_CNT_CNTRL_RESET_VALUE   0x00000021      /**< Reset value */
+
+#define TTC_COUNT_VALUE(hw_base)    __REG32(hw_base + 0x18)
+#define TTC_INTERVAL_VAL(hw_base)   __REG32(hw_base + 0x24)
+#define TTC_MATCH_0(hw_base)        __REG32(hw_base + 0x30)
+#define TTC_MATCH_1(hw_base)        __REG32(hw_base + 0x3C)
+#define TTC_MATCH_2(hw_base)        __REG32(hw_base + 0x48)
+
+#define TTC_ISR(hw_base)            __REG32(hw_base + 0x54)
+#define TTC_IXR_INTERVAL_MASK       0x00000001      /**< interval Interrupt */
+#define TTC_IXR_MATCH_0_MASK        0x00000002      /**< Match 1 Interrupt */
+#define TTC_IXR_MATCH_1_MASK        0x00000004      /**< Match 2 Interrupt */
+#define TTC_IXR_MATCH_2_MASK        0x00000008      /**< Match 3 Interrupt */
+#define TTC_IXR_CNT_OVR_MASK        0x00000010      /**< Counter Overflow */
+#define TTC_IXR_ALL_MASK            0x0000001F      /**< All valid Interrupts */
+
+#define TTC_IER(hw_base)    __REG32(hw_base + 0x60)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,41 @@
+#ifndef __ZYNQMP_R5_H__
+#define __ZYNQMP_R5_H__
+
+#include "xparameters.h"
+
+#define __REG64(x)  (*((volatile rt_uint64_t *)(x)))
+#define __REG32(x)  (*((volatile rt_uint32_t *)(x)))
+#define __REG16(x)  (*((volatile rt_uint16_t *)(x)))
+#define __REG8(x)  (*((volatile rt_uint8_t *)(x)))
+
+#define ZynqMP_CRL_APB_BASEADDR        XPAR_PSU_CRL_APB_S_AXI_BASEADDR
+#define ZynqMP_CRL_APB_IOPLL_CTRL	   0x020    
+#define ZynqMP_CRL_APB_IOPLL_CFG	   0x024   
+#define ZynqMP_CRL_APB_UART0_REF_CTRL  0x074   
+#define ZynqMP_CRL_APB_UART1_REF_CTRL  0x078   
+#define ZynqMP_CRL_APB_LPD_LSBUS_CTRL  0x0AC  
+#define ZynqMP_CRL_APB_RESET_CTRL      0x218
+#define ZynqMP_RESET_MASK       0x10
+
+#define ZynqMP_GIC_CPU_BASE            XPAR_PSU_RCPU_GIC_BASEADDR       /* Generic interrupt controller CPU interface */
+#define ZynqMP_GIC_DIST_BASE           XPAR_PSU_RCPU_GIC_DIST_BASEADDR  /* Generic interrupt controller distributor */
+
+/* ZynqMP on-board gic irq sources */
+#define IRQ_ZynqMP_MAXNR       195
+
+#define ARM_GIC_NR_IRQS     IRQ_ZynqMP_MAXNR
+/* only one GIC available */
+#define ARM_GIC_MAX_NR      1
+
+#define GIC_ACK_INTID_MASK  0x000003FF
+
+#define ZynqMP_R5_0_ID    0
+#define ZynqMP_R5_1_ID    1
+#define ZynqMP_R5_CPU_ID   ZynqMP_R5_0_ID
+
+static inline unsigned long rt_cpu_get_smp_id(void)
+{
+    return ZynqMP_R5_CPU_ID;
+}
+
+#endif
@@ -0,0 +1,190 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 20
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x40003
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* Using RapidIO */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define SOC_ZYNQMP_R5
+
+/* Hardware Drivers Config */
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_USING_SDIO
+#define BSP_USING_SD0
+
+/* Board extended module Drivers */
+
+
+#endif
@@ -0,0 +1,49 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='zynqmp-r5'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# only support GNU GCC compiler
+PLATFORM 	= 'gcc'
+EXEC_PATH 	= '/opt/arm-none-eabi-gcc'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -Wall -mcpu=cortex-r5 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LINK_SCRIPT = 'zynqmp-r5.ld'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=zynqmp-r5.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
+                SIZE + ' $TARGET \n'
@@ -0,0 +1,127 @@
+MEMORY
+{
+   psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
+   psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
+   psu_r5_0_atcm_MEM_0 : ORIGIN = 0x0, LENGTH = 0x10000
+   psu_r5_0_btcm_MEM_0 : ORIGIN = 0x20000, LENGTH = 0x10000
+   psu_r5_ddr_0_MEM_0 : ORIGIN = 0x100000, LENGTH = 0x7FE00000
+   psu_r5_tcm_ram_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x40000
+}
+
+ENTRY(_reset)
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SECTIONS
+{
+    .vectors : 
+    {
+        KEEP (*(.vectors))
+        *(.boot)
+        *(.text.isr)
+    } > psu_r5_0_atcm_MEM_0
+
+    __text_start = .;
+    .text :
+    {
+        *(.text)
+        *(.text.*)
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+        
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } > psu_r5_ddr_0_MEM_0 = 0
+    __text_end = .;
+
+    __exidx_start = .;
+    .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > psu_r5_ddr_0_MEM_0
+    __exidx_end = .;
+
+    .note-ABI-tag :
+    {
+        KEEP (*(.note-ABI-tag))
+    } > psu_r5_ddr_0_MEM_0
+
+    .note.gnu.build-id :
+    {
+        KEEP (*(.note.gnu.build-id))
+    } > psu_r5_ddr_0_MEM_0
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) } > psu_r5_ddr_0_MEM_0
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    } > psu_r5_ddr_0_MEM_0
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    } > psu_r5_ddr_0_MEM_0
+
+    . = ALIGN(4);
+    __data_start = .;
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    } > psu_r5_ddr_0_MEM_0
+    __data_end = .;
+
+    . = ALIGN(4);
+    __bss_start = .;
+    .bss       :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+    } > psu_r5_ddr_0_MEM_0
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'armcc':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'gcc':
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM == 'iar':
+    src += Glob('*_iar.S')
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
@@ -0,0 +1,67 @@
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef VFP_DATA_NR
+#define VFP_DATA_NR 32
+#endif
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long sp;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long cpsr;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+#endif
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-03-19 	  WangHuachen  first version
+ */
+#include <rthw.h>
+#include <rtdef.h>
+
+#include "xpseudo_asm_gcc.h"
+#include "xreg_cortexr5.h"
+
+#define IRQ_FIQ_MASK 0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
+
+typedef intptr_t INTPTR;
+typedef rt_uint32_t u32;
+
+#if defined (__GNUC__)
+#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
+
+#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
+#elif defined (__ICCARM__)
+#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
+		XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
+
+#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \
+		XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
+#endif
+
+
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0x00000000U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+
+			/* Invalidate L1 I-cache line */
+			asm_inval_ic_line_mva_pou(LocalAddr);
+
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+void Xil_DCacheFlushLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+		/* Wait for flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+		/* Select L1 Data cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+
+			Xil_DCacheFlushLine(tempadr);
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+
+			Xil_DCacheFlushLine(tempend);
+		}
+
+		while (tempadr < tempend) {
+
+		/* Invalidate Data cache line */
+		asm_inval_dc_line_mva_poc(tempadr);
+
+		tempadr += cacheline;
+		}
+	}
+
+	dsb();
+	mtcpsr(currmask);
+}
+
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0x00000000U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr &= ~(cacheline - 1U);
+
+		while (LocalAddr < end) {
+			/* Flush Data cache line */
+			asm_clean_inval_dc_line_mva_poc(LocalAddr);
+
+			LocalAddr += cacheline;
+		}
+	}
+	dsb();
+	mtcpsr(currmask);
+}
+
+void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_INVALIDATE)
+        Xil_ICacheInvalidateRange((INTPTR)addr, size);
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+    if (ops == RT_HW_CACHE_FLUSH)
+        Xil_DCacheFlushRange((intptr_t)addr, size);
+    else if (ops == RT_HW_CACHE_INVALIDATE)
+        Xil_DCacheInvalidateRange((intptr_t)addr, size);
+}
+
+rt_base_t rt_hw_cpu_icache_status(void)
+{
+	register u32 CtrlReg;
+#if defined (__GNUC__)
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
+#endif
+	return CtrlReg & XREG_CP15_CONTROL_I_BIT;
+}
+
+rt_base_t rt_hw_cpu_dcache_status(void)
+{
+	register u32 CtrlReg;
+#if defined (__GNUC__)
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	 mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
+#endif
+	return CtrlReg & XREG_CP15_CONTROL_C_BIT;
+}
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-03-19 	  WangHuachen  first version
+ */
+
+.section .text, "ax"
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    cpsid if
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    ldmfd sp!, {r1}				/* Restore floating point registers */
+    vmsr FPEXC, r1
+    ldmfd sp!, {r1}
+    vmsr FPSCR, r1
+    vldmia sp!, {d0-d15}
+#endif
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+
+.section .text.isr, "ax"
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    beq _ARM_MODE
+    orr r4, r4, #0x20       @ it's thumb code
+
+_ARM_MODE:
+    stmfd sp!, {r4}         @ push cpsr
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    vstmdb sp!, {d0-d15}     /* Store floating point registers */
+    vmrs r4, FPSCR
+    stmfd sp!,{r4}
+    vmrs r4, FPEXC
+    stmfd sp!,{r4}
+#endif
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    ldmfd sp!, {r1}				/* Restore floating point registers */
+    vmsr FPEXC, r1
+    ldmfd sp!, {r1}
+    vmsr FPSCR, r1
+    vldmia sp!, {d0-d15}
+#endif
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r3, [r2]
+    ldr r2, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    str r0, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-03-19 	  WangHuachen  first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "zynqmp-r5.h"
+
+void rt_hw_cpu_reset()
+{
+    __REG32(ZynqMP_CRL_APB_BASEADDR + ZynqMP_CRL_APB_RESET_CTRL) |= ZynqMP_RESET_MASK;
+    while (1);  /* loop forever and wait for reset to happen */
+    /* NEVER REACHED */
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-03-19 	  WangHuachen  first version
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq);
+void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+
+#endif
+
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-03-19 	  WangHuachen  first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "zynqmp-r5.h"
+#include "interrupt.h"
+#include "gic.h"
+
+#define MAX_HANDLERS                IRQ_ZynqMP_MAXNR
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+
+void rt_hw_interrupt_handle(int vector, void *param)
+{
+    rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
+}
+
+void rt_hw_interrupt_init(void)
+{
+    register rt_uint32_t idx;
+
+    /* the initialization is done in fsbl */
+
+    /* init exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+    for (idx = 0; idx < MAX_HANDLERS; idx++)
+    {
+        isr_table[idx].handler = rt_hw_interrupt_handle;
+    }
+
+    /* initialize ARM GIC */
+    arm_gic_dist_init(0, ZynqMP_GIC_DIST_BASE, 0);
+    arm_gic_cpu_init(0, ZynqMP_GIC_CPU_BASE);
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    arm_gic_mask(0, vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    arm_gic_umask(0, vector);
+}
+
+/**
+ * This function returns the active interrupt number.
+ * @param none
+ */
+int rt_hw_interrupt_get_irq(void)
+{
+    return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
+}
+
+/**
+ * This function acknowledges the interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_ack(int vector)
+{
+    arm_gic_ack(0, vector);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param handler the interrupt service routine to be installed
+ * @param param the parameter for interrupt service routine
+ * @param name the interrupt name
+ *
+ * @return the old handler
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(isr_table[vector].name, RT_NAME_MAX, "%s", name);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+        /* set the interrupt to this cpu */
+        arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
+    }
+
+    return old_handler;
+}
+
+void rt_hw_interrupt_trigger(int vector)
+{
+    arm_gic_trigger(0, 1 << rt_cpu_get_smp_id(), vector);
+}
+
+void rt_hw_interrupt_clear(int vector)
+{
+    /* SGI will be cleared automatically. */
+}
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-03-19 	  WangHuachen  first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_trigger(int vector);
+void rt_hw_interrupt_clear(int vector);
+void rt_hw_interrupt_ack(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ * 2020-11-24     WangHuachen  porting to zynqmp-r5
+ */
+#include <rtthread.h>
+#include "armv7.h"
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0xdeadbeef;                  /* r12 */
+    *(--stk) = 0xdeadbeef;                  /* r11 */
+    *(--stk) = 0xdeadbeef;                  /* r10 */
+    *(--stk) = 0xdeadbeef;                  /* r9 */
+    *(--stk) = 0xdeadbeef;                  /* r8 */
+    *(--stk) = 0xdeadbeef;                  /* r7 */
+    *(--stk) = 0xdeadbeef;                  /* r6 */
+    *(--stk) = 0xdeadbeef;                  /* r5 */
+    *(--stk) = 0xdeadbeef;                  /* r4 */
+    *(--stk) = 0xdeadbeef;                  /* r3 */
+    *(--stk) = 0xdeadbeef;                  /* r2 */
+    *(--stk) = 0xdeadbeef;                  /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    {
+        int i;
+        for (i = 0; i < VFP_DATA_NR; i++)
+        {
+            *(--stk) = 0;
+        }
+        /* FPSCR TODO: do we need to set the values other than 0? */
+        *(--stk) = 0;
+        /* FPEXC. Enable the FVP if no lazy stacking. */
+        *(--stk) = 0x40000000;
+    }
+#endif
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2020-11-24     WangHuachen  porting to zynqmp-r5
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "armv7.h"
+#include "interrupt.h"
+
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register (struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    int ir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+
+    if (ir == 1023)
+    {
+        /* Spurious interrupt */
+        return;
+    }
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+    isr_table[ir].counter++;
+#endif
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
+}
+
+void rt_hw_trap_fiq(void)
+{
+    void *param;
+    int ir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+    param = isr_table[ir].param;
+
+    /* turn to interrupt service routine */
+    isr_func(ir, param);
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
+}
+
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl 	16,0xdeadbeef