mirror of
https://github.com/RT-Thread/rt-thread.git
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Merge pull request #4107 from Wang-Huachen/master
[bsp] 添加对zynqmp-r5核心的支持和zynqmp-r5-axu4ev开发板的bsp
This commit is contained in:
Bernard Xiong
GitHub
4
.github/workflows/action.yml
vendored
4
.github/workflows/action.yml
vendored
@@ -403,6 +403,10 @@ jobs:
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RTT_BSP: "zynq7000"
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RTT_TOOL_CHAIN: "sourcery-arm"
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- action-version: "1.0"
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RTT_BSP: "zynqmp-r5-axu4ev"
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RTT_TOOL_CHAIN: "sourcery-arm"
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- action-version: "1.0"
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RTT_BSP: "frdm-k64f"
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RTT_TOOL_CHAIN: "sourcery-arm"
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515
bsp/zynqmp-r5-axu4ev/.config
Normal file
515
bsp/zynqmp-r5-axu4ev/.config
Normal file
File diff suppressed because it is too large
Load Diff
27
bsp/zynqmp-r5-axu4ev/Kconfig
Normal file
27
bsp/zynqmp-r5-axu4ev/Kconfig
Normal file
@@ -0,0 +1,27 @@
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mainmenu "RT-Thread Project Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config SOC_ZYNQMP_R5
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bool
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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source "$BSP_DIR/drivers/Kconfig"
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112
bsp/zynqmp-r5-axu4ev/README.md
Normal file
112
bsp/zynqmp-r5-axu4ev/README.md
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@@ -0,0 +1,112 @@
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# AXU4EV-E BSP (Board Support Package) Execution Instruction
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[中文页](README_zh.md) |
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## **Introduction**
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This document records the execution instruction of the BSP (board support package) for the AXU4EV-E development board.
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The document is covered in three parts:
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- AXU4EV-E Board Resources Introduction
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- Quickly Get Started
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- Advanced Features
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- BSP Migration
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By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
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## AXU4EV-E Resources Introduction
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ALINX AXU4EV-E: Xilinx Zynq UltraScale+ MPSOC XCZU4EV-1SFVC784I Ethernet FPGA development board, the SoM Core board is the smallest system, mainly composed of XCZU4EV-1SFVC784I + 5 DDR4 + eMMC + 1 QSPI FLASH. The Carrier board expands a wealth of peripheral interfaces for the core board, including 1 SATA M.2 interface, 1 DP output interface, 4 USB3.0 interfaces, 2 Gigabit Ethernet interfaces, 2 UART interfaces, 1 SD card interface, 2*40-pin Expansion Connectors for Modules, 2 CAN bus interfaces, 2 RS485 interfaces, 1 MIPI interface, Keys and LEDs. High-speed data exchange and transmission, data storage, pre-verification and post-application of data processing, video transmission processing, deep learning, artificial intelligence and industrial control, is a professional ZYNQ development platform. suitable for students, engineers and other groups engaged in the development of MPSoCs.
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For more details about this board, please refer to [Alinx Electronic Technology (Shanghai) Co.,Ltd.](http://www.alinx.com/en/)。
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## **Peripheral Condition**
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Each peripheral supporting condition for this BSP is as follows:
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| **Core** | **Support** | **Remark** |
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| :----------------- | :----------: | :------------------------------------- |
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| R5-CPU0 | Support | The R5-CPU0 is running the system |
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| **On-board Peripherals** | **Support** | **Remark** |
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| None | | |
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| **On-chip Peripherals** | **Support** | **Remark** |
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| GPIO | Support | |
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| UART | Support | UART0 |
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| TIMER | Support | TTC0 provides system clock |
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| EMMC | Support | SD0 Controller |
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## Execution Instruction
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### Quickly Get Started
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This BSP only support the GCC development environment. Here's an example to introduce how to run the system.
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#### Compile and Download
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1. Open the env tool under BSP. Enter `scons` to compile.
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2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
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3. Use Xilinx Vitis to generate fsbl, and then create "Debug Configuration", select the `rtthread-zynqmp-r5.elf` file as the application.
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4. Use the debugger to connect the PC and the development board. Set the dial switch to JTAG to start. Then connect the power supply. Click start debugging or running.
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Since the compiler has debugging information by default (see rtconfig.py In BUILD, so when debugging in Xilinx Vitis, you can also open source files to set breakpoints for debugging.
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#### Software Solidification
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1. Open the env tool under BSP. Enter `scons` to compile.
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2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
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3. Use Xilinx Vitis or Xilinx SDK to generate fsbl, and then use the bootgen tool provided by Xilinx to make fsbl BOOT.bin Documents.
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For example, use the command line:
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```
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bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on
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```
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And the outpu.bif file could be：
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```
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//arch = zynqmp; split = false; format = BIN
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the_ROM_image:
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{
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[bootloader, destination_cpu = r5-0]./fsbl.elf
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[destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf
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}
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```
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4. According to the document provided by Alinx, put BOOT.bin into SD card or burn to QSPI flash, set the startup mode through dial switch, and then connect the power supply to start.
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#### Running Results
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Once the project is successfully downloaded, the system runs automatically.
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Connect the serial port of the board to PC, communicate with it via a serial terminal tool (115200bps, 8N1). Restart the board and the startup information of RT-Thread will be observed:
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 4.0.3 build Nov 27 2020
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2006 - 2020 Copyright by rt-thread team
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msh />
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```
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### **Advanced Features**
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This BSP enables EMMC driver and DFS file system by default. If you need to use a file system, you can format and mount it by yourself.
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## BSP Migration
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If you need to ported the BSP to another development board of Xilinx Zynq UltraScale+ MPSOC development platform, it is also convenient. The main modifications are as follows:
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1. Memory: `psu_r5_ddr_0_MEM_0` in `zynqmp-r5.ld` (if DDR memory is less than 2G)
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2. Main Frequency: `XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ` in `zynqmp-r5.h`
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3. Pin and Frequency of Serial Port: `rxmio`, `txmio` and `XPAR_PSU_UART_0_UART_CLK_FREQ_HZ` in `drv_uart.c`
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4. Timer Frequency: `XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` in `drv_timer.c`
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5. SD Controller: Block device driver initialization in `drv_sdcard.c`
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The parameter macro definition in `xparameters.h` does not need to be modified manually. You can directly copy the `xparameters.h` file of the development board generated in Xilinx Vitis.
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133
bsp/zynqmp-r5-axu4ev/README_zh.md
Normal file
133
bsp/zynqmp-r5-axu4ev/README_zh.md
Normal file
@@ -0,0 +1,133 @@
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# AXU4EV-E 开发板 BSP 说明
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## 简介
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本文档是为 AXU4EV-E 开发板提供的 BSP (板级支持包) 说明。
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主要内容如下：
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- 开发板资源介绍
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- BSP 快速上手
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- 进阶使用方法
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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## 开发板介绍
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AXU4EV-E 开发板是 芯驿电子科技（上海）有限公司 推出的一款基于 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板。这款 MPSoCs 开发平台采用核心板加扩展板的模式，方便用户对核心板的二次开发利用。核心板使用 XILINX Zynq UltraScale+ EV 芯片 ZU4EV 的解决方案，它采用Processing System(PS)+Programmable Logic(PL)技术将四核ARM Cortex-A53 和FPGA 可编程逻辑集成在一颗芯片上。另外核心板上 PS 端带有 4 片共 4GB 高速 DDR4 SDRAM 芯片，1 片 8GB的 eMMC 存储芯片和 1 片 256Mb 的 QSPI FLASH 芯片；核心板上 PL 端带有 1 片 1GB 的DDR4 SDRAM 芯片 。
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开发板更多详细信息请参考[芯驿电子科技（上海）有限公司](http://www.alinx.cn/)。
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## 外设支持
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本 BSP 目前对外设的支持情况如下：
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| **核心** | **支持情况** | **备注** |
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| :----------------- | :----------: | :------------------------------------- |
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| R5-CPU0 | 支持 | 运行系统的为R5核的CPU0 |
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| **板载外设** | **支持情况** | **备注** |
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| 无 | | |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | |
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| UART | 支持 | UART0 |
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| TIMER | 支持 | TTC0提供系统时钟 |
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| EMMC | 支持 | SD0控制器 |
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## 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 快速上手
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本 BSP 为仅支持 GCC 开发环境，下面介绍如何将系统运行起来。
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#### 编译下载
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1. 在 bsp 下打开 env 工具，输入`scons`进行编译。
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2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。
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3. 使用 Xilinx Vitis 产生 FSBL，然后创建 “Debug Configuration”，Application 选择`rtthread-zynqmp-r5.elf` 文件。
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|
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4. 使用调试器连接 PC 和开发板，通过拨码开关设置为 JTAG 启动，然后连接电源，点击开始调试或运行即可。
|
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|
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由于编译时默认带有调试信息（见 rtconfig.py 中 BUILD），所以在 Xilinx Vitis 中调试时同样可以打开源文件设断点进行调试。
|
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|
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#### 固化程序
|
||||
|
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1. 在 bsp 下打开 env 工具，输入`scons`进行编译。
|
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|
||||
2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。
|
||||
|
||||
3. 使用 Xilinx Vitis 或 Xilinx SDK 产生 FSBL，然后使用 Xilinx 提供的 bootgen 工具制作 BOOT.bin 文件。
|
||||
|
||||
例如使用命令行方式：
|
||||
|
||||
```
|
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bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on
|
||||
```
|
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|
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其中 output.bif 文件可以是：
|
||||
```
|
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//arch = zynqmp; split = false; format = BIN
|
||||
the_ROM_image:
|
||||
{
|
||||
[bootloader, destination_cpu = r5-0]./fsbl.elf
|
||||
[destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf
|
||||
}
|
||||
```
|
||||
|
||||
4. 根据 ALINX 提供的文档将 BOOT.bin 放进SD卡或烧录到 QSPI FLASH 中，通过拨码开关设置启动方式，然后连接电源即可启动。
|
||||
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行。
|
||||
|
||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.3 build Nov 27 2020
|
||||
2006 - 2020 Copyright by rt-thread team
|
||||
msh />
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认开启了 EMMC 驱动和 DFS 文件系统，如果需要使用文件系统可以自行格式化并挂载。
|
||||
|
||||
|
||||
## 板级移植
|
||||
|
||||
如果需要将BSP移植到其他 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板上也比较方便，主要修改的地方有以下几点：
|
||||
|
||||
1. 内存： 如果 DDR memory 小于 2G，需要修改`zynqmp-r5.ld`链接文件中的`psu_r5_ddr_0_MEM_0`
|
||||
2. 主频： `xparameters.h`中的`XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ`
|
||||
3. 串口引脚和频率：`drv_uart.c`中的`rxmio`, `txmio` 和`xparameters.h`中的`XPAR_PSU_UART_0_UART_CLK_FREQ_HZ`
|
||||
4. 定时器频率：`xparameters.h`中的`XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ`
|
||||
5. SD控制器：`drv_sdcard.c`中的块设备驱动初始化
|
||||
|
||||
以上需要修改的`xparameters.h`中的参数宏定义不需要手动修改，可以直接将Xilinx Vitis中产生的开发板的`xparameters.h`文件复制过来即可。
|
||||
|
||||
|
||||
|
||||
## 注意事项
|
||||
|
||||
- 无
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [王华辰](https://github.com/Wang-Huachen/)
|
||||
14
bsp/zynqmp-r5-axu4ev/SConscript
Normal file
14
bsp/zynqmp-r5-axu4ev/SConscript
Normal file
@@ -0,0 +1,14 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
|
||||
cwd = str(Dir('#'))
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
30
bsp/zynqmp-r5-axu4ev/SConstruct
Normal file
30
bsp/zynqmp-r5-axu4ev/SConstruct
Normal file
@@ -0,0 +1,30 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
from building import *
|
||||
|
||||
TARGET = 'rtthread-zynqmp-r5.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
11
bsp/zynqmp-r5-axu4ev/applications/SConscript
Normal file
11
bsp/zynqmp-r5-axu4ev/applications/SConscript
Normal file
@@ -0,0 +1,11 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = os.path.join(str(Dir('#')), 'applications')
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
18
bsp/zynqmp-r5-axu4ev/applications/main.c
Normal file
18
bsp/zynqmp-r5-axu4ev/applications/main.c
Normal file
@@ -0,0 +1,18 @@
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define LED_PIN 40
|
||||
int main(void)
|
||||
{
|
||||
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
35
bsp/zynqmp-r5-axu4ev/drivers/Kconfig
Normal file
35
bsp/zynqmp-r5-axu4ev/drivers/Kconfig
Normal file
@@ -0,0 +1,35 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART0
|
||||
bool "Enable UART0"
|
||||
default y
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_SDIO
|
||||
bool "Enable SDIO"
|
||||
default y
|
||||
if BSP_USING_SDIO
|
||||
config BSP_USING_SD0
|
||||
bool "Enable SD0 EMMC"
|
||||
default y
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
26
bsp/zynqmp-r5-axu4ev/drivers/SConscript
Normal file
26
bsp/zynqmp-r5-axu4ev/drivers/SConscript
Normal file
@@ -0,0 +1,26 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
list = os.listdir(cwd)
|
||||
CPPPATH = [cwd]
|
||||
objs = []
|
||||
|
||||
if not GetDepend('BSP_USING_UART'):
|
||||
SrcRemove(src, ['drv_uart.c'])
|
||||
|
||||
if not GetDepend('BSP_USING_SDIO'):
|
||||
SrcRemove(src, ['drv_sdcard.c'])
|
||||
|
||||
if not GetDepend('RT_USING_PIN'):
|
||||
SrcRemove(src, ['drv_gpio.c'])
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
objs = objs + group
|
||||
|
||||
Return('objs')
|
||||
17
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/SConscript
Normal file
17
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/SConscript
Normal file
@@ -0,0 +1,17 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
objs = []
|
||||
|
||||
group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
if GetDepend('BSP_USING_SDIO'):
|
||||
objs = objs + SConscript('sdps_v3_9/SConscript')
|
||||
if GetDepend('RT_USING_PIN'):
|
||||
objs = objs + SConscript('gpiops_v3_7/SConscript')
|
||||
|
||||
objs = objs + group
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,15 @@
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [cwd]
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Glob('*.c')
|
||||
path = cwd
|
||||
|
||||
group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,267 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xgpiops.h
|
||||
* @addtogroup gpiops_v3_7
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
|
||||
* Controller.
|
||||
*
|
||||
* The GPIO Controller supports the following features:
|
||||
* - 4 banks
|
||||
* - Masked writes (There are no masked reads)
|
||||
* - Bypass mode
|
||||
* - Configurable Interrupts (Level/Edge)
|
||||
*
|
||||
* This driver is intended to be RTOS and processor independent. Any needs for
|
||||
* dynamic memory management, threads or thread mutual exclusion, virtual
|
||||
* memory, or cache control must be satisfied by the layer above this driver.
|
||||
|
||||
* This driver supports all the features listed above, if applicable.
|
||||
*
|
||||
* <b>Driver Description</b>
|
||||
*
|
||||
* The device driver enables higher layer software (e.g., an application) to
|
||||
* communicate to the GPIO.
|
||||
*
|
||||
* <b>Interrupts</b>
|
||||
*
|
||||
* The driver provides interrupt management functions and an interrupt handler.
|
||||
* Users of this driver need to provide callback functions. An interrupt handler
|
||||
* example is available with the driver.
|
||||
*
|
||||
* <b>Threads</b>
|
||||
*
|
||||
* This driver is not thread safe. Any needs for threads or thread mutual
|
||||
* exclusion must be satisfied by the layer above this driver.
|
||||
*
|
||||
* <b>Asserts</b>
|
||||
*
|
||||
* Asserts are used within all Xilinx drivers to enforce constraints on argument
|
||||
* values. Asserts can be turned off on a system-wide basis by defining, at
|
||||
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
|
||||
* is recommended that users leave asserts on during development.
|
||||
*
|
||||
* <b>Building the driver</b>
|
||||
*
|
||||
* The XGpioPs driver is composed of several source files. This allows the user
|
||||
* to build and link only those parts of the driver that are necessary.
|
||||
* <br><br>
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.00a sv 01/15/10 First Release
|
||||
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
|
||||
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
|
||||
* relevant to Zynq device.The interrupts are disabled
|
||||
* for output pins on all banks during initialization.
|
||||
* 1.02a hk 08/22/13 Added low level reset API
|
||||
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
|
||||
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
|
||||
* passed to APIs. CR# 822636
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/05/17 Added tabspace for return statements in functions of
|
||||
* gpiops examples for proper documentation while
|
||||
* generating doxygen.
|
||||
* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
|
||||
* for zcu102 and zc702 boards in polled and interrupt
|
||||
* example, configured Interrupt pin to input pin for
|
||||
* proper functioning of interrupt example.
|
||||
* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
|
||||
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and modified the code such as
|
||||
* Use of mixed mode arithmetic,Declared the pointer param
|
||||
* as Pointer to const,Casting operation to a pointer,
|
||||
* Literal value requires a U suffix.
|
||||
* 3.5 sne 03/14/19 Added Versal support.
|
||||
* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
|
||||
* sync with standalone BSP
|
||||
* 3.6 sne 06/12/19 Fixed IAR compiler warning.
|
||||
* 3.6 sne 08/14/19 Added interrupt handler support on versal.
|
||||
* 3.7 sne 12/04/19 Reverted versal examples support.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XGPIOPS_H /* prevent circular inclusions */
|
||||
#define XGPIOPS_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xstatus.h"
|
||||
#include "xgpiops_hw.h"
|
||||
#include "xplatform_info.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Interrupt types
|
||||
* @{
|
||||
* The following constants define the interrupt types that can be set for each
|
||||
* GPIO pin.
|
||||
*/
|
||||
#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
|
||||
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
|
||||
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
|
||||
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
|
||||
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
|
||||
/*@}*/
|
||||
|
||||
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
|
||||
#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
|
||||
#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
|
||||
#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
|
||||
#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
|
||||
|
||||
#ifdef XPAR_PSU_GPIO_0_BASEADDR
|
||||
#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
|
||||
#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
|
||||
#endif
|
||||
|
||||
#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
|
||||
* Zynq Ultrascale+ MP GPIO device
|
||||
*/
|
||||
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
|
||||
|
||||
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
|
||||
* Zynq Ultrascale+ MP GPIO device
|
||||
* 0 - 25, Bank 0
|
||||
* 26 - 51, Bank 1
|
||||
* 52 - 77, Bank 2
|
||||
* 78 - 109, Bank 3
|
||||
* 110 - 141, Bank 4
|
||||
* 142 - 173, Bank 5
|
||||
*/
|
||||
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
|
||||
* 0 - 31, Bank 0
|
||||
* 32 - 53, Bank 1
|
||||
* 54 - 85, Bank 2
|
||||
* 86 - 117, Bank 3
|
||||
*/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* This handler data type allows the user to define a callback function to
|
||||
* handle the interrupts for the GPIO device. The application using this
|
||||
* driver is expected to define a handler of this type, to support interrupt
|
||||
* driven mode. The handler executes in an interrupt context such that minimal
|
||||
* processing should be performed.
|
||||
*
|
||||
* @param CallBackRef is a callback reference passed in by the upper layer
|
||||
* when setting the callback functions for a GPIO bank. It is
|
||||
* passed back to the upper layer when the callback is invoked. Its
|
||||
* type is not important to the driver component, so it is a void
|
||||
* pointer.
|
||||
* @param Bank is the bank for which the interrupt status has changed.
|
||||
* @param Status is the Interrupt status of the GPIO bank.
|
||||
*
|
||||
*****************************************************************************/
|
||||
typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for a device.
|
||||
*/
|
||||
typedef struct {
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
u32 BaseAddr; /**< Register base address */
|
||||
} XGpioPs_Config;
|
||||
|
||||
/**
|
||||
* The XGpioPs driver instance data. The user is required to allocate a
|
||||
* variable of this type for the GPIO device in the system. A pointer
|
||||
* to a variable of this type is then passed to the driver API functions.
|
||||
*/
|
||||
typedef struct {
|
||||
XGpioPs_Config GpioConfig; /**< Device configuration */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
XGpioPs_Handler Handler; /**< Status handlers for all banks */
|
||||
void *CallBackRef; /**< Callback ref for bank handlers */
|
||||
u32 Platform; /**< Platform data */
|
||||
u32 MaxPinNum; /**< Max pins in the GPIO device */
|
||||
u8 MaxBanks; /**< Max banks in a GPIO device */
|
||||
u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
|
||||
} XGpioPs;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/* Functions in xgpiops.c */
|
||||
s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
|
||||
u32 EffectiveAddr);
|
||||
|
||||
/* Bank APIs in xgpiops.c */
|
||||
u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
|
||||
void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
|
||||
void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
|
||||
u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
|
||||
void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
|
||||
u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
|
||||
#ifdef versal
|
||||
void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
|
||||
#else
|
||||
void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
|
||||
#endif
|
||||
|
||||
/* Pin APIs in xgpiops.c */
|
||||
u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
|
||||
void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
|
||||
u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
|
||||
u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
|
||||
/* Diagnostic functions in xgpiops_selftest.c */
|
||||
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
|
||||
|
||||
/* Functions in xgpiops_intr.c */
|
||||
/* Bank APIs in xgpiops_intr.c */
|
||||
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
|
||||
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
|
||||
u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
|
||||
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
|
||||
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
|
||||
void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
|
||||
u32 IntrPolarity, u32 IntrOnAny);
|
||||
void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
|
||||
u32 *IntrPolarity, u32 *IntrOnAny);
|
||||
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
|
||||
XGpioPs_Handler FuncPointer);
|
||||
void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
|
||||
|
||||
/* Pin APIs in xgpiops_intr.c */
|
||||
void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
|
||||
u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
|
||||
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
|
||||
|
||||
/* Functions in xgpiops_sinit.c */
|
||||
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
@@ -0,0 +1,31 @@
|
||||
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by HSI.
|
||||
* Version: 2020.1
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
|
||||
*
|
||||
* Description: Driver configuration
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xgpiops.h"
|
||||
|
||||
/*
|
||||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PSU_GPIO_0_DEVICE_ID,
|
||||
XPAR_PSU_GPIO_0_BASEADDR
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
@@ -0,0 +1,240 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xgpiops_hw.c
|
||||
* @addtogroup gpiops_v3_7
|
||||
* @{
|
||||
*
|
||||
* This file contains low level GPIO functions.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.02a hk 08/22/13 First Release
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
|
||||
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and modified the code such as
|
||||
* Use of mixed mode arithmetic,Declared the pointer param
|
||||
* as Pointer to const,Casting operation to a pointer,
|
||||
* Literal value requires a U suffix.
|
||||
* 3.5 sne 03/14/19 Added versal support.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xgpiops_hw.h"
|
||||
#include "xgpiops.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* This function resets the GPIO module by writing reset values to
|
||||
* all registers
|
||||
*
|
||||
* @param Base address of GPIO module
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XGpioPs_ResetHw(u32 BaseAddress)
|
||||
{
|
||||
u32 BankCount;
|
||||
u32 Platform,MaxBanks;
|
||||
|
||||
Platform = XGetPlatform_Info();
|
||||
if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
|
||||
MaxBanks = (u32)6;
|
||||
}
|
||||
else if(Platform == (u32)XPLAT_VERSAL)
|
||||
{
|
||||
if (BaseAddress == (u32)XGPIOPS_PS_GPIO_BASEADDR)
|
||||
{
|
||||
MaxBanks = (u32)4;
|
||||
}
|
||||
else
|
||||
{
|
||||
MaxBanks = (u32)5;
|
||||
}
|
||||
}
|
||||
else {
|
||||
MaxBanks = (u32)4;
|
||||
}
|
||||
|
||||
if (Platform == (u32)XPLAT_VERSAL)
|
||||
{
|
||||
/* Write reset values to all mask data registers */
|
||||
for(BankCount = 3U; BankCount < (u32)MaxBanks; BankCount++) {
|
||||
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
|
||||
XGPIOPS_DATA_LSW_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
|
||||
XGPIOPS_DATA_MSW_OFFSET), 0x0U);
|
||||
}
|
||||
/* Write reset values to all output data registers */
|
||||
for(BankCount = 3U; BankCount < (u32)MaxBanks; BankCount++) {
|
||||
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
|
||||
XGPIOPS_DATA_OFFSET), 0x0U);
|
||||
}
|
||||
|
||||
/* Reset all registers of all GPIO banks */
|
||||
for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
|
||||
|
||||
|
||||
if((BaseAddress == (u32)XGPIOPS_PS_GPIO_BASEADDR) && ((BankCount == (u32)XGPIOPS_ONE) ||(BankCount == (u32)XGPIOPS_TWO)))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((BaseAddress != (u32)XGPIOPS_PS_GPIO_BASEADDR) && (BankCount == (u32)XGPIOPS_ONE))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
}
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_DIRM_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_OUTEN_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTMASK_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTEN_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTDIS_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTSTS_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTPOL_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTANY_OFFSET), 0x0U);
|
||||
|
||||
}
|
||||
|
||||
/* Bank 0 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
|
||||
XGPIOPS_INTTYPE_BANK0_RESET);
|
||||
/* Bank 1 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK1_RESET);
|
||||
/* Bank 3 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK3_RESET);
|
||||
/* Bank 4 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK4_RESET);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Write reset values to all mask data registers */
|
||||
for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
|
||||
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
|
||||
XGPIOPS_DATA_LSW_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
|
||||
XGPIOPS_DATA_MSW_OFFSET), 0x0U);
|
||||
}
|
||||
/* Write reset values to all output data registers */
|
||||
for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
|
||||
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
|
||||
XGPIOPS_DATA_OFFSET), 0x0U);
|
||||
}
|
||||
/* Reset all registers of all GPIO banks */
|
||||
for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
|
||||
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_DIRM_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_OUTEN_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTMASK_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTEN_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTDIS_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTSTS_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTPOL_OFFSET), 0x0U);
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((BankCount * XGPIOPS_REG_MASK_OFFSET) +
|
||||
XGPIOPS_INTANY_OFFSET), 0x0U);
|
||||
}
|
||||
/* Bank 0 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
|
||||
XGPIOPS_INTTYPE_BANK0_RESET);
|
||||
/* Bank 1 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK1_RESET);
|
||||
/* Bank 2 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK2_RESET);
|
||||
/* Bank 3 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK3_RESET);
|
||||
|
||||
if (Platform == (u32)XPLAT_ZYNQ_ULTRA_MP) {
|
||||
/* Bank 4 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK4_RESET);
|
||||
/* Bank 5 Int type */
|
||||
XGpioPs_WriteReg(BaseAddress,
|
||||
(((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
|
||||
XGPIOPS_INTTYPE_BANK5_RESET);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
/** @} */
|
||||
@@ -0,0 +1,146 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xgpiops_hw.h
|
||||
* @addtogroup gpiops_v3_7
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic driver functions (or
|
||||
* macros) that can be used to access the device. Other driver functions
|
||||
* are defined in xgpiops.h.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------
|
||||
* 1.00a sv 01/15/10 First Release
|
||||
* 1.02a hk 08/22/13 Added low level reset API function prototype and
|
||||
* related constant definitions
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.1 kvn 04/13/15 Corrected reset values of banks.
|
||||
* 3.5 sne 03/14/19 Added versal support.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
|
||||
#define XGPIOPS_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Register offsets for the GPIO. Each register is 32 bits.
|
||||
* @{
|
||||
*/
|
||||
#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */
|
||||
#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */
|
||||
#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */
|
||||
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */
|
||||
#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */
|
||||
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */
|
||||
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */
|
||||
#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */
|
||||
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/
|
||||
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */
|
||||
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */
|
||||
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */
|
||||
#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */
|
||||
/* @} */
|
||||
|
||||
/** @name Register offsets for each Bank.
|
||||
* @{
|
||||
*/
|
||||
#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */
|
||||
#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */
|
||||
#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */
|
||||
/* @} */
|
||||
|
||||
/* For backwards compatibility */
|
||||
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40
|
||||
|
||||
/** @name Interrupt type reset values for each bank
|
||||
* @{
|
||||
*/
|
||||
#ifdef XPAR_PSU_GPIO_0_BASEADDR
|
||||
#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
|
||||
#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU
|
||||
#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU
|
||||
#else
|
||||
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */
|
||||
#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU
|
||||
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU
|
||||
#endif
|
||||
|
||||
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */
|
||||
#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */
|
||||
#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU
|
||||
/* @} */
|
||||
#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /* Flag for Base Address for PS_GPIO in Versal */
|
||||
#define XGPIOPS_ZERO 0U /* Flag for 0 Value */
|
||||
#define XGPIOPS_ONE 1U /* Flag for 1 Value */
|
||||
#define XGPIOPS_TWO 2U /* Flag for 2 Value */
|
||||
#define XGPIOPS_THREE 3U /* Flag for 3 Value */
|
||||
#define XGPIOPS_FOUR 4U /* Flag for 4 Value */
|
||||
#define XGPIOPS_SIX 6U /* Flag for 6 Value */
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro reads the given register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the device.
|
||||
* @param RegOffset is the register offset to be read.
|
||||
*
|
||||
* @return The 32-bit value of the register
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
|
||||
Xil_In32((BaseAddr) + (u32)(RegOffset))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This macro writes to the given register.
|
||||
*
|
||||
* @param BaseAddr is the base address of the device.
|
||||
* @param RegOffset is the offset of the register to be written.
|
||||
* @param Data is the 32-bit value to write to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
|
||||
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void XGpioPs_ResetHw(u32 BaseAddress);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* XGPIOPS_HW_H */
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,112 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xgpiops_selftest.c
|
||||
* @addtogroup gpiops_v3_7
|
||||
* @{
|
||||
*
|
||||
* This file contains a diagnostic self-test function for the XGpioPs driver.
|
||||
*
|
||||
* Read xgpiops.h file for more information.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.00a sv 01/18/10 First Release
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and modified the code such as
|
||||
* Use of mixed mode arithmetic,Declared the pointer param
|
||||
* as Pointer to const,Casting operation to a pointer,
|
||||
* Literal value requires a U suffix.
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/***************************** Include Files ********************************/
|
||||
|
||||
#include "xstatus.h"
|
||||
#include "xgpiops.h"
|
||||
|
||||
/************************** Constant Definitions ****************************/
|
||||
|
||||
|
||||
/**************************** Type Definitions ******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/************************** Variable Definitions ****************************/
|
||||
|
||||
/************************** Function Prototypes *****************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function runs a self-test on the GPIO driver/device. This function
|
||||
* does a register read/write test on some of the Interrupt Registers.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XGpioPs instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if the self-test passed.
|
||||
* - XST_FAILURE otherwise.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr)
|
||||
{
|
||||
s32 Status = XST_SUCCESS;
|
||||
u32 IntrEnabled;
|
||||
u32 CurrentIntrType = 0U;
|
||||
u32 CurrentIntrPolarity = 0U;
|
||||
u32 CurrentIntrOnAny = 0U;
|
||||
u32 IntrType = 0U;
|
||||
u32 IntrPolarity = 0U;
|
||||
u32 IntrOnAny = 0U;
|
||||
u32 IntrTestValue = 0x22U;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/* Disable the Interrupts for Bank 0 . */
|
||||
IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
|
||||
XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
|
||||
|
||||
/*
|
||||
* Get the Current Interrupt properties for Bank 0.
|
||||
* Set them to a known value, read it back and compare.
|
||||
*/
|
||||
XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
|
||||
&CurrentIntrPolarity, &CurrentIntrOnAny);
|
||||
|
||||
XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
|
||||
IntrTestValue, IntrTestValue);
|
||||
|
||||
XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
|
||||
&IntrPolarity, &IntrOnAny);
|
||||
|
||||
if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
|
||||
(IntrOnAny != IntrTestValue)) {
|
||||
|
||||
Status = XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Restore the contents of all the interrupt registers modified in this
|
||||
* test.
|
||||
*/
|
||||
XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
|
||||
CurrentIntrPolarity, CurrentIntrOnAny);
|
||||
|
||||
XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
|
||||
|
||||
return Status;
|
||||
}
|
||||
/** @} */
|
||||
@@ -0,0 +1,75 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xgpiops_sinit.c
|
||||
* @addtogroup gpiops_v3_7
|
||||
* @{
|
||||
*
|
||||
* This file contains the implementation of the XGpioPs driver's static
|
||||
* initialization functionality.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
* <pre>
|
||||
*
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -----------------------------------------------
|
||||
* 1.00a sv 01/15/10 First Release
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xgpiops.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function looks for the device configuration based on the unique device
|
||||
* ID. The table XGpioPs_ConfigTable[] contains the configuration information
|
||||
* for each device in the system.
|
||||
*
|
||||
* @param DeviceId is the unique device ID of the device being looked up.
|
||||
*
|
||||
* @return A pointer to the configuration table entry corresponding to the
|
||||
* given device ID, or NULL if no match is found.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
XGpioPs_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
|
||||
if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XGpioPs_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (XGpioPs_Config *)CfgPtr;
|
||||
}
|
||||
/** @} */
|
||||
@@ -0,0 +1,15 @@
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
# get current directory
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [cwd]
|
||||
|
||||
# The set of source files associated with this SConscript file.
|
||||
|
||||
src = Glob('*.c')
|
||||
path = cwd
|
||||
|
||||
group = DefineGroup('ZYNQMP_HAL', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
420
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c
Normal file
420
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c
Normal file
@@ -0,0 +1,420 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xsdps.c
|
||||
* @addtogroup sdps_v3_9
|
||||
* @{
|
||||
*
|
||||
* Contains the interface functions of the XSdPs driver.
|
||||
* See xsdps.h for a detailed description of the device and driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- -----------------------------------------------
|
||||
* 1.00a hk/sg 10/17/13 Initial release
|
||||
* 2.0 hk 12/13/13 Added check for arm to use sleep.h and its API's
|
||||
* 2.1 hk 04/18/14 Add sleep for microblaze designs. CR# 781117.
|
||||
* 2.2 hk 07/28/14 Make changes to enable use of data cache.
|
||||
* 2.3 sk 09/23/14 Send command for relative card address
|
||||
* when re-initialization is done.CR# 819614.
|
||||
* Use XSdPs_Change_ClkFreq API whenever changing
|
||||
* clock.CR# 816586.
|
||||
* 2.4 sk 12/04/14 Added support for micro SD without
|
||||
* WP/CD. CR# 810655.
|
||||
* Checked for DAT Inhibit mask instead of CMD
|
||||
* Inhibit mask in Cmd Transfer API.
|
||||
* Added Support for SD Card v1.0
|
||||
* 2.5 sg 07/09/15 Added SD 3.0 features
|
||||
* kvn 07/15/15 Modified the code according to MISRAC-2012.
|
||||
* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
|
||||
* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
|
||||
* sk 12/10/15 Added support for MMC cards.
|
||||
* sk 02/16/16 Corrected the Tuning logic.
|
||||
* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
|
||||
* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
|
||||
* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
|
||||
* sk 07/16/16 Added support for UHS modes.
|
||||
* sk 07/07/16 Used usleep API for both arm and microblaze.
|
||||
* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
|
||||
* operating modes.
|
||||
* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
|
||||
* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
|
||||
* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
|
||||
* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
|
||||
* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
|
||||
* sk 02/01/17 Added HSD and DDR mode support for eMMC.
|
||||
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
|
||||
* sk 03/20/17 Add support for EL1 non-secure mode.
|
||||
* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
|
||||
* mn 07/17/17 Add support for running SD at 200MHz
|
||||
* mn 07/26/17 Fixed compilation warnings
|
||||
* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
|
||||
* mn 08/17/17 Added CCI support for A53 and disabled data cache
|
||||
* operations when it is enabled.
|
||||
* mn 08/22/17 Updated for Word Access System support
|
||||
* mn 09/06/17 Resolved compilation errors with IAR toolchain
|
||||
* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
|
||||
* 3.4 mn 10/17/17 Use different commands for single and multi block
|
||||
* transfers
|
||||
* mn 03/02/18 Move UHS macro check to SD card initialization routine
|
||||
* 3.5 mn 04/18/18 Resolve compilation warnings for sdps driver
|
||||
* 3.6 mn 07/06/18 Fix Cppcheck and Doxygen warnings for sdps driver
|
||||
* mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
|
||||
* mn 08/01/18 Add cache invalidation call before returning from
|
||||
* ReadPolled API
|
||||
* mn 08/14/18 Resolve compilation warnings for ARMCC toolchain
|
||||
* mn 10/01/18 Change Expected Response for CMD3 to R1 for MMC
|
||||
* mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
|
||||
* 3.7 mn 02/01/19 Add support for idling of SDIO
|
||||
* aru 03/12/19 Modified the code according to MISRAC-2012.
|
||||
* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
|
||||
* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
|
||||
* 3.9 sd 02/07/20 Added clock support
|
||||
* mn 03/03/20 Restructured the code for more readability and modularity
|
||||
* mn 03/30/20 Return XST_DEVICE_IS_STARTED when host is already started
|
||||
* mn 03/30/20 Move Clock enabling before checking for Host already started
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xsdps_core.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief
|
||||
* Initializes a specific XSdPs instance such that the driver is ready to use.
|
||||
*
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSdPs instance.
|
||||
* @param ConfigPtr is a reference to a structure containing information
|
||||
* about a specific SD device. This function initializes an
|
||||
* InstancePtr object for a specific device specified by the
|
||||
* contents of Config.
|
||||
* @param EffectiveAddr is the device base address in the virtual memory
|
||||
* address space. The caller is responsible for keeping the address
|
||||
* mapping from EffectiveAddr to the device physical base address
|
||||
* unchanged once this function is invoked. Unexpected errors may
|
||||
* occur if the address mapping changes after this function is
|
||||
* called. If address translation is not used, use
|
||||
* ConfigPtr->Config.BaseAddress for this device.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if successful.
|
||||
* - XST_DEVICE_IS_STARTED if the device is already started.
|
||||
* It must be stopped to re-initialize.
|
||||
*
|
||||
* @note This function initializes the host controller.
|
||||
* Initial clock of 400KHz is set.
|
||||
* Voltage of 3.3V is selected as that is supported by host.
|
||||
* Interrupts status is enabled and signal disabled by default.
|
||||
* Default data direction is card to host and
|
||||
* 32 bit ADMA2 is selected. Default Block size is 512 bytes.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
|
||||
u32 EffectiveAddr)
|
||||
{
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(ConfigPtr != NULL);
|
||||
|
||||
#if defined (XCLOCKING)
|
||||
InstancePtr->Config.RefClk = ConfigPtr->RefClk;
|
||||
Xil_ClockEnable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
/* If this API is getting called twice, return value accordingly */
|
||||
if (InstancePtr->IsReady == XIL_COMPONENT_IS_READY) {
|
||||
Status = (s32)XST_DEVICE_IS_STARTED;
|
||||
goto RETURN_PATH ;
|
||||
}
|
||||
|
||||
/* Set some default values. */
|
||||
InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
|
||||
InstancePtr->Config.BaseAddress = EffectiveAddr;
|
||||
InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
|
||||
InstancePtr->Config.CardDetect = ConfigPtr->CardDetect;
|
||||
InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect;
|
||||
InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
|
||||
InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
|
||||
InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
|
||||
InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
|
||||
InstancePtr->SectorCount = 0U;
|
||||
InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
|
||||
InstancePtr->OTapDelay = 0U;
|
||||
InstancePtr->ITapDelay = 0U;
|
||||
InstancePtr->Dma64BitAddr = 0U;
|
||||
InstancePtr->SlcrBaseAddr = XPS_SYS_CTRL_BASEADDR;
|
||||
|
||||
/* Host Controller version is read. */
|
||||
InstancePtr->HC_Version =
|
||||
(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
|
||||
|
||||
/*
|
||||
* Read capabilities register and update it in Instance pointer.
|
||||
* It is sufficient to read this once on power on.
|
||||
*/
|
||||
InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSDPS_CAPS_OFFSET);
|
||||
|
||||
/* Reset the SD bus lines */
|
||||
Status = XSdPs_ResetConfig(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH ;
|
||||
}
|
||||
|
||||
/* Configure the SD Host Controller */
|
||||
XSdPs_HostConfig(InstancePtr);
|
||||
|
||||
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
|
||||
|
||||
RETURN_PATH:
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockDisable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
return Status;
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief
|
||||
* Initialize Card with Identification mode sequence
|
||||
*
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if initialization was successful
|
||||
* - XST_FAILURE if failure - could be because
|
||||
* a) SD is already initialized
|
||||
* b) There is no card inserted
|
||||
* c) One of the steps (commands) in the
|
||||
* initialization cycle failed
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
|
||||
{
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/* Default settings */
|
||||
InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
|
||||
InstancePtr->CardType = XSDPS_CARD_SD;
|
||||
InstancePtr->Switch1v8 = 0U;
|
||||
InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
|
||||
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockEnable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
|
||||
/* Change the clock frequency to 400 KHz */
|
||||
Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH ;
|
||||
}
|
||||
|
||||
/* Identify the Card whether it is SD, MMC or eMMC */
|
||||
Status = XSdPs_IdentifyCard(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
/* Initialize the identified card */
|
||||
if (InstancePtr->CardType == XSDPS_CARD_SD) {
|
||||
Status = XSdPs_SdCardInitialize(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
} else {
|
||||
Status = XSdPs_MmcCardInitialize(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
}
|
||||
|
||||
RETURN_PATH:
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockDisable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief
|
||||
* This function performs SD read in polled mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param Arg is the address passed by the user that is to be sent as
|
||||
* argument along with the command.
|
||||
* @param BlkCnt - Block count passed by the user.
|
||||
* @param Buff - Pointer to the data buffer for a DMA transfer.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if initialization was successful
|
||||
* - XST_FAILURE if failure - could be because another transfer
|
||||
* is in progress or command or data inhibit is set
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
|
||||
{
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockEnable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
|
||||
/* Setup the Read Transfer */
|
||||
Status = XSdPs_SetupTransfer(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
/* Read from the card */
|
||||
Status = XSdPs_Read(InstancePtr, Arg, BlkCnt, Buff);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
RETURN_PATH:
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockDisable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @brief
|
||||
* This function performs SD write in polled mode.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance to be worked on.
|
||||
* @param Arg is the address passed by the user that is to be sent as
|
||||
* argument along with the command.
|
||||
* @param BlkCnt - Block count passed by the user.
|
||||
* @param Buff - Pointer to the data buffer for a DMA transfer.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if initialization was successful
|
||||
* - XST_FAILURE if failure - could be because another transfer
|
||||
* is in progress or command or data inhibit is set
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
|
||||
{
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockEnable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
|
||||
/* Setup the Write Transfer */
|
||||
Status = XSdPs_SetupTransfer(InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
/* Write to the card */
|
||||
Status = XSdPs_Write(InstancePtr, Arg, BlkCnt, Buff);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH;
|
||||
}
|
||||
|
||||
RETURN_PATH:
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockDisable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief
|
||||
* API to idle the SDIO Interface
|
||||
*
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSdPs instance.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSdPs_Idle(XSdPs *InstancePtr)
|
||||
{
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockEnable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
|
||||
/* Check if the bus is idle */
|
||||
Status = XSdPs_CheckBusIdle(InstancePtr, XSDPS_PSR_INHIBIT_CMD_MASK
|
||||
| XSDPS_PSR_INHIBIT_DAT_MASK
|
||||
| XSDPS_PSR_DAT_ACTIVE_MASK);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH ;
|
||||
}
|
||||
|
||||
/* Disable the Bus Power */
|
||||
XSdPs_DisableBusPower(InstancePtr);
|
||||
|
||||
/* Reset Command and Data Lines */
|
||||
Status = XSdPs_Reset(InstancePtr, XSDPS_SWRST_ALL_MASK);
|
||||
if (Status != XST_SUCCESS) {
|
||||
Status = XST_FAILURE;
|
||||
goto RETURN_PATH ;
|
||||
}
|
||||
|
||||
Status = XST_SUCCESS;
|
||||
|
||||
RETURN_PATH:
|
||||
#if defined (XCLOCKING)
|
||||
Xil_ClockDisable(InstancePtr->Config.RefClk);
|
||||
#endif
|
||||
return Status;
|
||||
}
|
||||
/** @} */
|
||||
295
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h
Normal file
295
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h
Normal file
@@ -0,0 +1,295 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xsdps.h
|
||||
* @addtogroup sdps_v3_9
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* This file contains the implementation of XSdPs driver.
|
||||
* This driver is used initialize read from and write to the SD card.
|
||||
* Features such as switching bus width to 4-bit and switching to high speed,
|
||||
* changing clock frequency, block size etc. are supported.
|
||||
* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
|
||||
* is done using 1-bit bus width and 400KHz clock frequency.
|
||||
* SD commands are classified as broadcast and addressed. Commands can be
|
||||
* those with response only (using only command line) or
|
||||
* response + data (using command and data lines).
|
||||
* Only one command can be sent at a time. During a data transfer however,
|
||||
* when dsta lines are in use, certain commands (which use only the command
|
||||
* line) can be sent, most often to obtain status.
|
||||
* This driver does not support multi card slots at present.
|
||||
*
|
||||
* Initialization:
|
||||
* This includes initialization on the host controller side to select
|
||||
* clock frequency, bus power and default transfer related parameters.
|
||||
* The default voltage is 3.3V.
|
||||
* On the SD card side, the initialization and identification state diagram is
|
||||
* implemented. This resets the card, gives it a unique address/ID and
|
||||
* identifies key card related specifications.
|
||||
*
|
||||
* Data transfer:
|
||||
* The SD card is put in transfer state to read from or write to it.
|
||||
* The default block size is 512 bytes and if supported,
|
||||
* default bus width is 4-bit and bus speed is High speed.
|
||||
* The read and write functions are implemented in polled mode using ADMA2.
|
||||
*
|
||||
* At any point, when key parameters such as block size or
|
||||
* clock/speed or bus width are modified, this driver takes care of
|
||||
* maintaining the same selection on host and card.
|
||||
* All error bits in host controller are monitored by the driver and in the
|
||||
* event one of them is set, driver will clear the interrupt status and
|
||||
* communicate failure to the upper layer.
|
||||
*
|
||||
* File system use:
|
||||
* This driver can be used with xilffs library to read and write files to SD.
|
||||
* (Please refer to procedure in diskio.c). The file system read/write example
|
||||
* in polled mode can used for reference.
|
||||
*
|
||||
* There is no example for using SD driver without file system at present.
|
||||
* However, the driver can be used without the file system. The glue layer
|
||||
* in filesystem can be used as reference for the same. The block count
|
||||
* passed to the read/write function in one call is limited by the ADMA2
|
||||
* descriptor table and hence care will have to be taken to call read/write
|
||||
* API's in a loop for large file sizes.
|
||||
*
|
||||
* Interrupt mode is not supported because it offers no improvement when used
|
||||
* with file system.
|
||||
*
|
||||
* eMMC support:
|
||||
* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
|
||||
* The features of eMMC supported by the driver will depend on those supported
|
||||
* by the host controller. The current driver supports read/write on eMMC card
|
||||
* using 4-bit and high speed mode currently.
|
||||
*
|
||||
* Features not supported include - card write protect, password setting,
|
||||
* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
|
||||
* 64-bit addressed ADMA2, erase/pre-erase commands.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- -----------------------------------------------
|
||||
* 1.00a hk/sg 10/17/13 Initial release
|
||||
* 2.0 hk 03/07/14 Version number revised.
|
||||
* 2.1 hk 04/18/14 Increase sleep for eMMC switch command.
|
||||
* Add sleep for microblaze designs. CR# 781117.
|
||||
* 2.2 hk 07/28/14 Make changes to enable use of data cache.
|
||||
* 2.3 sk 09/23/14 Send command for relative card address
|
||||
* when re-initialization is done.CR# 819614.
|
||||
* Use XSdPs_Change_ClkFreq API whenever changing
|
||||
* clock.CR# 816586.
|
||||
* 2.4 sk 12/04/14 Added support for micro SD without
|
||||
* WP/CD. CR# 810655.
|
||||
* Checked for DAT Inhibit mask instead of CMD
|
||||
* Inhibit mask in Cmd Transfer API.
|
||||
* Added Support for SD Card v1.0
|
||||
* 2.5 sg 07/09/15 Added SD 3.0 features
|
||||
* kvn 07/15/15 Modified the code according to MISRAC-2012.
|
||||
* 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601.
|
||||
* 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins.
|
||||
* sk 12/10/15 Added support for MMC cards.
|
||||
* 01/08/16 Added workaround for issue in auto tuning mode
|
||||
* of SDR50, SDR104 and HS200.
|
||||
* sk 02/16/16 Corrected the Tuning logic.
|
||||
* sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311.
|
||||
* 2.8 sk 04/20/16 Added new workaround for auto tuning.
|
||||
* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
|
||||
* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count.
|
||||
* sk 07/16/16 Added support for UHS modes.
|
||||
* sk 07/07/16 Used usleep API for both arm and microblaze.
|
||||
* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC
|
||||
* operating modes.
|
||||
* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
|
||||
* CR#956899.
|
||||
* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags.
|
||||
* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec
|
||||
* sk 10/19/16 Used emmc_hwreset pin to reset eMMC.
|
||||
* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
|
||||
* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value.
|
||||
* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec.
|
||||
* sk 02/01/17 Added HSD and DDR mode support for eMMC.
|
||||
* sk 02/01/17 Consider bus width parameter from design for switching
|
||||
* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
|
||||
* sk 03/20/17 Add support for EL1 non-secure mode.
|
||||
* 3.3 mn 05/17/17 Add support for 64bit DMA addressing
|
||||
* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only
|
||||
* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency
|
||||
* information.
|
||||
* mn 09/06/17 Resolved compilation errors with IAR toolchain
|
||||
* 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor
|
||||
* 3.7 mn 02/01/19 Add support for idling of SDIO
|
||||
* 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal
|
||||
* mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses
|
||||
* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
|
||||
* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
#ifndef SDPS_H_
|
||||
#define SDPS_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "xil_printf.h"
|
||||
#include "xil_cache.h"
|
||||
#include "xstatus.h"
|
||||
#include "xsdps_hw.h"
|
||||
#include "xplatform_info.h"
|
||||
#include "sleep.h"
|
||||
#include <string.h>
|
||||
#if defined (XCLOCKING)
|
||||
#include "xil_clocking.h"
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */
|
||||
#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */
|
||||
#define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */
|
||||
#define XSDPS_CMD8_VOL_PATTERN 0x1AAU
|
||||
#define XSDPS_RESPOCR_READY 0x80000000U
|
||||
#define XSDPS_ACMD41_HCS 0x40000000U
|
||||
#define XSDPS_ACMD41_3V3 0x00300000U
|
||||
#define XSDPS_CMD1_HIGH_VOL 0x00FF8000U
|
||||
#define XSDPS_CMD1_DUAL_VOL 0x00FF8010U
|
||||
#define HIGH_SPEED_SUPPORT 0x2U
|
||||
#define UHS_SDR12_SUPPORT 0x1U
|
||||
#define UHS_SDR25_SUPPORT 0x2U
|
||||
#define UHS_SDR50_SUPPORT 0x4U
|
||||
#define UHS_SDR104_SUPPORT 0x8U
|
||||
#define UHS_DDR50_SUPPORT 0x10U
|
||||
#define WIDTH_4_BIT_SUPPORT 0x4U
|
||||
#define SD_CLK_25_MHZ 25000000U
|
||||
#define SD_CLK_19_MHZ 19000000U
|
||||
#define SD_CLK_26_MHZ 26000000U
|
||||
#define EXT_CSD_DEVICE_TYPE_BYTE 196U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE1 212U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE2 213U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE3 214U
|
||||
#define EXT_CSD_SEC_COUNT_BYTE4 215U
|
||||
#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U
|
||||
#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U
|
||||
#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U
|
||||
#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U
|
||||
#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U
|
||||
#define CSD_SPEC_VER_3 0x3U
|
||||
#define SCR_SPEC_VER_3 0x80U
|
||||
#define ADDRESS_BEYOND_32BIT 0x100000000U
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
typedef struct {
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
u32 BaseAddress; /**< Base address of the device */
|
||||
u32 InputClockHz; /**< Input clock frequency */
|
||||
u32 CardDetect; /**< Card Detect */
|
||||
u32 WriteProtect; /**< Write Protect */
|
||||
u32 BusWidth; /**< Bus Width */
|
||||
u32 BankNumber; /**< MIO Bank selection for SD */
|
||||
u32 HasEMIO; /**< If SD is connected to EMIO */
|
||||
u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */
|
||||
#if defined (XCLOCKING)
|
||||
u32 RefClk; /**< Input clocks */
|
||||
#endif
|
||||
} XSdPs_Config;
|
||||
|
||||
/* ADMA2 32-Bit descriptor table */
|
||||
typedef struct {
|
||||
u16 Attribute; /**< Attributes of descriptor */
|
||||
u16 Length; /**< Length of current dma transfer */
|
||||
u32 Address; /**< Address of current dma transfer */
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment = 32
|
||||
} XSdPs_Adma2Descriptor32;
|
||||
#else
|
||||
} __attribute__((__packed__))XSdPs_Adma2Descriptor32;
|
||||
#endif
|
||||
|
||||
/* ADMA2 64-Bit descriptor table */
|
||||
typedef struct {
|
||||
u16 Attribute; /**< Attributes of descriptor */
|
||||
u16 Length; /**< Length of current dma transfer */
|
||||
u64 Address; /**< Address of current dma transfer */
|
||||
#ifdef __ICCARM__
|
||||
#pragma data_alignment = 32
|
||||
} XSdPs_Adma2Descriptor64;
|
||||
#else
|
||||
} __attribute__((__packed__))XSdPs_Adma2Descriptor64;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* The XSdPs driver instance data. The user is required to allocate a
|
||||
* variable of this type for every SD device in the system. A pointer
|
||||
* to a variable of this type is then passed to the driver API functions.
|
||||
*/
|
||||
typedef struct {
|
||||
XSdPs_Config Config; /**< Configuration structure */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
u32 Host_Caps; /**< Capabilities of host controller */
|
||||
u32 Host_CapsExt; /**< Extended Capabilities */
|
||||
u32 HCS; /**< High capacity support in card */
|
||||
u8 CardType; /**< Type of card - SD/MMC/eMMC */
|
||||
u8 Card_Version; /**< Card version */
|
||||
u8 HC_Version; /**< Host controller version */
|
||||
u8 BusWidth; /**< Current operating bus width */
|
||||
u32 BusSpeed; /**< Current operating bus speed */
|
||||
u8 Switch1v8; /**< 1.8V Switch support */
|
||||
u32 CardID[4]; /**< Card ID Register */
|
||||
u32 RelCardAddr; /**< Relative Card Address */
|
||||
u32 CardSpecData[4]; /**< Card Specific Data Register */
|
||||
u32 SectorCount; /**< Sector Count */
|
||||
u32 SdCardConfig; /**< Sd Card Configuration Register */
|
||||
u32 Mode; /**< Bus Speed Mode */
|
||||
u32 OTapDelay; /**< Output Tap Delay */
|
||||
u32 ITapDelay; /**< Input Tap Delay */
|
||||
u64 Dma64BitAddr; /**< 64 Bit DMA Address */
|
||||
u16 TransferMode; /**< Transfer Mode */
|
||||
u32 SlcrBaseAddr; /**< SLCR base address*/
|
||||
} XSdPs;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
|
||||
s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
|
||||
u32 EffectiveAddr);
|
||||
s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
|
||||
s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
|
||||
s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
|
||||
s32 XSdPs_Idle(XSdPs *InstancePtr);
|
||||
|
||||
s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
|
||||
s32 XSdPs_Pullup(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff);
|
||||
s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
|
||||
s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
|
||||
s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
|
||||
s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
|
||||
s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg);
|
||||
s32 XSdPs_Select_Card(XSdPs *InstancePtr);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SD_H_ */
|
||||
/** @} */
|
||||
1510
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c
Normal file
1510
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,115 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xsdps_include.h
|
||||
* @addtogroup sdps_v3_9
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic HW access driver
|
||||
* functions (or macros) that can be used to access the device. Other driver
|
||||
* functions are defined in xsdps.h.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- -----------------------------------------------
|
||||
* 3.9 mn 03/03/20 Restructured the code for more readability and modularity
|
||||
* mn 03/16/20 Move XSdPs_Select_Card API to User APIs
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef SDPS_INCLUDE_H_
|
||||
#define SDPS_INCLUDE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "xsdps.h"
|
||||
#if defined (__aarch64__)
|
||||
#include "xil_smc.h"
|
||||
#endif
|
||||
|
||||
/** @cond INTERNAL */
|
||||
s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
|
||||
s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
|
||||
s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
|
||||
s32 XSdPs_SetupTransfer(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Read(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
|
||||
s32 XSdPs_Write(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
|
||||
void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
|
||||
s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
|
||||
s32 XSdPs_DllReset(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
|
||||
void XSdPs_SetupADMA2DescTbl64Bit(XSdPs *InstancePtr, u32 BlkCnt);
|
||||
void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
|
||||
void XSdPs_DllRstCtrl(XSdPs *InstancePtr, u8 EnRst);
|
||||
void XSdPs_ConfigTapDelay(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
|
||||
void XSdPs_Setup32ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
|
||||
void XSdPs_Setup64ADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
|
||||
u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
|
||||
void XSdPs_SetTapDelay(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CheckResetDone(XSdPs *InstancePtr, u8 Value);
|
||||
s32 XSdPs_CheckVoltage18(XSdPs *InstancePtr);
|
||||
s32 XSdPs_SetupCmd(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt);
|
||||
void XSdPs_SetExecTuning(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CheckCardDetect(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CardReset(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CardIfCond(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CardOpCond(XSdPs *InstancePtr);
|
||||
s32 XSdPs_GetCardId(XSdPs *InstancePtr);
|
||||
s32 XSdPs_GetCsd(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CardSetVoltage18(XSdPs *InstancePtr);
|
||||
s32 XSdPs_SdModeInit(XSdPs *InstancePtr);
|
||||
s32 XSdPs_SdCardEnum(XSdPs *InstancePtr);
|
||||
s32 XSdPs_MmcCardEnum(XSdPs *InstancePtr);
|
||||
s32 XSdPs_MmcModeInit(XSdPs *InstancePtr);
|
||||
s32 XSdPs_EmmcModeInit(XSdPs *InstancePtr);
|
||||
s32 XSdPs_ResetConfig(XSdPs *InstancePtr);
|
||||
void XSdPs_HostConfig(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Reset(XSdPs *InstancePtr, u8 Value);
|
||||
void XSdPs_DisableBusPower(XSdPs *InstancePtr);
|
||||
void XSdPs_EnableBusPower(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CheckBusIdle(XSdPs *InstancePtr, u32 Value);
|
||||
s32 XSdPs_CheckBusHigh(XSdPs *InstancePtr);
|
||||
s32 XSdPs_SetupVoltageSwitch(XSdPs *InstancePtr);
|
||||
s32 XSdPs_AutoTuning(XSdPs *InstancePtr);
|
||||
s32 XSdPs_SetClock(XSdPs *InstancePtr, u32 SelFreq);
|
||||
u32 XSdPs_CalcClock(XSdPs *InstancePtr, u32 SelFreq);
|
||||
s32 XSdPs_EnableClock(XSdPs *InstancePtr, u16 ClockReg);
|
||||
s32 XSdps_CheckTransferDone(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Change_SdBusSpeed(XSdPs *InstancePtr);
|
||||
s32 XSdPs_Change_MmcBusSpeed(XSdPs *InstancePtr);
|
||||
s32 XSdPs_CalcBusSpeed(XSdPs *InstancePtr, u32 *Arg);
|
||||
void XSdPs_SetupReadDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, u8 *Buff);
|
||||
void XSdPs_SetupWriteDma(XSdPs *InstancePtr, u16 BlkCnt, u16 BlkSize, const u8 *Buff);
|
||||
s32 XSdPs_DoDmaTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
|
||||
s32 XSdPs_DoCmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
|
||||
s32 XSdPs_SetVoltage18(XSdPs *InstancePtr);
|
||||
s32 XSdPs_SendCmd(XSdPs *InstancePtr, u32 Cmd);
|
||||
void XSdPs_IdentifyEmmcMode(XSdPs *InstancePtr, const u8 *ExtCsd);
|
||||
s32 XSdPs_CheckEmmcTiming(XSdPs *InstancePtr, u8 *ExtCsd);
|
||||
void XSdPs_ConfigPower(XSdPs *InstancePtr);
|
||||
void XSdPs_ConfigDma(XSdPs *InstancePtr);
|
||||
void XSdPs_ConfigInterrupt(XSdPs *InstancePtr);
|
||||
|
||||
#if EL1_NONSECURE && defined (__aarch64__)
|
||||
void XSdps_Smc(XSdPs *InstancePtr, u32 RegOffset, u32 Mask, u32 Val);
|
||||
#endif
|
||||
/** @endcond */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by HSI.
|
||||
* Version: 2020.1
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
|
||||
*
|
||||
* Description: Driver configuration
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xsdps.h"
|
||||
|
||||
/*
|
||||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PSU_SD_0_DEVICE_ID,
|
||||
XPAR_PSU_SD_0_BASEADDR,
|
||||
XPAR_PSU_SD_0_SDIO_CLK_FREQ_HZ,
|
||||
XPAR_PSU_SD_0_HAS_CD,
|
||||
XPAR_PSU_SD_0_HAS_WP,
|
||||
XPAR_PSU_SD_0_BUS_WIDTH,
|
||||
XPAR_PSU_SD_0_MIO_BANK,
|
||||
XPAR_PSU_SD_0_HAS_EMIO,
|
||||
XPAR_PSU_SD_0_IS_CACHE_COHERENT
|
||||
},
|
||||
{
|
||||
XPAR_PSU_SD_1_DEVICE_ID,
|
||||
XPAR_PSU_SD_1_BASEADDR,
|
||||
XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
|
||||
XPAR_PSU_SD_1_HAS_CD,
|
||||
XPAR_PSU_SD_1_HAS_WP,
|
||||
XPAR_PSU_SD_1_BUS_WIDTH,
|
||||
XPAR_PSU_SD_1_MIO_BANK,
|
||||
XPAR_PSU_SD_1_HAS_EMIO,
|
||||
XPAR_PSU_SD_1_IS_CACHE_COHERENT
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
1801
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c
Normal file
1801
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c
Normal file
File diff suppressed because it is too large
Load Diff
1323
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h
Normal file
1323
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,75 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xsdps_sinit.c
|
||||
* @addtogroup sdps_v3_9
|
||||
* @{
|
||||
*
|
||||
* The implementation of the XSdPs component's static initialization
|
||||
* functionality.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- --- -------- -----------------------------------------------
|
||||
* 1.00a hk/sg 10/17/13 Initial release
|
||||
* kvn 07/15/15 Modified the code according to MISRAC-2012.
|
||||
* 3.7 aru 03/12/19 Modified the code according to MISRAC-2012.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xstatus.h"
|
||||
#include "xsdps.h"
|
||||
#include "xparameters.h"
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
extern XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES];
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief
|
||||
* Looks up the device configuration based on the unique device ID. A table
|
||||
* contains the configuration info for each device in the system.
|
||||
*
|
||||
* @param DeviceId contains the ID of the device to look up the
|
||||
* configuration for.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* A pointer to the configuration found or NULL if the specified device ID was
|
||||
* not found. See xsdps.h for the definition of XSdPs_Config.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
XSdPs_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
|
||||
if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XSdPs_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
return (XSdPs_Config *)CfgPtr;
|
||||
}
|
||||
/** @} */
|
||||
31
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h
Normal file
31
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h
Normal file
@@ -0,0 +1,31 @@
|
||||
#ifndef XLI_SLEEP_H
|
||||
#define XLI_SLEEP_H
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline void usleep(unsigned long useconds)
|
||||
{
|
||||
rt_uint32_t milliseconds = useconds/1000;
|
||||
useconds = useconds%1000;
|
||||
if (milliseconds) rt_thread_mdelay(milliseconds);
|
||||
if (useconds) rt_hw_us_delay(useconds);
|
||||
}
|
||||
|
||||
static inline void sleep(unsigned int seconds)
|
||||
{
|
||||
rt_thread_delay(seconds);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
21
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h
Normal file
21
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_assert.h
Normal file
@@ -0,0 +1,21 @@
|
||||
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
|
||||
#define XIL_ASSERT_H /* by using protection macros */
|
||||
|
||||
#include "xil_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
#define Xil_AssertNonvoid(Expression) RT_ASSERT(Expression)
|
||||
#define Xil_AssertVoid(Expression) RT_ASSERT(Expression)
|
||||
#define Xil_AssertVoidAlways() RT_ASSERT(0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/**
|
||||
* @} End of "addtogroup common_assert_apis".
|
||||
*/
|
||||
18
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h
Normal file
18
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_cache.h
Normal file
@@ -0,0 +1,18 @@
|
||||
#ifndef XIL_CACHE_H
|
||||
#define XIL_CACHE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define Xil_DCacheFlushRange(addr, size) rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)(addr), (size))
|
||||
#define Xil_DCacheInvalidateRange(addr, size) rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void*)(addr), (size))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/**
|
||||
* @} End of "addtogroup r5_cache_apis".
|
||||
*/
|
||||
204
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h
Normal file
204
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h
Normal file
@@ -0,0 +1,204 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xil_io.h
|
||||
*
|
||||
* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
|
||||
*
|
||||
* The xil_io.h file contains the interface for the general I/O component, which
|
||||
* encapsulates the Input/Output functions for the processors that do not
|
||||
* require any special I/O handling.
|
||||
*
|
||||
* @{
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- -------- -------- -----------------------------------------------
|
||||
* 5.00 pkp 05/29/14 First release
|
||||
* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
|
||||
* ARM processors
|
||||
* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
|
||||
* CR-1049218
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XIL_IO_H /* prevent circular inclusions */
|
||||
#define XIL_IO_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_printf.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
|
||||
#define INLINE inline
|
||||
#else
|
||||
#define INLINE __inline
|
||||
#endif
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an input operation for a memory location by reading
|
||||
* from the specified address and returning the 8 bit Value read from
|
||||
* that address.
|
||||
*
|
||||
* @param Addr: contains the address to perform the input operation
|
||||
*
|
||||
* @return The 8 bit Value read from the specified input address.
|
||||
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE u8 Xil_In8(UINTPTR Addr)
|
||||
{
|
||||
return *(volatile u8 *) Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an input operation for a memory location by reading from
|
||||
* the specified address and returning the 16 bit Value read from that
|
||||
* address.
|
||||
*
|
||||
* @param Addr: contains the address to perform the input operation
|
||||
*
|
||||
* @return The 16 bit Value read from the specified input address.
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE u16 Xil_In16(UINTPTR Addr)
|
||||
{
|
||||
return *(volatile u16 *) Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an input operation for a memory location by
|
||||
* reading from the specified address and returning the 32 bit Value
|
||||
* read from that address.
|
||||
*
|
||||
* @param Addr: contains the address to perform the input operation
|
||||
*
|
||||
* @return The 32 bit Value read from the specified input address.
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE u32 Xil_In32(UINTPTR Addr)
|
||||
{
|
||||
return *(volatile u32 *) Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an input operation for a memory location by reading the
|
||||
* 64 bit Value read from that address.
|
||||
*
|
||||
*
|
||||
* @param Addr: contains the address to perform the input operation
|
||||
*
|
||||
* @return The 64 bit Value read from the specified input address.
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE u64 Xil_In64(UINTPTR Addr)
|
||||
{
|
||||
return *(volatile u64 *) Addr;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an output operation for an memory location by
|
||||
* writing the 8 bit Value to the the specified address.
|
||||
*
|
||||
* @param Addr: contains the address to perform the output operation
|
||||
* @param Value: contains the 8 bit Value to be written at the specified
|
||||
* address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
|
||||
{
|
||||
volatile u8 *LocalAddr = (volatile u8 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an output operation for a memory location by writing the
|
||||
* 16 bit Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* @param Value contains the Value to be written at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
|
||||
{
|
||||
volatile u16 *LocalAddr = (volatile u16 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an output operation for a memory location by writing the
|
||||
* 32 bit Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* @param Value contains the 32 bit Value to be written at the specified
|
||||
* address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
|
||||
{
|
||||
#ifndef ENABLE_SAFETY
|
||||
volatile u32 *LocalAddr = (volatile u32 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
#else
|
||||
XStl_RegUpdate(Addr, Value);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @brief Performs an output operation for a memory location by writing the
|
||||
* 64 bit Value to the the specified address.
|
||||
*
|
||||
* @param Addr contains the address to perform the output operation
|
||||
* @param Value contains 64 bit Value to be written at the specified address.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
|
||||
{
|
||||
volatile u64 *LocalAddr = (volatile u64 *)Addr;
|
||||
*LocalAddr = Value;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/**
|
||||
* @} End of "addtogroup common_io_interfacing_apis".
|
||||
*/
|
||||
16
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h
Normal file
16
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_printf.h
Normal file
@@ -0,0 +1,16 @@
|
||||
#ifndef XIL_PRINTF_H
|
||||
#define XIL_PRINTF_H
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define xil_printf rt_kprintf
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
96
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h
Normal file
96
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h
Normal file
@@ -0,0 +1,96 @@
|
||||
#ifndef XIL_TYPES_H /* prevent circular inclusions */
|
||||
#define XIL_TYPES_H /* by using protection macros */
|
||||
|
||||
#include <rtdef.h>
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
# define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
# define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
|
||||
assigend to "IsReady" member of driver
|
||||
instance to indicate that driver
|
||||
instance is initialized and ready to use. */
|
||||
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
|
||||
"IsStarted" member of driver instance
|
||||
to indicate that driver instance is
|
||||
started and it can be enabled. */
|
||||
|
||||
typedef rt_uint8_t u8;
|
||||
typedef rt_uint16_t u16;
|
||||
typedef rt_uint32_t u32;
|
||||
|
||||
typedef char char8;
|
||||
typedef rt_int8_t s8;
|
||||
typedef rt_int16_t s16;
|
||||
typedef rt_int32_t s32;
|
||||
typedef rt_int64_t s64;
|
||||
typedef rt_uint64_t u64;
|
||||
typedef int sint32;
|
||||
|
||||
typedef intptr_t INTPTR;
|
||||
typedef uintptr_t UINTPTR;
|
||||
typedef ptrdiff_t PTRDIFF;
|
||||
|
||||
|
||||
#if !defined(LONG) || !defined(ULONG)
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
#endif
|
||||
|
||||
/** @{ */
|
||||
/**
|
||||
* This data type defines an interrupt handler for a device.
|
||||
* The argument points to the instance of the component
|
||||
*/
|
||||
typedef void (*XInterruptHandler) (void *InstancePtr);
|
||||
|
||||
/**
|
||||
* This data type defines an exception handler for a processor.
|
||||
* The argument points to the instance of the component
|
||||
*/
|
||||
typedef void (*XExceptionHandler) (void *InstancePtr);
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1U
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0U
|
||||
#endif
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0U
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/**
|
||||
* @} End of "addtogroup common_types".
|
||||
*/
|
||||
1511
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h
Normal file
1511
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h
Normal file
File diff suppressed because it is too large
Load Diff
325
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h
Normal file
325
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h
Normal file
@@ -0,0 +1,325 @@
|
||||
/******************************************************************************
|
||||
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* @file xparameters_ps.h
|
||||
*
|
||||
* @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions
|
||||
*
|
||||
* The xparameters_ps.h file contains the canonical definitions and constant
|
||||
* declarations for peripherals within hardblock, attached to the ARM Cortex R5
|
||||
* core. These definitions can be used by drivers or applications to access the
|
||||
* peripherals.
|
||||
*
|
||||
* @{
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------- -------- ---------------------------------------------------
|
||||
* 5.00 pkp 02/29/14 Initial version
|
||||
* 6.0 mus 08/18/16 Defined ARMR5 flag
|
||||
* 7.2 pm 03/25/20 Add wakeup Interrupt Id for usbpsu controller
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XPARAMETERS_PS_H_
|
||||
#define XPARAMETERS_PS_H_
|
||||
|
||||
#ifndef ARMR5
|
||||
#define ARMR5 ARMR5
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock
|
||||
*/
|
||||
|
||||
/* Canonical definitions for DDR MEMORY */
|
||||
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
|
||||
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
|
||||
|
||||
/* Canonical definitions for Interrupts */
|
||||
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID
|
||||
#define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
|
||||
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
|
||||
#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
|
||||
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
|
||||
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
|
||||
#define XPAR_XWDTPS_0_INTR XPS_CSU_WDT_INT_ID
|
||||
#define XPAR_XWDTPS_1_INTR XPS_LPD_SWDT_INT_ID
|
||||
#define XPAR_XWDTPS_2_INTR XPS_FPD_SWDT_INT_ID
|
||||
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
|
||||
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
|
||||
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
|
||||
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
|
||||
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
|
||||
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
|
||||
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
|
||||
#define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID
|
||||
#define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID
|
||||
#define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID
|
||||
#define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID
|
||||
#define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID
|
||||
#define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID
|
||||
#define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID
|
||||
#define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID
|
||||
#define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID
|
||||
#define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID
|
||||
#define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID
|
||||
#define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID
|
||||
#define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID
|
||||
#define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID
|
||||
#define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID
|
||||
#define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID
|
||||
#define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID
|
||||
#define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID
|
||||
#define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID
|
||||
#define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID
|
||||
#define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID
|
||||
#define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID
|
||||
#define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID
|
||||
#define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID
|
||||
#define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID
|
||||
#define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID
|
||||
#define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID
|
||||
#define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID
|
||||
#define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID
|
||||
#define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID
|
||||
#define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID
|
||||
#define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID
|
||||
#define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID
|
||||
#define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID
|
||||
#define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID
|
||||
#define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID
|
||||
#define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID
|
||||
#define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID
|
||||
#define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID
|
||||
#define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID
|
||||
#define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID
|
||||
#define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID
|
||||
#define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID
|
||||
#define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID
|
||||
#define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID
|
||||
#define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID
|
||||
#define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID
|
||||
#define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID
|
||||
#define XPAR_XUSBPS_1_WAKE_INTR XPS_USB3_1_WAKE_INT_ID
|
||||
#define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID
|
||||
#define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID
|
||||
#define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID
|
||||
#define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID
|
||||
#define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID
|
||||
#define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID
|
||||
#define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID
|
||||
|
||||
/* Canonical definitions for SCU GIC */
|
||||
#define XPAR_SCUGIC_NUM_INSTANCES 1U
|
||||
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
|
||||
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
|
||||
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U)
|
||||
#define XPAR_SCUGIC_ACK_BEFORE 0U
|
||||
|
||||
#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
|
||||
|
||||
|
||||
/*
|
||||
* This block contains constant declarations for the peripherals
|
||||
* within the hardblock. These have been put for bacwards compatibility
|
||||
*/
|
||||
|
||||
#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
|
||||
#define XPS_SCU_PERIPH_BASE 0xF9000000U
|
||||
|
||||
|
||||
/* Shared Peripheral Interrupts (SPI) */
|
||||
#define XPS_FPGA0_INT_ID 121U
|
||||
#define XPS_FPGA1_INT_ID 122U
|
||||
#define XPS_FPGA2_INT_ID 123U
|
||||
#define XPS_FPGA3_INT_ID 124U
|
||||
#define XPS_FPGA4_INT_ID 125U
|
||||
#define XPS_FPGA5_INT_ID 126U
|
||||
#define XPS_FPGA6_INT_ID 127U
|
||||
#define XPS_FPGA7_INT_ID 128U
|
||||
#define XPS_FPGA8_INT_ID 136U
|
||||
#define XPS_FPGA9_INT_ID 137U
|
||||
#define XPS_FPGA10_INT_ID 138U
|
||||
#define XPS_FPGA11_INT_ID 139U
|
||||
#define XPS_FPGA12_INT_ID 140U
|
||||
#define XPS_FPGA13_INT_ID 141U
|
||||
#define XPS_FPGA14_INT_ID 142U
|
||||
#define XPS_FPGA15_INT_ID 143U
|
||||
|
||||
/* Updated Interrupt-IDs */
|
||||
#define XPS_OCMINTR_INT_ID (10U + 32U)
|
||||
#define XPS_NAND_INT_ID (14U + 32U)
|
||||
#define XPS_QSPI_INT_ID (15U + 32U)
|
||||
#define XPS_GPIO_INT_ID (16U + 32U)
|
||||
#define XPS_I2C0_INT_ID (17U + 32U)
|
||||
#define XPS_I2C1_INT_ID (18U + 32U)
|
||||
#define XPS_SPI0_INT_ID (19U + 32U)
|
||||
#define XPS_SPI1_INT_ID (20U + 32U)
|
||||
#define XPS_UART0_INT_ID (21U + 32U)
|
||||
#define XPS_UART1_INT_ID (22U + 32U)
|
||||
#define XPS_CAN0_INT_ID (23U + 32U)
|
||||
#define XPS_CAN1_INT_ID (24U + 32U)
|
||||
#define XPS_RTC_ALARM_INT_ID (26U + 32U)
|
||||
#define XPS_RTC_SEC_INT_ID (27U + 32U)
|
||||
#define XPS_LPD_SWDT_INT_ID (52U + 32U)
|
||||
#define XPS_CSU_WDT_INT_ID (53U + 32U)
|
||||
#define XPS_FPD_SWDT_INT_ID (113U + 32U)
|
||||
#define XPS_TTC0_0_INT_ID (36U + 32U)
|
||||
#define XPS_TTC0_1_INT_ID (37U + 32U)
|
||||
#define XPS_TTC0_2_INT_ID (38U + 32U)
|
||||
#define XPS_TTC1_0_INT_ID (39U + 32U)
|
||||
#define XPS_TTC1_1_INT_ID (40U + 32U)
|
||||
#define XPS_TTC1_2_INT_ID (41U + 32U)
|
||||
#define XPS_TTC2_0_INT_ID (42U + 32U)
|
||||
#define XPS_TTC2_1_INT_ID (43U + 32U)
|
||||
#define XPS_TTC2_2_INT_ID (44U + 32U)
|
||||
#define XPS_TTC3_0_INT_ID (45U + 32U)
|
||||
#define XPS_TTC3_1_INT_ID (46U + 32U)
|
||||
#define XPS_TTC3_2_INT_ID (47U + 32U)
|
||||
#define XPS_SDIO0_INT_ID (48U + 32U)
|
||||
#define XPS_SDIO1_INT_ID (49U + 32U)
|
||||
#define XPS_AMS_INT_ID (56U + 32U)
|
||||
#define XPS_GEM0_INT_ID (57U + 32U)
|
||||
#define XPS_GEM0_WAKE_INT_ID (58U + 32U)
|
||||
#define XPS_GEM1_INT_ID (59U + 32U)
|
||||
#define XPS_GEM1_WAKE_INT_ID (60U + 32U)
|
||||
#define XPS_GEM2_INT_ID (61U + 32U)
|
||||
#define XPS_GEM2_WAKE_INT_ID (62U + 32U)
|
||||
#define XPS_GEM3_INT_ID (63U + 32U)
|
||||
#define XPS_GEM3_WAKE_INT_ID (64U + 32U)
|
||||
#define XPS_USB3_0_ENDPT_INT_ID (65U + 32U)
|
||||
#define XPS_USB3_1_ENDPT_INT_ID (70U + 32U)
|
||||
#define XPS_USB3_0_WAKE_INT_ID (75U + 32U)
|
||||
#define XPS_USB3_1_WAKE_INT_ID (76U + 32U)
|
||||
#define XPS_ADMA_CH0_INT_ID (77U + 32U)
|
||||
#define XPS_ADMA_CH1_INT_ID (78U + 32U)
|
||||
#define XPS_ADMA_CH2_INT_ID (79U + 32U)
|
||||
#define XPS_ADMA_CH3_INT_ID (80U + 32U)
|
||||
#define XPS_ADMA_CH4_INT_ID (81U + 32U)
|
||||
#define XPS_ADMA_CH5_INT_ID (82U + 32U)
|
||||
#define XPS_ADMA_CH6_INT_ID (83U + 32U)
|
||||
#define XPS_ADMA_CH7_INT_ID (84U + 32U)
|
||||
#define XPS_CSU_DMA_INT_ID (86U + 32U)
|
||||
#define XPS_XMPU_LPD_INT_ID (88U + 32U)
|
||||
#define XPS_ZDMA_CH0_INT_ID (124U + 32U)
|
||||
#define XPS_ZDMA_CH1_INT_ID (125U + 32U)
|
||||
#define XPS_ZDMA_CH2_INT_ID (126U + 32U)
|
||||
#define XPS_ZDMA_CH3_INT_ID (127U + 32U)
|
||||
#define XPS_ZDMA_CH4_INT_ID (128U + 32U)
|
||||
#define XPS_ZDMA_CH5_INT_ID (129U + 32U)
|
||||
#define XPS_ZDMA_CH6_INT_ID (130U + 32U)
|
||||
#define XPS_ZDMA_CH7_INT_ID (131U + 32U)
|
||||
#define XPS_XMPU_FPD_INT_ID (134U + 32U)
|
||||
#define XPS_FPD_CCI_INT_ID (154U + 32U)
|
||||
#define XPS_FPD_SMMU_INT_ID (155U + 32U)
|
||||
#define XPS_APM0_INT_ID (123U + 32U)
|
||||
#define XPS_APM1_INT_ID (25U + 32U)
|
||||
#define XPS_APM2_INT_ID (25U + 32U)
|
||||
#define XPS_APM5_INT_ID (123U + 32U)
|
||||
|
||||
/* REDEFINES for TEST APP */
|
||||
#define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID
|
||||
#define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID
|
||||
#define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID
|
||||
#define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID
|
||||
#define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID
|
||||
#define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID
|
||||
#define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID
|
||||
#define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID
|
||||
#define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID
|
||||
#define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID
|
||||
#define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID
|
||||
#define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
|
||||
#define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID
|
||||
#define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID
|
||||
#define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID
|
||||
#define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID
|
||||
#define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID
|
||||
#define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID
|
||||
#define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID
|
||||
#define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID
|
||||
#define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID
|
||||
#define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID
|
||||
#define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID
|
||||
#define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID
|
||||
#define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID
|
||||
#define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID
|
||||
#define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID
|
||||
#define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID
|
||||
#define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID
|
||||
|
||||
#define XPAR_XADCPS_NUM_INSTANCES 1U
|
||||
#define XPAR_XADCPS_0_DEVICE_ID 0U
|
||||
#define XPAR_XADCPS_0_BASEADDR (0xF8007000U)
|
||||
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
|
||||
|
||||
/* For backwards compatibility */
|
||||
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
|
||||
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
|
||||
|
||||
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
|
||||
#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
|
||||
#endif
|
||||
|
||||
#define XPAR_SCUWDT_DEVICE_ID 0U
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* protection macro */
|
||||
/**
|
||||
* @} End of "addtogroup r5_peripheral_definitions".
|
||||
*/
|
||||
@@ -0,0 +1,64 @@
|
||||
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
|
||||
#define XPLATFORM_INFO_H /* by using protection macros */
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (versal)
|
||||
#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
|
||||
#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
|
||||
#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
|
||||
XPAR_PMC_TAP_VERSION_OFFSET)
|
||||
#else
|
||||
#define XPAR_CSU_BASEADDR 0xFFCA0000U
|
||||
#define XPAR_CSU_VER_OFFSET 0x00000044U
|
||||
#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
|
||||
XPAR_CSU_VER_OFFSET)
|
||||
#endif
|
||||
#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
|
||||
#define XPLAT_ZYNQ_ULTRA_MP 0x1
|
||||
#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
|
||||
#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
|
||||
#define XPLAT_ZYNQ 0x4
|
||||
#define XPLAT_MICROBLAZE 0x5
|
||||
#define XPLAT_VERSAL 0x6U
|
||||
|
||||
#define XPS_VERSION_1 0x0
|
||||
#define XPS_VERSION_2 0x1
|
||||
#define XPLAT_INFO_MASK (0xF)
|
||||
|
||||
#if defined (versal)
|
||||
#define XPS_VERSION_INFO_MASK 0xFF00U
|
||||
#define XPS_VERSION_INFO_SHIFT 0x8U
|
||||
#define XPLAT_INFO_SHIFT 0x18U
|
||||
#else
|
||||
#define XPS_VERSION_INFO_MASK (0xF)
|
||||
#define XPS_VERSION_INFO_SHIFT 0x0U
|
||||
#define XPLAT_INFO_SHIFT 0xCU
|
||||
#endif
|
||||
|
||||
static INLINE u32 XGetPlatform_Info()
|
||||
{
|
||||
#if defined (versal)
|
||||
return XPLAT_VERSAL;
|
||||
#elif defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
|
||||
return XPLAT_ZYNQ_ULTRA_MP;
|
||||
#elif (__microblaze__)
|
||||
return XPLAT_MICROBLAZE;
|
||||
#else
|
||||
return XPLAT_ZYNQ;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/**
|
||||
* @} End of "addtogroup common_platform_info".
|
||||
*/
|
||||
513
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h
Normal file
513
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h
Normal file
File diff suppressed because it is too large
Load Diff
76
bsp/zynqmp-r5-axu4ev/drivers/board.c
Normal file
76
bsp/zynqmp-r5-axu4ev/drivers/board.c
Normal file
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-24 WangHuachen the first version
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <dfs_fs.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_timer.h"
|
||||
|
||||
#define ITERS_PER_USEC (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000)
|
||||
void rt_hw_us_delay(rt_uint32_t us)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"push {r0,r1,r3} \n"
|
||||
"mov r0, %[usec] \n"
|
||||
"mov r1, %[iter] \n"
|
||||
"1: \n"
|
||||
"mov r3, r1 \n"
|
||||
"2: \n"
|
||||
"subs r3, r3, #0x1\n"
|
||||
"bne 2b \n"
|
||||
"subs r0, r0, #0x1 \n"
|
||||
"bne 1b \n"
|
||||
"pop {r0,r1,r3} \n"
|
||||
::[iter] "r" (ITERS_PER_USEC), [usec] "r" (us)
|
||||
);
|
||||
}
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
|
||||
#include "drv_uart.h"
|
||||
void rt_hw_serial_putc(const char c)
|
||||
{
|
||||
UART_Registers *uart = (UART_Registers *)XPAR_PSU_UART_0_BASEADDR;
|
||||
if (c == '\n')
|
||||
rt_hw_serial_putc('\r');
|
||||
|
||||
while ((uart->SR) & UART_SR_TXFULL);
|
||||
uart->FIFO = c;
|
||||
}
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
{
|
||||
rt_hw_serial_putc(*str++);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* This function will initialize beaglebone board
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* initialize hardware interrupt */
|
||||
rt_hw_interrupt_init();
|
||||
/* initialize system heap */
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init(HEAP_BEGIN, HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
18
bsp/zynqmp-r5-axu4ev/drivers/board.h
Normal file
18
bsp/zynqmp-r5-axu4ev/drivers/board.h
Normal file
@@ -0,0 +1,18 @@
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "zynqmp-r5.h"
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif defined(__GNUC__)
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void*)&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END (void*)(0x80000000)
|
||||
|
||||
void rt_hw_board_init();
|
||||
|
||||
#endif
|
||||
85
bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c
Normal file
85
bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.c
Normal file
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-27 WangHuachen the first version
|
||||
*/
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include <rthw.h>
|
||||
#include "drv_gpio.h"
|
||||
#include "xgpiops.h"
|
||||
|
||||
#define DBG_TAG "drv.gpio"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include "rtdbg.h"
|
||||
|
||||
#define GPIO_DEVICE_ID XPAR_XGPIOPS_0_DEVICE_ID
|
||||
static XGpioPs Gpio; /* The driver instance for GPIO Device. */
|
||||
|
||||
void xgpiops_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
|
||||
{
|
||||
switch (mode)
|
||||
{
|
||||
case PIN_MODE_OUTPUT:
|
||||
case PIN_MODE_OUTPUT_OD:
|
||||
XGpioPs_SetDirectionPin(&Gpio, pin, 1);
|
||||
XGpioPs_SetOutputEnablePin(&Gpio, pin, 1);
|
||||
break;
|
||||
case PIN_MODE_INPUT:
|
||||
case PIN_MODE_INPUT_PULLUP:
|
||||
case PIN_MODE_INPUT_PULLDOWN:
|
||||
XGpioPs_SetDirectionPin(&Gpio, pin, 0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void xgpiops_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
|
||||
{
|
||||
if (pin >= Gpio.MaxPinNum)
|
||||
return;
|
||||
|
||||
XGpioPs_WritePin(&Gpio, pin, (value == PIN_HIGH)?1:0);
|
||||
}
|
||||
|
||||
int xgpiops_pin_read(rt_device_t dev, rt_base_t pin)
|
||||
{
|
||||
if (pin >= Gpio.MaxPinNum)
|
||||
return 0;
|
||||
|
||||
int DataRead = XGpioPs_ReadPin(&Gpio, pin);
|
||||
return DataRead?PIN_HIGH:PIN_LOW;
|
||||
}
|
||||
|
||||
const static struct rt_pin_ops _xgpiops_pin_ops =
|
||||
{
|
||||
xgpiops_pin_mode,
|
||||
xgpiops_pin_write,
|
||||
xgpiops_pin_read,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
};
|
||||
|
||||
int rt_hw_pin_init(void)
|
||||
{
|
||||
int result;
|
||||
XGpioPs_Config *ConfigPtr;
|
||||
/* Initialize the GPIO driver. */
|
||||
ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
|
||||
|
||||
if (XGpioPs_CfgInitialize(&Gpio, ConfigPtr,
|
||||
ConfigPtr->BaseAddr) == XST_SUCCESS)
|
||||
{
|
||||
result = rt_device_pin_register("pin", &_xgpiops_pin_ops, RT_NULL);
|
||||
return result;
|
||||
}
|
||||
return -RT_ERROR;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
||||
13
bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.h
Normal file
13
bsp/zynqmp-r5-axu4ev/drivers/drv_gpio.h
Normal file
@@ -0,0 +1,13 @@
|
||||
#ifndef __DRV_GPIO_H__
|
||||
#define __DRV_GPIO_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
472
bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c
Normal file
472
bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.c
Normal file
@@ -0,0 +1,472 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-11-24 WangHuachen the first version
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <dfs_fs.h>
|
||||
#include <drivers/mmcsd_core.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "drv_sdcard.h"
|
||||
#include "xsdps_core.h"
|
||||
|
||||
#define DBG_TAG "drv.sdcard"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include "rtdbg.h"
|
||||
|
||||
#define FILE_SYSTEM_INTERFACE_SD
|
||||
#define SD_CD_DELAY 10000U
|
||||
|
||||
typedef rt_uint8_t BYTE;
|
||||
typedef rt_uint32_t DWORD;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* Status of Disk Functions */
|
||||
typedef rt_uint8_t DSTATUS;
|
||||
|
||||
/* Results of Disk Functions */
|
||||
typedef enum
|
||||
{
|
||||
RES_OK = 0, /* 0: Successful */
|
||||
RES_ERROR, /* 1: R/W Error */
|
||||
RES_WRPRT, /* 2: Write Protected */
|
||||
RES_NOTRDY, /* 3: Not Ready */
|
||||
RES_PARERR /* 4: Invalid Parameter */
|
||||
} DRESULT;
|
||||
|
||||
/* Disk Status Bits (DSTATUS) */
|
||||
|
||||
#define STA_NOINIT 0x01 /* Drive not initialized */
|
||||
#define STA_NODISK 0x02 /* No medium in the drive */
|
||||
#define STA_PROTECT 0x04 /* Write protected */
|
||||
|
||||
static DSTATUS Stat[2] = {STA_NOINIT, STA_NOINIT}; /* Disk status */
|
||||
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
static XSdPs SdInstance[2];
|
||||
static u32 BaseAddress;
|
||||
static u32 CardDetect;
|
||||
static u32 WriteProtect;
|
||||
static u32 SlotType[2];
|
||||
static u8 HostCntrlrVer[2];
|
||||
#endif
|
||||
|
||||
static BYTE sdcard_drvnum = 0;
|
||||
static struct rt_device sdcard_device;
|
||||
static struct dfs_partition part;
|
||||
static struct rt_mutex sd_lock[2];
|
||||
|
||||
static DSTATUS disk_status(
|
||||
BYTE pdrv /* Drive number (0) */
|
||||
)
|
||||
{
|
||||
DSTATUS s = Stat[pdrv];
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
u32 StatusReg;
|
||||
u32 DelayCount = 0;
|
||||
|
||||
if (SdInstance[pdrv].Config.BaseAddress == (u32)0)
|
||||
{
|
||||
#ifdef XPAR_XSDPS_1_DEVICE_ID
|
||||
if (pdrv == 1)
|
||||
{
|
||||
BaseAddress = XPAR_XSDPS_1_BASEADDR;
|
||||
CardDetect = XPAR_XSDPS_1_HAS_CD;
|
||||
WriteProtect = XPAR_XSDPS_1_HAS_WP;
|
||||
}
|
||||
else
|
||||
{
|
||||
#endif
|
||||
BaseAddress = XPAR_XSDPS_0_BASEADDR;
|
||||
CardDetect = XPAR_XSDPS_0_HAS_CD;
|
||||
WriteProtect = XPAR_XSDPS_0_HAS_WP;
|
||||
#ifdef XPAR_XSDPS_1_DEVICE_ID
|
||||
}
|
||||
#endif
|
||||
HostCntrlrVer[pdrv] = (u8)(XSdPs_ReadReg16(BaseAddress,
|
||||
XSDPS_HOST_CTRL_VER_OFFSET) &
|
||||
XSDPS_HC_SPEC_VER_MASK);
|
||||
if (HostCntrlrVer[pdrv] == XSDPS_HC_SPEC_V3)
|
||||
{
|
||||
SlotType[pdrv] = XSdPs_ReadReg(BaseAddress,
|
||||
XSDPS_CAPS_OFFSET) &
|
||||
XSDPS_CAPS_SLOT_TYPE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SlotType[pdrv] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* If SD is not powered up then mark it as not initialized */
|
||||
if ((XSdPs_ReadReg8((u32)BaseAddress, XSDPS_POWER_CTRL_OFFSET) &
|
||||
XSDPS_PC_BUS_PWR_MASK) == 0U)
|
||||
{
|
||||
s |= STA_NOINIT;
|
||||
}
|
||||
|
||||
StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress);
|
||||
if (SlotType[pdrv] != XSDPS_CAPS_EMB_SLOT)
|
||||
{
|
||||
if (CardDetect)
|
||||
{
|
||||
while ((StatusReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)
|
||||
{
|
||||
if (DelayCount == 500U)
|
||||
{
|
||||
s = STA_NODISK | STA_NOINIT;
|
||||
goto Label;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Wait for 10 msec */
|
||||
usleep(SD_CD_DELAY);
|
||||
DelayCount++;
|
||||
StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress);
|
||||
}
|
||||
}
|
||||
}
|
||||
s &= ~STA_NODISK;
|
||||
if (WriteProtect)
|
||||
{
|
||||
if ((StatusReg & XSDPS_PSR_WPS_PL_MASK) == 0U)
|
||||
{
|
||||
s |= STA_PROTECT;
|
||||
goto Label;
|
||||
}
|
||||
}
|
||||
s &= ~STA_PROTECT;
|
||||
}
|
||||
else
|
||||
{
|
||||
s &= ~STA_NODISK & ~STA_PROTECT;
|
||||
}
|
||||
|
||||
Label:
|
||||
Stat[pdrv] = s;
|
||||
#endif
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
static DSTATUS disk_initialize(
|
||||
BYTE pdrv /* Physical drive number (0) */
|
||||
)
|
||||
{
|
||||
DSTATUS s;
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
s32 Status = XST_FAILURE;
|
||||
XSdPs_Config *SdConfig;
|
||||
#endif
|
||||
|
||||
s = disk_status(pdrv);
|
||||
if ((s & STA_NODISK) != 0U)
|
||||
{
|
||||
return s;
|
||||
}
|
||||
|
||||
/* If disk is already initialized */
|
||||
if ((s & STA_NOINIT) == 0U)
|
||||
{
|
||||
return s;
|
||||
}
|
||||
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
if (CardDetect)
|
||||
{
|
||||
/*
|
||||
* Card detection check
|
||||
* If the HC detects the No Card State, power will be cleared
|
||||
*/
|
||||
while (!((XSDPS_PSR_CARD_DPL_MASK |
|
||||
XSDPS_PSR_CARD_STABLE_MASK |
|
||||
XSDPS_PSR_CARD_INSRT_MASK) ==
|
||||
(XSdPs_GetPresentStatusReg((u32)BaseAddress) &
|
||||
(XSDPS_PSR_CARD_DPL_MASK |
|
||||
XSDPS_PSR_CARD_STABLE_MASK |
|
||||
XSDPS_PSR_CARD_INSRT_MASK))))
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the host controller
|
||||
*/
|
||||
SdConfig = XSdPs_LookupConfig((u16)pdrv);
|
||||
if (NULL == SdConfig)
|
||||
{
|
||||
s |= STA_NOINIT;
|
||||
return s;
|
||||
}
|
||||
|
||||
Status = XSdPs_CfgInitialize(&SdInstance[pdrv], SdConfig,
|
||||
SdConfig->BaseAddress);
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
s |= STA_NOINIT;
|
||||
return s;
|
||||
}
|
||||
|
||||
Status = XSdPs_CardInitialize(&SdInstance[pdrv]);
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
s |= STA_NOINIT;
|
||||
return s;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disk is initialized.
|
||||
* Store the same in Stat.
|
||||
*/
|
||||
s &= (~STA_NOINIT);
|
||||
|
||||
Stat[pdrv] = s;
|
||||
#endif
|
||||
|
||||
#ifdef FILE_SYSTEM_INTERFACE_RAM
|
||||
/* Assign RAMFS address value from xparameters.h */
|
||||
dataramfs = (char *)RAMFS_START_ADDR;
|
||||
|
||||
/* Clearing No init Status for RAM */
|
||||
s &= (~STA_NOINIT);
|
||||
Stat[pdrv] = s;
|
||||
#endif
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
static DRESULT disk_read(
|
||||
BYTE pdrv, /* Physical drive number (0) */
|
||||
BYTE *buff, /* Pointer to the data buffer to store read data */
|
||||
DWORD sector, /* Start sector number (LBA) */
|
||||
UINT count /* Sector count (1..128) */
|
||||
)
|
||||
{
|
||||
DSTATUS s;
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
s32 Status = XST_FAILURE;
|
||||
DWORD LocSector = sector;
|
||||
#endif
|
||||
|
||||
s = disk_status(pdrv);
|
||||
|
||||
if ((s & STA_NOINIT) != 0U)
|
||||
{
|
||||
return RES_NOTRDY;
|
||||
}
|
||||
if (count == 0U)
|
||||
{
|
||||
return RES_PARERR;
|
||||
}
|
||||
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
/* Convert LBA to byte address if needed */
|
||||
if ((SdInstance[pdrv].HCS) == 0U)
|
||||
{
|
||||
LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK;
|
||||
}
|
||||
|
||||
Status = XSdPs_ReadPolled(&SdInstance[pdrv], (u32)LocSector, count, buff);
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
return RES_ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef FILE_SYSTEM_INTERFACE_RAM
|
||||
memcpy(buff, dataramfs + (sector * SECTORSIZE), count * SECTORSIZE);
|
||||
#endif
|
||||
|
||||
return RES_OK;
|
||||
}
|
||||
|
||||
static DRESULT disk_write(
|
||||
BYTE pdrv, /* Physical drive nmuber (0..) */
|
||||
const BYTE *buff, /* Data to be written */
|
||||
DWORD sector, /* Sector address (LBA) */
|
||||
UINT count /* Number of sectors to write (1..128) */
|
||||
)
|
||||
{
|
||||
DSTATUS s;
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
s32 Status = XST_FAILURE;
|
||||
DWORD LocSector = sector;
|
||||
#endif
|
||||
|
||||
s = disk_status(pdrv);
|
||||
if ((s & STA_NOINIT) != 0U)
|
||||
{
|
||||
return RES_NOTRDY;
|
||||
}
|
||||
if (count == 0U)
|
||||
{
|
||||
return RES_PARERR;
|
||||
}
|
||||
|
||||
#ifdef FILE_SYSTEM_INTERFACE_SD
|
||||
/* Convert LBA to byte address if needed */
|
||||
if ((SdInstance[pdrv].HCS) == 0U)
|
||||
{
|
||||
LocSector *= (DWORD)XSDPS_BLK_SIZE_512_MASK;
|
||||
}
|
||||
|
||||
Status = XSdPs_WritePolled(&SdInstance[pdrv], (u32)LocSector, count, buff);
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
return RES_ERROR;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef FILE_SYSTEM_INTERFACE_RAM
|
||||
memcpy(dataramfs + (sector * SECTORSIZE), buff, count * SECTORSIZE);
|
||||
#endif
|
||||
|
||||
return RES_OK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_sdcard_init(rt_device_t dev)
|
||||
{
|
||||
char sdlock_name[20];
|
||||
BYTE drvnum = *((BYTE *)dev->user_data);
|
||||
|
||||
rt_snprintf(sdlock_name, sizeof(sdlock_name), "sdlock%d", drvnum);
|
||||
if (rt_mutex_init(&sd_lock[drvnum], sdlock_name, RT_IPC_FLAG_FIFO) != RT_EOK)
|
||||
{
|
||||
LOG_E("init sdlock semaphore failed\n");
|
||||
}
|
||||
else
|
||||
LOG_D("sdcard init OK\n");
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_sdcard_close(rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
|
||||
{
|
||||
RT_ASSERT(((rt_uint32_t)buffer % 4) == 0);
|
||||
DRESULT status;
|
||||
BYTE drvnum = *((BYTE *)dev->user_data);
|
||||
|
||||
rt_mutex_take(&sd_lock[drvnum], RT_WAITING_FOREVER);
|
||||
status = disk_read(drvnum, buffer, part.offset + pos, size);
|
||||
rt_mutex_release(&sd_lock[drvnum]);
|
||||
|
||||
if (status == RES_OK)
|
||||
return size;
|
||||
|
||||
LOG_E("sdcard read failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_sdcard_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
|
||||
{
|
||||
RT_ASSERT(((rt_uint32_t)buffer % 4) == 0);
|
||||
DRESULT status;
|
||||
BYTE drvnum = *((BYTE *)dev->user_data);
|
||||
|
||||
rt_mutex_take(&sd_lock[drvnum], RT_WAITING_FOREVER);
|
||||
status = disk_write(drvnum, buffer, part.offset + pos, size);
|
||||
rt_mutex_release(&sd_lock[drvnum]);
|
||||
|
||||
if (status == RES_OK)
|
||||
return size;
|
||||
|
||||
LOG_E("sdcard write failed\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
|
||||
BYTE drvnum = *((BYTE *)dev->user_data);
|
||||
|
||||
if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
|
||||
{
|
||||
struct rt_device_blk_geometry *geometry;
|
||||
|
||||
geometry = (struct rt_device_blk_geometry *)args;
|
||||
if (geometry == RT_NULL)
|
||||
return -RT_ERROR;
|
||||
|
||||
geometry->bytes_per_sector = 512;
|
||||
geometry->block_size = 128;
|
||||
geometry->sector_count = SdInstance[drvnum].SectorCount;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_SD0
|
||||
static int rh_hw_emmc_init(void)
|
||||
{
|
||||
if (disk_initialize(sdcard_drvnum) == RES_OK)
|
||||
{
|
||||
DRESULT status;
|
||||
rt_uint8_t *sector;
|
||||
|
||||
/* get the first sector to read partition table */
|
||||
sector = (rt_uint8_t *)rt_malloc(512);
|
||||
if (sector == RT_NULL)
|
||||
{
|
||||
LOG_E("allocate partition sector buffer failed\n");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
status = disk_read(0, sector, 0, 1);
|
||||
if (status == RES_OK)
|
||||
{
|
||||
/* get the first partition */
|
||||
if (dfs_filesystem_get_partition(&part, sector, 0) != 0)
|
||||
{
|
||||
/* there is no partition */
|
||||
part.offset = 0;
|
||||
part.size = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* there is no partition table */
|
||||
part.offset = 0;
|
||||
part.size = 0;
|
||||
}
|
||||
|
||||
/* release sector buffer */
|
||||
rt_free(sector);
|
||||
|
||||
/* register sdcard device */
|
||||
sdcard_device.type = RT_Device_Class_Block;
|
||||
sdcard_device.init = rt_sdcard_init;
|
||||
sdcard_device.open = rt_sdcard_open;
|
||||
sdcard_device.close = rt_sdcard_close;
|
||||
sdcard_device.read = rt_sdcard_read;
|
||||
sdcard_device.write = rt_sdcard_write;
|
||||
sdcard_device.control = rt_sdcard_control;
|
||||
|
||||
/* no private */
|
||||
sdcard_device.user_data = &sdcard_drvnum;
|
||||
rt_device_register(&sdcard_device, "sd0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
return -RT_ERROR;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rh_hw_emmc_init);
|
||||
#endif
|
||||
13
bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.h
Normal file
13
bsp/zynqmp-r5-axu4ev/drivers/drv_sdcard.h
Normal file
@@ -0,0 +1,13 @@
|
||||
#ifndef __DRV_SDCARD_H__
|
||||
#define __DRV_SDCARD_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
65
bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c
Normal file
65
bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-03-19 WangHuachen the first version
|
||||
*/
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "drv_timer.h"
|
||||
|
||||
#define TTC0_0_BASEADDR XPAR_PSU_TTC_0_BASEADDR
|
||||
#define TTC0_0_CLK_FREQ_HZ XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
|
||||
|
||||
|
||||
static void rt_hw_timer_isr(int vector, void *param)
|
||||
{
|
||||
rt_tick_increase();
|
||||
/* clear interrupt */
|
||||
TTC_ISR(TTC0_0_BASEADDR);
|
||||
}
|
||||
|
||||
static int rt_hw_timer_init(void)
|
||||
{
|
||||
/* Stop timer */
|
||||
TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_DIS_MASK;
|
||||
|
||||
/* Initialize TTC */
|
||||
TTC_CNT_CNTRL(TTC0_0_BASEADDR) = TTC_CNT_CNTRL_RESET_VALUE;
|
||||
TTC_CLK_CNTRL(TTC0_0_BASEADDR) = 0x00;
|
||||
TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = 0x00;
|
||||
TTC_MATCH_0(TTC0_0_BASEADDR) = 0x00;
|
||||
TTC_MATCH_1(TTC0_0_BASEADDR) = 0x00;
|
||||
TTC_MATCH_2(TTC0_0_BASEADDR) = 0x00;
|
||||
TTC_IER(TTC0_0_BASEADDR) = 0x00;
|
||||
TTC_ISR(TTC0_0_BASEADDR) = 0x00;
|
||||
|
||||
/* Reset counter */
|
||||
TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_RST_MASK;
|
||||
|
||||
/* Interval mode select */
|
||||
TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_INT_MASK;
|
||||
/* Setup interval */
|
||||
TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = TTC0_0_CLK_FREQ_HZ / RT_TICK_PER_SECOND;
|
||||
/* Clear all of the prescaler control bits in the register */
|
||||
TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK |
|
||||
TTC_CLK_CNTRL_PS_EN_MASK);
|
||||
/* We do not need a prescaler*/
|
||||
|
||||
/* Register the ticker handler with the GIC */
|
||||
rt_hw_interrupt_install(XPAR_XTTCPS_0_INTR, rt_hw_timer_isr, RT_NULL, "tick");
|
||||
/* Enable TTC interrupts in the GIC */
|
||||
rt_hw_interrupt_umask(XPAR_XTTCPS_0_INTR);
|
||||
/* Enable interval interrupt */
|
||||
TTC_IER(TTC0_0_BASEADDR) |= TTC_IXR_INTERVAL_MASK;
|
||||
/* Start timer */
|
||||
TTC_CNT_CNTRL(TTC0_0_BASEADDR) &=~ TTC_CNT_CNTRL_DIS_MASK;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_timer_init);
|
||||
48
bsp/zynqmp-r5-axu4ev/drivers/drv_timer.h
Normal file
48
bsp/zynqmp-r5-axu4ev/drivers/drv_timer.h
Normal file
@@ -0,0 +1,48 @@
|
||||
#ifndef __DRV_TIMER_H__
|
||||
#define __DRV_TIMER_H__
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define TTC_CLK_CNTRL(hw_base) __REG32(hw_base + 0x00)
|
||||
#define TTC_CLK_CNTRL_PS_EN_MASK 0x00000001 /**< Prescale enable */
|
||||
#define TTC_CLK_CNTRL_PS_VAL_MASK 0x0000001E /**< Prescale value */
|
||||
#define TTC_CLK_CNTRL_PS_VAL_SHIFT 1 /**< Prescale shift */
|
||||
#define TTC_CLK_CNTRL_PS_DISABLE 16 /**< Prescale disable */
|
||||
#define TTC_CLK_CNTRL_SRC_MASK 0x00000020 /**< Clock source */
|
||||
#define TTC_CLK_CNTRL_EXT_EDGE_MASK 0x00000040 /**< External Clock edge */
|
||||
|
||||
#define TTC_CNT_CNTRL(hw_base) __REG32(hw_base + 0x0C)
|
||||
#define TTC_CNT_CNTRL_DIS_MASK 0x00000001 /**< Disable the counter */
|
||||
#define TTC_CNT_CNTRL_INT_MASK 0x00000002 /**< interval mode */
|
||||
#define TTC_CNT_CNTRL_DECR_MASK 0x00000004 /**< Decrement mode */
|
||||
#define TTC_CNT_CNTRL_MATCH_MASK 0x00000008 /**< Match mode */
|
||||
#define TTC_CNT_CNTRL_RST_MASK 0x00000010 /**< Reset counter */
|
||||
#define TTC_CNT_CNTRL_EN_WAVE_MASK 0x00000020 /**< Enable waveform */
|
||||
#define TTC_CNT_CNTRL_POL_WAVE_MASK 0x00000040 /**< Waveform polarity */
|
||||
#define TTC_CNT_CNTRL_RESET_VALUE 0x00000021 /**< Reset value */
|
||||
|
||||
#define TTC_COUNT_VALUE(hw_base) __REG32(hw_base + 0x18)
|
||||
#define TTC_INTERVAL_VAL(hw_base) __REG32(hw_base + 0x24)
|
||||
#define TTC_MATCH_0(hw_base) __REG32(hw_base + 0x30)
|
||||
#define TTC_MATCH_1(hw_base) __REG32(hw_base + 0x3C)
|
||||
#define TTC_MATCH_2(hw_base) __REG32(hw_base + 0x48)
|
||||
|
||||
#define TTC_ISR(hw_base) __REG32(hw_base + 0x54)
|
||||
#define TTC_IXR_INTERVAL_MASK 0x00000001 /**< interval Interrupt */
|
||||
#define TTC_IXR_MATCH_0_MASK 0x00000002 /**< Match 1 Interrupt */
|
||||
#define TTC_IXR_MATCH_1_MASK 0x00000004 /**< Match 2 Interrupt */
|
||||
#define TTC_IXR_MATCH_2_MASK 0x00000008 /**< Match 3 Interrupt */
|
||||
#define TTC_IXR_CNT_OVR_MASK 0x00000010 /**< Counter Overflow */
|
||||
#define TTC_IXR_ALL_MASK 0x0000001F /**< All valid Interrupts */
|
||||
|
||||
#define TTC_IER(hw_base) __REG32(hw_base + 0x60)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
318
bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c
Normal file
318
bsp/zynqmp-r5-axu4ev/drivers/drv_uart.c
Normal file
@@ -0,0 +1,318 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-03-19 WangHuachen the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "gic.h"
|
||||
|
||||
#include "drv_uart.h"
|
||||
|
||||
#define IOU_SLCR_BASE_ADDR XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR
|
||||
#define ZynqMP_IOU_SLCR_MIO_PIN(x) (IOU_SLCR_BASE_ADDR + 0x04 * x)
|
||||
|
||||
#define XUARTPS_MAX_RATE 921600U
|
||||
#define XUARTPS_MIN_RATE 110U
|
||||
#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
|
||||
|
||||
#define ZynqMP_UART_INT_DISABLE(UART) \
|
||||
(UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL))
|
||||
#define ZynqMP_UART_INT_ENABLE(UART) \
|
||||
(UART->IER |= (UART_IXR_RXOVR | UART_IXR_RXFULL))
|
||||
|
||||
#define ZynqMP_UART_SENDCHAR(UART, ch) \
|
||||
do { \
|
||||
while ((UART->SR) & UART_SR_TXFULL); \
|
||||
UART->FIFO = ch; \
|
||||
} while(0)
|
||||
|
||||
#define ZynqMP_UART_GETCHAR(UART, ch) \
|
||||
do { \
|
||||
if (UART->ISR & UART_IXR_RXOVR) \
|
||||
{ \
|
||||
ch = UART->FIFO & 0xff; \
|
||||
UART->ISR = (UART_IXR_RXOVR | UART_IXR_RXFULL); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
static void UartEnable(UART_Registers* uart)
|
||||
{
|
||||
uint32_t tmp = uart->CR;
|
||||
tmp &= ~UART_CR_EN_DIS_MASK;
|
||||
tmp |= (UART_CR_TX_EN | UART_CR_RX_EN);
|
||||
|
||||
uart->CR = tmp;
|
||||
}
|
||||
|
||||
static void UartDisable(UART_Registers* uart)
|
||||
{
|
||||
uint32_t tmp = uart->CR;
|
||||
tmp &= ~UART_CR_EN_DIS_MASK;
|
||||
tmp |= (UART_CR_TX_DIS | UART_CR_RX_DIS);
|
||||
uart->CR = tmp;
|
||||
}
|
||||
|
||||
static void UartResetTXRXLogic(UART_Registers* uart)
|
||||
{
|
||||
uart->CR |= (UART_CR_TXRST | UART_CR_RXRST);
|
||||
while (uart->CR & (UART_CR_TXRST | UART_CR_RXRST));
|
||||
}
|
||||
|
||||
/* UART TxD/RxD | L3 Mux | L2 Mux | L1 Mux */
|
||||
#define RX_MIO_PIN_MODE ((0x6 << 5) | (0x0 << 3) | (0x0 << 2) | (0x0 << 1))
|
||||
#define TX_MIO_PIN_MODE ((0x6 << 5) | (0x0 << 3) | (0x0 << 2) | (0x0 << 1))
|
||||
|
||||
struct hw_uart_device
|
||||
{
|
||||
UART_Registers * uart;
|
||||
rt_uint32_t irqno;
|
||||
rt_uint32_t inputClockHz;
|
||||
|
||||
/* MIO pin mode address */
|
||||
rt_uint32_t *rxmio;
|
||||
rt_uint32_t *txmio;
|
||||
};
|
||||
|
||||
/* RT-Thread UART interface */
|
||||
|
||||
static void rt_hw_uart_isr(int irqno, void *param)
|
||||
{
|
||||
struct rt_serial_device *serial = (struct rt_serial_device *)param;
|
||||
|
||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
|
||||
static rt_err_t XUartPsSetBandRate(struct hw_uart_device *pdev, rt_uint32_t targetBandRate)
|
||||
{
|
||||
rt_uint32_t IterBAUDDIV; /* Iterator for available baud divisor values */
|
||||
rt_uint32_t BRGR_Value; /* Calculated value for baud rate generator */
|
||||
rt_uint32_t CalcBaudRate; /* Calculated baud rate */
|
||||
rt_uint32_t BaudError; /* Diff between calculated and requested baud rate */
|
||||
rt_uint32_t Best_BRGR = 0U; /* Best value for baud rate generator */
|
||||
rt_uint8_t Best_BAUDDIV = 0U; /* Best value for baud divisor */
|
||||
rt_uint32_t Best_Error = 0xFFFFFFFFU;
|
||||
rt_uint32_t PercentError;
|
||||
rt_uint32_t ModeReg;
|
||||
rt_uint32_t InputClk;
|
||||
|
||||
if ((targetBandRate > (rt_uint32_t)XUARTPS_MAX_RATE) ||
|
||||
(targetBandRate < (rt_uint32_t)XUARTPS_MIN_RATE))
|
||||
return -RT_EINVAL;
|
||||
/*
|
||||
* Make sure the baud rate is not impossilby large.
|
||||
* Fastest possible baud rate is Input Clock / 2.
|
||||
*/
|
||||
if ((targetBandRate * 2) > pdev->inputClockHz)
|
||||
return -RT_EINVAL;
|
||||
|
||||
/* Check whether the input clock is divided by 8 */
|
||||
ModeReg = pdev->uart->MR;
|
||||
InputClk = pdev->inputClockHz;
|
||||
if(ModeReg & UART_MR_CLKSEL)
|
||||
InputClk = pdev->inputClockHz / 8;
|
||||
|
||||
/*
|
||||
* Determine the Baud divider. It can be 4to 254.
|
||||
* Loop through all possible combinations
|
||||
*/
|
||||
for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++)
|
||||
{
|
||||
/* Calculate the value for BRGR register */
|
||||
BRGR_Value = InputClk / (targetBandRate * (IterBAUDDIV + 1));
|
||||
|
||||
/* Calculate the baud rate from the BRGR value */
|
||||
CalcBaudRate = InputClk / (BRGR_Value * (IterBAUDDIV + 1));
|
||||
|
||||
/* Avoid unsigned integer underflow */
|
||||
if (targetBandRate > CalcBaudRate)
|
||||
BaudError = targetBandRate - CalcBaudRate;
|
||||
else
|
||||
BaudError = CalcBaudRate - targetBandRate;
|
||||
|
||||
/* Find the calculated baud rate closest to requested baud rate. */
|
||||
if (Best_Error > BaudError)
|
||||
{
|
||||
Best_BRGR = BRGR_Value;
|
||||
Best_BAUDDIV = IterBAUDDIV;
|
||||
Best_Error = BaudError;
|
||||
}
|
||||
}
|
||||
|
||||
/* Make sure the best error is not too large. */
|
||||
PercentError = (Best_Error * 100) / targetBandRate;
|
||||
if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError)
|
||||
return -RT_ERROR;
|
||||
|
||||
pdev->uart->BAUDGEN = Best_BRGR;
|
||||
pdev->uart->BAUDDIV = Best_BAUDDIV;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
uint32_t mr;
|
||||
struct hw_uart_device *pdev = serial->parent.user_data;
|
||||
UART_Registers *uart = pdev->uart;
|
||||
|
||||
UartDisable(uart);
|
||||
UartResetTXRXLogic(uart);
|
||||
UartEnable(uart);
|
||||
|
||||
mr = uart->MR & ~(UART_MR_CHARLEN_MASK |
|
||||
UART_MR_STOPMODE_MASK |
|
||||
UART_MR_PARITY_MASK);
|
||||
|
||||
if (cfg->stop_bits == STOP_BITS_2)
|
||||
mr |= UART_MR_STOPMODE_2_BIT;
|
||||
else if (cfg->stop_bits == STOP_BITS_1)
|
||||
mr |= UART_MR_STOPMODE_1_BIT;
|
||||
else
|
||||
return -RT_EINVAL;
|
||||
|
||||
if (cfg->parity == PARITY_EVEN)
|
||||
mr |= UART_MR_PARITY_EVEN;
|
||||
else if (cfg->parity == PARITY_ODD)
|
||||
mr |= UART_MR_PARITY_ODD;
|
||||
else if (cfg->parity == PARITY_NONE)
|
||||
mr |= UART_MR_PARITY_NONE;
|
||||
else
|
||||
return -RT_EINVAL;
|
||||
|
||||
if (cfg->data_bits == DATA_BITS_8)
|
||||
mr |= UART_MR_CHARLEN_8_BIT;
|
||||
else if (cfg->data_bits == DATA_BITS_7)
|
||||
mr |= UART_MR_CHARLEN_7_BIT;
|
||||
else if (cfg->data_bits == DATA_BITS_6)
|
||||
mr |= UART_MR_CHARLEN_6_BIT;
|
||||
else
|
||||
return -RT_EINVAL;
|
||||
|
||||
uart->MR = mr;
|
||||
|
||||
uart->TXWM = 8;
|
||||
uart->RXWM = 1;
|
||||
|
||||
if (XUartPsSetBandRate(pdev, cfg->baud_rate) != RT_EOK)
|
||||
{
|
||||
rt_kprintf("baudrate %d not implemented yet\n", cfg->baud_rate);
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
/* disable all interrupts */
|
||||
uart->IDR = UART_IXR_MASK;
|
||||
|
||||
/* configure the pin */
|
||||
*(pdev->txmio) = TX_MIO_PIN_MODE;
|
||||
*(pdev->rxmio) = RX_MIO_PIN_MODE;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct hw_uart_device *pdev;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
pdev = serial->parent.user_data;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
ZynqMP_UART_INT_DISABLE(pdev->uart);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
ZynqMP_UART_INT_ENABLE(pdev->uart);
|
||||
rt_hw_interrupt_install(pdev->irqno, rt_hw_uart_isr, serial, serial->parent.parent.name);
|
||||
/* set the interrupt to this cpu */
|
||||
arm_gic_set_cpu(0, pdev->irqno, 1 << rt_cpu_get_smp_id());
|
||||
rt_hw_interrupt_umask(pdev->irqno);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int uart_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct hw_uart_device *dev;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
dev = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
ZynqMP_UART_SENDCHAR(dev->uart, c);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int uart_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch;
|
||||
struct hw_uart_device *dev;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
dev = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
ch = -1;
|
||||
ZynqMP_UART_GETCHAR(dev->uart, ch);
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops _uart_ops =
|
||||
{
|
||||
uart_configure,
|
||||
uart_control,
|
||||
uart_putc,
|
||||
uart_getc,
|
||||
};
|
||||
|
||||
/* UART device driver structure */
|
||||
#ifdef BSP_USING_UART0
|
||||
static struct hw_uart_device _uart_device0 =
|
||||
{
|
||||
.uart = (UART_Registers*)XPAR_PSU_UART_0_BASEADDR,
|
||||
.irqno = XPAR_PSU_UART_0_INTR,
|
||||
.inputClockHz = XPAR_PSU_UART_0_UART_CLK_FREQ_HZ,
|
||||
|
||||
.rxmio = (rt_uint32_t*)ZynqMP_IOU_SLCR_MIO_PIN(42), /* MIO42 */
|
||||
.txmio = (rt_uint32_t*)ZynqMP_IOU_SLCR_MIO_PIN(43), /* MIO43 */
|
||||
};
|
||||
static struct rt_serial_device _serial0;
|
||||
#endif
|
||||
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct serial_configure config;
|
||||
|
||||
config.baud_rate = BAUD_RATE_115200;
|
||||
config.bit_order = BIT_ORDER_LSB;
|
||||
config.data_bits = DATA_BITS_8;
|
||||
config.parity = PARITY_NONE;
|
||||
config.stop_bits = STOP_BITS_1;
|
||||
config.invert = NRZ_NORMAL;
|
||||
config.bufsz = RT_SERIAL_RB_BUFSZ;
|
||||
|
||||
/* register uart device */
|
||||
#ifdef BSP_USING_UART0
|
||||
_serial0.ops = &_uart_ops;
|
||||
_serial0.config = config;
|
||||
rt_hw_serial_register(&_serial0, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
||||
&_uart_device0);
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_uart_init);
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user