stm32wb

bsp/stm32/libraries/HAL_Drivers/SConscript

@@ -82,6 +82,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
 if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32H7']):
     src += ['drv_flash/drv_flash_h7.c']
 
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32WB']):
+    src += ['drv_flash/drv_flash_wb.c']
+
 if GetDepend('RT_USING_HWCRYPTO'):
     src += ['drv_crypto.c']
 

bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+    
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Request = QSPI_DMA_REQUEST,                      \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/spi_config.h

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI1,                                   \
+        .bus_name = "spi1",                                 \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_TX_DMA_RCC,                         \
+        .Instance = SPI1_TX_DMA_INSTANCE,                   \
+        .request = SPI1_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_RX_DMA_RCC,                         \
+        .Instance = SPI1_RX_DMA_INSTANCE,                   \
+        .request = SPI1_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI2,                                   \
+        .bus_name = "spi2",                                 \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_TX_DMA_RCC,                         \
+        .Instance = SPI2_TX_DMA_INSTANCE,                   \
+        .request = SPI2_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_RX_DMA_RCC,                         \
+        .Instance = SPI2_RX_DMA_INSTANCE,                   \
+        .request = SPI2_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI3,                                   \
+        .bus_name = "spi3",                                 \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_TX_DMA_RCC,                         \
+        .Instance = SPI3_TX_DMA_INSTANCE,                   \
+        .request = SPI3_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_RX_DMA_RCC,                         \
+        .Instance = SPI3_RX_DMA_INSTANCE,                   \
+        .request = SPI3_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM15,                    \
+       .tim_irqn                = TIM1_BRK_TIM15_IRQn,      \
+       .name                    = "timer15",                \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM1_UP_TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wb/uart_config.h

@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */  
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .request  = UART1_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif 
+
+#endif

bsp/stm32/libraries/HAL_Drivers/config/wb/usbd_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       		Notes
+ * 2020-10-14     Dozingfiretruck   first version
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_adc.c

@@ -9,7 +9,7 @@
  * 2018-12-12     greedyhao    Porting for stm32f7xx
  * 2019-02-01     yuneizhilin  fix the stm32_adc_init function initialization issue
  * 2020-06-17     thread-liu   Porting for stm32mp1xx
- * 2020-10-09     thread-liu   Porting for stm32h7xx
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #include <board.h>
@@ -52,7 +52,7 @@ static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
 
     if (enabled)
     {
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined (SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
         ADC_Enable(stm32_adc_handler);
 #else
         __HAL_ADC_ENABLE(stm32_adc_handler);
@@ -60,7 +60,7 @@ static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
     }
     else
     {
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined (SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
         ADC_Disable(stm32_adc_handler);
 #else
         __HAL_ADC_DISABLE(stm32_adc_handler);
@@ -205,7 +205,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
-#elif defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
 #elif defined(SOC_SERIES_STM32MP1)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_810CYCLES_5;
@@ -213,11 +213,11 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_64CYCLES_5;
 #endif
 
-#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
     ADC_ChanConf.Offset = 0;
 #endif
 
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
     ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
     ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
 #elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
@@ -228,7 +228,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
 
     /* perform an automatic ADC calibration to improve the conversion accuracy */
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
     if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_ChanConf.SingleDiff) != HAL_OK)
     {
         LOG_E("ADC calibration error!\n");

bsp/stm32/libraries/HAL_Drivers/drv_config.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author            Notes
  * 2018-10-30     SummerGift        first version
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
  
 #ifndef __DRV_CONFIG_H__
@@ -113,6 +114,15 @@ extern "C" {
 #include "mp1/dac_config.h"    
 #include "mp1/tim_config.h"
 #include "mp1/pwm_config.h"    
+#elif  defined(SOC_SERIES_STM32WB)
+#include "wb/adc_config.h"
+#include "wb/dma_config.h"
+#include "wb/pwm_config.h"
+#include "wb/qspi_config.h" 
+#include "wb/spi_config.h"
+#include "wb/tim_config.h"
+#include "wb/uart_config.h"
+#include "wb/usbd_config.h"
 #endif
 
 #ifdef __cplusplus

bsp/stm32/libraries/HAL_Drivers/drv_crypto.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2019-07-10     Ernest       1st version
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #include <rtthread.h>
@@ -28,7 +29,7 @@ struct hash_ctx_des
     CRC_HandleTypeDef contex;
 };
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB)
 static struct hwcrypto_crc_cfg  crc_backup_cfg;
 
 static int reverse_bit(rt_uint32_t n)
@@ -48,12 +49,12 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
     rt_uint32_t result = 0;
     struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
 
-#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB)
     CRC_HandleTypeDef *HW_TypeDef = (CRC_HandleTypeDef *)(ctx->parent.contex);
 #endif
 
     rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB)
     if (memcmp(&crc_backup_cfg, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)) != 0)
     {
         if (HW_TypeDef->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_DISABLE)
@@ -112,7 +113,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
 
     result = HAL_CRC_Accumulate(ctx->parent.contex, (rt_uint32_t *)in, length);
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB)
     if (HW_TypeDef->Init.OutputDataInversionMode)
     {
         ctx ->crc_cfg.last_val = reverse_bit(result);
@@ -194,7 +195,7 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
         }
 
         hcrc->Instance = CRC;
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB)
         hcrc->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE;
         hcrc->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE;
         hcrc->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_BYTE;
@@ -305,7 +306,7 @@ int stm32_hw_crypto_device_init(void)
     _crypto_dev.dev.ops = &_ops;
 #if defined(BSP_USING_UDID)
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32WB)
     cpuid[0] = HAL_GetUIDw0();
     cpuid[1] = HAL_GetUIDw1();
 #elif defined(SOC_SERIES_STM32H7)

bsp/stm32/libraries/HAL_Drivers/drv_dma.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-10     SummerGift   first version
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #ifndef __DRV_DMA_H_
@@ -19,7 +20,7 @@ extern "C" {
 #endif
 
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
-	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
+	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
 	|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
@@ -36,7 +37,7 @@ struct dma_config {
 #endif
 
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
-    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
     rt_uint32_t request;
 #endif
 };

bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c

@@ -8,6 +8,7 @@
  * 2018-12-10     zylx         first version
  * 2020-06-16     thread-liu   Porting for stm32mp1
  * 2020-08-25     linyongkang  Fix the timer clock frequency doubling problem
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #include <board.h>
@@ -210,6 +211,8 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
         if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
 #elif defined(SOC_SERIES_STM32L4)
         if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32WB)
+        if (tim->Instance == TIM16 || tim->Instance == TIM17)
 #elif defined(SOC_SERIES_STM32MP1)
        if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
 #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
@@ -236,7 +239,7 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
             tim->Init.CounterMode   = TIM_COUNTERMODE_DOWN;
         }
         tim->Init.RepetitionCounter = 0;
-#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1)
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
         tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 #endif
         if (HAL_TIM_Base_Init(tim) != HAL_OK)
@@ -338,7 +341,9 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
         if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
 #elif defined(SOC_SERIES_STM32L4)
         if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
-#elif defined(SOC_SERIES_STM32MP1)
+#elif defined(SOC_SERIES_STM32WB)
+        if (tim->Instance == TIM16 || tim->Instance == TIM17)
+			#elif defined(SOC_SERIES_STM32MP1)
        if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)  
 #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         if (0)
@@ -475,7 +480,7 @@ void TIM1_BRK_TIM15_IRQHandler(void)
 }
 #endif
 #ifdef BSP_USING_TIM16
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) 
     void TIM1_UP_TIM16_IRQHandler(void)
 #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1) 
     void TIM16_IRQHandler(void)
@@ -489,7 +494,7 @@ void TIM1_BRK_TIM15_IRQHandler(void)
 }
 #endif
 #ifdef BSP_USING_TIM17
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) 
     void TIM1_TRG_COM_TIM17_IRQHandler(void)
 #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1) 
     void TIM17_IRQHandler(void)

bsp/stm32/libraries/HAL_Drivers/drv_rtc.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date         Author        Notes
  * 2018-12-04   balanceTWK    first version
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #include "board.h"
@@ -101,16 +102,23 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
 
 static void rt_rtc_init(void)
 {
-#ifndef SOC_SERIES_STM32H7
+#if !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32WB)
     __HAL_RCC_PWR_CLK_ENABLE();
 #endif
 
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 #ifdef BSP_RTC_USING_LSI
+#ifdef SOC_SERIES_STM32WB
+RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+    RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+    RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+#else
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
     RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
     RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+#endif
 #else
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
@@ -189,7 +197,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
         RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
         RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
         RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
-#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
 
         /* set the frequency division */
 #ifdef BSP_RTC_USING_LSI

bsp/stm32/libraries/HAL_Drivers/drv_spi.c

@@ -10,6 +10,7 @@
  * 2019-01-03     zylx         modify DMA initialization and spixfer function
  * 2020-01-15     whj4674672   Porting for stm32h7xx
  * 2020-06-18     thread-liu   Porting for stm32mp1xx
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #include <rtthread.h>
@@ -212,7 +213,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
     spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
     spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
     spi_handle->State = HAL_SPI_STATE_RESET;
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32WB)
     spi_handle->Init.NSSPMode          = SPI_NSS_PULSE_DISABLE;
 #elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
     spi_handle->Init.Mode                       = SPI_MODE_MASTER;
@@ -236,7 +237,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
     }
 
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
-        || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0)
+        || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32WB)
     SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
 #endif
 
@@ -419,7 +420,7 @@ static int rt_hw_spi_bus_init(void)
             spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
             spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
-#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1)
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
             spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
 #endif
             spi_bus_obj[i].dma.handle_rx.Init.Direction           = DMA_PERIPH_TO_MEMORY;
@@ -442,7 +443,7 @@ static int rt_hw_spi_bus_init(void)
                 /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
                 SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
                 tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
-#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
                 SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
                 /* Delay after an RCC peripheral clock enabling */
                 tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
@@ -461,7 +462,7 @@ static int rt_hw_spi_bus_init(void)
             spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
             spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
-#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1)
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
             spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
 #endif
             spi_bus_obj[i].dma.handle_tx.Init.Direction           = DMA_MEMORY_TO_PERIPH;
@@ -484,7 +485,7 @@ static int rt_hw_spi_bus_init(void)
                 /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
                 SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
                 tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
-#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
                 SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
                 /* Delay after an RCC peripheral clock enabling */
                 tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);

bsp/stm32/libraries/HAL_Drivers/drv_usart.c

@@ -9,6 +9,7 @@
  * 2020-03-16     SummerGift   add device close feature
  * 2020-03-20     SummerGift   fix bug caused by ORE
  * 2020-05-02     whj4674672   support stm32h7 uart dma
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #include "board.h"
@@ -243,7 +244,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
     UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
     || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
-    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
     uart->handle.Instance->TDR = c;
 #else
     uart->handle.Instance->DR = c;
@@ -264,7 +265,7 @@ static int stm32_getc(struct rt_serial_device *serial)
     {
 #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
     || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
-    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
         ch = uart->handle.Instance->RDR & 0xff;
 #else
         ch = uart->handle.Instance->DR & 0xff;
@@ -367,7 +368,7 @@ static void uart_isr(struct rt_serial_device *serial)
         }
 #if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
     && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
-    && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1)
+    && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
         {
             UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
@@ -866,12 +867,12 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
         tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
 #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \
-    || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7)
+    || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
         tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
 
-#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1)
+#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
         /* enable DMAMUX clock for L4+ and G4 */
         __HAL_RCC_DMAMUX1_CLK_ENABLE();   
 #elif defined(SOC_SERIES_STM32MP1)
@@ -897,7 +898,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
 #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     DMA_Handle->Instance                 = dma_config->Instance;
     DMA_Handle->Init.Channel             = dma_config->channel;
-#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
     || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
     DMA_Handle->Instance                 = dma_config->Instance;
     DMA_Handle->Init.Request             = dma_config->request;

bsp/stm32/libraries/HAL_Drivers/drv_usart.h

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018.10.30     SummerGift   first version
  * 2019.03.05     whj4674672   add stm32h7
+ * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
 #ifndef __DRV_USART_H__
@@ -21,7 +22,7 @@
 int rt_hw_usart_init(void);
 
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) \
-    || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
+    || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
     || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
@@ -30,7 +31,7 @@ int rt_hw_usart_init(void);
 
 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) \
     || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
-    || defined(SOC_SERIES_STM32G4)
+    || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
 #elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
     || defined(SOC_SERIES_STM32MP1)

bsp/stm32/libraries/Kconfig

@@ -60,3 +60,8 @@ config SOC_SERIES_STM32MP1
     bool
     select ARCH_ARM_CORTEX_M4
     select SOC_FAMILY_STM32
+
+config SOC_SERIES_STM32WB
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_STM32

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h

@@ -0,0 +1,174 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32WBxx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32WBxx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32wbxx
+  * @{
+  */
+
+#ifndef __STM32WBxx_H
+#define __STM32WBxx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32WB)
+#define STM32WB
+#endif /* STM32WB */
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32WBxx_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32WBxx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */
+#define __STM32WBxx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32WBxx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32WBxx_CMSIS_DEVICE_VERSION        ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
+                                                |(__STM32WBxx_CMSIS_VERSION_SUB1 << 16)\
+                                                |(__STM32WBxx_CMSIS_VERSION_SUB2 << 8 )\
+                                                |(__STM32WBxx_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32WB55xx)
+  #include "stm32wb55xx.h"
+#elif defined(STM32WB5Mxx)
+  #include "stm32wb5mxx.h"
+#elif defined(STM32WB50xx)
+  #include "stm32wb50xx.h"
+#elif defined(STM32WB35xx)
+  #include "stm32wb35xx.h"
+#elif defined(STM32WB30xx)
+  #include "stm32wb30xx.h"
+#else
+ #error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32wbxx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32WBxx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Include/system_stm32wbxx.h

@@ -0,0 +1,113 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32wbxx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device System Source File for STM32WBxx devices.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32wbxx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32WBXX_H
+#define __SYSTEM_STM32WBXX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#include <stdint.h>
+
+/** @addtogroup STM32WBxx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32WBxx_System_Exported_types
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency */
+
+extern const uint32_t AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint32_t APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[16];    /*!< MSI ranges table values     */
+
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
+extern const uint32_t SmpsPrescalerTable[4][6];  /*!< SMPS factor ranges table values     */
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WBxx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32WBXX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_flash_cm4.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x200327FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb30xx_sram_cm4.icf

@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20038000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2003A7FF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_flash_cm4.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x200327FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb35xx_sram_cm4.icf

@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20003FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20004000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x20007FFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20038000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x2003A7FF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_flash_cm4.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x200327FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb50xx_sram_cm4.icf

@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20007FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20008000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2000FFFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20030000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x20037FFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_flash_cm4.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x200327FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb55xx_sram_cm4.icf

@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20017FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20018000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2002FFFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20030000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x20037FFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_flash_cm4.icf

@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+/***** FLASH Part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000004;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __ICFEDIT_region_RAM_SHARED_start__ = 0x20030000;
+define symbol __ICFEDIT_region_RAM_SHARED_end__   = 0x200327FF;
+
+define memory mem with size = 4G;
+define region ROM_region        = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region        = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM_SHARED_region = mem:[from __ICFEDIT_region_RAM_SHARED_start__   to __ICFEDIT_region_RAM_SHARED_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+/* MB_MEM1 and MB_MEM2 are sections reserved to mailbox communication. It is placed in the shared memory */
+initialize by copy { readwrite };
+do not initialize  { section .noinit,
+                     section MAPPING_TABLE,
+                     section MB_MEM1 };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region        { readonly };
+place in RAM_region        { readwrite,block CSTACK, block HEAP };
+place in RAM_SHARED_region { first section MAPPING_TABLE};
+place in RAM_SHARED_region { section MB_MEM1};
+place in RAM_SHARED_region { section MB_MEM2};

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Device/ST/STM32WBxx/Source/Templates/iar/linker/stm32wb5mxx_sram_cm4.icf

@@ -0,0 +1,39 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20000000;
+/*-Memory Regions-*/
+/***** RAM dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x20017FFF;
+
+define symbol __ICFEDIT_region_RAM_start__  = 0x20018000  ;
+define symbol __ICFEDIT_region_RAM_end__    = 0x2002FFFF ;
+
+/***** RAM2a *****/
+define symbol __ICFEDIT_region_RAM_SHARED_start__  = 0x20030000  ;
+define symbol __ICFEDIT_region_RAM_SHARED_end__    = 0x20037FFF  ;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Include/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/stm32/libraries/STM32WBxx_HAL/CMSIS/Include/tz_context.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

bsp/stm32/libraries/STM32WBxx_HAL/SConscript

@@ -0,0 +1,89 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Split('''
+CMSIS/Device/ST/STM32WBxx/Source/Templates/system_stm32wbxx.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_comp.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_cortex.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_crc.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_crc_ex.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_cryp.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_cryp_ex.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_dma.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_dma_ex.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_exti.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pwr.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pwr_ex.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rcc.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rcc_ex.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rng.c
+STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_gpio.c
+''')
+  
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_uart.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_uart_ex.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_usart.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_usart_ex.c']
+    
+if GetDepend(['RT_USING_I2C']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_i2c.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_i2c_ex.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_spi.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_spi_ex.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_qspi.c']
+
+if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
+#    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_hcd.c'] 
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pcd.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_pcd_ex.c']
+#    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_ll_usb.c']
+
+if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_lptim.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_tim.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_tim_ex.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_adc.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_adc_ex.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rtc.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_rtc_ex.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_iwdg.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_wwdg.c']
+
+if GetDepend(['RT_USING_AUDIO']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_sai.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_sai_ex.c']
+
+if GetDepend(['RT_USING_PM']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_lptim.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_flash.c']
+    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_flash_ex.c']
+#    src += ['STM32WBxx_HAL_Driver/Src/STM32wbxx_hal_flash_ramfunc.c']
+	
+	
+	
+
+path = [cwd + '/STM32WBxx_HAL_Driver/Inc',
+    cwd + '/CMSIS/Device/ST/STM32WBxx/Include',
+    cwd + '/CMSIS/Include']
+
+CPPDEFINES = ['USE_HAL_DRIVER']
+group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/stm32/libraries/STM32WBxx_HAL/STM32WBxx_HAL_Driver/Inc/stm32_assert_template.h

@@ -0,0 +1,57 @@
+/**
+  ******************************************************************************
+  * @file    stm32_assert.h
+  * @author  MCD Application Team
+  * @brief   STM32 assert template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32_assert.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_ASSERT_H
+#define STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_ASSERT_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WBxx_HAL/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_crc_ex.h

@@ -0,0 +1,153 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_crc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBxx_HAL_CRC_EX_H
+#define STM32WBxx_HAL_CRC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal_def.h"
+
+/** @addtogroup STM32WBxx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
+  * @{
+  */
+#define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
+#define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
+#define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
+/**
+  * @}
+  */
+
+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
+  * @{
+  */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Set CRC output reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+
+/**
+  * @brief  Unset CRC output reversal
+  * @param  __HANDLE__ CRC handle
+  * @retval None
+  */
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+
+/**
+  * @brief  Set CRC non-default polynomial
+  * @param  __HANDLE__ CRC handle
+  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+  * @retval None
+  */
+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+  * @{
+  */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CRCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBxx_HAL_CRC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WBxx_HAL/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cryp_ex.h

@@ -0,0 +1,133 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_cryp_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CRYPEx HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBxx_HAL_CRYP_EX_H
+#define STM32WBxx_HAL_CRYP_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal_def.h"
+
+/** @addtogroup STM32WBxx_HAL_Driver
+  * @{
+  */
+
+
+
+/** @defgroup CRYPEx CRYPEx
+  * @brief CRYP Extension HAL module driver.
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
+  * @{
+  */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
+  * @{
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRYPEx_Exported_Functions_Group2
+  * @{
+  */
+void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
+void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBxx_HAL_CRYP_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WBxx_HAL/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash_ex.h

@@ -0,0 +1,115 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBxx_HAL_FLASH_EX_H
+#define STM32WBxx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal_def.h"
+
+/** @addtogroup STM32WBxx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+/** @defgroup FLASHEx_EMPTY_CHECK FLASHEx Empty Check
+  * @{
+  */
+#define FLASH_PROG_NOT_EMPTY            0x00000000U     /*!< 1st location in Flash is programmed */
+#define FLASH_PROG_EMPTY                FLASH_ACR_EMPTY /*!< 1st location in Flash is empty      */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/* Extended Program operation functions  *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+uint32_t          HAL_FLASHEx_FlashEmptyCheck(void);
+void              HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_SuspendOperation(void);
+void              HAL_FLASHEx_AllowOperation(void);
+uint32_t          HAL_FLASHEx_IsOperationSuspended(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
+  *  @{
+  */
+#define IS_FLASH_EMPTY_CHECK(__VALUE__)     (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+  * @{
+  */
+void              FLASH_PageErase(uint32_t Page);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBxx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WBxx_HAL/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c_ex.h

@@ -0,0 +1,159 @@
+/**
+  ******************************************************************************
+  * @file    stm32wbxx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32WBxx_HAL_I2C_EX_H
+#define STM32WBxx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32wbxx_hal_def.h"
+
+/** @addtogroup STM32WBxx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         0x00000000U
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
+  * @{
+  */
+#define I2C_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C3           (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported  */
+#endif
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
+                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
+                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
+                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
+                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
+                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
+
+
+
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32wbxx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32WBxx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/