Merge pull request #1540 from flyingcys/dev_wifi

add amebaz bsp
This commit is contained in:
Bernard Xiong authored and GitHub committed 2018-06-14 11:09:11 +08:00
commit ae1eb1d628
32 files changed
+17902

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mainmenu "RT-Thread Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config $ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "$ENV_DIR/tools/scripts/cmds/Kconfig"
config RT_USING_UART0
bool "Using RT_USING_UART0"
default y
select PKG_USING_REALTEK_AMEBA
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# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)
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import rtconfig
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd, str(Dir('#'))]
src = Glob('*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
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/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-08-31 Bernard first implementation
* 2018-03-01 flyingcys add realtek ameba
*/
#include <rthw.h>
#include <rtthread.h>
/**
* @addtogroup ameba
*/
/*@{*/
int main(void)
{
rt_kprintf("build time: %s %s\n", __DATE__, __TIME__);
rt_kprintf("Hello RT-Thread!\n");
return 0;
}
/*@}*/
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/* Bootloader symbol list */
define exported symbol BOOT_FLASH_RDP_VALID = 0x08000123;
define exported symbol BOOT_FLASH_SetStatusReg = 0x080003f5;
define exported symbol BOOT_FLASH_Image1 = 0x0800043b;
define exported symbol IMAGE1$$Base = 0x10002001;
define exported symbol RamStartTable = 0x10002001;
define exported symbol RAM_IMG1_VALID_PATTEN = 0x10002019;
define exported symbol boot_export_symbol = 0x10002021;
define exported symbol BOOT_System_Init1 = 0x10002251;
define exported symbol BOOT_System_Init2 = 0x10002263;
define exported symbol BOOT_Swd_Off = 0x10002275;
define exported symbol boot_ram_end = 0x10002455;
define exported symbol IMAGE1$$Limit = 0x10002459;
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from building import *
cwd = GetCurrentDir()
list = os.listdir(cwd)
objs = []
src = Split('''
board.c
drv_uart.c
''')
if GetDepend(['RT_USING_LWIP']):
src += Split('''
drv_wifi.c
''')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
objs = objs + group
Return('objs')
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/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2018-03-15 flyingcys add amebaz
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
#ifdef __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#elif defined(__GNUC__)
extern int __rtt_heap_start;
#define HEAP_BEGIN (&__rtt_heap_start)
#else
#error "not support toolchain!!!"
#endif
#define HEAP_END (0x1002FFFF)
#ifdef __GNUC__
void __wrap_rtl_printf(const char *fmt, ...)
{
va_list args;
rt_size_t length;
static char rt_log_buf[RT_CONSOLEBUF_SIZE];
va_start(args, fmt);
/* the return value of vsnprintf is the number of bytes that would be
* written to buffer had if the size of the buffer been sufficiently
* large excluding the terminating null byte. If the output string
* would be larger than the rt_log_buf, we have to adjust the output
* length. */
length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args);
if (length > RT_CONSOLEBUF_SIZE - 1)
length = RT_CONSOLEBUF_SIZE - 1;
rt_kprintf("%s", rt_log_buf);
va_end(args);
}
#endif
/**
* This is the timer interrupt service routine.
*
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
/**
* This function will initial board.
*/
void rt_hw_board_init(void)
{
extern uint32_t SystemCoreClock;
SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND);
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
/*@}*/
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
* 2018-03-15 flyingcys add amebaz
*/
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef __BOARD_H__
#define __BOARD_H__
#include "rtl8710b.h"
void rt_hw_board_init(void);
#endif
//*** <<< end of configuration section >>> ***
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/*
* File : drv_uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-05-30 Bernard the first version
* 2018-03-15 flyingcys add amebaz
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#include "ameba_soc.h"
#include "serial_api.h"
#if defined(CONFIG_PLATFORM_8711B)
// 8710B
#define UART_TX PA_23
#define UART_RX PA_18
#else
// 8711AM
#define UART_TX PA_7
#define UART_RX PA_6
//8711AF
//#define UART_TX PA_4
//#define UART_RX PA_0
#endif
int rt_hw_uart_init(void);
#endif /* __DRV_UART_H__ */
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/*
* File : drv_wifi.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef __DRV_WIFI_H__
#define __DRV_WIFI_H__
int rt_hw_wifi_init(void);
#endif /* __DRV_WIFI_H__ */
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import rtconfig
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd, str(Dir('#'))]
src = []
if GetDepend(['RT_USING_LWIP']):
src += Split('''
amebaz_wlan.c
''')
group = DefineGroup('amebaz_wlan', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
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/*
* File : amebaz_wlan.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
* 2018-6-12 flyingcys add amebaz wlan interface
*/
#ifndef __AMEBAZ_WLAN_H__
#define __AMEBAZ_WLAN_H__
int amebaz_wifi_scan();
void amebaz_wifi_info_init(void);
int amebaz_wifi_set_sta_info(char *ssid, char *passwd);
int amebaz_wifi_set_ap_info(char *ssid, char *passwd);
int amebaz_wifi_connect(char *ssid, char *passwd);
int amebaz_wifi_disconnect(void);
int amebaz_wifi_ap_start(char *ssid, char *passwd, int channel);
int amebaz_wifi_ap_stop(void);
int amebaz_wifi_get_rssi(void);
void amebaz_wifi_set_channel(int channel);
int amebaz_wifi_get_channel(void);
int amebaz_wifi_init(rt_wlan_mode_t mode);
#endif /* __AMEBAZ_WLAN_H__ */
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import re
import subprocess
import os
import platform
tool_pwd=os.path.normpath(os.getcwd()+r'/packages/realtek_ameba/sdk-ameba-v4.0b_without_NDA_GCC_V1.0.0/component/soc/realtek/8711b/misc/iar_utility/common/tools')
def grep_func(file,str):
fd=open(file,'r')
strtmp=r'^[0-9]{8}\s[a-zA-Z]{1}\s%s$' % str
for line in fd.readlines():
if re.match(strtmp,line):
#print(line)
value=re.split(r'[\s+]+',line)
fd.close()
return value[0]
fd.close()
#=====================start=======================
os.system(r'arm-none-eabi-objdump -d rtthread.axf > application.asm')
os.system(r'arm-none-eabi-size rtthread.axf')
os.system(r'arm-none-eabi-nm rtthread.axf | sort > application.nmap')
#====================process=====================
addr1=grep_func(r'application.nmap','__ram_image2_text_start__')
addr2=grep_func(r'application.nmap','__ram_image2_text_end__')
addr3=grep_func(r'application.nmap','__ram_image2_text_start__')
addr4=grep_func(r'application.nmap','__ram_image2_text_end__')
addr5=grep_func(r'application.nmap','__xip_image2_start__')
addr6=grep_func(r'application.nmap','__xip_image2_start__')
sysstr = platform.system()
print(sysstr)
if(sysstr == "Linux"):
exec_pick = tool_pwd + r'/pick'
exec_checksum = tool_pwd + r'/checksum'
os.system('chmod +x ' + exec_pick)
os.system('chmod +x ' + exec_checksum)
#print(exec_pick)
elif(sysstr == "Windows"):
exec_pick=tool_pwd+r'/pick.exe'
exec_checksum = tool_pwd + r'/checksum.exe'
#print(exec_pick)
else:
print("not support!!!")
exec_pick_param1=r' 0x%s 0x%s ram_2.r.bin ram_2.bin raw' % (addr1,addr2)
exec_pick_param2=r' 0x%s 0x%s ram_2.bin ram_2.p.bin' % (addr3,addr4)
exec_pick_param3=r' 0x%s 0x%s xip_image2.bin xip_image2.p.bin' % (addr5,addr6)
#print(exec_pick_param1)
#print(exec_pick_param2)
#print(exec_pick_param3)
exec_cmd1=exec_pick+exec_pick_param1
exec_cmd2=exec_pick+exec_pick_param2
exec_cmd3=exec_pick+exec_pick_param3
#print(exec_cmd1)
#print(exec_cmd2)
#print(exec_cmd3)
os.system(exec_cmd1)
os.system(exec_cmd2)
os.system(exec_cmd3)
#================create bin file================
if os.path.exists('image2_all_ota1.bin'):
os.remove('image2_all_ota1.bin')
with open('xip_image2.p.bin','rb') as src:
with open('image2_all_ota1.bin', 'wb') as dst:
dst.write(src.read())
with open('ram_2.p.bin','rb') as src:
with open('image2_all_ota1.bin', 'ab') as dst:
dst.write(src.read())
exec_cmd4 = exec_checksum + ' image2_all_ota1.bin || true'
os.system(exec_cmd4)
os.remove("ram_2.bin")
os.remove("ram_2.p.bin")
os.remove("ram_2.r.bin")
os.remove("xip_image2.bin")
os.remove("xip_image2.p.bin")
os.remove("rdp.bin")
print("Done...")
#=====================end=======================
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/**/
/**/
include "rom_symbol_v01_iar.icf";
/****************************************
* Memory Regions *
****************************************/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_ROMBSS_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_ROMBSS_RAM_end__ = 0x10001FFF;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_start__ = 0x10002000;
define symbol __ICFEDIT_region_BOOTLOADER_RAM_end__ = 0x10004FFF;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10005000;
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1002FFFF;
define symbol __ICFEDIT_region_MSP_RAM_start__ = 0x1003E000;
define symbol __ICFEDIT_region_MSP_RAM_end__ = 0x1003EFFF;
define symbol __ICFEDIT_region_RDP_RAM_start__ = 0x1003F000;
define symbol __ICFEDIT_region_RDP_RAM_end__ = 0x1003FFEF;
define symbol __ICFEDIT_region_IMG2_TEMP_start__ = 0x10006000;
define symbol __ICFEDIT_region_IMG2_TEMP_end__ = 0x1000BFFF;
define symbol __ICFEDIT_region_XIP_BOOT_start__ = 0x08000000+0x20;
define symbol __ICFEDIT_region_XIP_BOOT_end__ = 0x08003FFF;
define symbol __ICFEDIT_region_XIP_OTA1_start__ = 0x0800B000+0x20;
define symbol __ICFEDIT_region_XIP_OTA1_end__ = 0x080FFFFF;
/****************************************
* Sizes *
****************************************/
/*define symbol __ICFEDIT_size_cstack__ = 0x400;*/
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region ROM_BSS_region = mem:[from __ICFEDIT_region_ROMBSS_RAM_start__ to __ICFEDIT_region_ROMBSS_RAM_end__];
define region BOOT_RAM_region = mem:[from __ICFEDIT_region_BOOTLOADER_RAM_start__ to __ICFEDIT_region_BOOTLOADER_RAM_end__];
define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
define region IMG2_TEMP_region = mem:[from __ICFEDIT_region_IMG2_TEMP_start__ to __ICFEDIT_region_IMG2_TEMP_end__];
define region XIP_BOOT_region = mem:[from __ICFEDIT_region_XIP_BOOT_start__ to __ICFEDIT_region_XIP_BOOT_end__];
define region XIP_OTA1_region = mem:[from __ICFEDIT_region_XIP_OTA1_start__ to __ICFEDIT_region_XIP_OTA1_end__];
define region RDP_RAM_region = mem:[from __ICFEDIT_region_RDP_RAM_start__ to __ICFEDIT_region_RDP_RAM_end__];
/*define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };*/
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
//initialize by copy { readwrite };
//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
//do not initialize { section * };
//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
//
/****************************************
* ROM Section config *
****************************************/
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
keep { section .rom.text };
keep { section .rom.rodata };
place at start of ROM_region { readonly, section .rom.text, section .rom.rodata};
/****************************************
* ROM BSS Section config *
****************************************/
keep { section .ram_vector_table1 };
keep { section .ram_vector_table2 };
keep { section .ram_vector_table3 };
keep { section .hal.rom.bss* };
keep { section .wlan_ram_map* };
keep { section .libc.ram.bss* };
keep { section .ssl_ram_map* };
define block .hal.rom.bss with fixed order{ section .ram_vector_table1,
section .ram_vector_table2,
section .ram_vector_table3,
section .hal.rom.bss*,
section .wlan_ram_map*,
section .libc.ram.bss*,
section .ssl_ram_map*,
};
define block ROM_BSS with fixed order { block .hal.rom.bss};
place at start of ROM_BSS_region { readwrite,
block ROM_BSS,
};
/****************************************
* BOOT RAM Section config *
****************************************/
keep { section .image1.entry.data* };
keep { section .image1.validate.rodata* };
define block .ram_image1.entry with fixed order{section .image1.entry.data*,
section .image1.validate.rodata*,
};
keep { section .boot.ram.text* };
keep { section .boot.rodata* };
define block .ram_image1.text with fixed order{section .boot.ram.text*,
section .boot.rodata*,
};
keep { section .boot.ram.data* };
define block .ram_image1.data with fixed order{section .boot.ram.data*,
};
keep { section .boot.ram.bss* };
define block .ram_image1.bss with fixed order{section .boot.ram.bss*,
};
define block IMAGE1 with fixed order { block .ram_image1.entry, block .ram_image1.text, block .ram_image1.data, block .ram_image1.bss};
place at start of BOOT_RAM_region { readwrite,
block IMAGE1,
};
/****************************************
* BD RAM Section config *
****************************************/
keep { section .image2.entry.data* };
keep { section .image2.validate.rodata* };
define block .ram_image2.entry with fixed order{ section .image2.entry.data*,
section .image2.validate.rodata*,
};
define block SHT$$PREINIT_ARRAY { preinit_array };
define block SHT$$INIT_ARRAY { init_array };
define block CPP_INIT with fixed order { block SHT$$PREINIT_ARRAY,
block SHT$$INIT_ARRAY };
define block .ram.data with fixed order{ section .data*,
section DATA,
section .iar.init_table,
section __DLIB_PERTHREAD,
block CPP_INIT,
section .mdns.data,
section .mdns.text
};
define block .ram.text with fixed order{ section .image2.ram.text*,
};
define block IMAGE2 with fixed order { block .ram_image2.entry,
block .ram.data,
block .ram.text,
};
define block .ram_image2.bss with fixed order{ section .bss*,
section COMMON,
};
define block .ram_image2.skb.bss with fixed order{ section .bdsram.data* };
define block .ram_heap.data with fixed order{ section .bfsram.data* };
place in BD_RAM_region { readwrite,
block IMAGE2,
block .ram_image2.bss,
block .ram_image2.skb.bss,
block .ram_heap.data,
section .heap.stdlib,
last block HEAP,
};
/****************************************
* XIP BOOT Section config *
****************************************/
keep { section .flashboot.text* };
define block .xip_image1.text with fixed order{ section .flashboot.text* };
define block Bootloader with fixed order { section LOADER };
place at start of XIP_BOOT_region { block Bootloader,
readwrite,
block .xip_image1.text };
/****************************************
* XIP OTA1 Section config *
****************************************/
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
define block .xip_image2.text with fixed order{ section .img2_custom_signature*,
section .text*,
section .rodata*,
section .debug_trace,
section CODE,
section Veneer, // object startup.o,
section FSymTab,
section VSymTab,
section .rti_fn*,
};
place at start of XIP_OTA1_region { readwrite,
block .xip_image2.text };
/****************************************
* RDP Section config *
****************************************/
keep { section .rdp.ram.text* };
keep { section .rdp.ram.data* };
define block .RDP_RAM with fixed order {
section .rdp.ram.text*,
section .rdp.ram.data* };
place at start of RDP_RAM_region{
readwrite,
block .RDP_RAM };
define exported symbol __ram_start_table_start__= 0x10002000; // use in rom
define exported symbol __image1_validate_code__= 0x10002018; // needed by ram code
define exported symbol __rom_top_4k_start_= 0x1003F000; // needed by ram code
define exported symbol __flash_text_start__= 0x0800b020; // needed by ram code
define exported symbol boot_export_symbol = 0x10002020;
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>
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ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
*(.heap.stdlib*)
. = ALIGN(4);
__rtt_heap_start = .;
} > BD_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text*)
*(.rodata*)
*(.debug_trace*)
__flash_text_end__ = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN (16);
} > XIP1
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}
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ENTRY(Reset_Handler)
INCLUDE "export-rom_symbol_v01.txt"
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x2B000 /* MAIN RAM: 228 */
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 32k, 32 Bytes resvd for header*/
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
}
SECTIONS
{
.rom.text : { } > ROM
.rom.rodata : { } > ROM
.hal.rom.bss : { } > ROMBSS_RAM
/* image1 entry, this section should in RAM and fixed address for ROM */
.ram_image1.entry :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.image1.entry.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.image1.export.symb*))
} > BOOTLOADER_RAM
/* Add . to assign the start address of the section */
/* to prevent the change of the start address by ld doing section alignment */
.ram_image1.text . :
{
/* image1 text */
*(.boot.ram.text*)
*(.boot.rodata*)
} > BOOTLOADER_RAM
.ram_image1.data . :
{
__ram_image1_data_start__ = .;
KEEP(*(.boot.ram.data*))
__ram_image1_data_end__ = .;
__ram_image1_text_end__ = .;
} > BOOTLOADER_RAM
.ram_image1.bss . :
{
__image1_bss_start__ = .;
KEEP(*(.boot.ram.bss*))
KEEP(*(.boot.ram.end.bss*))
__image1_bss_end__ = .;
} > BOOTLOADER_RAM
.ram_image2.entry :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
KEEP(*(SORT(.image2.entry.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.image2.ram.text*))
} > BD_RAM
.ram_image2.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
. = ALIGN(16);
} > BD_RAM
.ram_image2.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
} > BD_RAM
.ram_image2.skb.bss :
{
*(.bdsram.data*)
__bss_end__ = .;
} > BD_RAM
.ram_heap.data :
{
*(.bfsram.data*)
*(.heap.stdlib*)
. = ALIGN(4);
__rtt_heap_start = .;
} > BD_RAM
.ram_rdp.text :
{
__rom_top_4k_start_ = .;
__rdp_text_start__ = .;
KEEP(*(.rdp.ram.text*))
KEEP(*(.rdp.ram.data*))
__rdp_text_end__ = .;
. = ALIGN(16);
} > RDP_RAM
.xip_image1.text :
{
__flash_boot_text_start__ = .;
*(.flashboot.text*)
__flash_boot_text_end__ = .;
. = ALIGN(16);
} > XIPBOOT
.xip_image2.text :
{
__flash_text_start__ = .;
*(.img2_custom_signature*)
*(.text*)
*(.rodata*)
*(.debug_trace*)
__flash_text_end__ = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN (16);
} > XIP2
}
SECTIONS
{
/* Bootloader symbol list */
boot_export_symbol = 0x10002020;
}
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_DEBUG
#define RT_USING_OVERFLOW_CHECK
#define RT_DEBUG_INIT 0
#define RT_DEBUG_THREAD 0
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "dbg"
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SERIAL
#define RT_USING_PIN
#define RT_USING_WIFI
#define RT_USING_WLAN_STA
#define RT_USING_WLAN_AP
#define WIFI_DEVICE_STA_NAME "w0"
#define WIFI_DEVICE_AP_NAME "ap"
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
/* Network stack */
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP141
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_NETIF_LOOPBACK 0
/* Modbus master and slave stack */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
#define PKG_USING_REALTEK_AMEBA
#define PKG_USING_REALTEK_AMEBA_LATEST_VERSION
/* miscellaneous packages */
/* sample package */
/* example package: hello */
/* Env config */
#define RT_USING_UART0
#endif
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import os
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin'
else:
print 'Please make sure your toolchains is GNU GCC!'
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'axf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
NM = PREFIX + 'nm'
DEVICE = ' -DM3 -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -g2 -w -O2 -Wno-pointer-sign -fno-common -fmessage-length=0 -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-short-enums -DF_CPU=166000000L -std=gnu99 -fsigned-char'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -g --specs=nano.specs -nostartfiles -Wl,-Map=rtthread.map -Os -Wl,--gc-sections -Wl,--cref -Wl,--entry=Reset_Handler -Wl,--no-enum-size-warning -Wl,--no-wchar-size-warning -T./rlx8711B-symbol-v02-img2_xip1.ld'
LFLAGS += ' -Wl,-wrap,rtl_printf'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -j .ram_image2.entry -j .ram_image2.data -j .ram_image2.bss -j .ram_image2.skb.bss -j .ram_heap.data -Obinary rtthread.axf ram_2.r.bin \n' \
+ OBJCPY + ' -j .xip_image2.text -Obinary rtthread.axf xip_image2.bin \n' \
+ OBJCPY + ' -j .ram_rdp.text -Obinary rtthread.axf rdp.bin \n'
POST_ACTION += 'python gen_bin.py'
M_CFLAGS = CFLAGS + ' -mlong-calls -Dsourcerygxx -O0 -fPIC '
M_LFLAGS = DEVICE + ' -Wl,-z,max-page-size=0x4 -shared -fPIC -e main -nostdlib'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu=cortex-m4.fp'
CFLAGS = DEVICE + ' --apcs=interwork -DSTM32F429_439xx'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32f429_flash.sct'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu None'
LFLAGS = ' --config stm32f429_flash.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = ''
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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<range>CODE 0x8000000 0x8004fff</range>
<loader>$PROJ_DIR$\packages\realtek_ameba\sdk-ameba-v4.0b_without_NDA_GCC_V1.0.0\component\soc\realtek\8711b\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash</loader>
<abs_offset>0x00000000</abs_offset>
</pass>
<pass>
<range>CODE 0x800b020 0x807ffff</range>
<loader>$PROJ_DIR$\packages\realtek_ameba\sdk-ameba-v4.0b_without_NDA_GCC_V1.0.0\component\soc\realtek\8711b\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash</loader>
<abs_offset>0xb020</abs_offset>
</pass>
<pass>
<range>CODE 0x10005000 0x10005A43</range>
<loader>$PROJ_DIR$\packages\realtek_ameba\sdk-ameba-v4.0b_without_NDA_GCC_V1.0.0\component\soc\realtek\8711b\misc\iar_utility\common\flashloader\FlashRTL8195aMP.flash</loader>
<abs_offset>0xb000</abs_offset>
<args>--concat</args>
</pass>
<ignore>CODE 0x10005a44 0x1003dfff</ignore>
</flash_board>