[bsp] rpi 4b smart & rtos fixups (#7114)

* [bsp] rpi 4b smart & rtos fixups

* [format] remove spaces & modify readme

* [bsp] update rpi4b readme

bsp/raspberry-pi/raspi4-64/Kconfig

@@ -21,10 +21,11 @@ source "$PKGS_DIR/Kconfig"
 config BCM2711_SOC
     bool
     select ARCH_ARMV8
+    select ARCH_ARM_MMU
     select RT_USING_CACHE
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     select ARCH_CPU_64BIT
     default y
 
-source "driver/Kconfig"
+source "drivers/Kconfig"

bsp/raspberry-pi/raspi4-64/README.md

@@ -11,61 +11,16 @@
 
 ## 2. 编译说明
 
-
-
-### 2.1 Window上的环境搭建
-
-Windows环境下推荐使用[env工具](https://www.rt-thread.org/page/download.html)进行编译。
-
-首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
-
-将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
-
-接着修改`bsp\raspberry-pi\raspi4-64\rtconfig.py`
-
-修改路径：
+推荐使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到`bsp\raspberry-pi\raspi4-64`目录中，运行以下命令：
 
 ```
-EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
+scons
 ```
 
-然后在`bsp\raspberry-pi\raspi4-64\`下输入scons编译即可。
+来编译这个板级支持包。如果编译正确无误，会产生 `rtthread.elf`, `rtthread.bin` 文件。
 
-**window环境搭建注意**
-
-下载完成`gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf.tar.xz`交叉编译工具链后，最好采用7-zip解压工具进行两次解压。
-确保解压目录下的`/bin/aarch64-elf-ld.exe`文件的size不为0。
-否则编译会出现如下错误:
-
-```
-collect2.exe:fatal error:CreateProcess:No such file or directory
-```
-
-### 2.2 Linux上的环境搭建
-
-Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
-
-将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。
-
-```
-PLATFORM    = 'gcc'
-EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
-```
-
-直接进入`bsp\raspberry-pi\raspi4-64`，输入scons编译即可。
-
-
-## 3. 执行
-
-### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
-
-首先下载镜像
-
-* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
-* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
-* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
-
-### 3.2 准备好串口线
+## 3. 环境搭建
+### 3.1 准备好串口线
 
 目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
 
@@ -73,27 +28,61 @@ EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
 
 串口参数： 115200 8N1 ，硬件和软件流控为关。
 
-### 3.3 程序下载
+### 3.2 RTT固件放在SD卡运行
 
-当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
+暂时不支持，需要使用 u-boot 加载。
+
+### 3.3 RTT程序用uboot加载
+
+此 bsp 的 `tools` 下可以找到 [u-boot64.bin](./tools/u-boot64.bin) 和 [config.txt](./tools/config.txt) 两个文件。将其与准备好的 sd 卡中文件替换即可。sd 卡推荐通过树莓派 [imager](https://www.raspberrypi.com/software/) 制作。
+
+需要注意的以下步骤：
+
+**1.电脑上启动tftp服务器**
+
+windows系统电脑上可以安装tftpd搭建tftp服务器。将目录指定到`bsp\raspberry-pi\raspi4-64`。
+
+**2.修改设置uboot**
+
+在控制台输入下列命令：
 
 ```
-enable_uart=1
-arm_64bit=1
-kernel=rtthread.bin
-core_freq=250
+setenv bootcmd "dhcp 0x00208000 x.x.x.x:rtthread.bin;dcache flush;go 0x00208000"
+saveenv
+reset
 ```
 
-按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
+其中`x.x.x.x`为tftp服务器的pc的ip地址。
 
-```text
-heap: 0x000c9350 - 0x040c9350
+**3.修改链接脚本**
 
+链接脚本会在 python 脚本中自行替换，不用处理
+
+**3.插入网线**
+
+上述准备完成后，将网线插入，保证开发板和tftp服务器在同一个网段的路由器上。上电后uboot可以自动从tftp服务器上获取固件，然后开始执行了。
+
+完成后可以看到串口的输出信息
+
+```
  \ | /
 - RT -     Thread Operating System
- / | \     4.0.3 build Apr 16 2020
- 2006 - 2020 Copyright by rt-thread team
-Hi, this is RT-Thread!!
+ / | \     5.0.0 build Mar 29 2023 10:56:23
+ 2006 - 2022 Copyright by RT-Thread team
+lwIP-2.1.2 initialized!
+EMMC: assuming clock rate to be 100MHz
+[I/sal.skt] Socket Abstraction Layer initialize success.
+[I/utest] utest is initialize success.
+[I/utest] total utest testcase num: (0)
+[I/DBG] version is B1
+
+[I/SDIO] SD card capacity 31166976 KB.
+found part[0], begin: 4194304, size: 256.0MB
+found part[1], begin: 272629760, size: 3.856GB
+file system initialization done!
+cpu 2 boot success
+cpu 1 boot success
+cpu 3 boot success
 msh />
 ```
 
@@ -103,11 +92,18 @@ msh />
 | ------ | ----  | :------:  |
 | UART | 支持 | UART0,UART2,UART3,UART4,UART5 |
 | GPIO | 支持 | - |
+| SPI | 支持 | SPI0 |
 | MAILBOX | 支持 | - |
+| WATCHDOG | 支持 | - |
+| HDMI | 支持 | - |
 | SDIO | 支持 | - |
 | ETH | 支持 | - |
 
-## 5. 联系人信息
+## 5. 注意事项
+
+目前rt-thread程序可以使用的内存在100MB以内，可以通过调整`board.c`中`platform_mem_desc`表的数据进行相关内存的映射以及修改`board.h`来确定程序使用的堆栈大小。
+
+## 6. 联系人信息
 
 维护人：[bernard][5]
 

bsp/raspberry-pi/raspi4-64/SConstruct

@@ -11,20 +11,24 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT
 
 DefaultEnvironment(tools=[])
 env = Environment(tools = ['mingw'],
-    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
-    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
-    AR = rtconfig.AR, ARFLAGS = '-rc',
+    AS   = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC   = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX  = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR   = rtconfig.AR, ARFLAGS = '-rc',
     LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 env['ASCOM'] = env['ASPPCOM']
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
 
 Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+objs = PrepareBuilding(env, RTT_ROOT)
+
+if GetDepend('RT_USING_SMART'):
+    # use smart link.lds
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds')
 
 # make a building
 DoBuilding(TARGET, objs)
-

bsp/raspberry-pi/raspi4-64/applications/SConscript

@@ -1,9 +1,8 @@
 from building import *
-import os
 
-cwd = GetCurrentDir()
-src = Glob('*.c')
-CPPPATH = [cwd]
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
 
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 

bsp/raspberry-pi/raspi4-64/driver/SConscript

@@ -1,9 +0,0 @@
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/raspberry-pi/raspi4-64/driver/board.c

@@ -1,172 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- * 2021-12-28     GuEe-GUI       add smp support
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#include "drv_uart.h"
-
-#include "mmu.h"
-#include "gic.h"
-#include "gtimer.h"
-#include "cpuport.h"
-#include "interrupt.h"
-#include "mbox.h"
-
-struct mem_desc platform_mem_desc[] =
-{
-    {0, 0x6400000, 0, NORMAL_MEM},
-    {0xFE200000, 0xFE400000, 0xFE200000, DEVICE_MEM}, /* uart gpio */
-    {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM}, /* gic timer */
-    {WDT_BASE, WDT_BASE + 0x1000, WDT_BASE, DEVICE_MEM}, /* wdt */
-    {MBOX_ADDR, MBOX_ADDR + 0x200000, MBOX_ADDR, DEVICE_MEM}, /* mbox msg */
-    {STIMER_BASE, STIMER_BASE + 0x200000, STIMER_BASE, DEVICE_MEM}, /* stimer */
-    {MAC_BASE_ADDR, MAC_BASE_ADDR + 0x80000, MAC_BASE_ADDR, DEVICE_MEM}, /* mac */
-    {MMC2_BASE_ADDR, MMC2_BASE_ADDR + 0x200000, MMC2_BASE_ADDR, DEVICE_MEM}, /* mmc */
-    {ARM_TIMER_BASE, ARM_TIMER_BASE + 0x200000, ARM_TIMER_BASE, DEVICE_MEM}, /* arm timer */
-    {SEND_DATA_NO_CACHE, SEND_DATA_NO_CACHE + 0x200000, SEND_DATA_NO_CACHE, NORMAL_MEM}, /* eth send */
-    {RECV_DATA_NO_CACHE, RECV_DATA_NO_CACHE + 0x200000, RECV_DATA_NO_CACHE, NORMAL_MEM}, /* eth recv */
-};
-
-const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
-
-#if !defined(BSP_USING_CORETIMER) && !defined(RT_USING_SMP)
-void rt_hw_timer_isr(int vector, void *parameter)
-{
-    ARM_TIMER_IRQCLR = 0;
-    rt_tick_increase();
-}
-#endif
-
-void rt_hw_timer_init(void)
-{
-#if defined(BSP_USING_CORETIMER) || defined(RT_USING_SMP)
-    rt_hw_gtimer_init();
-    core_timer_enable(0);
-#else
-    rt_uint32_t apb_clock = 0;
-    rt_uint32_t timer_clock = 1000000;
-
-    apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
-    ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1);
-
-    ARM_TIMER_RELOAD = 0;
-    ARM_TIMER_LOAD   = 0;
-    ARM_TIMER_IRQCLR = 1;
-    ARM_TIMER_CTRL   = 0;
-
-    ARM_TIMER_RELOAD = 1000000 / RT_TICK_PER_SECOND;
-    ARM_TIMER_LOAD   = 1000000 / RT_TICK_PER_SECOND;
-
-    /* 23-bit counter, enable interrupt, enable timer */
-    ARM_TIMER_CTRL   = (1 << 1) | (1 << 5) | (1 << 7);
-
-    rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
-    rt_hw_interrupt_umask(ARM_TIMER_IRQ);
-#endif
-}
-
-void idle_wfi(void)
-{
-    asm volatile ("wfi");
-}
-
-/**
- *  Initialize the Hardware related stuffs. Called from rtthread_startup()
- *  after interrupt disabled.
- */
-void rt_hw_board_init(void)
-{
-    extern void *MMUTable;
-    rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
-    rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
-
-    /* initialize hardware interrupt */
-    rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
-
-    /* initialize uart */
-    rt_hw_uart_init();      // driver/drv_uart.c
-#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
-    /* set console device */
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-
-#ifdef RT_USING_HEAP
-    /* initialize memory system */
-    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
-#endif
-    /* initialize timer for os tick */
-    rt_hw_timer_init();
-    rt_thread_idle_sethook(idle_wfi);
-
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-
-#ifdef RT_USING_SMP
-    /* install IPI handle */
-    rt_hw_ipi_handler_install(IRQ_ARM_IPI_KICK, rt_scheduler_ipi_handler);
-    arm_gic_umask(0, IRQ_ARM_IPI_KICK);
-#endif
-}
-
-#ifdef RT_USING_SMP
-static unsigned long cpu_release_paddr[] =
-{
-    [0] = 0xd8,
-    [1] = 0xe0,
-    [2] = 0xe8,
-    [3] = 0xf0,
-    [4] = 0
-};
-
-void rt_hw_secondary_cpu_up(void)
-{
-    int i;
-    extern void secondary_cpu_start(void);
-
-    for (i = 1; i < RT_CPUS_NR && cpu_release_paddr[i]; ++i)
-    {
-        __asm__ volatile ("str %0, [%1]"::"rZ"((unsigned long)secondary_cpu_start), "r"(cpu_release_paddr[i]));
-        rt_hw_dcache_flush_range(cpu_release_paddr[i], sizeof(cpu_release_paddr[i]));
-        __DSB();
-        __SEV();
-    }
-}
-
-void secondary_cpu_c_start(void)
-{
-    int id;
-
-    rt_hw_mmu_init();
-
-    id = rt_hw_cpu_id();
-    rt_hw_spin_lock(&_cpus_lock);
-
-    arm_gic_cpu_init(0, platform_get_gic_cpu_base());
-    rt_hw_vector_init();
-    rt_hw_gtimer_local_enable();
-    core_timer_enable(id);
-    arm_gic_umask(0, IRQ_ARM_IPI_KICK);
-
-    rt_kprintf("\rcall cpu %d on success\n", id);
-
-    rt_system_scheduler_start();
-}
-
-void rt_hw_secondary_cpu_idle_exec(void)
-{
-    __WFE();
-}
-#endif
-

bsp/raspberry-pi/raspi4-64/driver/board.h

@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#ifndef BOARD_H__
-#define BOARD_H__
-
-#include <stdint.h>
-#include "raspi4.h"
-
-extern unsigned char __bss_start;
-extern unsigned char __bss_end;
-
-#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
-#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
-
-#ifndef RT_USING_SMART
-#define PV_OFFSET 0
-#define KERNEL_VADDR_START 0
-#endif
-
-void rt_hw_board_init(void);
-
-#endif

bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c

@@ -1,187 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#include "drv_gpio.h"
-
-#ifdef BSP_USING_PIN
-
-uint32_t raspi_get_pin_state(uint32_t fselnum)
-{
-    uint32_t gpfsel = 0;
-
-    switch (fselnum)
-    {
-    case 0:
-        gpfsel = GPIO_REG_GPFSEL0(GPIO_BASE);
-        break;
-    case 1:
-        gpfsel = GPIO_REG_GPFSEL1(GPIO_BASE);
-        break;
-    case 2:
-        gpfsel = GPIO_REG_GPFSEL2(GPIO_BASE);
-        break;
-    case 3:
-        gpfsel = GPIO_REG_GPFSEL3(GPIO_BASE);
-        break;
-    case 4:
-        gpfsel = GPIO_REG_GPFSEL4(GPIO_BASE);
-        break;
-    case 5:
-        gpfsel = GPIO_REG_GPFSEL5(GPIO_BASE);
-        break;
-    default:
-        break;
-    }
-    return gpfsel;
-}
-
-void raspi_set_pin_state(uint32_t fselnum, uint32_t gpfsel)
-{
-    switch (fselnum)
-    {
-    case 0:
-        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
-        break;
-    case 1:
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
-        break;
-    case 2:
-        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
-        break;
-    case 3:
-        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
-        break;
-    case 4:
-        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
-        break;
-    case 5:
-        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
-        break;
-    default:
-        break;
-    }
-}
-
-static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
-{
-    uint32_t fselnum = pin / 10;
-    uint32_t fselrest = pin % 10;
-
-    uint32_t gpfsel = 0;
-    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
-    gpfsel |= (uint32_t)(mode << (fselrest * 3));
-
-    switch (fselnum)
-    {
-    case 0:
-        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
-        break;
-    case 1:
-        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
-        break;
-    case 2:
-        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
-        break;
-    case 3:
-        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
-        break;
-    case 4:
-        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
-        break;
-    case 5:
-        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
-        break;
-    default:
-        break;
-    }
-}
-
-void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode)
-{
-    uint32_t fselnum = pin / 10;
-    uint32_t fselrest = pin % 10;
-    uint32_t gpfsel = 0;
-
-    gpfsel = raspi_get_pin_state(fselnum);
-    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
-    gpfsel |= (uint32_t)(mode << (fselrest * 3));
-    raspi_set_pin_state(fselnum, gpfsel);
-}
-
-static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
-{
-    uint32_t num = pin / 32;
-
-    if(num == 0)
-    {
-        if(value == 0)
-        {
-            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
-        }
-        else
-        {
-            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
-        }
-    }
-    else
-    {
-        if(value == 0)
-        {
-            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
-        }
-        else
-        {
-            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
-        }
-
-    }
-}
-
-static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
-{
-    return 0;
-}
-
-static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
-{
-    return RT_EOK;
-}
-
-static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
-{
-    return RT_EOK;
-}
-
-rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
-{
-    return RT_EOK;
-}
-
-static const struct rt_pin_ops ops =
-{
-    raspi_pin_mode,
-    raspi_pin_write,
-    raspi_pin_read,
-    raspi_pin_attach_irq,
-    raspi_pin_detach_irq,
-    raspi_pin_irq_enable,
-    RT_NULL,
-};
-#endif
-
-int rt_hw_gpio_init(void)
-{
-#ifdef BSP_USING_PIN
-    rt_device_pin_register("gpio", &ops, RT_NULL);
-#endif
-
-    return 0;
-}
-INIT_DEVICE_EXPORT(rt_hw_gpio_init);

bsp/raspberry-pi/raspi4-64/driver/mbox.h

@@ -1,188 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-09-10     bigmagic       first version
- */
-
-#ifndef __MBOX_H__
-#define __MBOX_H__
-
-#include <rtthread.h>
-#include <stdint.h>
-
-// https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
-// https://github.com/hermanhermitage/videocoreiv
-
-/* a properly aligned buffer */
-extern volatile unsigned int *mbox;
-
-#define MBOX_REQUEST            0
-
-/* channels */
-#define MBOX_CH_POWER           0
-#define MBOX_CH_FB              1
-#define MBOX_CH_VUART           2
-#define MBOX_CH_VCHIQ           3
-#define MBOX_CH_LEDS            4
-#define MBOX_CH_BTNS            5
-#define MBOX_CH_TOUCH           6
-#define MBOX_CH_COUNT           7
-#define MBOX_CH_PROP            8
-
-/* tags */
-#define MBOX_TAG_SETPOWER       0x28001
-#define MBOX_TAG_SETCLKRATE     0x38002
-#define MBOX_GET_MAC_ADDRESS    0x10003
-#define MBOX_TAG_LAST           0
-
-#define MMIO_BASE               0xFE000000
-#define VIDEOCORE_MBOX          (MMIO_BASE+0x0000B880)
-#define MBOX_READ               ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0))
-#define MBOX_POLL               ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10))
-#define MBOX_SENDER             ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14))
-#define MBOX_STATUS             ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18))
-#define MBOX_CONFIG             ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C))
-#define MBOX_WRITE              ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20))
-#define MBOX_RESPONSE           0x80000000
-#define MBOX_FULL               0x80000000
-#define MBOX_EMPTY              0x40000000
-
-#define DEVICE_ID_SD_CARD       (0)
-#define DEVICE_ID_USB_HCD       (3)
-#define POWER_STATE_OFF         (0 << 0)
-#define POWER_STATE_ON          (1 << 0)
-#define POWER_STATE_WAIT        (1 << 1)
-#define POWER_STATE_NO_DEVICE   (1 << 1)    // in response
-#define MMU_ENABLE              (1)
-#define MMU_DISABLE             (0)
-
-/*
- * raspi hardware info
- */
-enum
-{
-    MBOX_TAG_HARDWARE_GET_MODEL         = 0x00010001,
-    MBOX_TAG_HARDWARE_GET_REV           = 0x00010002,
-    MBOX_TAG_HARDWARE_GET_MAC_ADDRESS   = 0x00010003,
-    MBOX_TAG_HARDWARE_GET_SERIAL        = 0x00010004,
-    MBOX_TAG_HARDWARE_GET_ARM_MEMORY    = 0x00010005,
-    MBOX_TAG_HARDWARE_GET_VC_MEMORY     = 0x00010006,
-    MBOX_TAG_HARDWARE_GET_CLOCKS        = 0x00010007,
-};
-
-/*
- * raspi clock
- */
-enum
-{
-    MBOX_TAG_CLOCK_GET_TURBO    = 0x00030009,
-    MBOX_TAG_CLOCK_SET_TURBO    = 0x00038009,
-    MBOX_TAG_CLOCK_GET_STATE    = 0x00030001,
-    MBOX_TAG_CLOCK_SET_STATE    = 0x00038001,
-    MBOX_TAG_CLOCK_GET_RATE     = 0x00030002,
-    MBOX_TAG_CLOCK_SET_RATE     = 0x00038002,
-    MBOX_TAG_CLOCK_GET_MAX_RATE = 0x00030004,
-    MBOX_TAG_CLOCK_GET_MIN_RATE = 0x00030007,
-};
-
-/*
- * raspi power
- */
-enum
-{
-    MBOX_TAG_POWER_GET_STATE    = 0x00020001,
-    MBOX_TAG_POWER_SET_STATE    = 0x00028001,
-};
-
-/*
- * raspi temperature
- */
-enum
-{
-    MBOX_TAG_TEMP_GET       = 0x00030006,
-    MBOX_TAG_TEMP_GET_MAX   = 0x0003000A,
-};
-
-/*
- * raspi Memory
- */
-enum
-{
-    MBOX_TAG_ALLOCATE_MEMORY = 0x0003000C,  // Memory: Allocates Contiguous Memory On The GPU (Response: Handle)
-    MBOX_TAG_LOCK_MEMORY     = 0x0003000D,  // Memory: Unlock Buffer (Response: Status)
-    MBOX_TAG_UNLOCK_MEMORY   = 0x0003000E,  // Memory: Unlock Buffer (Response: Status)
-    MBOX_TAG_RELEASE_MEMORY  = 0x0003000F,  // Memory: Free The Memory Buffer (Response: Status)
-    MBOX_TAG_EXECUTE_CODE    = 0x00030010,  // Memory: Calls The Function At Given (Bus) Address And With Arguments Given
-};
-
-/*
- * raspi GPU
- */
-enum
-{
-    MBOX_TAG_EXECUTE_QPU = 0x00030011,      // QPU: Calls The QPU Function At Given (Bus) Address And With Arguments Given
-    //      (Response: Number Of QPUs, Control, No Flush, Timeout In ms)
-    MBOX_TAG_ENABLE_QPU  = 0x00030012,      // QPU: Enables The QPU (Response: Enable State)
-};
-
-/*
- * raspi HDMI
- */
-#define MBOX_TAG_GET_EDID_BLOCK        0x00030020   // HDMI: Read Specificed EDID Block From Attached HDMI/DVI Device
-//      (Response: Block Number, Status, EDID Block (128 Bytes))
-
-/*
- * raspi NOTIFY
- */
-#define MBOX_TAG_NOTIFY_REBOOT         0x00030048
-#define MBOX_TAG_NOTIFY_XHCI_RESET     0x00030058
-
-/*
-* touch
-*/
-#define MBOX_TAG_GET_TOUCHBUF          (0x0004000F)
-
-#define MBOX_ADDR 0x08000000
-
-#define RES_CLK_ID                      (0x000000000)
-#define EMMC_CLK_ID                     (0x000000001)
-#define UART_CLK_ID                     (0x000000002)
-#define ARM_CLK_ID                      (0x000000003)
-#define CORE_CLK_ID                     (0x000000004)
-#define V3D_CLK_ID                      (0x000000005)
-#define H264_CLK_ID                     (0x000000006)
-#define ISP_CLK_ID                      (0x000000007)
-#define SDRAM_CLK_ID                    (0x000000008)
-#define PIXEL_CLK_ID                    (0x000000009)
-#define PWM_CLK_ID                      (0x00000000a)
-
-int mbox_call(unsigned char ch, int mmu_enable);
-int bcm271x_mbox_poweroff_devices(int id);
-int bcm271x_mbox_get_touch(void);
-int bcm271x_notify_reboot(void);
-int bcm271x_notify_xhci_reset(void);
-int bcm271x_gpu_enable(void);
-int bcm271x_mbox_hardware_get_model(void);
-int bcm271x_mbox_hardware_get_revison(void);
-int bcm271x_mbox_hardware_get_mac_address(uint8_t *mac);
-int bcm271x_mbox_hardware_get_serial(rt_uint64_t *sn);
-int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t *base, rt_uint32_t *size);
-int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t *base, rt_uint32_t *size);
-int bcm271x_mbox_clock_get_turbo(void);
-int bcm271x_mbox_clock_set_turbo(int level);
-int bcm271x_mbox_clock_get_state(int id);
-int bcm271x_mbox_clock_set_state(int id, int state);
-int bcm271x_mbox_clock_get_rate(int id);
-int bcm271x_mbox_clock_set_rate(int id, int rate);
-int bcm271x_mbox_clock_get_max_rate(int id);
-int bcm271x_mbox_clock_get_min_rate(int id);
-int bcm271x_mbox_power_get_state(int id);
-int bcm271x_mbox_power_set_state(int id, int state);
-int bcm271x_mbox_temp_get(void);
-int bcm271x_mbox_temp_get_max(void);
-
-#endif

bsp/raspberry-pi/raspi4-64/driver/raspi4.h

@@ -1,167 +0,0 @@
-#ifndef __RASPI4_H__
-#define __RASPI4_H__
-
-#include <rthw.h>
-
-#define __REG32(x)              (*((volatile unsigned int *)(x)))
-
-//base address
-#define PER_BASE                (0xFE000000)
-
-//gpio offset
-#define GPIO_BASE_OFFSET        (0x00200000)
-
-//pl011 offset
-#define PL011_UART_BASE_OFFSET  (0x00201000)
-
-//pactl cs offset
-#define PACTL_CS_OFFSET         (0x00204E00)
-
-//aux offset
-#define AUX_BASE_OFFSET         (0x00215000)
-
-//gpio
-#define GPIO_BASE               (PER_BASE + GPIO_BASE_OFFSET)
-#define GPIO_IRQ_NUM            (3)         //40 pin mode
-#define IRQ_GPIO0               (96 + 49)   //bank0 (0 to 27)
-#define IRQ_GPIO1               (96 + 50)   //bank1 (28 to 45)
-#define IRQ_GPIO2               (96 + 51)   //bank2 (46 to 57)
-#define IRQ_GPIO3               (96 + 52)   //bank3
-
-//system timer
-#define ARM_TIMER_IRQ           (64)
-#define ARM_TIMER_BASE          (PER_BASE + 0xB000)
-#define ARM_TIMER_LOAD          HWREG32(ARM_TIMER_BASE + 0x400)
-#define ARM_TIMER_VALUE         HWREG32(ARM_TIMER_BASE + 0x404)
-#define ARM_TIMER_CTRL          HWREG32(ARM_TIMER_BASE + 0x408)
-#define ARM_TIMER_IRQCLR        HWREG32(ARM_TIMER_BASE + 0x40C)
-#define ARM_TIMER_RAWIRQ        HWREG32(ARM_TIMER_BASE + 0x410)
-#define ARM_TIMER_MASKIRQ       HWREG32(ARM_TIMER_BASE + 0x414)
-#define ARM_TIMER_RELOAD        HWREG32(ARM_TIMER_BASE + 0x418)
-#define ARM_TIMER_PREDIV        HWREG32(ARM_TIMER_BASE + 0x41C)
-#define ARM_TIMER_CNTR          HWREG32(ARM_TIMER_BASE + 0x420)
-
-//uart
-#define UART_BASE               (PER_BASE + PL011_UART_BASE_OFFSET)
-#define UART0_BASE              (UART_BASE + 0x0)
-#define UART2_BASE              (UART_BASE + 0x400)
-#define UART3_BASE              (UART_BASE + 0x600)
-#define UART4_BASE              (UART_BASE + 0x800)
-#define UART5_BASE              (UART_BASE + 0xA00)
-#define IRQ_AUX_UART            (96 + 29)
-#define UART_REFERENCE_CLOCK    (48000000)
-
-//aux
-#define AUX_BASE                (PER_BASE + AUX_BASE_OFFSET)
-#define IRQ_PL011               (96 + 57)
-
-//pactl cs
-#define PACTL_CS_ADDR           (PER_BASE + PACTL_CS_OFFSET)
-#define PACTL_CS                HWREG32(PACTL_CS_ADDR)
-typedef enum
-{
-    IRQ_SPI0 = 0x00000000,
-    IRQ_SPI1 = 0x00000002,
-    IRQ_SPI2 = 0x00000004,
-    IRQ_SPI3 = 0x00000008,
-    IRQ_SPI4 = 0x00000010,
-    IRQ_SPI5 = 0x00000020,
-    IRQ_SPI6 = 0x00000040,
-    IRQ_I2C0 = 0x00000100,
-    IRQ_I2C1 = 0x00000200,
-    IRQ_I2C2 = 0x00000400,
-    IRQ_I2C3 = 0x00000800,
-    IRQ_I2C4 = 0x00001000,
-    IRQ_I2C5 = 0x00002000,
-    IRQ_I2C6 = 0x00004000,
-    IRQ_I2C7 = 0x00008000,
-    IRQ_UART5 = 0x00010000,
-    IRQ_UART4 = 0x00020000,
-    IRQ_UART3 = 0x00040000,
-    IRQ_UART2 = 0x00080000,
-    IRQ_UART0 = 0x00100000
-} PACTL_CS_VAL;
-
-// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
-#define CORE_TIMER_IRQ_CTRL(n)  HWREG32((unsigned long)(0xFF800040 + (n) * 4))
-#define TIMER_IRQ               30
-#define NON_SECURE_TIMER_IRQ    (1 << 1)
-rt_inline void core_timer_enable(int cpu_id)
-{
-    CORE_TIMER_IRQ_CTRL(cpu_id) |= NON_SECURE_TIMER_IRQ;
-}
-
-//core timer
-#define ST_BASE_OFFSET          (0x003000)
-#define STIMER_BASE             (PER_BASE  + ST_BASE_OFFSET)
-#define STIMER_CS               HWREG32(STIMER_BASE + 0x0000)
-#define STIMER_CLO              HWREG32(STIMER_BASE + 0x0004)
-#define STIMER_CHI              HWREG32(STIMER_BASE + 0x0008)
-#define STIMER_C0               HWREG32(STIMER_BASE + 0x000C)
-#define STIMER_C1               HWREG32(STIMER_BASE + 0x0010)
-#define STIMER_C2               HWREG32(STIMER_BASE + 0x0014)
-#define STIMER_C3               HWREG32(STIMER_BASE + 0x0018)
-
-#define DELAY_MICROS(micros) \
-do { \
-    rt_uint32_t compare = STIMER_CLO + micros * 25; \
-    while (STIMER_CLO < compare); \
-} while (0) \
-
-//mmc
-#define MMC0_BASE_ADDR          (PER_BASE + 0x300000)
-#define MMC2_BASE_ADDR          (PER_BASE + 0x340000)
-
-//eth
-#define MAC_BASE_ADDR           (0xfd580000)
-#define MAC_REG_BASE_ADDR       (void *)(MAC_BASE_ADDR)
-#define ETH_IRQ                 (160 + 29)
-#define SEND_DATA_NO_CACHE      (0x08200000)
-#define RECV_DATA_NO_CACHE      (0x08400000)
-
-//watchdog
-#define WDT_BASE                    (PER_BASE + 0x00100000)
-#define PM_RSTC                     HWREG32(WDT_BASE + 0x0000001c)
-#define PM_RSTS                     HWREG32(WDT_BASE + 0x00000020)
-#define PM_WDOG                     HWREG32(WDT_BASE + 0x00000024)
-
-#define PM_PASSWORD                 (0x5A000000)
-#define PM_WDOG_TIME_SET            (0x000fffff)
-#define PM_RSTS_HADWRH_SET          (0x00000040)
-#define PM_RSTC_WRCFG_FULL_RESET    (0x00000020)
-#define PM_RSTC_WRCFG_CLR           (0xffffffcf)
-#define PM_RSTC_RESET               (0x00000102)
-
-//gic max
-#define MAX_HANDLERS                (256)
-#define ARM_GIC_NR_IRQS             (512)
-#define INTC_BASE                   (0xff800000)
-#define ARM_GIC_MAX_NR              (512)
-#define GIC_V2_BASE                 (INTC_BASE + 0x00040000)
-#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
-#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
-#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
-#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
-
-/* ipi interrupt number */
-#define IRQ_ARM_IPI_KICK            0
-#define IRQ_ARM_IPI_CALL            1
-
-#define GIC_IRQ_START               0
-#define GIC_ACK_INTID_MASK          0x000003ff
-
-#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
-#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
-
-/* the basic constants and interfaces needed by gic */
-rt_inline rt_uint32_t platform_get_gic_dist_base(void)
-{
-    return GIC_PL400_DISTRIBUTOR_PPTR;
-}
-
-rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
-{
-    return GIC_PL400_CONTROLLER_PPTR;
-}
-
-#endif

bsp/raspberry-pi/raspi4-64/drivers/Kconfig

@@ -1,3 +1,12 @@
+
+config BSP_SUPPORT_FPU
+    bool "Using Float"
+    default n
+
+menuconfig BSP_USING_VM_MODE
+    bool "Enable VM mode"
+    default n
+
 menu "Hardware Drivers Config"
     menu "BCM Peripheral Drivers"
         menuconfig BSP_USING_UART
@@ -26,20 +35,44 @@ menu "Hardware Drivers Config"
                 bool "Enable UART 5"
                 default n
             endif
-
-        config BSP_USING_GIC
-            bool
+            
+        menuconfig BSP_USING_GIC
+            bool "Enable GIC"
+            select RT_USING_GIC
             default y
-
+        if BSP_USING_GIC
             config BSP_USING_GICV2
-                bool
+                bool "Enable GIC400(GICV2)"
                 default y
+            config BSP_USING_GICV3
+                bool "Enable GIC500(GICV3)"
+                default n
+        endif
 
         config BSP_USING_PIN
             bool "Using PIN"
             select RT_USING_PIN
             default y
 
+            menuconfig BSP_USING_SPI
+            bool "Enable SPI"
+            select RT_USING_SPI
+            default n
+        
+        if BSP_USING_SPI   
+            config BSP_USING_SPI0_BUS
+                bool "Enable SPI0 BUS"
+                default n
+            config BSP_USING_SPI0_DEVICE0
+                bool "Enable SPI0 DEVICE0"
+                select BSP_USING_SPI0_BUS
+                default n
+            config BSP_USING_SPI0_DEVICE1
+                bool "Enable SPI0 DEVICE1"
+                select BSP_USING_SPI0_BUS
+                default n
+        endif
+
         config BSP_USING_CORETIMER
             bool "Using core timer"
             select RT_USING_CORETIMER
@@ -59,10 +92,6 @@ menu "Hardware Drivers Config"
                 default n
         endif
 
-        config BSP_USING_ETH
-            bool "Enable ETH"
-            default n
-
         config BSP_USING_WDT
             bool "Enable WDT"
             select RT_USING_WDT
@@ -103,5 +132,9 @@ menu "Hardware Drivers Config"
                 bool "HDMI DISPLAY"
                 default n
         endif
+
+        menuconfig BSP_USING_TOUCH
+            bool "Enable Touch"
+            default n
     endmenu
 endmenu

bsp/raspberry-pi/raspi4-64/drivers/SConscript

@@ -0,0 +1,19 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH)
+
+# build for sub-directory
+list = os.listdir(cwd)
+objs = []
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+group = group + objs
+
+Return('group')

bsp/raspberry-pi/raspi4-64/drivers/board.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+#include "raspi4.h"
+#include "mmu.h"
+#include "ioremap.h"
+
+extern int __bss_end;
+#define HEAP_BEGIN      ((void*)&__bss_end)
+
+#ifdef RT_USING_SMART
+#define HEAP_END        ((size_t)KERNEL_VADDR_START + 32 * 1024 * 1024)
+#define PAGE_START      HEAP_END
+#define PAGE_END        ((size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
+#else
+#define KERNEL_VADDR_START 0x0
+
+#define HEAP_END        (KERNEL_VADDR_START + 64 * 1024 * 1024)
+#define PAGE_START      HEAP_END
+#define PAGE_END        ((size_t)PAGE_START + 64 * 1024 * 1024)
+#endif
+
+void rt_hw_board_init(void);
+
+#endif

bsp/raspberry-pi/raspi4-64/drivers/drv_gpio.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,6 +17,14 @@
 #include "board.h"
 #include "interrupt.h"
 
+struct gpio_irq_def
+{
+    void  *irq_arg[32];
+    void (*irq_cb[32])(void *param);
+    rt_uint8_t irq_type[32];
+    rt_uint8_t state[32];
+};
+
 #define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
 #define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
 #define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)
@@ -59,6 +67,10 @@
 #define GPIO_REG_GPPUDCLK1(BASE)           HWREG32(BASE + 0x9C)
 #define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
 #define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
+#define GPIO_PUP_PDN_CNTRL_REG0(BASE)      HWREG32(BASE + 0xE4)
+#define GPIO_PUP_PDN_CNTRL_REG1(BASE)      HWREG32(BASE + 0xE8)
+#define GPIO_PUP_PDN_CNTRL_REG2(BASE)      HWREG32(BASE + 0xEC)
+#define GPIO_PUP_PDN_CNTRL_REG3(BASE)      HWREG32(BASE + 0xF0)
 
 typedef enum {
     GPIO_PIN_0,
@@ -115,6 +127,12 @@ typedef enum {
     ALT5 = 0b010
 } GPIO_FUNC;
 
+typedef enum {
+    RASPI_NO_RESISTOR = 0x00,
+    RASPI_PULL_UP = 0x01,
+    RASPI_PULL_DOWN = 0x10
+} GPIO_PUPD_FUNC;
+
 void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode);
 void prev_raspi_pin_write(GPIO_PIN pin, int pin_value);
 int rt_hw_gpio_init(void);

bsp/raspberry-pi/raspi4-64/drivers/drv_gtimer.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <rtthread.h>
+#include "interrupt.h"
+
+#ifndef RT_CPUS_NR
+#define RT_CPUS_NR 1
+#endif
+
+#define GTIMER_IRQ                      (27)
+
+static uint64_t _tickval[RT_CPUS_NR];
+static uint64_t _increaseval[RT_CPUS_NR];
+#define tickval _tickval[cpu_id]
+#define increaseval _increaseval[cpu_id]
+
+/**
+ * This function is the gtimer isr handler.
+ *
+ * @param vector interrupt ID
+ * @param parameter the parameter specified by rt_hw_interrupt_install
+ *
+ * @return none
+ */
+static void _hw_timer_isr(int vector, void *parameter)
+{
+#ifdef RT_USING_SMP
+    int cpu_id = rt_hw_cpu_id();
+#else
+    int cpu_id = 0;
+#endif
+    uint64_t cntvct_el0;
+    do
+    {
+        tickval += increaseval;
+        __asm__ volatile("msr CNTV_CVAL_EL0, %0"::"r"(tickval));
+        __asm__ volatile("mrs %0, CNTVCT_EL0":"=r"(cntvct_el0));
+    } while (cntvct_el0 >= tickval);
+    rt_tick_increase();
+}
+
+/**
+ * The function will initialize the general timer used for the system tick.
+ *
+ * @param none
+ *
+ * @return none
+ */
+rt_weak int rt_hw_gtimer_init(void)
+{
+#ifdef RT_USING_SMP
+    int cpu_id = rt_hw_cpu_id();
+#else
+    int cpu_id = 0;
+#endif
+    uint64_t val;
+
+    rt_hw_interrupt_install(GTIMER_IRQ, _hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(GTIMER_IRQ);
+
+    __asm__ volatile("mrs %0, CNTFRQ_EL0":"=r"(val));
+    increaseval = val / RT_TICK_PER_SECOND;
+
+    __asm__ volatile("msr CNTV_CTL_EL0, %0"::"r"(val));
+    tickval = increaseval;
+    __asm__ volatile("msr CNTV_CVAL_EL0, %0"::"r"(tickval));
+    val = 1;
+    __asm__ volatile("msr CNTV_CTL_EL0, %0"::"r"(val));
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_gtimer_init);

bsp/raspberry-pi/raspi4-64/drivers/drv_hdmi.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-10-26     bigmagic       first version
+ */
+#ifndef __DRV_HDMI_H__
+#define __DRV_HDMI_H__
+
+#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
+
+struct rt_hdmi_fb_device
+{
+    struct rt_device parent;
+
+    rt_uint32_t width;
+    rt_uint32_t height;
+    rt_uint32_t depth;
+    rt_uint32_t pitch;
+    rt_uint32_t pixel_format;
+
+    rt_uint8_t *fb;
+};
+#endif/* __DRV_HDMI_H__ */

bsp/raspberry-pi/raspi4-64/drivers/drv_spi.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-06-16     bigmagic       first version
+ */
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include "drv_gpio.h"
+
+#define SPI_REG_CS(BASE)            HWREG32(BASE + 0x00)
+#define SPI_REG_FIFO(BASE)          HWREG32(BASE + 0x04)
+#define SPI_REG_CLK(BASE)           HWREG32(BASE + 0x08)
+#define SPI_REG_DLEN(BASE)          HWREG32(BASE + 0x0C)
+#define SPI_REG_LTOH(BASE)          HWREG32(BASE + 0x10)
+#define SPI_REG_DC(BASE)            HWREG32(BASE + 0x14)
+
+/* CS Register */
+#define SPI_CS_LOSSI_LONG_32BIT         (1 << 25)
+#define SPI_CS_LOSSI_DMA_MODE           (1 << 24)
+#define SPI_CS_CSPOL2                   (1 << 23)
+#define SPI_CS_CSPOL1                   (1 << 22)
+#define SPI_CS_CSPOL0                   (1 << 21)
+#define SPI_CS_RX_FIFO_FULL             (1 << 20)
+#define SPI_CS_RX_FIFO_3_QUARTER        (1 << 19)
+#define SPI_CS_TX_DATA                  (1 << 18)
+#define SPI_CS_RX_DATA                  (1 << 17)
+#define SPI_CS_DONE                     (1 << 16)
+#define SPI_CS_LOSSI_EN                 (1 << 13)
+#define SPI_CS_READ_EN                  (1 << 12)
+#define SPI_CS_AUTO_CS                  (1 << 11)
+#define SPI_CS_INTR_RXR                 (1 << 10)
+#define SPI_CS_INTR_DONE                (1 << 9)
+#define SPI_CS_DMA_EN                   (1 << 8)
+#define SPI_CS_TA                       (1 << 7)
+#define SPI_CS_CSPOL_HIGH               (1 << 6)
+#define SPI_CS_CLEAR_RX                 (2 << 4)
+#define SPI_CS_CLEAR_TX                 (1 << 4)
+#define SPI_CS_CPOL                     (1 << 3)
+#define SPI_CS_CPHA                     (1 << 2)
+#define SPI_CS_CHIP_SELECT_2            (2 << 0)
+#define SPI_CS_CHIP_SELECT_1            (1 << 0)
+#define SPI_CS_CHIP_SELECT_0            (0 << 0)
+
+struct raspi_spi_hw_config
+{
+    rt_uint8_t spi_num;
+    GPIO_PIN   sclk_pin;
+    GPIO_FUNC  sclk_mode;
+    GPIO_PIN   mosi_pin;
+    GPIO_FUNC  mosi_mode;
+    GPIO_PIN   miso_pin;
+    GPIO_FUNC  miso_mode;
+#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0)
+    GPIO_PIN   ce0_pin;
+    GPIO_FUNC  ce0_mode;
+#endif
+
+#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1)
+    GPIO_PIN   ce1_pin;
+    GPIO_FUNC  ce1_mode;
+#endif
+
+#if defined (BSP_USING_SPI1_DEVICE2)
+    GPIO_PIN   ce2_pin;
+    GPIO_FUNC  ce2_mode;
+#endif
+    rt_ubase_t hw_base;
+
+};
+
+struct raspi_spi_device
+{
+    char *device_name;
+    struct rt_spi_bus *spi_bus;
+    struct rt_spi_device *spi_device;
+    struct raspi_spi_hw_config *spi_hw_config;
+    GPIO_PIN cs_pin;
+};
+
+int rt_hw_spi_init(void);
+
+#endif

bsp/raspberry-pi/raspi4-64/drivers/drv_uart.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -81,26 +81,26 @@
 /*
  *  Auxiliary
  */
-#define AUX_IRQ(BASE)                   HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
-#define AUX_ENABLES(BASE)               HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
-#define AUX_MU_IO_REG(BASE)             HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
-#define AUX_MU_IER_REG(BASE)            HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
-#define AUX_MU_IIR_REG(BASE)            HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
-#define AUX_MU_LCR_REG(BASE)            HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
-#define AUX_MU_MCR_REG(BASE)            HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
-#define AUX_MU_LSR_REG(BASE)            HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
-#define AUX_MU_MSR_REG(BASE)            HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
-#define AUX_MU_SCRATCH(BASE)            HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
-#define AUX_MU_CNTL_REG(BASE)           HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
-#define AUX_MU_STAT_REG(BASE)           HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
-#define AUX_MU_BAUD_REG(BASE)           HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
-#define AUX_SPI0_CNTL0_REG(BASE)        HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
-#define AUX_SPI0_CNTL1_REG(BASE)        HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
-#define AUX_SPI0_STAT_REG(BASE)         HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
-#define AUX_SPI0_IO_REG(BASE)           HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
-#define AUX_SPI0_PEEK_REG(BASE)         HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
-#define AUX_SPI1_CNTL0_REG(BASE)        HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
-#define AUX_SPI1_CNTL1_REG(BASE)        HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
+#define AUX_IRQ(BASE)             HWREG32(BASE + 0x00)   /* Auxiliary Interrupt status 3 */
+#define AUX_ENABLES(BASE)         HWREG32(BASE + 0x04)   /* Auxiliary enables 3bit */
+#define AUX_MU_IO_REG(BASE)       HWREG32(BASE + 0x40)   /* Mini Uart I/O Data 8bit */
+#define AUX_MU_IER_REG(BASE)      HWREG32(BASE + 0x44)   /* Mini Uart Interrupt Enable 8bit */
+#define AUX_MU_IIR_REG(BASE)      HWREG32(BASE + 0x48)   /* Mini Uart Interrupt Identify 8bit */
+#define AUX_MU_LCR_REG(BASE)      HWREG32(BASE + 0x4C)   /* Mini Uart Line Control 8bit */
+#define AUX_MU_MCR_REG(BASE)      HWREG32(BASE + 0x50)   /* Mini Uart Modem Control 8bit */
+#define AUX_MU_LSR_REG(BASE)      HWREG32(BASE + 0x54)   /* Mini Uart Line Status 8bit */
+#define AUX_MU_MSR_REG(BASE)      HWREG32(BASE + 0x58)   /* Mini Uart Modem Status 8bit */
+#define AUX_MU_SCRATCH(BASE)      HWREG32(BASE + 0x5C)   /* Mini Uart Scratch 8bit */
+#define AUX_MU_CNTL_REG(BASE)     HWREG32(BASE + 0x60)   /* Mini Uart Extra Control 8bit */
+#define AUX_MU_STAT_REG(BASE)     HWREG32(BASE + 0x64)   /* Mini Uart Extra Status 32bit */
+#define AUX_MU_BAUD_REG(BASE)     HWREG32(BASE + 0x68)   /* Mini Uart Baudrate 16bit */
+#define AUX_SPI0_CNTL0_REG(BASE)  HWREG32(BASE + 0x80)   /* SPI 1 Control register 0 32bit */
+#define AUX_SPI0_CNTL1_REG(BASE)  HWREG32(BASE + 0x84)   /* SPI 1 Control register 1 8bit */
+#define AUX_SPI0_STAT_REG(BASE)   HWREG32(BASE + 0x88)   /* SPI 1 Status 32bit */
+#define AUX_SPI0_IO_REG(BASE)     HWREG32(BASE + 0x90)   /* SPI 1 Data 32bit */
+#define AUX_SPI0_PEEK_REG(BASE)   HWREG32(BASE + 0x94)   /* SPI 1 Peek 16bit */
+#define AUX_SPI1_CNTL0_REG(BASE)  HWREG32(BASE + 0xC0)   /* SPI 2 Control register 0 32bit */
+#define AUX_SPI1_CNTL1_REG(BASE)  HWREG32(BASE + 0xC4)   /* SPI 2 Control register 1 8bit */
 
 int rt_hw_uart_init(void);
 

bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,11 +7,8 @@
  * Date           Author         Notes
  * 2020-10-26     bigmagic       first version
  */
-
 #include <rthw.h>
 #include "drv_wdt.h"
-#include "drv_gpio.h"
-#include "mbox.h"
 #include "raspi4.h"
 
 #ifdef BSP_USING_WDT
@@ -62,26 +59,22 @@ rt_uint64_t raspi_watchdog_get_timeleft()
 
 static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt)
 {
-    /* init for 10S */
+    /*init for 10S*/
     raspi_watchdog_init(1000000);
     raspi_watchdog_start();
     raspi_watchdog_stop();
-
     return RT_EOK;
 }
 
 static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
 {
-    rt_uint64_t timeout_us = 0;
-
+    rt_uint64_t  timeout_us = 0;
     switch (cmd)
     {
     case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
         timeout_us = *((rt_uint32_t *)arg) * 1000000;
         if (timeout_us >= 0xFFFFFFFF)
-        {
             timeout_us = 0xFFFFFFFF;
-        }
         raspi_watchdog_set_timeout((rt_uint32_t)timeout_us);
         break;
     case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
@@ -102,9 +95,8 @@ static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
         raspi_watchdog_stop();
         break;
     default:
-        return -RT_EIO;
+        return RT_EIO;
     }
-
     return RT_EOK;
 }
 
@@ -124,48 +116,6 @@ int rt_hw_wdt_init(void)
 }
 INIT_DEVICE_EXPORT(rt_hw_wdt_init);
 
-void poweroff(void)
-{
-    unsigned long r;
-
-    rt_kprintf("poweroff...\n");
-
-    /* power off devices one by one */
-    for (r = 0; r < 16; ++r)
-    {
-        bcm271x_mbox_poweroff_devices(r);
-    }
-
-    /* power off gpio pins (but not VCC pins) */
-    GPIO_REG_GPFSEL0(GPIO_BASE) = 0;
-    GPIO_REG_GPFSEL1(GPIO_BASE) = 0;
-    GPIO_REG_GPFSEL2(GPIO_BASE) = 0;
-    GPIO_REG_GPFSEL3(GPIO_BASE) = 0;
-    GPIO_REG_GPFSEL4(GPIO_BASE) = 0;
-    GPIO_REG_GPFSEL5(GPIO_BASE) = 0;
-    GPIO_REG_GPPUD(GPIO_BASE) = 0;
-    rt_thread_mdelay(150);
-
-    GPIO_REG_GPPUDCLK0(GPIO_BASE) = 0xffffffff;
-    GPIO_REG_GPPUDCLK1(GPIO_BASE) = 0xffffffff;
-    rt_thread_mdelay(150);
-
-    /* flush GPIO setup */
-    GPIO_REG_GPPUDCLK0(GPIO_BASE) = 0;
-    GPIO_REG_GPPUDCLK1(GPIO_BASE) = 0;
-
-    /* power off the SoC (GPU + CPU), partition 63 used to indicate halt */
-    r = PM_RSTS;
-    r &= ~0xfffffaaa;
-    r |= 0x555;
-    PM_RSTS |= PM_PASSWORD | r;
-    PM_WDOG |= PM_PASSWORD | 0x0A;
-    PM_RSTC |= PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
-
-    while (1) {};
-}
-MSH_CMD_EXPORT(poweroff, poweroff...);
-
 void reboot(void)
 {
     unsigned int r;
@@ -173,13 +123,13 @@ void reboot(void)
     rt_kprintf("reboot system...\n");
     rt_thread_mdelay(100);
     r = PM_RSTS;
-    /* trigger a restart by instructing the GPU to boot from partition 0 */
+    // trigger a restart by instructing the GPU to boot from partition 0
     r &= ~0xfffffaaa;
-    PM_RSTS |= (PM_PASSWORD | r);   /* boot from partition 0 */
+    PM_RSTS |= (PM_PASSWORD | r);   // boot from partition 0
     PM_WDOG |= (PM_PASSWORD | 0x0A);
     PM_RSTC |= (PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET);
-
-    while (1) {};
+    
+    while (1);
 }
-MSH_CMD_EXPORT(reboot, reboot system...);
+MSH_CMD_EXPORT(reboot,reboot system...);
 #endif /*BSP_USING_WDT */

bsp/raspberry-pi/raspi4-64/drivers/drv_wdt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,6 @@
  * Date           Author         Notes
  * 2020-10-26     bigmagic       first version
  */
-
 #ifndef __DRV_WDT_H__
 #define __DRV_WDT_H__
 

bsp/raspberry-pi/raspi4-64/drivers/mbox.h

@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-09-10     bigmagic       first version
+ */
+
+#ifndef __MBOX_H__
+#define __MBOX_H__
+
+#include <rtthread.h>
+
+//https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
+//https://github.com/hermanhermitage/videocoreiv
+
+/* a properly aligned buffer */
+extern volatile unsigned int* mbox;
+
+#define MBOX_REQUEST    0
+
+/* channels */
+#define MBOX_CH_POWER   0
+#define MBOX_CH_FB      1
+#define MBOX_CH_VUART   2
+#define MBOX_CH_VCHIQ   3
+#define MBOX_CH_LEDS    4
+#define MBOX_CH_BTNS    5
+#define MBOX_CH_TOUCH   6
+#define MBOX_CH_COUNT   7
+#define MBOX_CH_PROP    8
+
+/* tags */
+#define MBOX_TAG_SETPOWER       0x28001
+#define MBOX_TAG_SETCLKRATE     0x38002
+#define MBOX_GET_MAC_ADDRESS    0x10003
+#define MBOX_TAG_LAST           0
+
+#define MMIO_BASE       0xFE000000
+#define VIDEOCORE_MBOX  (MMIO_BASE+0x0000B880)
+extern size_t videocore_mbox;
+#define MBOX_READ       ((volatile unsigned int*)(videocore_mbox+0x0))
+#define MBOX_POLL       ((volatile unsigned int*)(videocore_mbox+0x10))
+#define MBOX_SENDER     ((volatile unsigned int*)(videocore_mbox+0x14))
+#define MBOX_STATUS     ((volatile unsigned int*)(videocore_mbox+0x18))
+#define MBOX_CONFIG     ((volatile unsigned int*)(videocore_mbox+0x1C))
+#define MBOX_WRITE      ((volatile unsigned int*)(videocore_mbox+0x20))
+#define MBOX_RESPONSE   0x80000000
+#define MBOX_FULL       0x80000000
+#define MBOX_EMPTY      0x40000000
+
+#define DEVICE_ID_SD_CARD        (0)
+#define DEVICE_ID_USB_HCD        (3)
+#define POWER_STATE_OFF          (0 << 0)
+#define POWER_STATE_ON           (1 << 0)
+#define POWER_STATE_WAIT         (1 << 1)
+#define POWER_STATE_NO_DEVICE    (1 << 1)    // in response
+#define MMU_ENABLE               (1)
+#define MMU_DISABLE              (0)
+
+/*
+ * raspi hardware info
+ */
+enum {
+    MBOX_TAG_HARDWARE_GET_MODEL         = 0x00010001,
+    MBOX_TAG_HARDWARE_GET_REV           = 0x00010002,
+    MBOX_TAG_HARDWARE_GET_MAC_ADDRESS   = 0x00010003,
+    MBOX_TAG_HARDWARE_GET_SERIAL        = 0x00010004,
+    MBOX_TAG_HARDWARE_GET_ARM_MEMORY    = 0x00010005,
+    MBOX_TAG_HARDWARE_GET_VC_MEMORY     = 0x00010006,
+    MBOX_TAG_HARDWARE_GET_CLOCKS        = 0x00010007,
+};
+
+/*
+ * raspi clock
+ */
+enum {
+    MBOX_TAG_CLOCK_GET_TURBO    = 0x00030009,
+    MBOX_TAG_CLOCK_SET_TURBO    = 0x00038009,
+    MBOX_TAG_CLOCK_GET_STATE    = 0x00030001,
+    MBOX_TAG_CLOCK_SET_STATE    = 0x00038001,
+    MBOX_TAG_CLOCK_GET_RATE     = 0x00030002,
+    MBOX_TAG_CLOCK_SET_RATE     = 0x00038002,
+    MBOX_TAG_CLOCK_GET_MAX_RATE = 0x00030004,
+    MBOX_TAG_CLOCK_GET_MIN_RATE = 0x00030007,
+};
+
+/*
+ * raspi power
+ */
+enum {
+    MBOX_TAG_POWER_GET_STATE    = 0x00020001,
+    MBOX_TAG_POWER_SET_STATE    = 0x00028001,
+};
+
+/*
+ * raspi temperature
+ */
+enum {
+    MBOX_TAG_TEMP_GET       = 0x00030006,
+    MBOX_TAG_TEMP_GET_MAX   = 0x0003000A,
+};
+
+/*
+ * raspi Memory
+ */
+enum {
+    MBOX_TAG_ALLOCATE_MEMORY = 0x0003000C, // Memory: Allocates Contiguous Memory On The GPU (Response: Handle)
+    MBOX_TAG_LOCK_MEMORY     = 0x0003000D, // Memory: Unlock Buffer (Response: Status)
+    MBOX_TAG_UNLOCK_MEMORY   = 0x0003000E, // Memory: Unlock Buffer (Response: Status)
+    MBOX_TAG_RELEASE_MEMORY  = 0x0003000F, // Memory: Free The Memory Buffer (Response: Status)
+    MBOX_TAG_EXECUTE_CODE    = 0x00030010, // Memory: Calls The Function At Given (Bus) Address And With Arguments Given
+};
+
+/*
+ * raspi GPU
+ */
+enum {
+    MBOX_TAG_EXECUTE_QPU = 0x00030011, // QPU: Calls The QPU Function At Given (Bus) Address And With Arguments Given (Response: Number Of QPUs, Control, No Flush, Timeout In ms)
+    MBOX_TAG_ENABLE_QPU  = 0x00030012, // QPU: Enables The QPU (Response: Enable State)
+};
+
+/*
+ * raspi HDMI
+ */
+#define MBOX_TAG_GET_EDID_BLOCK        0x00030020 // HDMI: Read Specificed EDID Block From Attached HDMI/DVI Device (Response: Block Number, Status, EDID Block (128 Bytes))
+
+/*
+ * raspi NOTIFY
+ */
+#define MBOX_TAG_NOTIFY_REBOOT         0x00030048
+#define MBOX_TAG_NOTIFY_XHCI_RESET     0x00030058
+
+/*
+* touch
+*/
+#define MBOX_TAG_GET_TOUCHBUF          (0x0004000F)
+
+#define MBOX_ADDR 0x08000000
+extern size_t mbox_addr;
+
+#define    RES_CLK_ID           (0x000000000)
+#define    EMMC_CLK_ID          (0x000000001)
+#define    UART_CLK_ID          (0x000000002)
+#define    ARM_CLK_ID           (0x000000003)
+#define    CORE_CLK_ID          (0x000000004)
+#define    V3D_CLK_ID           (0x000000005)
+#define    H264_CLK_ID          (0x000000006)
+#define    ISP_CLK_ID           (0x000000007)
+#define    SDRAM_CLK_ID         (0x000000008)
+#define    PIXEL_CLK_ID         (0x000000009)
+#define    PWM_CLK_ID           (0x00000000a)
+
+int mbox_call(unsigned char ch, int mmu_enable);
+int bcm271x_mbox_get_touch(void);
+int bcm271x_notify_reboot(void);
+int bcm271x_notify_xhci_reset(void);
+int bcm271x_gpu_enable(void);
+int bcm271x_mbox_hardware_get_model(void);
+int bcm271x_mbox_hardware_get_revison(void);
+int bcm271x_mbox_hardware_get_mac_address(uint8_t * mac);
+int bcm271x_mbox_hardware_get_serial(rt_uint64_t* sn);
+int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size);
+int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size);
+int bcm271x_mbox_clock_get_turbo(void);
+int bcm271x_mbox_clock_set_turbo(int level);
+int bcm271x_mbox_clock_get_state(int id);
+int bcm271x_mbox_clock_set_state(int id, int state);
+int bcm271x_mbox_clock_get_rate(int id);
+int bcm271x_mbox_clock_set_rate(int id, int rate);
+int bcm271x_mbox_clock_get_max_rate(int id);
+int bcm271x_mbox_clock_get_min_rate(int id);
+int bcm271x_mbox_power_get_state(int id);
+int bcm271x_mbox_power_set_state(int id, int state);
+int bcm271x_mbox_temp_get(void);
+int bcm271x_mbox_temp_get_max(void);
+
+#endif

bsp/raspberry-pi/raspi4-64/drivers/raspi4.h

@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2023-02-06     RT-Thread      first version
+ */
+#ifndef __RASPI4_H__
+#define __RASPI4_H__
+
+#include <rtthread.h>
+
+//https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0.pdf
+
+#define __REG32(x)  (*((volatile unsigned int *)(x)))
+#define __REG16(x)  (*((volatile unsigned short *)(x)))
+
+/* GIC IRQ MAX */
+#define MAX_HANDLERS                (256)
+
+/* base address */
+#define PER_BASE                    (0xFE000000)
+
+//gpio offset
+#define GPIO_BASE_OFFSET            (0x00200000)
+
+
+#define PL011_UART_BASE_OFFSET      (0x00201000)
+//pl011 offset
+#define PL011_UART0_BASE_OFFSET     (0x00201000)
+#define PL011_UART2_BASE_OFFSET     (0x00201400)
+#define PL011_UART3_BASE_OFFSET     (0x00201600)
+#define PL011_UART4_BASE_OFFSET     (0x00201800)
+#define PL011_UART5_BASE_OFFSET     (0x00201A00)
+
+//pactl cs offset
+#define PACTL_CS_OFFSET             (0x00204E00)
+
+//aux offset
+#define AUX_BASE_OFFSET             (0x00215000)
+
+/* GPIO */
+#define GPIO_BASE_ADDR              (PER_BASE + GPIO_BASE_OFFSET)
+extern size_t gpio_base_addr;
+#define GPIO_BASE                   (gpio_base_addr)
+#define GPIO_IRQ_NUM                (3)   //40 pin mode
+#define IRQ_GPIO0                   (96 + 49) //bank0 (0 to 27)
+#define IRQ_GPIO1                   (96 + 50) //bank1 (28 to 45)
+#define IRQ_GPIO2                   (96 + 51) //bank2 (46 to 57)
+#define IRQ_GPIO3                   (96 + 52) //bank3
+
+/* Timer (ARM side) */
+#define ARM_TIMER_IRQ       (64)
+extern size_t arm_timer_base;
+#define ARM_TIMER_BASE      (PER_BASE + 0xB000)
+#define ARM_TIMER_LOAD      HWREG32(arm_timer_base + 0x400)
+#define ARM_TIMER_VALUE     HWREG32(arm_timer_base + 0x404)
+#define ARM_TIMER_CTRL      HWREG32(arm_timer_base + 0x408)
+#define ARM_TIMER_IRQCLR    HWREG32(arm_timer_base + 0x40C)
+#define ARM_TIMER_RAWIRQ    HWREG32(arm_timer_base + 0x410)
+#define ARM_TIMER_MASKIRQ   HWREG32(arm_timer_base + 0x414)
+#define ARM_TIMER_RELOAD    HWREG32(arm_timer_base + 0x418)
+#define ARM_TIMER_PREDIV    HWREG32(arm_timer_base + 0x41C)
+#define ARM_TIMER_CNTR      HWREG32(arm_timer_base + 0x420)
+
+/* UART PL011 */
+#define UART_BASE                   (PER_BASE + PL011_UART_BASE_OFFSET)
+//extern uint32_t uart_base_addr;
+#define UART0_BASE                  (UART_BASE + 0x0)
+#define UART2_BASE                  (UART_BASE + 0x400)
+#define UART3_BASE                  (UART_BASE + 0x600)
+#define UART4_BASE                  (UART_BASE + 0x800)
+#define UART5_BASE                  (UART_BASE + 0xA00)
+#define IRQ_AUX_UART                (96 + 29)
+#define UART_REFERENCE_CLOCK        (48000000)
+
+/* AUX */
+//#define AUX_BASE_ADDR               (PER_BASE + AUX_BASE_OFFSET)
+//extern uint32_t aux_addr;
+//#define AUX_BASE                    (aux_addr + 0x0)
+
+#define AUX_BASE                    (PER_BASE + AUX_BASE_OFFSET)
+#define IRQ_PL011                   (96 + 57)
+
+/* Peripheral IRQ OR-ing */
+#define PACTL_CS_ADDR               (PER_BASE + PACTL_CS_OFFSET)
+extern size_t     pactl_cs_base;
+#define PACTL_CS                    HWREG32(pactl_cs_base)
+typedef enum
+{
+    IRQ_SPI0 = 0x00000000,
+    IRQ_SPI1 = 0x00000002,
+    IRQ_SPI2 = 0x00000004,
+    IRQ_SPI3 = 0x00000008,
+    IRQ_SPI4 = 0x00000010,
+    IRQ_SPI5 = 0x00000020,
+    IRQ_SPI6 = 0x00000040,
+    IRQ_I2C0 = 0x00000100,
+    IRQ_I2C1 = 0x00000200,
+    IRQ_I2C2 = 0x00000400,
+    IRQ_I2C3 = 0x00000800,
+    IRQ_I2C4 = 0x00001000,
+    IRQ_I2C5 = 0x00002000,
+    IRQ_I2C6 = 0x00004000,
+    IRQ_I2C7 = 0x00008000,
+    IRQ_UART5 = 0x00010000,
+    IRQ_UART4 = 0x00020000,
+    IRQ_UART3 = 0x00040000,
+    IRQ_UART2 = 0x00080000,
+    IRQ_UART0 = 0x00100000
+} PACTL_CS_VAL;
+
+// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
+#define CORE0_TIMER_IRQ_CTRL        HWREG32(0xFF800040)
+#define TIMER_IRQ                   30
+#define NON_SECURE_TIMER_IRQ        (1 << 1)
+
+/* GIC */
+#define INTC_BASE                   (0xff800000)
+#define ARM_GIC_NR_IRQS             (512)
+#define ARM_GIC_MAX_NR              (512)
+#define GIC_V2_BASE                 (INTC_BASE + 0x00040000)
+extern size_t gic_base_addr;
+#define GIC_V2_DISTRIBUTOR_BASE     (gic_base_addr + 0x1000)
+#define GIC_V2_CPU_INTERFACE_BASE   (gic_base_addr + 0x2000)
+#define GIC_V2_HYPERVISOR_BASE      (gic_base_addr + 0x4000)
+#define GIC_V2_VIRTUAL_CPU_BASE     (gic_base_addr + 0x6000)
+
+#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
+#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
+
+#define GIC_IRQ_START   0
+
+#define GIC_ACK_INTID_MASK  0x000003ff
+
+
+//watchdog
+#define WDT_BASE        (PER_BASE + 0x00100000)
+extern size_t         wdt_base_addr;
+#define PM_RSTC         HWREG32(wdt_base_addr + 0x1c)
+#define PM_RSTS         HWREG32(wdt_base_addr + 0x20)
+#define PM_WDOG         HWREG32(wdt_base_addr + 0x24)
+
+#define PM_PASSWORD                 (0x5A000000)
+#define PM_WDOG_TIME_SET            (0x000fffff)
+#define PM_RSTS_HADWRH_SET          (0x00000040)
+#define PM_RSTC_WRCFG_FULL_RESET    (0x00000020)
+#define PM_RSTC_WRCFG_CLR           (0xffffffcf)
+#define PM_RSTC_RESET               (0x00000102)
+
+//timer
+#define ST_BASE_OFFSET     (0x003000)
+#define STIMER_BASE  (PER_BASE  + ST_BASE_OFFSET)
+extern size_t stimer_base_addr;
+#define STIMER_CS    __REG32(stimer_base_addr + 0x0000)
+#define STIMER_CLO   __REG32(stimer_base_addr + 0x0004)
+#define STIMER_CHI   __REG32(stimer_base_addr + 0x0008)
+#define STIMER_C0    __REG32(stimer_base_addr + 0x000C)
+#define STIMER_C1    __REG32(stimer_base_addr + 0x0010)
+#define STIMER_C2    __REG32(stimer_base_addr + 0x0014)
+#define STIMER_C3    __REG32(stimer_base_addr + 0x0018)
+
+#define DELAY_MICROS(micros)                            \
+    do{                                                 \
+        rt_uint32_t compare = STIMER_CLO + micros * 25; \
+        while (STIMER_CLO < compare);                   \
+    } while (0)
+
+//External Mass Media Controller (SD Card)
+#define MMC0_BASE_ADDR    (PER_BASE+0x300000)
+extern size_t mmc0_base_addr;
+#define MMC2_BASE_ADDR    (PER_BASE+0x340000)
+extern size_t mmc2_base_addr;
+
+//mac
+#define MAC_REG                 (void *)(0xfd580000)
+extern uint8_t *                mac_reg_base_addr;
+
+#define ETH_IRQ                 (160+29)
+
+#define SEND_DATA_NO_CACHE      (0x08200000)
+extern uint8_t *                eth_send_no_cache;
+
+#define RECV_DATA_NO_CACHE      (0x08400000)
+extern uint8_t *                eth_recv_no_cache;
+
+/* the basic constants and interfaces needed by gic */
+rt_inline size_t platform_get_gic_dist_base(void)
+{
+    return GIC_PL400_DISTRIBUTOR_PPTR;
+}
+
+rt_inline size_t platform_get_gic_cpu_base(void)
+{
+    return GIC_PL400_CONTROLLER_PPTR;
+}
+
+#endif

bsp/raspberry-pi/raspi4-64/link_smart.lds

@@ -0,0 +1,109 @@
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+SECTIONS
+{
+    /* . = 0x208000; */
+    . = 0xffff000000008000;
+
+    __text_start = .;
+    .text :
+    {
+        KEEP(*(.text.entrypoint))
+        KEEP(*(.vectors))
+        *(.text)
+        *(.text.*)
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    .ARM.exidx   :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(8);
+    __data_start = .;
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(8);
+    __bss_start = .;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+	__data_size = SIZEOF(.data);
+	__bss_size = SIZEOF(.bss);
+
+    _end = .;
+}

bsp/raspberry-pi/raspi4-64/rtconfig.py

@@ -35,15 +35,15 @@ if PLATFORM == 'gcc':
     OBJCPY  = PREFIX + 'objcopy'
 
     DEVICE = ' -march=armv8-a -mtune=cortex-a72'
-    CFLAGS = DEVICE + ' -Wall -Wno-cpp'
+    CFLAGS = DEVICE + ' -Wall -Wno-cpp -D_POSIX_SOURCE'
     AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
     LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
     CPATH   = ''
     LPATH   = ''
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
     else:
         CFLAGS += ' -O2'
 

bsp/raspberry-pi/raspi4-64/tools/config.txt

@@ -0,0 +1,5 @@
+enable_uart=1
+kernel=u-boot64.bin
+#kernel=kernel7.img
+#kernel_address=0xc0000000
+arm_64bit=1