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[libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management
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Browse Source
This commit is contained in:
Evlers
2026-05-19 15:07:23 +08:00
committed by Rbb666
parent c96fc44ba3
commit ad205d2bf3
3 changed files with 24 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libcpu/arm/cortex-m33/context_gcc.S
+8 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -10,6 +10,7 @@
* 2013-06-18 aozima add restore MSP feature.
* 2013-06-23 aozima support lazy stack optimized.
* 2018-07-24 aozima enhancement hard fault exception handler.
* 2026-05-19 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
*/
/**
@@ -34,6 +35,7 @@
* rt_base_t rt_hw_interrupt_disable();
*/
.global rt_hw_interrupt_disable
.weak rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
MRS r0, PRIMASK
@@ -44,6 +46,7 @@ rt_hw_interrupt_disable:
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.global rt_hw_interrupt_enable
.weak rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
MSR PRIMASK, r0
@@ -258,6 +261,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I
/* clear the BASEPRI register to disable masking priority */
MOV r0, #0x00
MSR BASEPRI, r0
/* ensure PendSV exception taken place before subsequent operation */
DSB
ISB
libcpu/arm/cortex-m33/context_iar.S
+8 -3
View File
@@ -1,5 +1,5 @@
;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; * Copyright (c) 2006-2026, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
@@ -11,6 +11,7 @@
; * 2013-06-18 aozima add restore MSP feature.
; * 2013-06-23 aozima support lazy stack optimized.
; * 2018-07-24 aozima enhancement hard fault exception handler.
; * 2026-05-19 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
; */
;/**
@@ -39,7 +40,7 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
PUBWEAK rt_hw_interrupt_disable
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
@@ -48,7 +49,7 @@ rt_hw_interrupt_disable:
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
PUBWEAK rt_hw_interrupt_enable
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
@@ -253,6 +254,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I
; clear the BASEPRI register to disable masking priority
MOV r0, #0x00
MSR BASEPRI, r0
; ensure PendSV exception taken place before subsequent operation
DSB
ISB
libcpu/arm/cortex-m33/context_rvds.S
+8 -3
View File
@@ -1,5 +1,5 @@
;/*
;* Copyright (c) 2006-2018, RT-Thread Development Team
;* Copyright (c) 2006-2026, RT-Thread Development Team
;*
;* SPDX-License-Identifier: Apache-2.0
;*
@@ -10,6 +10,7 @@
; * 2013-06-18 aozima add restore MSP feature.
; * 2013-06-23 aozima support lazy stack optimized.
; * 2018-07-24 aozima enhancement hard fault exception handler.
; * 2026-05-19 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
; */
;/**
@@ -39,7 +40,7 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
EXPORT rt_hw_interrupt_disable [WEAK]
MRS r0, PRIMASK
CPSID I
BX LR
@@ -49,7 +50,7 @@ rt_hw_interrupt_disable PROC
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
EXPORT rt_hw_interrupt_enable [WEAK]
MSR PRIMASK, r0
BX LR
ENDP
@@ -254,6 +255,10 @@ rt_hw_context_switch_to PROC
CPSIE F
CPSIE I
; clear the BASEPRI register to disable masking priority
MOV r0, #0x00
MSR BASEPRI, r0
; ensure PendSV exception taken place before subsequent operation
DSB
ISB