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first console project

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This commit is contained in:
supperthomas
2021-02-11 04:45:50 +08:00
parent 0fe8fccfbd
commit abcac46fcf
76 changed files with 21199 additions and 13707 deletions
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89
bsp/maxim/MAX32660_EVSYS/.config
View File

@@ -54,6 +54,7 @@ CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
@@ -63,9 +64,7 @@ CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
# CONFIG_RT_USING_CONSOLE is not set
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -73,10 +72,8 @@ CONFIG_RT_VER_NUM=0x40003
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_COMPONENTS_INIT is not set
# CONFIG_RT_USING_USER_MAIN is not set
#
# C++ features
@@ -86,21 +83,7 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
# CONFIG_RT_USING_FINSH is not set
#
# Device virtual file system
@@ -297,6 +280,8 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
#
# tools packages
@@ -311,6 +296,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
@@ -318,6 +304,8 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
#
# system packages
@@ -344,10 +332,16 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
#
@@ -407,6 +401,10 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_BSAL is not set
#
# miscellaneous packages
@@ -416,6 +414,7 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
@@ -436,63 +435,33 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_NRF52840=y
CONFIG_NRFX_CLOCK_ENABLED=1
CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
CONFIG_SOC_NORDIC=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_JLINK_TO_USART=y
# CONFIG_BSP_USING_QSPI_FLASH is not set
CONFIG_SOC_MAXIM=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_NRFX_GPIOTE_ENABLED=1
# CONFIG_BSP_USING_SAADC is not set
# CONFIG_BSP_USING_PWM is not set
CONFIG_BSP_USING_UART=y
CONFIG_NRFX_USING_UART=y
# CONFIG_NRFX_USING_UARTE is not set
CONFIG_NRFX_UART_ENABLED=1
CONFIG_BSP_USING_UART0=y
CONFIG_NRFX_UART0_ENABLED=1
CONFIG_BSP_UART0_RX_PIN=8
CONFIG_BSP_UART0_TX_PIN=6
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
#
# On-chip flash config
#
CONFIG_MCU_FLASH_START_ADDRESS=0x00000000
CONFIG_MCU_FLASH_SIZE_KB=1024
CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
CONFIG_MCU_SRAM_SIZE_KB=256
CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
CONFIG_BLE_STACK_USING_NULL=y
# CONFIG_BSP_USING_SOFTDEVICE is not set
# CONFIG_BSP_USING_NIMBLE is not set

4
bsp/maxim/MAX32660_EVSYS/SConstruct
View File

@@ -48,10 +48,10 @@ print(SDK_LIB)
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
# include cmsis
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

17
bsp/maxim/MAX32660_EVSYS/applications/application.c
View File

@@ -13,19 +13,24 @@
#include <rtdevice.h>
#define DK_BOARD_LED_1 13
#define DK_BOARD_LED_2 14
#include "gpio.h"
const gpio_cfg_t led_pin[] = {
{PORT_0, PIN_13, GPIO_FUNC_OUT, GPIO_PAD_NONE},
};
int main(void)
{
int count = 1;
rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
GPIO_Config(&led_pin[0]);
//rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
GPIO_OutSet(&led_pin[0]);
while (count++)
{
rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
//rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
rt_thread_mdelay(500);
GPIO_OutToggle(&led_pin[0]);
//rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
//rt_thread_mdelay(500);
}
return RT_EOK;
}

262
bsp/maxim/MAX32660_EVSYS/applications/drv_uart.c Normal file
View File

@@ -0,0 +1,262 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-08 Supperthomas first version
*/
#include "board.h"
#include "uart.h"
#include "rtdevice.h"
#define BUFF_SIZE 10
uint8_t rxdata[BUFF_SIZE]={0};
#define UART0_CONFIG \
{ \
.name = "uart0", \
.Instance = MXC_UART_GET_UART(0), \
.irq_type = MXC_UART_GET_IRQ(0), \
}
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = MXC_UART_GET_UART(1), \
.irq_type = MXC_UART_GET_IRQ(1), \
}
struct mcu_uart_config
{
const char *name;
mxc_uart_regs_t *Instance;
IRQn_Type irq_type;
};
struct mcu_uart
{
mxc_uart_regs_t *handle;
struct mcu_uart_config *config;
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
//#define LOG_TAG "drv.usart"
//#include <drv_log.h>
#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
enum
{
#ifdef BSP_USING_UART0
UART0_INDEX,
#endif
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
};
static struct mcu_uart_config uart_config[] =
{
#ifdef BSP_USING_UART0
UART0_CONFIG,
#endif
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
};
static struct mcu_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
#ifdef BSP_USING_UART1
void UART1_IRQHandler(void)
{
rt_interrupt_enter();
rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
/* leave interrupt */
uint32_t intst = 0;
intst = MXC_UART1->int_fl;
MXC_UART1->int_fl = intst;
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_UART0
void UART0_IRQHandler(void)
{
//UART_Handler(MXC_UART0);
/* enter interrupt */
rt_interrupt_enter();
rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
/* leave interrupt */
uint32_t intst = 0;
intst = MXC_UART0->int_fl;
MXC_UART0->int_fl = intst;
/* leave interrupt */
rt_interrupt_leave();
}
#endif
static rt_err_t mcu_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
int error, i;
struct mcu_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
const sys_cfg_uart_t sys_uart_cfg = {
MAP_A,
UART_FLOW_DISABLE,
};
uart = rt_container_of(serial, struct mcu_uart, serial);
uart_cfg_t mcu_cfg;
uart->handle = uart->config->Instance;
mcu_cfg.baud = cfg->baud_rate;
mcu_cfg.stop = UART_STOP_1;
mcu_cfg.parity = UART_PARITY_DISABLE;
mcu_cfg.size = UART_DATA_SIZE_8_BITS;
mcu_cfg.flow = UART_FLOW_CTRL_EN;
mcu_cfg.pol = UART_FLOW_POL_EN;
error= UART_Init(uart->handle, &mcu_cfg, &sys_uart_cfg);
return RT_EOK;
}
static rt_err_t mcu_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct mcu_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct mcu_uart, serial);
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
// NVIC_DisableIRQ(uart->config->irq_type);
NVIC_ClearPendingIRQ(uart->config->irq_type);
NVIC_DisableIRQ(uart->config->irq_type);
/* disable interrupt */
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_SetPriority(uart->config->irq_type, 1);
NVIC_EnableIRQ(uart->config->irq_type);
/* enable interrupt */
uart->handle->ctrl |= 0x05 << MXC_F_UART_CTRL_RX_TO_POS;
uart->handle->int_en |= MXC_F_UART_INT_EN_RX_FIFO_THRESH | MXC_F_UART_INT_EN_RX_TIMEOUT;
#define UART_ER_IE (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
MXC_F_UART_INT_EN_RX_PARITY_ERROR | \
MXC_F_UART_INT_EN_RX_OVERRUN )
uart->handle->int_en |= UART_ER_IE;
uart->handle->thresh_ctrl=MXC_UART_FIFO_DEPTH<<
MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
break;
#ifdef RT_SERIAL_USING_DMA
case RT_DEVICE_CTRL_CONFIG:
stm32_dma_config(serial, ctrl_arg);
break;
#endif
case RT_DEVICE_CTRL_CLOSE:
// if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
// {
// RT_ASSERT(0)
// }
break;
}
return RT_EOK;
}
static int mcu_putc(struct rt_serial_device *serial, char c)
{
struct mcu_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct mcu_uart, serial);
UART_WriteByte(uart->handle, c);
return 1;
}
static int mcu_getc(struct rt_serial_device *serial)
{
int ch;
struct mcu_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct mcu_uart, serial);
ch = -1;
if(UART_NumReadAvail(uart->handle))
{
ch = UART_ReadByte(uart->handle);
}
return ch;
}
static const struct rt_uart_ops mcu_uart_ops =
{
.configure = mcu_configure,
.control = mcu_control,
.putc = mcu_putc,
.getc = mcu_getc,
};
int rt_hw_usart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct mcu_uart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
for (int i = 0; i < obj_num; i++)
{
/* init UART object */
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &mcu_uart_ops;
uart_obj[i].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
, NULL);
RT_ASSERT(result == RT_EOK);
}
return result;
}
//INIT_BOARD_EXPORT(rt_hw_usart_init);
#endif /* RT_USING_SERIAL */

18
bsp/maxim/MAX32660_EVSYS/applications/drv_usart.h Normal file
View File

@@ -0,0 +1,18 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018.10.30 SummerGift first version
* 2019.03.05 whj4674672 add stm32h7
* 2020-10-14 Dozingfiretruck Porting for stm32wbxx
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
int rt_hw_usart_init(void);
#endif /* __DRV_USART_H__ */

482
bsp/maxim/MAX32660_EVSYS/board/Kconfig
View File

File diff suppressed because it is too large Load Diff

61
bsp/maxim/MAX32660_EVSYS/board/board.c
View File

@@ -10,11 +10,12 @@
*/
#include <rtthread.h>
#include <rthw.h>
#include <nrfx_systick.h>
#include <stdio.h>
#include "board.h"
#include "drv_uart.h"
#include <nrfx_clock.h>
#include "mxc_sys.h"
#ifdef RT_USING_SERIAL
#include "drv_usart.h"
#endif
/**
* This is the timer interrupt service routine.
@@ -31,63 +32,49 @@ void SysTick_Handler(void)
rt_interrupt_leave();
}
static void clk_event_handler(nrfx_clock_evt_type_t event){}
void SysTick_Configuration(void)
{
nrfx_clock_init(clk_event_handler);
nrfx_clock_enable();
nrfx_clock_lfclk_start();
/* Set interrupt priority */
NVIC_SetPriority(SysTick_IRQn, 0xf);
/* Configure SysTick to interrupt at the requested rate. */
nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND);
nrf_systick_val_clear();
nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
| NRF_SYSTICK_CSR_ENABLE);
uint32_t error;
error = SYS_SysTick_Config(SYS_SysTick_GetFreq()/RT_TICK_PER_SECOND, 1, MXC_TMR0);
if (error != E_NO_ERROR) {
printf("ERROR: Ticks is not valid");
}
}
mxc_uart_regs_t *ConsoleUART = MXC_UART_GET_UART(1);
const sys_cfg_uart_t console_uart_sys_cfg = {
MAP_A,
UART_FLOW_DISABLE,
};
void rt_hw_board_init(void)
{
rt_hw_interrupt_enable(0);
// rt_hw_interrupt_enable(0);
// sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
/* Activate deep sleep mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
SysTick_Configuration();
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
rt_system_heap_init((void *)(0x20000000+16*1024), (void *)(0x20000000+64*1024));
#endif
#ifdef RT_USING_SERIAL
rt_hw_uart_init();
rt_hw_usart_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef BSP_USING_SOFTDEVICE
extern uint32_t Image$$RW_IRAM1$$Base;
uint32_t const *const m_ram_start = &Image$$RW_IRAM1$$Base;
if ((uint32_t)m_ram_start == 0x20000000)
{
rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start);
while (1);
}
else
{
rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start);
}
#endif
}

1
bsp/maxim/MAX32660_EVSYS/board/board.h
View File

@@ -3,7 +3,6 @@
#include <rtthread.h>
#include <rthw.h>
#include "nrf.h"
#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
#define MCU_FLASH_END_ADDRESS ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))

7
bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.sct
View File

@@ -2,13 +2,14 @@
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x100000 { ; load region size_region
ER_IROM1 0x00000000 0x100000 { ; load address = execution address
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x40000 { ; RW data
RW_IRAM1 0x20000000 0x00018000 { ; RW data
.ANY (+RW +ZI)
}
}

47
bsp/maxim/MAX32660_EVSYS/board/nrfx_config.h
View File

@@ -1,47 +0,0 @@
/**
* Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRFX_CONFIG_H__
#define NRFX_CONFIG_H__
// TODO - temporary redirection
#include <sdk_config.h>
#endif // NRFX_CONFIG_H__

269
bsp/maxim/MAX32660_EVSYS/board/nrfx_glue.h
View File

@@ -1,269 +0,0 @@
/*
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRFX_GLUE_H__
#define NRFX_GLUE_H__
// THIS IS A TEMPLATE FILE.
// It should be copied to a suitable location within the host environment into
// which nrfx is integrated, and the following macros should be provided with
// appropriate implementations.
// And this comment should be removed from the customized file.
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include "nrf.h"
/**
* @defgroup nrfx_glue nrfx_glue.h
* @{
* @ingroup nrfx
*
* @brief This file contains macros that should be implemented according to
* the needs of the host environment into which @em nrfx is integrated.
*/
// Uncomment this line to use the standard MDK way of binding IRQ handlers
// at linking time.
#include <soc/nrfx_irqs.h>
//------------------------------------------------------------------------------
/**
* @brief Macro for placing a runtime assertion.
*
* @param expression Expression to be evaluated.
*/
#define NRFX_ASSERT(expression)
/**
* @brief Macro for placing a compile time assertion.
*
* @param expression Expression to be evaluated.
*/
#define NRFX_STATIC_ASSERT(expression)
//------------------------------------------------------------------------------
/**
* @brief Macro for setting the priority of a specific IRQ.
*
* @param irq_number IRQ number.
* @param priority Priority to be set.
*/
#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) NVIC_SetPriority(irq_number, priority)
/**
* @brief Macro for enabling a specific IRQ.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_ENABLE(irq_number) NVIC_EnableIRQ(irq_number)
/**
* @brief Macro for checking if a specific IRQ is enabled.
*
* @param irq_number IRQ number.
*
* @retval true If the IRQ is enabled.
* @retval false Otherwise.
*/
#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number)
static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
{
return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
}
/**
* @brief Macro for disabling a specific IRQ.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number)
static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
{
NVIC_DisableIRQ(irq_number);
}
/**
* @brief Macro for setting a specific IRQ as pending.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_PENDING_SET(irq_number)
/**
* @brief Macro for clearing the pending status of a specific IRQ.
*
* @param irq_number IRQ number.
*/
#define NRFX_IRQ_PENDING_CLEAR(irq_number)
/**
* @brief Macro for checking the pending status of a specific IRQ.
*
* @retval true If the IRQ is pending.
* @retval false Otherwise.
*/
#define NRFX_IRQ_IS_PENDING(irq_number)
/** @brief Macro for entering into a critical section. */
#define NRFX_CRITICAL_SECTION_ENTER()
/** @brief Macro for exiting from a critical section. */
#define NRFX_CRITICAL_SECTION_EXIT()
//------------------------------------------------------------------------------
/**
* @brief When set to a non-zero value, this macro specifies that
* @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
* A compilation error is generated if the DWT unit is not present
* in the SoC used.
*/
#define NRFX_DELAY_DWT_BASED 0
/**
* @brief Macro for delaying the code execution for at least the specified time.
*
* @param us_time Number of microseconds to wait.
*/
#define NRFX_DELAY_US(us_time)
//------------------------------------------------------------------------------
/** @brief Atomic 32-bit unsigned type. */
#define nrfx_atomic_t
/**
* @brief Macro for storing a value to an atomic object and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value to store.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_STORE(p_data, value)
/**
* @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the OR operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_OR(p_data, value)
/**
* @brief Macro for running a bitwise AND operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the AND operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_AND(p_data, value)
/**
* @brief Macro for running a bitwise XOR operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the XOR operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_XOR(p_data, value)
/**
* @brief Macro for running an addition operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the ADD operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_ADD(p_data, value)
/**
* @brief Macro for running a subtraction operation on an atomic object
* and returning its previous value.
*
* @param[in] p_data Atomic memory pointer.
* @param[in] value Value of the second operand in the SUB operation.
*
* @return Previous value of the atomic object.
*/
#define NRFX_ATOMIC_FETCH_SUB(p_data, value)
//------------------------------------------------------------------------------
/**
* @brief When set to a non-zero value, this macro specifies that the
* @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
* in a customized way and the default definitions from @c <nrfx_error.h>
* should not be used.
*/
#define NRFX_CUSTOM_ERROR_CODES 0
//------------------------------------------------------------------------------
/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_CHANNELS_USED 0
/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
#define NRFX_DPPI_GROUPS_USED 0
/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
#define NRFX_PPI_CHANNELS_USED 0
/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
#define NRFX_PPI_GROUPS_USED 0
/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
#define NRFX_EGUS_USED 0
/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
#define NRFX_TIMERS_USED 0
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRFX_GLUE_H__

135
bsp/maxim/MAX32660_EVSYS/board/nrfx_log.h
View File

@@ -1,135 +0,0 @@
/*
* Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef NRFX_LOG_H__
#define NRFX_LOG_H__
// THIS IS A TEMPLATE FILE.
// It should be copied to a suitable location within the host environment into
// which nrfx is integrated, and the following macros should be provided with
// appropriate implementations.
// And this comment should be removed from the customized file.
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrfx_log nrfx_log.h
* @{
* @ingroup nrfx
*
* @brief This file contains macros that should be implemented according to
* the needs of the host environment into which @em nrfx is integrated.
*/
/**
* @brief Macro for logging a message with the severity level ERROR.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_ERROR(format, ...)
/**
* @brief Macro for logging a message with the severity level WARNING.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_WARNING(format, ...)
/**
* @brief Macro for logging a message with the severity level INFO.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_INFO(format, ...)
/**
* @brief Macro for logging a message with the severity level DEBUG.
*
* @param format printf-style format string, optionally followed by arguments
* to be formatted and inserted in the resulting string.
*/
#define NRFX_LOG_DEBUG(format, ...)
/**
* @brief Macro for logging a memory dump with the severity level ERROR.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level WARNING.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level INFO.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
/**
* @brief Macro for logging a memory dump with the severity level DEBUG.
*
* @param[in] p_memory Pointer to the memory region to be dumped.
* @param[in] length Length of the memory region in bytes.
*/
#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
/**
* @brief Macro for getting the textual representation of a given error code.
*
* @param[in] error_code Error code.
*
* @return String containing the textual representation of the error code.
*/
#define NRFX_LOG_ERROR_STRING_GET(error_code)
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRFX_LOG_H__

11704
bsp/maxim/MAX32660_EVSYS/board/sdk_config.h
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File diff suppressed because it is too large Load Diff

1029
bsp/maxim/MAX32660_EVSYS/project.uvoptx
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File diff suppressed because it is too large Load Diff

480
bsp/maxim/MAX32660_EVSYS/project.uvprojx
View File

File diff suppressed because it is too large Load Diff

82
bsp/maxim/MAX32660_EVSYS/rtconfig.h
View File

@@ -1,6 +1,32 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
#define RT_USING_USER_MAIN
#define RT_TICK_PER_SECOND 1000
#define BSP_USING_UART1
#define BSP_USING_UART0
#define RT_USING_COMPONENTS_INIT
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
@@ -10,7 +36,8 @@
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
@@ -38,36 +65,16 @@
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
@@ -138,6 +145,9 @@
/* system packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
#define PKG_USING_NRFX
@@ -149,37 +159,15 @@
/* samples: kernel and components samples */
/* games: games run on RT-Thread console */
/* Hardware Drivers Config */
#define SOC_NRF52840
#define NRFX_CLOCK_ENABLED 1
#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
#define NRFX_CLOCK_CONFIG_LF_SRC 1
#define SOC_NORDIC
/* Onboard Peripheral Drivers */
#define BSP_USING_JLINK_TO_USART
#define SOC_MAXIM
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define NRFX_GPIOTE_ENABLED 1
#define BSP_USING_UART
#define NRFX_USING_UART
#define NRFX_UART_ENABLED 1
#define BSP_USING_UART0
#define NRFX_UART0_ENABLED 1
#define BSP_UART0_RX_PIN 8
#define BSP_UART0_TX_PIN 6
/* On-chip flash config */
#define MCU_FLASH_START_ADDRESS 0x00000000
#define MCU_FLASH_SIZE_KB 1024
#define MCU_SRAM_START_ADDRESS 0x20000000
#define MCU_SRAM_SIZE_KB 256
#define MCU_FLASH_PAGE_SIZE 0x1000
#define BLE_STACK_USING_NULL
#endif

12
bsp/maxim/MAX32660_EVSYS/template.uvoptx
View File

@@ -77,7 +77,7 @@
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>5</CpuCode>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
@@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@@ -114,18 +114,18 @@
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
<Key>CMSIS_AGDI</Key>
<Name>-X"CMSIS-DAP" -U04440000e28e0cd70000000000000000 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MAX32660.FLM -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)</Name>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MAX32660 -FL040000 -FS00 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>

34
bsp/maxim/MAX32660_EVSYS/template.uvprojx
View File

@@ -14,16 +14,16 @@
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>nRF52840_xxAA</Device>
<Vendor>Nordic Semiconductor</Vendor>
<PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.32.1</PackID>
<PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
<Cpu>IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<Device>MAX32660</Device>
<Vendor>Maxim</Vendor>
<PackID>Maxim.MAX32660.1.2.0</PackID>
<PackURL>http://www.mxim.net/microcontroller/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm))</FlashDriverDll>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MAX32660 -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:nRF52840_xxAA$Device\Include\nrf.h</RegisterFile>
<RegisterFile>$$Device:MAX32660$Libraries\Device\Maxim\MAX32660\Include\max32660.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
@@ -33,7 +33,7 @@
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:nRF52840_xxAA$SVD\nrf52840.svd</SFDFile>
<SFDFile>$$Device:MAX32660$SVD\MAX32660\max32660.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
@@ -110,11 +110,11 @@
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
@@ -245,12 +245,12 @@
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x40000</Size>
<Size>0x18000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x100000</Size>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
@@ -275,7 +275,7 @@
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x100000</Size>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
@@ -300,7 +300,7 @@
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x40000</Size>
<Size>0x18000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
@@ -315,7 +315,7 @@
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
@@ -336,7 +336,7 @@
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--reduce_paths</MiscControls>
<Define>BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S140 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74</Define>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
@@ -372,7 +372,7 @@
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc>--diag_suppress 6330</Misc>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>

24
bsp/maxim/libraries/CMSIS/RTE_Components.h Normal file
View File

@@ -0,0 +1,24 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'Hello_World'
* Target: 'Debug'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "max32660.h"
#define BOARD EvKit_V1 /* Target Board */
#define RTE_USING_FINSH
#define TARGET 32660 /* Target Device Part Number */
#define TARGET_REV 0x4131 /* Target Device Revision Number */
#endif /* RTE_COMPONENTS_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**
* @file max32660.h
* @brief Device-specific perhiperal header file
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#ifndef _MAX32660_REGS_H_
#define _MAX32660_REGS_H_
#ifndef TARGET_NUM
#define TARGET_NUM 32660
#endif
#include <stdint.h>
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
#if !defined (__GNUC__)
#define CMSIS_VECTAB_VIRTUAL
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
#endif /* !__GNUC__ */
/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
#if defined ( __GNUC__ ) /* GCC */
#define __weak __attribute__((weak))
#elif defined ( __CC_ARM) /* Keil */
#define inline __inline
#pragma anon_unions
#endif
typedef enum {
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
/* Device-specific interrupt sources (external to ARM core) */
/* table entry number */
/* |||| */
/* |||| table offset address */
/* vvvv vvvvvv */
PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */
RTC_IRQn, /* 0x13 0x004C 19: RTC */
RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */
TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */
RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */
RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */
RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */
RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */
I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
SPI17Y_IRQn, /* 0x20 0x0080 32: SPI17Y */
SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */
RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */
RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */
RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */
RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */
RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */
FLC_IRQn, /* 0x27 0x009C 39: FLC */
GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */
RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */
RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */
DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */
RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */
RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */
RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */
I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */
RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */
RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */
RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */
RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */
RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */
RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */
RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */
RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */
RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */
RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */
RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */
RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */
RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */
RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */
RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */
RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */
GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
MXC_IRQ_EXT_COUNT,
} IRQn_Type;
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present or not */
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_max32660.h" /*!< System Header */
/* ================================================================================ */
/* ================== Device Specific Memory Section ================== */
/* ================================================================================ */
#define MXC_FLASH_MEM_BASE 0x00000000UL
#define MXC_FLASH_PAGE_SIZE 0x00002000UL
#define MXC_FLASH_MEM_SIZE 0x00040000UL
#define MXC_INFO_MEM_BASE 0x00040000UL
#define MXC_INFO_MEM_SIZE 0x00001000UL
#define MXC_SRAM_MEM_BASE 0x20000000UL
#define MXC_SRAM_MEM_SIZE 0x00018000UL
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/*
Base addresses and configuration settings for all MAX32660 peripheral modules.
*/
/******************************************************************************/
/* Global control */
#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
/******************************************************************************/
/* Non-battery backed SI Registers */
#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
/******************************************************************************/
/* Watchdog */
#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
/******************************************************************************/
/* Real Time Clock */
#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
/******************************************************************************/
/* Power Sequencer */
#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
/******************************************************************************/
/* GPIO */
#define MXC_CFG_GPIO_INSTANCES (1)
#define MXC_CFG_GPIO_PINS_PORT (14)
#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1)
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0)
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0)
/******************************************************************************/
/* Timer */
#define MXC_CFG_TMR_INSTANCES (3)
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
(i) == 1 ? TMR1_IRQn : \
(i) == 2 ? TMR2_IRQn : 0)
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
(i) == 1 ? MXC_BASE_TMR1 : \
(i) == 2 ? MXC_BASE_TMR2 : 0)
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
(i) == 1 ? MXC_TMR1 : \
(i) == 2 ? MXC_TMR2 : 0)
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
(p) == MXC_TMR1 ? 1 : \
(p) == MXC_TMR2 ? 2 : -1)
/******************************************************************************/
/* SPIMSS */
#define MXC_SPIMSS_INSTANCES (1)
#define MXC_SPIMSS_FIFO_DEPTH (8)
#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL)
#define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS)
#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1)
#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0)
/******************************************************************************/
/* I2C */
#define MXC_I2C_INSTANCES (2)
#define MXC_I2C_FIFO_DEPTH (8)
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
(i) == 1 ? I2C1_IRQn : 0)
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
(i) == 1 ? MXC_BASE_I2C1 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
(i) == 1 ? MXC_I2C1 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
(p) == MXC_I2C1 ? 1 : -1)
/******************************************************************************/
/* DMA */
#define MXC_DMA_CHANNELS (4)
#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA)
/******************************************************************************/
/* FLC */
#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC)
/******************************************************************************/
/* Instruction Cache */
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC)
/******************************************************************************/
/* UART / Serial Port Interface */
#define MXC_UART_INSTANCES (2)
#define MXC_UART_FIFO_DEPTH (8)
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
(i) == 1 ? UART1_IRQn : 0)
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
(i) == 1 ? MXC_BASE_UART1 : 0)
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
(i) == 1 ? MXC_UART1 : 0)
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
(p) == MXC_UART1 ? 1 : -1)
/******************************************************************************/
/* SPI */
#define MXC_SPI17Y_INSTANCES (4)
#define MXC_SPI17Y_SS_INSTANCES (1)
#define MXC_SPI17Y_FIFO_DEPTH (32)
#define MXC_BASE_SPI17Y ((uint32_t)0x40046000UL)
#define MXC_SPI17Y ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y)
#define MXC_SPI17Y_GET_IDX(p) ((p) == MXC_SPI17Y ? 0 : -1)
#define MXC_SPI17Y_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI17Y : 0)
#define MXC_SPI17Y_GET_SPI17Y(i) ((i) == 0 ? MXC_SPI17Y : 0)
/******************************************************************************/
/* Bit Shifting */
#define MXC_F_BIT_0 (1 << 0)
#define MXC_F_BIT_1 (1 << 1)
#define MXC_F_BIT_2 (1 << 2)
#define MXC_F_BIT_3 (1 << 3)
#define MXC_F_BIT_4 (1 << 4)
#define MXC_F_BIT_5 (1 << 5)
#define MXC_F_BIT_6 (1 << 6)
#define MXC_F_BIT_7 (1 << 7)
#define MXC_F_BIT_8 (1 << 8)
#define MXC_F_BIT_9 (1 << 9)
#define MXC_F_BIT_10 (1 << 10)
#define MXC_F_BIT_11 (1 << 11)
#define MXC_F_BIT_12 (1 << 12)
#define MXC_F_BIT_13 (1 << 13)
#define MXC_F_BIT_14 (1 << 14)
#define MXC_F_BIT_15 (1 << 15)
#define MXC_F_BIT_16 (1 << 16)
#define MXC_F_BIT_17 (1 << 17)
#define MXC_F_BIT_18 (1 << 18)
#define MXC_F_BIT_19 (1 << 19)
#define MXC_F_BIT_20 (1 << 20)
#define MXC_F_BIT_21 (1 << 21)
#define MXC_F_BIT_22 (1 << 22)
#define MXC_F_BIT_23 (1 << 23)
#define MXC_F_BIT_24 (1 << 24)
#define MXC_F_BIT_25 (1 << 25)
#define MXC_F_BIT_26 (1 << 26)
#define MXC_F_BIT_27 (1 << 27)
#define MXC_F_BIT_28 (1 << 28)
#define MXC_F_BIT_29 (1 << 29)
#define MXC_F_BIT_30 (1 << 30)
#define MXC_F_BIT_31 (1 << 31)
/******************************************************************************/
/* Bit Banding */
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask))
/******************************************************************************/
/* SCB CPACR */
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
#endif /* _MAX32660_REGS_H_ */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.1.1
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
(((MPU_RASR_ENABLE_Msk))))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if shareable) or 010b (if non-shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/**
* @file mxc_config.h
* @brief Top-level include file for device configuration.
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
******************************************************************************/
#ifndef _MXC_CONFIG_H
#define _MXC_CONFIG_H
#if !defined __GNUC__
#include "RTE_Components.h"
#endif /* not __GNUC__ */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_pins.h"
#endif /* _CONFIG_H */

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a
; copy of this software and associated documentation files (the "Software"),
; to deal in the Software without restriction, including without limitation
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
; and/or sell copies of the Software, and to permit persons to whom the
; Software is furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included
; in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
; OTHER DEALINGS IN THE SOFTWARE.
;
; Except as contained in this notice, the name of Maxim Integrated
; Products, Inc. shall not be used except as stated in the Maxim Integrated
; Products, Inc. Branding Policy.
;
; The mere transfer of this software does not imply any licenses
; of trade secrets, proprietary technology, copyrights, patents,
; trademarks, maskwork rights, or any other form of intellectual
; property whatsoever. Maxim Integrated Products, Inc. retains all
; ownership rights.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; To map FreeRTOS function names to their CMSIS equivalents add following lines to FreeRTOSConfig.h
; #define vPortSVCHandler SVC_Handler
; #define xPortPendSVHandler PendSV_Handler
; #define xPortSysTickHandler SysTick_Handler
; *------- <<< Use Configuration Wizard in Context Menu to Modify Stack Size and Heap Size. >>> ----
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp ; Name used with Keil Configuration Wizard and Keil MicroLib
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
EXPORT __isr_vector
IMPORT SysTick_Handler
__isr_vector DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Device-specific Interrupts
DCD PF_IRQHandler ; 0x10 0x0040 16: Power Fail
DCD WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0
DCD RSV00_IRQHandler ; 0x12 0x0048 18: RSV00
DCD RTC_IRQHandler ; 0x13 0x004C 19: RTC
DCD RSV01_IRQHandler ; 0x14 0x0050 20: RSV1
DCD TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0
DCD TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1
DCD TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2
DCD RSV02_IRQHandler ; 0x18 0x0060 24: RSV02
DCD RSV03_IRQHandler ; 0x19 0x0064 25: RSV03
DCD RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04
DCD RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05
DCD RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06
DCD I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0
DCD UART0_IRQHandler ; 0x1E 0x0078 30: UART 0
DCD UART1_IRQHandler ; 0x1F 0x007C 31: UART 1
DCD SPI0_IRQHandler ; 0x20 0x0080 32: SPIY17
DCD SPI1_IRQHandler ; 0x21 0x0084 33: SPIMSS
DCD RSV07_IRQHandler ; 0x22 0x0088 34: RSV07
DCD RSV08_IRQHandler ; 0x23 0x008C 35: RSV08
DCD RSV09_IRQHandler ; 0x24 0x0090 36: RSV09
DCD RSV10_IRQHandler ; 0x25 0x0094 37: RSV10
DCD RSV11_IRQHandler ; 0x26 0x0098 38: RSV11
DCD FLC_IRQHandler ; 0x27 0x009C 39: FLC
DCD GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0
DCD RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12
DCD RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13
DCD RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14
DCD DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0
DCD DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1
DCD DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2
DCD DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3
DCD RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15
DCD RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16
DCD RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17
DCD RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18
DCD I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1
DCD RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19
DCD RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20
DCD RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21
DCD RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22
DCD RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23
DCD RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24
DCD RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25
DCD RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26
DCD RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27
DCD RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28
DCD RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29
DCD RSV30_IRQHandler ; 0x40 0x0100 64: RSV30
DCD RSV31_IRQHandler ; 0x41 0x0104 65: RSV31
DCD RSV32_IRQHandler ; 0x42 0x0108 66: RSV32
DCD RSV33_IRQHandler ; 0x43 0x010C 67: RSV33
DCD RSV34_IRQHandler ; 0x44 0x0110 68: RSV34
DCD RSV35_IRQHandler ; 0x45 0x0114 69: RSV35
DCD GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup
__isr_vector_end
__isr_vector_size EQU __isr_vector_end - __isr_vector
__Vectors EQU __isr_vector
__Vectors_End EQU __isr_vector_end
__Vectors_Size EQU __isr_vector_size
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT PreInit
;IMPORT SystemInit
IMPORT __main
LDR R0, =PreInit ; Call to PreInit (prior to RAM initialization)
BLX R0
LDR R0, =__main ; SystemInit() is called from post scatter memory initialization in function $Sub$$__main_after_scatterload - system_max32660.c
BX R0
__SPIN
WFI
BL __SPIN
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
Default_Handler\
PROC
; MAX32660 Device-specific Interrupts
EXPORT PF_IRQHandler [WEAK] ; 0x10 0x0040 16: Power Fail
EXPORT WDT0_IRQHandler [WEAK] ; 0x11 0x0044 17: Watchdog 0
EXPORT RSV00_IRQHandler [WEAK] ; 0x12 0x0048 18: RSV00
EXPORT RTC_IRQHandler [WEAK] ; 0x13 0x004C 19: RTC
EXPORT RSV01_IRQHandler [WEAK] ; 0x14 0x0050 20: RSV01
EXPORT TMR0_IRQHandler [WEAK] ; 0x15 0x0054 21: Timer 0
EXPORT TMR1_IRQHandler [WEAK] ; 0x16 0x0058 22: Timer 1
EXPORT TMR2_IRQHandler [WEAK] ; 0x17 0x005C 23: Timer 2
EXPORT RSV02_IRQHandler [WEAK] ; 0x18 0x0060 24: RSV02
EXPORT RSV03_IRQHandler [WEAK] ; 0x19 0x0064 25: RSV03
EXPORT RSV04_IRQHandler [WEAK] ; 0x1A 0x0068 26: RSV04
EXPORT RSV05_IRQHandler [WEAK] ; 0x1B 0x006C 27: RSV05
EXPORT RSV06_IRQHandler [WEAK] ; 0x1C 0x0070 28: RSV06
EXPORT I2C0_IRQHandler [WEAK] ; 0x1D 0x0074 29: I2C0
EXPORT UART0_IRQHandler [WEAK] ; 0x1E 0x0078 30: UART 0
EXPORT UART1_IRQHandler [WEAK] ; 0x1F 0x007C 31: UART 1
EXPORT SPI0_IRQHandler [WEAK] ; 0x20 0x0080 32: SPIY17
EXPORT SPI1_IRQHandler [WEAK] ; 0x21 0x0084 33: SPIMSS
EXPORT RSV07_IRQHandler [WEAK] ; 0x22 0x0088 34: RSV07
EXPORT RSV08_IRQHandler [WEAK] ; 0x23 0x008C 35: RSV08
EXPORT RSV09_IRQHandler [WEAK] ; 0x24 0x0090 36: RSV09
EXPORT RSV10_IRQHandler [WEAK] ; 0x25 0x0094 37: RSV10
EXPORT RSV11_IRQHandler [WEAK] ; 0x26 0x0098 38: RSV11
EXPORT FLC_IRQHandler [WEAK] ; 0x27 0x009C 39: FLC
EXPORT GPIO0_IRQHandler [WEAK] ; 0x28 0x00A0 40: GPIO0
EXPORT RSV12_IRQHandler [WEAK] ; 0x29 0x00A4 41: RSV12
EXPORT RSV13_IRQHandler [WEAK] ; 0x2A 0x00A8 42: RSV13
EXPORT RSV14_IRQHandler [WEAK] ; 0x2B 0x00AC 43: RSV14
EXPORT DMA0_IRQHandler [WEAK] ; 0x2C 0x00B0 44: DMA0
EXPORT DMA1_IRQHandler [WEAK] ; 0x2D 0x00B4 45: DMA1
EXPORT DMA2_IRQHandler [WEAK] ; 0x2E 0x00B8 46: DMA2
EXPORT DMA3_IRQHandler [WEAK] ; 0x2F 0x00BC 47: DMA3
EXPORT RSV15_IRQHandler [WEAK] ; 0x30 0x00C0 48: RSV15
EXPORT RSV16_IRQHandler [WEAK] ; 0x31 0x00C4 49: RSV16
EXPORT RSV17_IRQHandler [WEAK] ; 0x32 0x00C8 50: RSV17
EXPORT RSV18_IRQHandler [WEAK] ; 0x33 0x00CC 51: RSV18
EXPORT I2C1_IRQHandler [WEAK] ; 0x34 0x00D0 52: I2C1
EXPORT RSV19_IRQHandler [WEAK] ; 0x35 0x00D4 53: RSV19
EXPORT RSV20_IRQHandler [WEAK] ; 0x36 0x00D8 54: RSV20
EXPORT RSV21_IRQHandler [WEAK] ; 0x37 0x00DC 55: RSV21
EXPORT RSV22_IRQHandler [WEAK] ; 0x38 0x00E0 56: RSV22
EXPORT RSV23_IRQHandler [WEAK] ; 0x39 0x00E4 57: RSV23
EXPORT RSV24_IRQHandler [WEAK] ; 0x3A 0x00E8 58: RSV24
EXPORT RSV25_IRQHandler [WEAK] ; 0x3B 0x00EC 59: RSV25
EXPORT RSV26_IRQHandler [WEAK] ; 0x3C 0x00F0 60: RSV26
EXPORT RSV27_IRQHandler [WEAK] ; 0x3D 0x00F4 61: RSV27
EXPORT RSV28_IRQHandler [WEAK] ; 0x3E 0x00F8 62: RSV28
EXPORT RSV29_IRQHandler [WEAK] ; 0x3F 0x00FC 63: RSV29
EXPORT RSV30_IRQHandler [WEAK] ; 0x40 0x0100 64: RSV30
EXPORT RSV31_IRQHandler [WEAK] ; 0x41 0x0104 65: RSV31
EXPORT RSV32_IRQHandler [WEAK] ; 0x42 0x0108 66: RSV32
EXPORT RSV33_IRQHandler [WEAK] ; 0x43 0x010C 67: RSV33
EXPORT RSV34_IRQHandler [WEAK] ; 0x44 0x0110 68: RSV34
EXPORT RSV35_IRQHandler [WEAK] ; 0x45 0x0114 69: RSV35
EXPORT GPIOWAKE_IRQHandler [WEAK] ; 0x46 0x0118 70: GPIO Wakeup
;*******************************************************************************
; Default handler implementations
;*******************************************************************************
PF_IRQHandler ; 0x10 0x0040 16: Power Fail
WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0
RSV00_IRQHandler ; 0x12 0x0048 18: RSV00
RTC_IRQHandler ; 0x13 0x004C 19: RTC
RSV01_IRQHandler ; 0x14 0x0050 20: RSV01
TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0
TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1
TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2
RSV02_IRQHandler ; 0x18 0x0060 24: RSV02
RSV03_IRQHandler ; 0x19 0x0064 25: RSV03
RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04
RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05
RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06
I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0
UART0_IRQHandler ; 0x1E 0x0078 30: UART 0
UART1_IRQHandler ; 0x1F 0x007C 31: UART 1
SPI0_IRQHandler ; 0x20 0x0080 32: SPI0
SPI1_IRQHandler ; 0x21 0x0084 33: SPI1
RSV07_IRQHandler ; 0x22 0x0088 34: RSV07
RSV08_IRQHandler ; 0x23 0x008C 35: RSV08
RSV09_IRQHandler ; 0x24 0x0090 36: RSV09
RSV10_IRQHandler ; 0x25 0x0094 37: RSV10
RSV11_IRQHandler ; 0x26 0x0098 38: RSV11
FLC_IRQHandler ; 0x27 0x009C 39: FLC
GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0
RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12
RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13
RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14
DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0
DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1
DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2
DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3
RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15
RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16
RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17
RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18
I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1
RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19
RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20
RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21
RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22
RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23
RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24
RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25
RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26
RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27
RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28
RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29
RSV30_IRQHandler ; 0x40 0x0100 64: RSV30
RSV31_IRQHandler ; 0x41 0x0104 65: RSV31
RSV32_IRQHandler ; 0x42 0x0108 66: RSV32
RSV33_IRQHandler ; 0x43 0x010C 67: RSV33
RSV34_IRQHandler ; 0x44 0x0110 68: RSV34
RSV35_IRQHandler ; 0x45 0x0114 69: RSV35
GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap\
PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
;;;;;;;;;;;;;;;;;;;;;;;;;
;; End of file.
;;;;;;;;;;;;;;;;;;;;;;;;;

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/**
* @file system_max32660.c
* @brief System-level initialization implementation file
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include "max32660.h"
#include "gcr_regs.h"
#include "pwrseq_regs.h"
#include "tmr_regs.h"
#include "wdt_regs.h"
#include "mxc_sys.h"
extern void (* const __isr_vector[])(void);
uint32_t SystemCoreClock = HIRC96_FREQ;
__weak void SystemCoreClockUpdate(void)
{
uint32_t base_freq, div, clk_src,ovr;
// Get the clock source and frequency
clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL);
if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_HFXIN) {
base_freq = HFX_FREQ;
} else {
if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_NANORING) {
base_freq = NANORING_FREQ;
} else {
ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
base_freq = HIRC96_FREQ/4;
} else {
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
base_freq = HIRC96_FREQ/2;
} else {
base_freq = HIRC96_FREQ;
}
}
}
}
// Get the clock divider
div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
SystemCoreClock = base_freq >> div;
}
/* This function is called before C runtime initialization and can be
* implemented by the application for early initializations. If a value other
* than '0' is returned, the C runtime initialization will be skipped.
*
* You may over-ride this function in your program by defining a custom
* PreInit(), but care should be taken to reproduce the initilization steps
* or a non-functional system may result.
*/
__weak int PreInit(void)
{
/* Do nothing */
return 0;
}
/* This function can be implemented by the application to initialize the board */
__weak int Board_Init(void)
{
/* Do nothing */
return 0;
}
/* This function is called just before control is transferred to main().
*
* You may over-ride this function in your program by defining a custom
* SystemInit(), but care should be taken to reproduce the initialization
* steps or a non-functional system may result.
*/
__weak void SystemInit(void)
{
/* Configure the interrupt controller to use the application vector table in */
/* the application space */
/* IAR & Keil must set vector table after all memory initialization. */
SCB->VTOR = (unsigned long)__isr_vector;
MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
__DSB();
__ISB();
/* Switch system clock to HIRC */
SYS_Clock_Select(SYS_CLOCK_HIRC, MXC_TMR0);
/* Disable clocks to peripherals by default to reduce power */
SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA);
SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y);
SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0);
SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1);
SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0);
SYS_ClockDisable(SYS_PERIPH_CLOCK_T0);
SYS_ClockDisable(SYS_PERIPH_CLOCK_T1);
SYS_ClockDisable(SYS_PERIPH_CLOCK_T2);
SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1);
Board_Init();
}
#if defined ( __CC_ARM )
/* Global variable initialization does not occur until post scatterload in Keil tools.*/
/* External function called after our post scatterload function implementation. */
extern void $Super$$__main_after_scatterload(void);
/**
* @brief Initialization function for SystemCoreClock and Board_Init.
* @details $Sub$$__main_after_scatterload is called during system startup in the Keil
* toolset. Global variable and static variable space must be set up by the compiler
* prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
* require global memory for variable storage and are called from this function in
* the Keil tool chain.
*/
void $Sub$$__main_after_scatterload(void)
{
SystemInit();
$Super$$__main_after_scatterload();
}
#endif /* __CC_ARM */

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/**
* @file system_max32660.h
* @brief System-specific header file
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#ifndef _SYSTEM_MAX32660_H_
#define _SYSTEM_MAX32660_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifndef HFX_FREQ
#define HFX_FREQ 32768
#endif
#ifndef NANORING_FREQ
#define NANORING_FREQ 8000
#endif
#ifndef HIRC96_FREQ
#define HIRC96_FREQ 96000000
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
#ifndef PeripheralClock
#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */
#endif
/*
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void);
/*
* Update SystemCoreClock variable
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MAX32660_H_ */

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/**
* @file
* @brief Direct Memory Access (DMA) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $
* $Revision: 44383 $
*
*************************************************************************** */
#ifndef _DMA_H_
#define _DMA_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "dma_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup dma Direct Memory Access (DMA)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* Enumeration for the DMA Channel's priority level.
*/
typedef enum {
DMA_PRIO_HIGH = MXC_S_DMA_CFG_PRI_HIGH, /**< High Priority */
DMA_PRIO_MEDHIGH = MXC_S_DMA_CFG_PRI_MEDHIGH, /**< Medium High Priority */
DMA_PRIO_MEDLOW = MXC_S_DMA_CFG_PRI_MEDLOW, /**< Medium Low Priority */
DMA_PRIO_LOW = MXC_S_DMA_CFG_PRI_LOW, /**< Low Priority */
} dma_priority_t;
/** @brief DMA request select */
typedef enum {
DMA_REQSEL_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, /**< Memory to Memory DMA Request Selection */
DMA_REQSEL_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, /**< SPI0 Receive DMA Request Selection */
DMA_REQSEL_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, /**< SPI1 Receive DMA Request Selection */
DMA_REQSEL_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, /**< UART0 Receive DMA Request Selection */
DMA_REQSEL_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, /**< UART1 Receive DMA Request Selection */
DMA_REQSEL_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, /**< I2C0 Receive DMA Request Selection */
DMA_REQSEL_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, /**< I2C1 Receive DMA Request Selection */
DMA_REQSEL_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, /**< SPI0 Transmit DMA Request Selection */
DMA_REQSEL_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, /**< SPI1 Transmit DMA Request Selection */
DMA_REQSEL_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, /**< UART0 Transmit DMA Request Selection */
DMA_REQSEL_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, /**< UART1 Transmit DMA Request Selection */
DMA_REQSEL_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, /**< I2C0 Transmit DMA Request Selection */
DMA_REQSEL_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, /**< I2C1 Transmit DMA Request Selection */
} dma_reqsel_t;
/** @brief Enumeration for the DMA prescaler */
typedef enum {
DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, /**< Prescaler disabled */
DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, /**< Divide by 256 */
DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, /**< Divide by 65,536 */
DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, /**< Divide by 16,777,216 */
} dma_prescale_t;
/** @brief Enumeration for the DMA timeout value */
typedef enum {
DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, /**< DMA timeout of 4 clocks */
DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, /**< DMA timeout of 8 clocks */
DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, /**< DMA timeout of 16 clocks */
DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, /**< DMA timeout of 32 clocks */
DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, /**< DMA timeout of 64 clocks */
DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, /**< DMA timeout of 128 clocks */
DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, /**< DMA timeout of 256 clocks */
DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, /**< DMA timeout of 512 clocks */
} dma_timeout_t;
/** @brief DMA transfer data width */
typedef enum {
/* Using the '_V_' define instead of the '_S_' since these same values will be used to
specify the DSTWD also. The API functions will shift the value the correct amount
prior to writing the cfg register. */
DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, /**< DMA transfer in bytes */
DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, /**< DMA transfer in 16-bit half-words */
DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, /**< DMA transfer in 32-bit words */
} dma_width_t;
/** @brief Convenience defines for options */
#define DMA_FALSE 0 /**< Define for passing 0 to DMA functions */
#define DMA_TRUE 1 /**< Define for passing 1 to DMA functions */
/* **** Function Prototypes **** */
/**
* @brief Initialize DMA resources
* @details This initialization is required before using the DMA driver functions.
* @return #E_NO_ERROR if successful
*/
int DMA_Init(void);
/**
* @brief Request DMA channel
* @details Returns a handle to the first free DMA channel, which can be used via API calls
* or direct access to channel registers using the DMA_GetCHRegs(int ch) function.
* @return Non-negative channel handle (inclusive of zero).
* @return #E_NONE_AVAIL All channels in use.
* @return #E_BAD_STATE DMA is not initialized, call DMA_Init() first.
* @return #E_BUSY DMA is currently busy (locked), try again later.
*/
int DMA_AcquireChannel(void);
/**
* @brief Release DMA channel
* @details Stops any DMA operation on the channel and returns it to the pool of free channels.
*
* @param ch channel handle to release
*
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int DMA_ReleaseChannel(int ch);
/**
* @brief Configure the DMA channel
* @details Configures the channel, which was previously requested by DMA_Getchannel()
*
* @param ch The channel to configure
* @param prio The channel's priority
* @param reqsel Select the DMA request line
* @param reqwait_en The enable delay before request
* @param tosel The transfer timer timeout select
* @param pssel The transfer timer prescale select
* @param srcwd The size of the read transactions
* @param srcinc_en Enable auto-increment source pointer
* @param dstwd The size of write transactions
* @param dstinc_en Enable auto-increment destination pointer
* @param burst_size The number of bytes transferred in one transaction
* @param chdis_inten The channel disable interrupt enable
* @param ctz_inten The count-to-zero interrupt enable
*
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_ConfigChannel(int ch,
dma_priority_t prio,
dma_reqsel_t reqsel, unsigned int reqwait_en,
dma_timeout_t tosel, dma_prescale_t pssel,
dma_width_t srcwd, unsigned int srcinc_en,
dma_width_t dstwd, unsigned int dstinc_en,
unsigned int burst_size, unsigned int chdis_inten,
unsigned int ctz_inten);
/**
* @brief Set channel source, destination, and count for transfer
* @param ch channel handle
* @param src_addr source address (*)
* @param dst_addr destination address (*)
* @param count number of bytes to transfer
* @details This function is used to set the source and destination addresses and the number
* of bytes to transfer using the channel, @p ch.
* @note Unless the channel request select is #DMA_REQSEL_MEMTOMEM,
* either src_addr or dst_addr will be ignored by the DMA engine.
* In these cases, the address is a don't-care. See the User's
* Guide for more information.
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_SetSrcDstCnt(int ch,
void *src_addr,
void *dst_addr,
unsigned int count);
/**
* @brief Set channel reload values
* @param ch channel handle
* @param src_addr_reload source address
* @param dst_addr_reload destination address
* @param count_reload number of bytes to transfer
* @details This function will set the values which will be loaded after the
* channel count register reaches zero. After enabling, call with
* count_reload set to zero to disable reload.
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_SetReload(int ch,
void *src_addr_reload,
void *dst_addr_reload,
unsigned int count_reload);
/**
* @brief Set channel interrupt callback
* @param ch channel handle
* @param callback Pointer to a function to call when the channel
* interrupt flag is set and interrupts are enabled or
* when DMA is shutdown by the driver.
* @details Configures the channel interrupt callback. The @p callback
* function is called for two conditions:
* -# When the channel's interrupt flag is set and DMA interrupts
* are enabled.
* -# If the driver calls the DMA_Shutdown() function. The
* callback function prototype is:
* @code
* void callback_fn(int ch, int reason);
* @endcode
* @p ch indicates the channel that generated the callback, @p
* reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN
* if the DMA is being shutdown.
*
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_SetCallback(int ch, void (*callback)(int, int));
/**
* @brief Enable channel interrupt
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_EnableInterrupt(int ch);
/**
* @brief Disable channel interrupt
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_DisableInterrupt(int ch);
/**
* @brief Read channel interrupt flags
* @param ch channel handle
* @param fl flags to get
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_GetFlags(int ch, unsigned int *fl);
/**
* @brief Clear channel interrupt flags
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_ClearFlags(int ch);
/**
* @brief Start transfer
* @param ch channel handle
* @details Start the DMA channel transfer, assumes that DMA_SetSrcDstCnt() has been called beforehand.
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_Start(int ch);
/**
* @brief Stop DMA transfer, irrespective of status (complete or in-progress)
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_Stop(int ch);
/**
* @brief Get a pointer to the DMA channel registers
* @param ch channel handle
* @details If direct access to DMA channel registers is required, this
* function can be used on a channel handle returned by DMA_AcquireChannel().
* @return NULL if an unused or invalid channel handle, or a valid pointer otherwise
*/
mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch);
/**
* @brief Interrupt handler function
* @param ch channel handle
* @details Call this function as the ISR for each DMA channel under driver control.
* Interrupt flags for channel ch will be automatically cleared before return.
* @return NULL if an unused or invalid channel handle, or a valid pointer otherwise
*/
void DMA_Handler(int ch);
/**@} end of group dma */
#ifdef __cplusplus
}
#endif
#endif /* _DMA_H_ */

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/**
* @file
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
* $Revision: 43696 $
*
*************************************************************************** */
#ifndef _FLC_H_
#define _FLC_H_
/* **** Includes **** */
#include "flc_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup flc Flash Controller
* @ingroup periphlibs
* @{
*/
/***** Definitions *****/
/// Bit mask that can be used to find the starting address of a page in flash
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
/// Calculate the address of a page in flash from the page number
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
/***** Function Prototypes *****/
/**
* @brief Initializes the flash controller for erase/write operations
* @param sys_cfg Reserved for future use. Use NULL as this parameter's value.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_Init(const sys_cfg_flc_t *sys_cfg);
/**
* @brief Checks if Flash controller is busy.
* @details Reading or executing from flash is not possible if flash is busy
* with an erase or write operation.
* @return If non-zero, flash operation is in progress
*/
int FLC_Busy(void);
/**
* @brief Erases the entire flash array.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_MassErase(void);
/**
* @brief Erases the page of flash at the specified address.
* @param address Any address within the page to erase.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_PageErase(uint32_t address);
/**
* @brief Page erase from start to end address.
* @note All data within the selected pages will be erased.
* @param start Any address within the first page to erase.
* @param end Any address within the last page to erase.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_Erase(uint32_t start, uint32_t end);
/**
* @brief Erase from start to end address. Restoring any flash page contents outside the given range.
* @param start Starting address to erase, inclusive.
* @param end Ending address to erase, exclusive.
* @param buffer Data buffer to restore data in beginning and ending pages.
* @param length Length of given buffer.
*
* @note Buffer should be appropriate size to store all of the data remaining in the
* first and last pages. length should be greater than or equal to
* (start % MXC_FLASH_PAGE_SIZE) and ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE).
*
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length);
/**
* @brief Writes the specified 32-bit value to flash.
* @param address 32-bit aligned address in flash to write.
* @param data value to be written to flash.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_Write32(uint32_t address, uint32_t data);
/**
* @brief Writes the specified 128-bits of data to flash.
* @param address 128-bit aligned address in flash to write.
* @param data pointer to data to be written to flash.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_Write128(uint32_t address, uint32_t *data);
/**
* @brief Writes data to flash.
* @param address Address in flash to start writing from.
* @param length Number of bytes to be written.
* @param buffer Pointer to data to be written to flash.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer);
/**
* @brief Enable flash interrupts
* @param mask Interrupts to enable
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_EnableInt(uint32_t mask);
/**
* @brief Disable flash interrupts
* @param mask Interrupts to disable
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_DisableInt(uint32_t mask);
/**
* @brief Retrieve flash interrupt flags
* @return Mask of active flags.
*/
int FLC_GetFlags(void);
/**
* @brief Clear flash interrupt flags
* @note Provide the bit position to clear, even if the flag is write-0-to-clear
* @param mask Mask of flags to clear
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_ClearFlags(uint32_t mask);
/**
* @brief Unlock info block
*
* @return #E_NO_ERROR If function is successful.
*/
int FLC_UnlockInfoBlock(void);
/**
* @brief Lock info block
*
* @return #E_NO_ERROR If function is successful.
*/
int FLC_LockInfoBlock(void);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_H_ */

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/**
* @file gpio.h
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _GPIO_H_
#define _GPIO_H_
/* **** Includes **** */
#include "gpio_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup gpio General-Purpose Input/Output (GPIO)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* @defgroup gpio_port_pin Port and Pin Definitions
* @ingroup gpio
* @{
* @defgroup gpio_port Port Definitions
* @ingroup gpio_port_pin
* @{
*/
#define PORT_0 ((uint32_t)(0UL)) /**< Port 0 Define*/
#define PORT_1 ((uint32_t)(1UL)) /**< Port 1 Define*/
#define PORT_2 ((uint32_t)(2UL)) /**< Port 2 Define*/
#define PORT_3 ((uint32_t)(3UL)) /**< Port 3 Define*/
#define PORT_4 ((uint32_t)(4UL)) /**< Port 4 Define*/
/**@} end of gpio_port group*/
/**
* @defgroup gpio_pin Pin Definitions
* @ingroup gpio_port_pin
* @{
*/
#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */
#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */
#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */
#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */
#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */
#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */
#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */
#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */
#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */
#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */
#define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */
#define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */
#define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */
#define PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */
#define PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */
#define PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */
#define PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */
#define PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */
#define PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */
#define PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */
#define PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */
#define PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */
#define PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */
#define PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */
#define PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */
#define PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */
#define PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */
#define PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */
#define PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */
#define PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */
#define PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */
#define PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */
/**@} end of gpio_pin group */
/**@} end of gpio_port_pin group */
/**
* Enumeration type for the GPIO Function Type
*/
typedef enum {
GPIO_FUNC_IN, /**< GPIO Input */
GPIO_FUNC_OUT, /**< GPIO Output */
GPIO_FUNC_ALT1, /**< Alternate Function Selection */
GPIO_FUNC_ALT2, /**< Alternate Function Selection */
GPIO_FUNC_ALT3, /**< Alternate Function Selection */
GPIO_FUNC_ALT4, /**< Alternate Function Selection */
} gpio_func_t;
/**
* Enumeration type for the type of GPIO pad on a given pin.
*/
typedef enum {
GPIO_PAD_NONE, /**< No pull-up or pull-down */
GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */
GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */
} gpio_pad_t;
/**
* Structure type for configuring a GPIO port.
*/
typedef struct {
uint32_t port; /**< Index of GPIO port */
uint32_t mask; /**< Pin mask (multiple pins may be set) */
gpio_func_t func; /**< Function type */
gpio_pad_t pad; /**< Pad type */
} gpio_cfg_t;
/**
* Enumeration type for the interrupt modes.
*/
typedef enum {
GPIO_INT_LEVEL = 0, /**< Interrupt is level sensitive */
GPIO_INT_EDGE = 1 /**< Interrupt is edge sensitive */
} gpio_int_mode_t;
/**
* Enumeration type for the interrupt polarity.
*/
typedef enum {
GPIO_INT_FALLING = 0, /**< Interrupt triggers on falling edge */
GPIO_INT_HIGH = GPIO_INT_FALLING, /**< Interrupt triggers when level is high */
GPIO_INT_RISING, /**< Interrupt triggers on rising edge */
GPIO_INT_LOW = GPIO_INT_RISING, /**< Interrupt triggers when level is low */
GPIO_INT_BOTH /**< Interrupt triggers on either edge */
} gpio_int_pol_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize GPIO.
* @return #E_NO_ERROR if everything is successful.
*/
int GPIO_Init(void);
/**
* @brief Configure GPIO pin(s).
* @param cfg Pointer to configuration structure describing the pin.
* @return #E_NO_ERROR if everything is successful.
*/
int GPIO_Config(const gpio_cfg_t *cfg);
/**
* @brief Gets the pin(s) input state.
* @param cfg Pointer to configuration structure describing the pin.
* @return The requested pin state.
*/
uint32_t GPIO_InGet(const gpio_cfg_t *cfg);
/**
* @brief Sets the pin(s) to a high level output.
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_OutSet(const gpio_cfg_t *cfg);
/**
* @brief Clears the pin(s) to a low level output.
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_OutClr(const gpio_cfg_t *cfg);
/**
* @brief Gets the pin(s) output state.
* @param cfg Pointer to configuration structure describing the pin.
*
* @return The state of the requested pin.
*
*/
uint32_t GPIO_OutGet(const gpio_cfg_t *cfg);
/**
* @brief Write the pin(s) to a desired output level.
* @param cfg Pointer to configuration structure describing the pin.
* @param val Desired output level of the pin(s). This will be masked
* with the configuration mask.
*/
void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val);
/**
* @brief Toggles the the pin(s) output level.
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_OutToggle(const gpio_cfg_t *cfg);
/**
* @brief Configure GPIO interrupt(s)
* @param cfg Pointer to configuration structure describing the pin.
* @param mode Requested interrupt mode.
* @param pol Requested interrupt polarity.
* @return #E_NO_ERROR if everything is successful.
*/
int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol);
/**
* @brief Enables the specified GPIO interrupt
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_IntEnable(const gpio_cfg_t *cfg);
/**
* @brief Disables the specified GPIO interrupt.
* @param cfg Pointer to configuration structure describing the pin.
*/
void GPIO_IntDisable(const gpio_cfg_t *cfg);
/**
* @brief Gets the interrupt(s) status on a GPIO pin.
* @param cfg Pointer to configuration structure describing the pin
* for which the status is being requested.
* @return The requested interrupt status.
*/
uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg);
/**
* @brief Clears the interrupt(s) status on a GPIO pin.
* @param cfg Pointer to configuration structure describing the pin
* to clear the interrupt state of.
*/
void GPIO_IntClr(const gpio_cfg_t *cfg);
/**
* @brief Type alias for a GPIO callback function with prototype:
* @code
void callback_fn(void *cbdata);
* @endcode
* @param cbdata A void pointer to the data type as registered when
* GPIO_RegisterCallback() was called.
*/
typedef void (*gpio_callback_fn)(void *cbdata);
/**
* @brief Registers a callback for the interrupt on a given port and pin.
* @param cfg Pointer to configuration structure describing the pin
* @param callback A pointer to a function of type \c #gpio_callback_fn.
* @param cbdata The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs.
*
*/
void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
/**
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
* interrupt, the callback function will be called.
*
* @param port number of the port that generated the interrupt service routine.
*
*/
void GPIO_Handler(unsigned int port);
/**@} end of group gpio */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_H_ */

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/**
* @file i2c.h
* @brief Inter-integrated circuit (I2C) communications interface driver.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-06-28 09:42:42 -0500 (Fri, 28 Jun 2019) $
* $Revision: 44330 $
*
*************************************************************************** */
#ifndef _I2C_H_
#define _I2C_H_
#include <stdint.h>
#include "i2c_regs.h"
#include "mxc_sys.h"
/**
* @defgroup i2c I2C
* @ingroup periphlibs
* @{
*/
/***** Definitions *****/
/// @brief I2C Speed Modes
typedef enum {
I2C_STD_MODE = 100000, //!< 100KHz Bus Speed
I2C_FAST_MODE = 400000, //!< 400KHz Bus Speed
I2C_FASTPLUS_MODE = 1000000, //!< 1MHz Bus Speed
I2C_HS_MODE = 3400000 //!< 3.4MHz Bus Speed
} i2c_speed_t;
//State for Master
typedef enum {
I2C_STATE_READING = 0,
I2C_STATE_WRITING = 1
} i2c_state_t;
// @brief Enable/Disable TXFIFO Autoflush mode
typedef enum {
I2C_AUTOFLUSH_ENABLE = 0,
I2C_AUTOFLUSH_DISABLE = 1
} i2c_autoflush_disable_t;
// @brief I2C Transaction request.
typedef struct i2c_req i2c_req_t;
struct i2c_req {
uint8_t addr; /**< @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the @p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
*/
const uint8_t *tx_data; ///< Data for mater write/slave read.
uint8_t *rx_data; ///< Data for master read/slave write.
unsigned tx_len; ///< Length of tx data.
unsigned rx_len; ///< Length of rx.
unsigned tx_num; ///< Number of tx bytes sent.
unsigned rx_num; ///< Number of rx bytes sent.
i2c_state_t state; ///< Read or Write.
/**
* @details 0 to send a stop bit at the end of the transaction,
otherwise send a restart. Only used in master trasnactions.
*/
int restart; /**< @parblock Restart or stop bit indicator.
* @arg 0 to send a stop bit at the end of the transaction
* @arg Non-zero to send a restart at end of the transaction
* @note Only used for Master transactions.
* @endparblock
*/
i2c_autoflush_disable_t sw_autoflush_disable; ///< Enable/Disable autoflush.
/**
* @brief Callback for asynchronous request.
* @param i2c_req_t* Pointer to the transaction request.
* @param int Error code.
*/
void (*callback)(i2c_req_t*, int);
};
/***** Function Prototypes *****/
/**
* @brief Initialize and enable I2C.
* @param i2c Pointer to I2C peripheral registers.
* @param i2cspeed desired speed (I2C mode)
* @param sys_cfg System configuration object
* @returns \c #E_NO_ERROR if everything is successful,
* @ref MXC_Error_Codes if an error occurred.
*/
int I2C_Init(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg);
/**
* @brief Shutdown I2C module.
* @param i2c Pointer to the I2C registers.
* @returns #E_NO_ERROR I2C shutdown successfully, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int I2C_Shutdown(mxc_i2c_regs_t *i2c);
/**
* @brief Master write data. Will block until transaction is complete.
* @param i2c Pointer to I2C regs.
* @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the \p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
* @param data Data to be written.
* @param len Number of bytes to Write.
* @param restart 0 to send a stop bit at the end of the transaction,
otherwise send a restart.
* @returns Bytes transacted if everything is successful,
* @ref MXC_Error_Codes if an error occurred.
*/
int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart);
/**
* @brief Master read data. Will block until transaction is complete.
* @param i2c Pointer to I2C regs.
* @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the @p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
* @param data Data to be written.
* @param len Number of bytes to Write.
* @param restart 0 to send a stop bit at the end of the transaction,
otherwise send a restart.
* @returns Bytes transacted if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart);
/**
* @brief Slave read data. Will block until transaction is complete.
* @param i2c Pointer to I2C regs.
* @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the @p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
* @param read_data Buffer that the master will read from.
* @param read_len Number of bytes the master can read.
* @param write_data Buffer that the master will write to.
* @param write_len Number of bytes the master can write.
* @param tx_num Number of bytes transmitted by the slave.
* @param rx_num Number of bytes received by the slave.
* @param sw_autoflush_disable TX Autoflush enabled by default.Set this bit to disable autoflush manually.
* @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data,
int read_len, uint8_t* write_data, int write_len, int* tx_num,
int* rx_num, i2c_autoflush_disable_t sw_autoflush_disable);
/**
* @brief Master Read and Write Asynchronous.
* @param i2c Pointer to I2C regs.
* @param req Request for an I2C transaction.
* @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
/**
* @brief Slave Read and Write Asynchronous.
* @param i2c Pointer to I2C regs.
* @param req Request for an I2C transaction.
* @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
/**
* @brief I2C interrupt handler.
* @details This function should be called by the application from the interrupt
* handler if I2C interrupts are enabled. Alternately, this function
* can be periodically called by the application if I2C interrupts are
* disabled.
* @param i2c Base address of the I2C module.
*/
void I2C_Handler(mxc_i2c_regs_t *i2c);
/**
* @brief Drain all of the data in the RXFIFO.
* @param i2c Pointer to I2C regs.
*/
void I2C_DrainRX(mxc_i2c_regs_t *i2c);
/**
* @brief Drain all of the data in the TXFIFO.
* @param i2c Pointer to I2C regs.
*/
void I2C_DrainTX(mxc_i2c_regs_t *i2c);
/**
* @brief Abort Async request based on the request you want to abort.
* @param req Pointer to I2C Transaction.
*/
int I2C_AbortAsync(i2c_req_t *req);
/**
* @brief Enable and Set Timeout
*
* @param i2c pointer to I2C regs
* @param[in] us micro seconds to delay
*
* @return E_NO_ERROR or E_BAD_PARAM if delay is to long.
*/
int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us);
/**
* @brief clear and disable timeout
*
* @param i2c pointer to I2C regs
*/
void I2C_ClearTimeout(mxc_i2c_regs_t *i2c);
/**@} end of group i2c */
#endif /* _I2C_H_ */

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/**
* @file i2s.h
* @brief I2S (Inter-Integrated Sound) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
#ifndef _I2S_H_
#define _I2S_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "dma.h"
#include "spimss_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup i2s Inter-Integrated Sound (I2S)
* @ingroup spi
* @{
*/
/* **** Definitions **** */
/** @brief I2S audio directions */
typedef enum {
AUDIO_OUT = 1,
AUDIO_IN = 2,
} i2s_direction_t;
/** @brief I2S Configuration Struct */
typedef struct {
uint8_t left_justify;
uint8_t mono_audio;
i2s_direction_t audio_direction;
unsigned int sample_rate;
unsigned int start_immediately;
void *dma_src_addr;
void *dma_dst_addr;
unsigned int dma_cnt;
unsigned int dma_reload_en;
} i2s_cfg_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize I2S resources
* @param cfg I2S Configuration Struct
* @param dma_ctz_cb Optional function to be called when the DMA completes
a transfer. Set to NULL if unused.
* @param sys_cfg_i2s System configuration object
* @details This initialization is required before using the I2S driver functions.
* @return \c #E_NO_ERROR if successful
*/
int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s);
/**
* @brief Release I2S
* @details De-configures the I2S protocol and stops DMA request
* @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise
*/
int I2S_Shutdown(void);
/**
* @brief Mute I2S Output
* @details Sets I2S data to zero, continues sending clock and accessing DMA
* @return \c #E_NO_ERROR
*/
int I2S_Mute(void);
/**
* @brief Unmute I2S Output
* @details Restores I2S data
* @return \c #E_NO_ERROR
*/
int I2S_Unmute(void);
/**
* @brief Pause I2S Output
* @details Similar to mute, but stops FIFO and DMA access, clocks continue
* @return \c #E_NO_ERROR
*/
int I2S_Pause(void);
/**
* @brief Unpause I2S Output
* @details Similar to mute, but restarts FIFO and DMA access
* @return \c #E_NO_ERROR
*/
int I2S_Unpause(void);
/**
* @brief Stops I2S Output
* @details Similar to pause, but also halts clock
* @return \c #E_NO_ERROR
*/
int I2S_Stop(void);
/**
* @brief Starts I2S Output
* @details Starts I2S Output, automatically called by configure if requested
* @return \c #E_NO_ERROR
*/
int I2S_Start(void);
/**
* @brief Clears DMA Interrupt Flags
* @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb
* @return \c #E_NO_ERROR
*/
int I2S_DMA_ClearFlags(void);
/**
* @brief Set DMA Addr (Source or Dest) and bytes to transfer
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details Sets the address to read/write data in memory and the length of
* the transfer. The unused addr parameter is ignored.
* @return \c #E_NO_ERROR
*/
int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
/**
* @brief Sets the DMA reload address and count
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details If DMA reload is enabled, when the DMA has transfered $count bytes
* (a CTZ event occurs) the src, dst, and count registers will be
* set to these. The DMA reload flag clears after a reload occurs.
* @return \c #E_NO_ERROR
*/
int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
/**@} end of group i2s */
#ifdef __cplusplus
}
#endif
#endif /* _I2S_H_ */

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/**
* @file icc.h
* @brief Instruction Controller Cache(ICC) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _ICC_H_
#define _ICC_H_
/* **** Includes **** */
#include <stdint.h>
#include "icc_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup icc Internal Cache Controller (ICC)
* @ingroup periphlibs
* @{
*/
/**
* @brief Enumeration type for the Cache ID Register
*/
typedef enum {
ICC_CACHE_ID_RELNUM, // Identifies the RTL release version
ICC_CACHE_ID_PARTNUM, // Specifies the value of C_ID Port Number
ICC_CACHE_ID_CCHID // Specifies the value of Cache ID
} icc_cache_id_t;
/**
* @brief Reads the data from the Cache Id Register.
* @param cid Enumeration type for Cache Id Register.
* @retval Returns the contents of Cache Id Register.
*/
int ICC_ID(icc_cache_id_t cid);
/**
* @brief Enable the instruction cache controller.
*/
void ICC_Enable(void);
/**
* @brief Disable the instruction cache controller.
*/
void ICC_Disable(void);
/**
* @brief Flush the instruction cache controller.
*/
void ICC_Flush(void);
/**@} end of group icc */
#ifdef __cplusplus
}
#endif
#endif /* _ICC_H_ */

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/**
* @file lp.h
* @brief Low power function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
* $Revision: 38105 $
*
*************************************************************************** */
// Define to prevent redundant inclusion
#ifndef _LP_H_
#define _LP_H_
/***** Includes *****/
#include "gpio.h"
#include "pwrseq_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
typedef enum {
LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */
LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */
LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */
} lp_ovr_t;
/**
* @brief Clears the low power wakeup flags
*/
void LP_ClearWakeStatus(void);
/**
* @brief Enables power to RAM addresses 0x20010000-0x20017FFF.
*/
void LP_EnableSRAM3(void);
/**
* @brief Enables power to RAM addresses 0x20008000-0x2000FFFF.
*/
void LP_EnableSRAM2(void);
/**
* @brief Enables power to RAM addresses 0x20004000-0x20007FFF.
*/
void LP_EnableSRAM1(void);
/**
* @brief Enables power to RAM addresses 0x20000000-0x20003FFF.
*/
void LP_EnableSRAM0(void);
/**
* @brief Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM3(void);
/**
* @brief Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM2(void);
/**
* @brief Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM1(void);
/**
* @brief Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM0(void);
/**
* @brief Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM0LightSleep(void);
/**
* @brief Places the instruction cache in active mode.
*/
void LP_DisableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode.
*/
void LP_DisableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode.
*/
void LP_DisableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode.
*/
void LP_DisableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode.
*/
void LP_DisableSysRAM0LightSleep(void);
/**
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
* Call this function multiple times to enable pins on multiple ports. This function does not configure
* the GPIO pins nor does it setup their interrupt functionality.
* @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
*/
void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins);
/**
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
* Call this function multiple times to disable pins on multiple ports.
* @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
*/
void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins);
/**
* @brief Enables the RTC alarm to wake up the device from any low power mode.
*/
void LP_EnableRTCAlarmWakeup(void);
/**
* @brief Disables the RTC alarm from waking up the device.
*/
void LP_DisableRTCAlarmWakeup(void);
/**
* @brief Places the device into SLEEP mode. This function returns once any interrupt occurs.
* @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void LP_EnterSleepMode(void);
/**
* @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur.
* @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void LP_EnterDeepSleepMode(void);
/**
* @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC or external interrupt occur.
* @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void LP_EnterBackupMode(void);
/**
* @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur.
*/
void LP_EnterShutDownMode(void);
/**
* @brief Set operating voltage and change the clock to match the new voltage.
* @param system reset configuration struct
*/
void LP_SetOperatingVoltage(lp_ovr_t ovr);
/**
* @brief Enables Data Retention to RAM addresses 0x20000000-0x20003FFF.
*/
void LP_EnableSRamRet0(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20000000-0x20003FFF.
*/
void LP_DisableSRamRet0(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20004000-0x20007FFF.
*/
void LP_EnableSRamRet1(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20004000-0x20007FFF.
*/
void LP_DisableSRamRet1(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
*/
void LP_EnableSRamRet2(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
*/
void LP_DisableSRamRet2(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20010000-0x20017FFF.
*/
void LP_EnableSRamRet3(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20010000-0x20017FFF.
*/
void LP_DisableSRamRet3(void);
/**
* @brief Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time.
*/
void LP_EnableBlockDetect(void);
/**
* @brief Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time
*/
void LP_DisableBlockDetect(void);
/**
* @brief RAM Retention Regulator Enable for BACKUP Mode
*/
void LP_EnableRamRetReg(void);
/**
* @brief RAM Retention Regulator Disabels for BACKUP Mode
*/
void LP_DisableRamRetReg(void);
/**
* @brief Enables Fast wake up from deepsleep
*/
void LP_EnableFastWk(void);
/**
* @brief Disables Fast wake up from deepsleep
*/
void LP_DisableFastWk(void);
/**
* @brief Turns on band gap during deepsleep and backup mode.
*/
void LP_EnableBandGap(void);
/**
* @brief Turns off band gap during deepsleep and backup mode.
*/
void LP_DisableBandGap(void);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_EnableVCorePORSignal(void);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_DisableVCorePORSignal(void);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_EnableLDO(void);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_DisableLDO(void);
/**
* @brief Enables V CORE Supply Voltage Monitor
*/
void LP_EnableVCoreSVM(void);
/**
* @brief Disables V CORE Supply Voltage Monitor
*/
void LP_DisableVCoreSVM(void);
/**
* @brief Enables VDDIO Power-On-Reset Monitor
*/
void LP_EnableVDDIOPorMonitor(void);
/**
* @brief Disables VDDIO Power-On-Reset Monitor
*/
void LP_DisableVDDIOPorMonitor(void);
#ifdef __cplusplus
}
#endif
#endif /* _LP_H_ */

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/**
* @file
* @brief Assertion checks for debugging.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_ASSERT_H_
#define _MXC_ASSERT_H_
/* **** Includes **** */
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup mxc_assertions Assertion Checks for Debugging
* @brief Assertion checks for debugging.
* @{
*/
/* **** Definitions **** */
/**
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
///@cond
#ifdef MXC_ASSERT_ENABLE
/**
* Macro that checks the expression for true and generates an assertion.
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
#define MXC_ASSERT(expr) \
if (!(expr)) \
{ \
mxc_assert(#expr, __FILE__, __LINE__); \
}
/**
* Macro that generates an assertion with the message "FAIL".
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__);
#else
#define MXC_ASSERT(expr)
#define MXC_ASSERT_FAIL()
#endif
///@endcond
/* **** Globals **** */
/* **** Function Prototypes **** */
/**
* @brief Assert an error when the given expression fails during debugging.
* @param expr String with the expression that failed the assertion.
* @param file File containing the failed assertion.
* @param line Line number for the failed assertion.
* @note This is defined as a weak function and can be overridden at the
* application layer to print the debugging information.
* @code
* printf("%s, file: %s, line %d\n", expr, file, line);
* @endcode
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
void mxc_assert(const char *expr, const char *file, int line);
/**@} end of group MXC_Assertions*/
#ifdef __cplusplus
}
#endif
#endif /* _MXC_ASSERT_H_ */

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/**
* @file mxc_config.h
* @brief Top-level include file for device configuration.
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
******************************************************************************/
#ifndef _MXC_CONFIG_H
#define _MXC_CONFIG_H
#if !defined __GNUC__
#include "RTE_Components.h"
#endif /* not __GNUC__ */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_pins.h"
#endif /* _CONFIG_H */

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/**
* @file
* @brief Asynchronous delay routines based on the SysTick Timer.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-11-05 09:52:05 -0600 (Mon, 05 Nov 2018) $
* $Revision: 38934 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _DELAY_H_
#define _DELAY_H_
/**
* @defgroup MXC_delay Delay Utility Functions
* @ingroup devicelibs
* @brief Asynchronous delay routines based on the SysTick Timer
* @{
*/
/***** Definitions *****/
/**
* Macro used to specify a microsecond timing parameter in seconds.
* \code
* x = SEC(3) // 3 seconds -> x = 3,000,000
* \endcode
*/
#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL)
/**
* Macro used to specify a microsecond timing parameter in milliseconds.
* \code
* x = MSEC(3) // 3ms -> x = 3,000
* \endcode
*/
#define MXC_DELAY_MSEC(ms) (ms * 1000UL)
/**
* Macro used to specify a microsecond timing parameter.
* \code
* x = USEC(3) // 3us -> x = 3
* \endcode
*/
#define MXC_DELAY_USEC(us) (us)
/***** Function Prototypes *****/
/**
* @brief Blocks and delays for the specified number of microseconds.
* @details Uses the SysTick to create the requested delay. If the SysTick is
* running, the current settings will be used. If the SysTick is not
* running, it will be started.
* @param us microseconds to delay
* @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int mxc_delay(unsigned long us);
/**
* @brief Starts a non-blocking delay for the specified number of
* microseconds.
* @details Uses the SysTick to time the requested delay. If the SysTick is
* running, the current settings will be used. If the SysTick is not
* running, it will be started.
* @note mxc_delay_handler() must be called from the SysTick interrupt service
* routine or at a rate greater than the SysTick overflow rate.
* @param us microseconds to delay
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
* delay request.
*/
int mxc_delay_start(unsigned long us);
/**
* @brief Returns the status of a non-blocking delay request
* @pre Start the asynchronous delay by calling mxc_delay_start().
* @return #E_BUSY until the requested delay time has expired.
*/
int mxc_delay_check(void);
/**
* @brief Stops an asynchronous delay previously started.
* @pre Start the asynchronous delay by calling mxc_delay_start().
*/
void mxc_delay_stop(void);
/**
* @brief Processes the delay interrupt.
* @details This function must be called from the SysTick IRQ or polled at a
* rate greater than the SysTick overflow rate.
*/
void mxc_delay_handler(void);
/**@} end of group MXC_delay */
#endif /* _DELAY_H_ */

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/**
* @file
* @brief List of common error return codes for Maxim Integrated libraries.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_ERRORS_H_
#define _MXC_ERRORS_H_
/**
* @ingroup syscfg
* @defgroup MXC_Error_Codes Error Codes
* @brief A list of common error codes used by the API.
* @note A Negative Error Convention is used to avoid conflict with
* positive, Non-Error, returns.
* @{
*/
/** No Error */
#define E_NO_ERROR 0
/** No Error, success */
#define E_SUCCESS 0
/** Pointer is NULL */
#define E_NULL_PTR -1
/** No such device */
#define E_NO_DEVICE -2
/** Parameter not acceptable */
#define E_BAD_PARAM -3
/** Value not valid or allowed */
#define E_INVALID -4
/** Module not initialized */
#define E_UNINITIALIZED -5
/** Busy now, try again later */
#define E_BUSY -6
/** Operation not allowed in current state */
#define E_BAD_STATE -7
/** Generic error */
#define E_UNKNOWN -8
/** General communications error */
#define E_COMM_ERR -9
/** Operation timed out */
#define E_TIME_OUT -10
/** Expected response did not occur */
#define E_NO_RESPONSE -11
/** Operations resulted in unexpected overflow */
#define E_OVERFLOW -12
/** Operations resulted in unexpected underflow */
#define E_UNDERFLOW -13
/** Data or resource not available at this time */
#define E_NONE_AVAIL -14
/** Event was shutdown */
#define E_SHUTDOWN -15
/** Event was aborted */
#define E_ABORT -16
/** The requested operation is not supported */
#define E_NOT_SUPPORTED -17
/**@} end of MXC_Error_Codes group */
#endif /* _MXC_ERRORS_H_ */

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/**
* @file
* @brief Exclusive access lock utility functions.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_LOCK_H_
#define _MXC_LOCK_H_
/* **** Includes **** */
#include "mxc_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup mxc_lock_utilities Exclusive Access Locks
* @brief Lock functions to obtain and release a variable for exclusive
* access. These functions are marked interrupt safe if they are
* interrupt safe.
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Function Prototypes **** */
/**
* @brief Attempts to acquire the lock.
* @details This in an interrupt safe function that can be used as a mutex.
* The lock variable must remain in scope until the lock is
* released. Will not block if another thread has already acquired
* the lock.
* @param lock Pointer to variable that is used for the lock.
* @param value Value to be place in the lock. Can not be 0.
*
* @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
*/
int mxc_get_lock(uint32_t *lock, uint32_t value);
/**
* @brief Free the given lock.
* @param[in,out] lock Pointer to the variable used for the lock. When the lock
* is free, the value pointed to by @p lock is set to zero.
*/
void mxc_free_lock(uint32_t *lock);
/**@} end of group mxc_lock_utilities */
#ifdef __cplusplus
}
#endif
#endif /* _MXC_LOCK_H_ */

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/**
* @file mxc_pins.h
* @brief This file contains constant pin configurations for the peripherals.
*/
/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
**************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_PINS_H_
#define _MXC_PINS_H_
/* **** Includes **** */
#include "gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
/* **** Global Variables **** */
// Predefined GPIO Configurations
/***** @brief TIMER pins *****/
extern const gpio_cfg_t gpio_cfg_tmr0;
/***** @brief UART pins *****/
extern const gpio_cfg_t gpio_cfg_uart0rtscts;
extern const gpio_cfg_t gpio_cfg_uart0a;
extern const gpio_cfg_t gpio_cfg_uart1rtscts;
extern const gpio_cfg_t gpio_cfg_uart1a;
extern const gpio_cfg_t gpio_cfg_uart1b;
extern const gpio_cfg_t gpio_cfg_uart1c;
extern const gpio_cfg_t gpio_cfg_uart2;
/***** @brief I2C pins *****/
extern const gpio_cfg_t gpio_cfg_i2c0;
extern const gpio_cfg_t gpio_cfg_i2c1;
/***** @brief SPI/I2S pins *****/
extern const gpio_cfg_t gpio_cfg_spi17y; // SPI0A
extern const gpio_cfg_t gpio_cfg_spimss1a; // SPI1A
extern const gpio_cfg_t gpio_cfg_spimss1b; // SPI1B
extern const gpio_cfg_t gpio_cfg_i2s1a; // same port as SPI1A
extern const gpio_cfg_t gpio_cfg_i2s1b; // same port as SPI1B
/***** @brief SWD pins *****/
extern const gpio_cfg_t gpio_cfg_swd;
/***** @brief RTC pins *****/
extern const gpio_cfg_t gpio_cfg_rtc;
#ifdef __cplusplus
}
#endif
#endif /* _MXC_PINS_H_ */

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/**
* @file
* @brief System level header file.
*/
/*******************************************************************************
* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-04-15 09:35:40 -0500 (Mon, 15 Apr 2019) $
* $Revision: 42499 $
*
******************************************************************************/
#ifndef _MXC_SYS_H_
#define _MXC_SYS_H_
#include "mxc_config.h"
#include "uart_regs.h"
#include "i2c_regs.h"
#include "gcr_regs.h"
#include "tmr_regs.h"
#include "icc_regs.h"
#include "spi17y_regs.h"
#include "spimss_regs.h"
#include "gpio.h"
#include "flc_regs.h"
#include "dma.h"
#include "wdt_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM ) /* Suppressing the warning: "enum value is out of range of int" for Keil */
#pragma push
#pragma diag_suppress 66
#endif /* __CC_ARM */
/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
typedef enum {
SYS_RESET0_DMA = MXC_F_GCR_RSTR0_DMA, /**< Reset DMA */
SYS_RESET0_WDT = MXC_F_GCR_RSTR0_WDT, /**< Reset WDT */
SYS_RESET0_GPIO0 = MXC_F_GCR_RSTR0_GPIO0, /**< Reset GPIO0 */
SYS_RESET0_TIMER0 = MXC_F_GCR_RSTR0_TIMER0, /**< Reset TIMER0 */
SYS_RESET0_TIMER1 = MXC_F_GCR_RSTR0_TIMER1, /**< Reset TIMER1 */
SYS_RESET0_TIMER2 = MXC_F_GCR_RSTR0_TIMER2, /**< Reset TIMER2 */
SYS_RESET0_UART0 = MXC_F_GCR_RSTR0_UART0, /**< Reset UART0 */
SYS_RESET0_UART1 = MXC_F_GCR_RSTR0_UART1, /**< Reset UART1 */
SYS_RESET0_SPI0 = MXC_F_GCR_RSTR0_SPI0, /**< Reset SPI0 */
SYS_RESET0_SPI1 = MXC_F_GCR_RSTR0_SPI1, /**< Reset SPI1 */
SYS_RESET0_I2C0 = MXC_F_GCR_RSTR0_I2C0, /**< Reset I2C0 */
SYS_RESET0_RTC = MXC_F_GCR_RSTR0_RTC, /**< Reset RTC */
SYS_RESET0_SRST = MXC_F_GCR_RSTR0_SRST, /**< Soft reset */
SYS_RESET0_PRST = MXC_F_GCR_RSTR0_PRST, /**< Peripheral reset */
SYS_RESET0_SYSTEM = MXC_F_GCR_RSTR0_SYSTEM, /**< System reset */
} sys_reset0_t;
/** @brief System reset1 enumeration. Used in SYS_PeriphReset1 function */
typedef enum {
SYS_RESET1_I2C1 = MXC_F_GCR_RSTR1_I2C1, /**< Reset I2C1 */
} sys_reset1_t;
/** @brief System clock disable enumeration. Used in SYS_ClockDisable and SYS_ClockEnable functions */
typedef enum {
SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PERCKCN0_GPIO0D, /**< Disable MXC_F_GCR_PERCKCN0_GPIO0D clock */
SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PERCKCN0_DMAD, /**< Disable MXC_F_GCR_PERCKCN0_DMAD clock */
SYS_PERIPH_CLOCK_SPI17Y = MXC_F_GCR_PERCKCN0_SPI0D, /**< Disable MXC_F_GCR_PERCKCN0_SPI0D clock */
SYS_PERIPH_CLOCK_SPIMSS = MXC_F_GCR_PERCKCN0_SPI1D, /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */
SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PERCKCN0_UART0D, /**< Disable MXC_F_GCR_PERCKCN0_UART0D clock */
SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PERCKCN0_UART1D, /**< Disable MXC_F_GCR_PERCKCN0_UART1D clock */
SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PERCKCN0_I2C0D, /**< Disable MXC_F_GCR_PERCKCN0_I2C0D clock */
SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PERCKCN0_T0D, /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */
SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PERCKCN0_T1D, /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */
SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PERCKCN0_T2D, /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */
SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PERCKCN0_I2C1D, /**< Disable MXC_F_GCR_PERCKCN0_I2C1D clock */
} sys_periph_clock_t;
/** @brief Clock source */
typedef enum {
SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */
SYS_CLOCK_HFXIN = MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */
} sys_system_clock_t;
typedef void* sys_cfg_t;
typedef sys_cfg_t sys_cfg_i2c_t;
typedef sys_cfg_t sys_cfg_flc_t;
typedef sys_cfg_t sys_cfg_wdt_t;
/** @brief Map control */
typedef enum {
MAP_A,
MAP_B,
MAP_C,
} sys_map_t;
/** @brief UART Flow control */
typedef enum {
UART_FLOW_DISABLE,
UART_FLOW_ENABLE,
} sys_uart_flow_t;
/** @brief UART system configuration object */
typedef struct {
sys_map_t map;
sys_uart_flow_t flow_flag;
} sys_cfg_uart_t;
/** @brief SPI17Y system configuration object */
typedef struct {
sys_map_t map;
} sys_cfg_spi17y_t;
/** @brief SPIMSS system configuration object */
typedef struct {
sys_map_t map;
} sys_cfg_spimss_t;
/** @brief I2S system configuration object */
typedef struct {
sys_map_t map;
dma_reqsel_t dma_reqsel_tx;
dma_reqsel_t dma_reqsel_rx;
} sys_cfg_i2s_t;
/** @brief TIMER system configuration object */
typedef struct {
int out_en;
} sys_cfg_tmr_t;
/** @brief Real Time Clock system configuration object */
typedef struct {
mxc_tmr_regs_t* tmr;
} sys_cfg_rtc_t;
/** @brief Pulse Train System Configuration Object */
typedef gpio_cfg_t sys_cfg_pt_t;
#if defined ( __CC_ARM ) /* Restore the warning: "enum is out of int range" for Keil */
#pragma pop
#endif /* __CC_ARM */
/***** Function Prototypes *****/
/**
* @brief Selects the system clock and enables it once ready
* @param clock Enumeration for desired clock.
* @param tmr Optional tmr pointer for timeout. NULL if undesired.
*
* @returns #E_NO_ERROR is clock is succesfully selected
*/
int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr);
/**
* @brief Enables the selected peripheral clock.
* @param clock Enumeration for desired clock.
*/
void SYS_ClockEnable(sys_periph_clock_t clock);
/**
* @brief Disables the selected peripheral clock.
* @param clock Enumeration for desired clock.
*/
void SYS_ClockDisable(sys_periph_clock_t clock);
/**
* @brief Enables the external 32k oscillator.
* @param sys_cfg system configuration object
*
* @returns #E_NO_ERROR is successful, appropriate error otherwise
*/
int SYS_ClockEnable_X32K(sys_cfg_rtc_t *sys_cfg);
/**
* @brief Disables the external 32k oscillator.
*
* @returns #E_NO_ERROR is successful, appropriate error otherwise
*/
int SYS_ClockDisable_X32K(void);
/**
* @brief System level initialization for UART module.
* @param uart Pointer to UART module registers
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg);
/**
* @brief System level shutdown for UART module
* @param uart Pointer to UART module registers
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_UART_Shutdown(mxc_uart_regs_t *uart);
/**
* @brief System level initialization for I2C module.
* @param i2c Pointer to I2C module registers
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_I2C_Init(mxc_i2c_regs_t *i2c, const sys_cfg_i2c_t* sys_cfg);
/**
* @brief System level Shutdown for I2C module.
* @param i2c Pointer to I2C module registers
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c);
/**
* @brief Init DMA system settings
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_DMA_Init(void);
/**
* @brief Shutdown DMA system specific settings
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_DMA_Shutdown(void);
/**
* @brief Get the frequency of the I2C module source clock
* @param spim Unused, pointer to I2C module registers
*
* @returns frequency in Hz
*/
unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c);
/**
* @brief Get the frequency of the Timer module source clock.
* @params tmr Unused, pointer to timer module registers
*
* @returns frequency in Hz
*/
unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr);
/**
* @brief Reset the peripherals and/or CPU in the rstr0 register.
* @param Enumeration for what to reset. Can reset multiple items at once.
*/
void SYS_Reset0(sys_reset0_t reset);
/**
* @brief Reset the peripherals and/or CPU in the rstr1 register.
* @param Enumeration for what to reset. Can reset multiple items at once.
*/
void SYS_Reset1(sys_reset1_t reset);
/**
* @brief Clear Cache and Line buffer.
*/
void SYS_Flash_Operation(void);
/**
* @brief Init TMR system settings
* @param tmr Pointer to timer module registers
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg);
/**
* @brief Init flash system settings
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg);
/**
* @brief Shutdown flash system specific settings
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_FLC_Shutdown(void);
/**
* @brief System level initialization for SPI17Y module.
* @param spi pointer to spi module registers
* @param sys_cfg System configuration object
*
* @returns E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_SPI17Y_Init( mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg);
/**
* @brief System level shutdown for SPI17Y module
* @param pointer to spi module registers
*
* @returns E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi);
/**
* @brief System level initialization for SPIMSS module.
* @param spi pointer to spi module registers
* @param sys_cfg System configuration object
*
* @returns E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_SPIMSS_Init(mxc_spimss_regs_t *spi, const sys_cfg_spimss_t* sys_cfg);
/**
* @brief System level shutdown for SPIMSS module
* @param pointer to spi module registers
*
* @returns E_NO_ERROR if everything is successful
*/
int SYS_SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
/**
* @brief Shutdown Timer system specific settings
* @param tmr pointer to timer module registers
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr);
/**
* @brief System level initialization for I2S Module
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_I2S_Init(const sys_cfg_i2s_t* sys_cfg);
/**
* @brief System level shutdown of I2S module
*
* @returns #E_NO_ERROR if everything is successful
*/
int SYS_I2S_Shutdown(void);
/**
* @brief Get the frequency of the I2S module source clock
* @param spimss Pointer to I2S module registers
*
* @returns frequency in Hz
*/
int SYS_I2S_GetFreq(mxc_spimss_regs_t *spimss);
/**
* @brief Init system settings for RTC square wave output.
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg);
/**
* @brief System Tick Configuration Helper
*
* The function enables selection of the external clock source for
* the System Tick Timer. It initializes the System Timer and its
* interrupt, and starts the System Tick Timer. Counter is in free
* running mode to generate periodic interrupts.
*
* @param ticks Number of ticks between two interrupts.
* @param clk_src Selects between default SystemClock or External Clock.
* - 0 Use external clock source
* @param tmr Optional tmr pointer for timeout. NULL if undesired.
* - 1 SystemClock
*
* @return #E_NO_ERROR Function succeeded, of #E_INVALID if an invalid value is requested
*/
int SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t* tmr);
/**
* @brief Disable System Tick timer
*/
void SYS_SysTick_Disable(void);
/**
* @brief Delay a requested number of SysTick Timer Ticks.
* @param ticks Number of System Ticks to delay.
* @note This delay function is based on the clock used for the SysTick
* timer if the SysTick timer is enabled. If the SysTick timer is
* not enabled, the current SysTick registers are saved and the
* timer will use the SystemClock as the source for the delay. The
* delay is measured in clock ticks and is not based on the SysTick
* interval.
*
* @return #E_NO_ERROR if everything is successful
*/
int SYS_SysTick_Delay(uint32_t ticks);
/**
* @brief Get the frequency of the SysTick Timer
*
* @return frequency in Hz
*/
uint32_t SYS_SysTick_GetFreq(void);
/**
* @brief Delay a requested number of microseconds.
* @param us Number of microseconds to delay.
* @note Calls SYS_SysTick_Delay().
*/
void SYS_SysTick_DelayUs(uint32_t us);
/**
* @brief Init WDT system settings
* @param wdt watchdog registers
* @param sys_cfg System configuration object
*/
int SYS_WDT_Init(mxc_wdt_regs_t* wdt, const sys_cfg_wdt_t* sys_cfg);
#ifdef __cplusplus
}
#endif
#endif /* _MXC_SYS_H_*/

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/**
* @file nvic_table.h
* @brief Interrupt vector table manipulation functions.
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2020-04-20 15:48:35 -0500 (Mon, 20 Apr 2020) $
* $Revision: 53144 $
*
******************************************************************************/
#ifndef _NVIC_TABLE_H
#define _NVIC_TABLE_H
#include "mxc_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup nvic NVIC Table
* @brief functions handling the nvic table.
* @{
*/
/**
* @brief Set an IRQ hander callback function. If the IRQ table is in
* flash, this will copy it to RAM and set NVIC to RAM based table.
*
* @param irqn ARM external IRQ number
* @param irq_callback Function to be called at IRQ context
*
*/
void NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void));
/**
* @brief Copy NVIC vector table to RAM and set NVIC to RAM based table.
*
*/
void NVIC_SetRAM(void);
/**
* @brief Get Interrupt Vector
* @details Reads an interrupt vector from interrupt vector table. The
* interrupt number can be positive to specify a device specific
* interrupt, or negative to specify a processor exception.
* @param[in] IRQn Interrupt number.
* @return Address of interrupt handler function
*/
uint32_t NVIC_GetVector(IRQn_Type IRQn);
/**@} end of group nvic */
#ifdef __cplusplus
}
#endif
#endif /* _NVIC_TABLE_H */

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/**
* @file
* @brief Real Time Clock (RTC) functions and prototypes.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
* $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
* $Revision: 47429 $
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _RTC_H_
#define _RTC_H_
/* **** Includes **** */
#include <stdint.h>
#include "mxc_config.h"
#include "rtc_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup rtc RTC
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
typedef enum {
SQUARE_WAVE_DISABLED, /**< Sq. wave output disabled */
SQUARE_WAVE_ENABLED, /**< Sq. wave output enabled */
} rtc_sqwave_en_t;
typedef enum {
F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, /**< 1Hz (Compensated) */
F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, /**< 512Hz (Compensated) */
F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, /**< 4Khz */
F_32KHZ = 32, /**< 32Khz */
} rtc_freq_sel_t;
typedef enum {
NOISE_IMMUNE_MODE = MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE,
QUIET_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETMODE,
QUIET_STOP_WARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP,
QUIET_STOP_NOWARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP,
} rtc_osc_mode_t;
/**
*@brief Enables Time-of-Day's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_EnableTimeofdayInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Disable Time-of-Day's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Enables Sub-Second's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Disable Sub-Second's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Set Time-of-Day alarm value and enable Interrupt
*@param rtc pointer to the rtc register structure
*@param ras 20-bit value 0-0xFFFFF
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras);
/**
*@brief Set Sub-Second alarm value and enable interrupt,
*@brief this is to be called after the init_rtc() function
*@param rtc pointer to the rtc register structure
*@param rssa 32-bit value 0-0xFFFFFFFF
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa);
/**
*@brief Enable/Start the Real Time Clock
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_EnableRTCE(mxc_rtc_regs_t *rtc);
/**
*@brief Disable/Stop the Real Time Clock
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_DisableRTCE(mxc_rtc_regs_t *rtc);
/**
* @brief Initialize the sec and ssec registers and enable RTC
* @param rtc pointer to the rtc register structure
* @param sec set the RTC Sec counter (32-bit)
* @param ssec set the RTC Sub-second counter (8-bit)
* @param sys_cfg The system configuration
* @return #E_SUCCESS=pass
* @return #E_BAD_STATE=fail
*/
int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint8_t ssec, sys_cfg_rtc_t *sys_cfg);
/**
* @brief Allow generation of Square Wave on the SQW pin
* @param rtc pointer to the rtc register structure
* @param sqe Enable/Disable square wave output
* @param ft Frequency output selection
* @param x32kmd 32KHz Oscillator mode
* @param sys_cfg The system configuration
* @return #E_SUCCESS=Pass
* @return #E_BUSY=Fail
*/
int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg);
/**
*@brief Set Trim register value
*@param rtc pointer to the rtc register structure
*@param trm set the RTC Trim (8-bit, +/- 127)
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trm);
/**
*@brief Check if BUSY bit is 0.
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_CheckBusy(void);
/**
*@brief Gets Interrupt flags.
*@return Interrupts flags that have not been cleared
*/
int RTC_GetFlags(void);
/**
*@brief Clear Interrupt flag.
*@param flags the flags that need to be cleared
*/
int RTC_ClearFlags(int flags);
/**
*@brief Get SubSecond
*@return Returns subsecond value
*/
int RTC_GetSubSecond(void);
/**
* @brief Get Second
* @return returns Second value
*/
int RTC_GetSecond(void);
/**
* @brief Read seconds, then subseconds, and finally seconds. If RTC ready flag ever gets cleared during this sequence,
the RTC is in the middle of updating the counts and the user should come back later and try again. If the first
read of the seconds register doesn't match the next read, then a subsecond overflow condition has happened and
another attempt to read the counts should be made.
* @param sec variable that will be changed to hold second value
* @param subsec variable that will be changed to hold Subsecond value
* @return #E_NO_ERROR=Pass
* @return #E_BUSY=Fail
*/
int RTC_GetTime(uint32_t* sec, uint32_t* subsec);
/**
*@brief Check if RTC is already running
*/
int RTC_IsEnabled(void);
#ifdef __cplusplus
}
#endif
/**@} end of group rtc */
#endif /* _RTC_H_ */

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/**
* @file spi.h
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-11-07 14:48:15 -0600 (Wed, 07 Nov 2018) $
* $Revision: 39010 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPI_H_
#define _SPI_H_
/* **** Includes **** */
#include "spi17y_regs.h"
#include "spimss_regs.h"
#include "spimss.h"
#include "spi17y.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spi SPI
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* @brief Enums assigning numbers to SPI
*/
typedef enum {
SPI0A, // SPI17Y (0A)
SPI1A, // SPIMSS (1A)
SPI1B, // SPIMSS (1B)
}spi_type;
/**
* @brief Renaming the SPI address names
*/
#define MXC_SPI0 MXC_SPI17Y // SPI0A
#define MXC_SPI1 MXC_SPIMSS // SPI1A & SPI1B
/**
* @brief Renaming Interrupt SPI Interrupt sources
*/
#define SPI0_IRQn SPI17Y_IRQn // SPI0A
#define SPI1_IRQn SPIMSS_IRQn // SPI1A & SPI1B
/**
* @brief Renaming SPI Width
*/
#define SPI0_WIDTH_1 SPI17Y_WIDTH_1 /**< 1 Data Line. */
#define SPI0_WIDTH_2 SPI17Y_WIDTH_2 /**< 2 Data Lines (x2). */
#define SPI0_WIDTH_4 SPI17Y_WIDTH_4 /**< 4 Data Lines (x4). */
/**
* @brief Renaming SPI Polarity
*/
#define SPI_POL_LOW SPI17Y_POL_LOW /**< Slave Select polarity Low. */
#define SPI_POL_HIGH SPI17Y_POL_HIGH /**< Slave Select polarity High. */
/**
* @brief Structure type representing a SPI Master Transaction request.
*/
typedef struct spi_req spi_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
* @addtogroup spi_async
*/
typedef void (*spi_callback_fn)(void * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
* @addtogroup spi_async
*/
struct spi_req {
uint8_t ssel; /**< Slave select line to use. (Master only) */
uint8_t deass; /**< Non-zero to de-assert slave select after transaction. (Master only)*/
spi17y_sspol_t ssel_pol; /**< Slave select line polarity. */
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
spi17y_width_t width; /**< Number of data lines to use, see #spi17y_width_t. */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
spi_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi_name spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_Init(spi_type spi_name, unsigned mode, unsigned freq);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_MasterTransAsync(spi_type spi_name, spi_req_t *req);
/**
* @brief Execute a master transaction.
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_MasterTrans(spi_type spi_name, spi_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_SlaveTransAsync(spi_type spi_name, spi_req_t *req);
/**
* @brief Execute a slave transaction.
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_SlaveTrans(spi_type spi_name, spi_req_t *req);
/**
* @brief Shutdown SPI module.
* @param spi_name SPI instance being used
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Shutdown(spi_type spi_name);
/**
* @brief Aborts an Asynchronous request
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_AbortAsync(spi_type spi_name, spi_req_t *req);
/**
* @brief Execute SPI transaction based on interrupt handler
* @param spi_name SPI instance being used
*
* @return #E_NO_ERROR if successful,
* @return #E_BAD_PARAM otherwise
*/
int SPI_Handler(spi_type spi_name);
/**
* @brief Enable SPI
* @param spi_name Pointer to spi module.
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Enable(spi_type spi_name);
/**
* @brief Disable SPI
* @param spi_name Pointer to spi module.
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Disable(spi_type spi_name);
/**
* @brief Clear the TX and RX FIFO
* @param spi_name Pointer to spi module.
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Clear_fifo(spi_type spi_name);
//-------------------------------------------------------------------------------------------
/**@} end of group spi */
#ifdef __cplusplus
}
#endif
#endif /* _SPI_H_ */

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/**
* @file spi17y.h
* @brief Serial Peripheral Interface (SPI17Y) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPI17Y_H_
#define _SPI17Y_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "spi17y_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spi17y SPI17Y
* @ingroup spi
* @{
*/
/* **** Definitions **** */
/**
* Enumeration type for setting the number data lines to use for communication.
*/
typedef enum {
SPI17Y_WIDTH_1 = 0, /**< 1 Data Line. */
SPI17Y_WIDTH_2 = 1, /**< 2 Data Lines (x2). */
SPI17Y_WIDTH_4 = 2 /**< 4 Data Lines (x4). */
} spi17y_width_t;
/**
* Enumeration type for setting the polarity of ss lines.
*/
typedef enum {
SPI17Y_POL_LOW = 0, /**< Polarity Low. */
SPI17Y_POL_HIGH = 1 /**< Polarity High. */
} spi17y_sspol_t;
/**
* Structure type representing a SPI17Y Master Transaction request.
*/
typedef struct spi17y_req spi17y_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi17y_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
* @addtogroup spi_async
*/
typedef void (*spi17y_callback_fn)(spi17y_req_t * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
* @addtogroup spi_async
*/
struct spi17y_req {
uint8_t ssel; /**< Slave select line to use. (Master only, ignored in slave mode) */
uint8_t deass; /**< Non-zero to de-assert slave select after transaction. (Master only, ignored in slave mode)*/
spi17y_sspol_t ssel_pol; /**< Slave select line polarity. */
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
spi17y_width_t width; /**< Number of data lines to use, see #spi17y_width_t. */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
spi17y_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi Pointer to spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
* @param sys_cfg System configuration object
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq, const sys_cfg_spi17y_t* sys_cfg);
/**
* @brief Shutdown SPI module.
* @param spi Pointer to SPI regs.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi);
/**
* @brief Processing function for asynchronous SPI operations.
* This function must be called either from the SPI interrupt
* handler or periodically.
*
* @param spi Pointer to spi module.
*/
void SPI17Y_Handler(mxc_spi17y_regs_t *spi);
/**
* @brief Execute a master transaction.
* This function will block until the transaction is complete.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Execute a slave transaction.
* This function will block until the transaction is complete.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Aborts an Asynchronous request
*
* @param req Pointer to spi request
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_AbortAsync(spi17y_req_t *req);
/**
* @brief Enable SPI
* @param spi Pointer to spi module.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
void SPI17Y_Enable(mxc_spi17y_regs_t* spi);
/**
* @brief Disable SPI. Any pending asynchronous transactions will not
* complete and their callbacks will not be executed.
* @param spi Pointer to spi module.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
void SPI17Y_Disable(mxc_spi17y_regs_t* spi);
/**
* @brief Clear the TX and RX FIFO
* @param spi Pointer to spi module.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi);
/**@} end of group spi17y */
#ifdef __cplusplus
}
#endif
#endif /* _SPI17Y_H_ */

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/**
* @file spimss.h
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPIMSS_H_
#define _SPIMSS_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "mxc_sys.h"
#include "spimss_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spimss SPIMSS
* @ingroup spi
* @{
*/
/* **** Definitions **** */
/**
* @brief Enumeration type for setting the number data lines to use for communication.
*/
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
DUMMY_1, /**< NOT USED */
DUMMY_2, /**< NOT USED */
DUMMY_3, /**< NOT USED */
} spimss_width_t;
/**
* @brief Structure type representing a SPI Master Transaction request.
*/
typedef struct spimss_req spimss_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
* @addtogroup spi_async
*/
typedef void (*spimss_callback_fn)(spimss_req_t * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
* @addtogroup spi_async
*/
struct spimss_req {
uint8_t ssel; /**< Not Used*/
uint8_t deass; /**< Not Used*/
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
spimss_width_t width; /**< Not Used */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi Pointer to spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
* @param sys_cfg System configuration object
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg);
/**
* @brief Shutdown SPI module.
* @param spi Pointer to SPI regs.
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
/**
* @brief Execute a master transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Execute SPI transaction based on interrupt handler
* @param spi The spi
*
*/
void SPIMSS_Handler(mxc_spimss_regs_t *spi);
/**
* @brief Execute a slave transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Aborts an Asynchronous request
*
* @param req Pointer to spi request
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_AbortAsync(spimss_req_t *req);
/**@} end of group spimss */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_H_ */

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