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Merge pull request #9 from RT-Thread/master

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HubretXie
2019-12-12 14:54:04 +08:00
committed by GitHub
parent 7f56898fad 44123368a9
commit aa52a30b82
92 changed files with 8422 additions and 1996 deletions
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bsp/lpc54114-lite/README.md
+2 -2
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@@ -41,8 +41,8 @@ LPC54114-Lite 开发板的更多详细信息请参考万利电子 [开发板用
| SPI Flash | 支持 |- |
| SPI TF 卡 | 支持 |- |
| I2C 温度传感器 <BR>(PCT2075DP) | 支持 |- |
| I2S 音频输入 / 输出接口 <BR>(WM8904) | 暂不支持 |- |
| PDM 数字麦克风 <BR>(SPH0641LM4H) | 暂不支持 |- |
| I2S 音频输入 / 输出接口 <BR>(WM8904) | 支持 |仅支持解码 |
| PDM 数字麦克风 <BR>(SPH0641LM4H) | 支持 |- |
|**片上外设** |**支持情况**|**备注** |
| GPIO | 支持 | PIO0_0 ... PIO1_31 ---> PIN: 0, 1...63 |
| UART | 支持 | UART0 |
bsp/lpc54114-lite/drivers/Kconfig
+15
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@@ -35,4 +35,19 @@ menu "LPC54110 Bsp Config"
select BSP_USING_SPI2
default y
config BSP_USING_AUDIO
bool "Enable Audio(WM8904&SPH0641LU4H)"
select RT_USING_AUDIO
default n
if BSP_USING_AUDIO
config BSP_USING_AUDIO_REPLAY
bool "Enable WM8904(only replay)"
select BSP_USING_I2C4
default y
config BSP_USING_AUDIO_RECORD
bool "Enable SPH0641LU4H"
default y
endif
endmenu
bsp/lpc54114-lite/drivers/SConscript
+10
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@@ -29,6 +29,16 @@ if GetDepend('BSP_USING_SDCARD'):
if GetDepend('BSP_USING_SPIFLASH'):
src = src + ['drv_spi_flash.c']
if GetDepend('BSP_USING_AUDIO_REPLAY'):
src = src + ['audio/drv_sound.c']
src = src + ['audio/fsl_wm8904.c']
if GetDepend('BSP_USING_AUDIO_RECORD'):
src = src + ['audio/drv_mic.c']
if GetDepend('BSP_USING_AUDIO_REPLAY') or GetDepend('BSP_USING_AUDIO_RECORD'):
CPPPATH += [cwd+'audio']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/lpc54114-lite/drivers/audio/drv_mic.c
+163
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@@ -0,0 +1,163 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-11-17 LiWeiHao First implementation
*/
#include "drv_mic.h"
#include "fsl_common.h"
#include "fsl_iocon.h"
#include "fsl_dmic.h"
#include "fsl_dma.h"
#include "fsl_dmic_dma.h"
struct mic_device
{
dma_handle_t dma_handle;
dmic_dma_handle_t dmic_dma_handle;
struct rt_audio_device audio;
struct rt_audio_configure config;
rt_uint8_t *rx_fifo;
};
#define DMAREQ_DMIC0 16U
#define DMAREQ_DMIC1 17U
#define DMAREQ_CHANNEL DMAREQ_DMIC0
#define DMIC_CHANNEL kDMIC_Channel0
#define DMIC_CHANNEL_ENABLE DMIC_CHANEN_EN_CH0(1)
#define FIFO_DEPTH 15U
#define RX_DMA_FIFO_SIZE (2048)
struct mic_device mic_dev;
void dmic_dma_transfer_callback(DMIC_Type *base,
dmic_dma_handle_t *handle,
status_t status,
void *userData)
{
struct mic_device *mic_dev = (struct mic_device *)userData;
rt_audio_rx_done(&mic_dev->audio, &mic_dev->rx_fifo[0], RX_DMA_FIFO_SIZE);
dmic_transfer_t dmic_transfer;
dmic_transfer.data = (uint16_t *)&mic_dev->rx_fifo[0];
dmic_transfer.dataSize = RX_DMA_FIFO_SIZE / 2;
DMIC_TransferReceiveDMA(DMIC0, &mic_dev->dmic_dma_handle, &dmic_transfer, kDMIC_Channel0);
}
rt_err_t mic_device_init(struct rt_audio_device *audio)
{
dmic_channel_config_t dmic_channel_cfg;
CLOCK_EnableClock(kCLOCK_Iocon);
CLOCK_EnableClock(kCLOCK_InputMux);
CLOCK_EnableClock(kCLOCK_Gpio0);
IOCON_PinMuxSet(IOCON, 1, 16, IOCON_FUNC1 | IOCON_DIGITAL_EN);
IOCON_PinMuxSet(IOCON, 1, 15, IOCON_FUNC1 | IOCON_DIGITAL_EN);
CLOCK_AttachClk(kFRO12M_to_DMIC);
CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 14, false);
dmic_channel_cfg.divhfclk = kDMIC_PdmDiv1;
dmic_channel_cfg.osr = 25U;
dmic_channel_cfg.gainshft = 2U;
dmic_channel_cfg.preac2coef = kDMIC_CompValueZero;
dmic_channel_cfg.preac4coef = kDMIC_CompValueZero;
dmic_channel_cfg.dc_cut_level = kDMIC_DcCut155;
dmic_channel_cfg.post_dc_gain_reduce = 1;
dmic_channel_cfg.saturate16bit = 1U;
dmic_channel_cfg.sample_rate = kDMIC_PhyFullSpeed;
DMIC_Init(DMIC0);
DMIC_ConfigIO(DMIC0, kDMIC_PdmDual);
DMIC_Use2fs(DMIC0, true);
DMIC_SetOperationMode(DMIC0, kDMIC_OperationModeDma);
DMIC_ConfigChannel(DMIC0, DMIC_CHANNEL, kDMIC_Left, &dmic_channel_cfg);
DMIC_FifoChannel(DMIC0, DMIC_CHANNEL, FIFO_DEPTH, true, true);
DMIC_EnableChannnel(DMIC0, DMIC_CHANNEL_ENABLE);
DMA_EnableChannel(DMA0, DMAREQ_CHANNEL);
/* Request dma channels from DMA manager. */
DMA_CreateHandle(&mic_dev.dma_handle, DMA0, DMAREQ_CHANNEL);
/* Create DMIC DMA handle. */
DMIC_TransferCreateHandleDMA(DMIC0,
&mic_dev.dmic_dma_handle,
dmic_dma_transfer_callback,
(void *)&mic_dev,
&mic_dev.dma_handle);
return RT_EOK;
}
rt_err_t mic_device_start(struct rt_audio_device *audio, int stream)
{
struct mic_device *mic_dev = (struct mic_device *)audio->parent.user_data;
if (stream == AUDIO_STREAM_RECORD)
{
dmic_transfer_t dmic_transfer;
dmic_transfer.data = (uint16_t *)&mic_dev->rx_fifo[0];
dmic_transfer.dataSize = RX_DMA_FIFO_SIZE / 2;
DMIC_TransferReceiveDMA(DMIC0, &mic_dev->dmic_dma_handle, &dmic_transfer, kDMIC_Channel0);
}
return RT_EOK;
}
rt_err_t mic_device_stop(struct rt_audio_device *audio, int stream)
{
struct mic_device *mic_dev = (struct mic_device *)audio->parent.user_data;
if (stream == AUDIO_STREAM_RECORD)
{
DMIC_TransferAbortReceiveDMA(DMIC0, &mic_dev->dmic_dma_handle);
}
return RT_EOK;
}
rt_err_t mic_device_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
return RT_EOK;
}
rt_err_t mic_device_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
return RT_EOK;
}
static struct rt_audio_ops _mic_audio_ops =
{
.getcaps = mic_device_getcaps,
.configure = mic_device_configure,
.init = mic_device_init,
.start = mic_device_start,
.stop = mic_device_stop,
.transmit = RT_NULL,
.buffer_info = RT_NULL,
};
int rt_hw_mic_init(void)
{
struct rt_audio_device *audio = &mic_dev.audio;
/* mic default */
mic_dev.rx_fifo = rt_calloc(1, RX_DMA_FIFO_SIZE);
if (mic_dev.rx_fifo == RT_NULL)
{
return -RT_ENOMEM;
}
mic_dev.config.channels = 1;
mic_dev.config.samplerate = 16000;
mic_dev.config.samplebits = 16;
/* register mic device */
audio->ops = &_mic_audio_ops;
rt_audio_register(audio, "mic0", RT_DEVICE_FLAG_RDONLY, (void *)&mic_dev);
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_mic_init);
bsp/lpc54114-lite/drivers/audio/drv_mic.h
+17
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@@ -0,0 +1,17 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-11-17 LiWeiHao First implementation
*/
#ifndef __DRV_MIC_H__
#define __DRV_MIC_H__
#include <rtthread.h>
#include <rtdevice.h>
#endif
bsp/lpc54114-lite/drivers/audio/drv_sound.c
+361
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@@ -0,0 +1,361 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-11-17 LiWeiHao First implementation
*/
#include "drv_sound.h"
#include "fsl_common.h"
#include "fsl_iocon.h"
#include "fsl_dma.h"
#include "fsl_i2s.h"
#include "fsl_i2s_dma.h"
#include "fsl_wm8904.h"
#include "fsl_i2c.h"
#define TX_FIFO_SIZE (4096)
#define I2S_TX I2S1
#define I2S_RX I2S0
#define I2S_DMA_TX 15
#define I2S_DMA_RX 12
#ifndef CODEC_I2C_NAME
#define CODEC_I2C_NAME "i2c4"
#endif
struct sound_device
{
wm8904_handle_t wm8904_handle;
dma_handle_t tx_dma_handle;
i2s_dma_handle_t tx_i2s_dma_handle;
struct rt_audio_device audio;
struct rt_audio_configure replay_config;
rt_uint8_t volume;
rt_uint8_t *tx_fifo;
};
const pll_setup_t pll_setup =
{
.syspllctrl = SYSCON_SYSPLLCTRL_BANDSEL_MASK | SYSCON_SYSPLLCTRL_SELP(0x1FU) | SYSCON_SYSPLLCTRL_SELI(0x8U),
.syspllndec = SYSCON_SYSPLLNDEC_NDEC(0x2DU),
.syspllpdec = SYSCON_SYSPLLPDEC_PDEC(0x42U),
.syspllssctrl = {SYSCON_SYSPLLSSCTRL0_MDEC(0x34D3U) | SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK, 0x00000000U},
.pllRate = 24576000U, /* 16 bits * 2 channels * 44.1 kHz * 16 */
.flags = PLL_SETUPFLAG_WAITLOCK
};
static struct sound_device snd_dev;
void i2s_tx_transfer_callback(I2S_Type *base,
i2s_dma_handle_t *handle,
status_t completionStatus,
void *userData)
{
struct sound_device *snd_dev = (struct sound_device *)userData;
rt_audio_tx_complete(&snd_dev->audio);
}
static rt_err_t lpc_audio_init(struct rt_audio_device *audio)
{
i2s_config_t tx_i2s_config;
wm8904_config_t wm8904_config;
CLOCK_EnableClock(kCLOCK_Iocon);
CLOCK_EnableClock(kCLOCK_InputMux);
CLOCK_EnableClock(kCLOCK_Gpio0);
CLOCK_EnableClock(kCLOCK_Gpio1);
CLOCK_AttachClk(kFRO12M_to_SYS_PLL);
CLOCK_AttachClk(kSYS_PLL_to_FLEXCOMM7);
RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
CLOCK_SetPLLFreq(&pll_setup);
CLOCK_AttachClk(kSYS_PLL_to_MCLK);
SYSCON->MCLKDIV = SYSCON_MCLKDIV_DIV(0U);
// Flexcomm 7 I2S Tx
IOCON_PinMuxSet(IOCON, 1, 12, IOCON_FUNC4 | IOCON_DIGITAL_EN); /* Flexcomm 7 / SCK */
IOCON_PinMuxSet(IOCON, 1, 13, IOCON_FUNC4 | IOCON_DIGITAL_EN); /* Flexcomm 7 / SDA */
IOCON_PinMuxSet(IOCON, 1, 14, IOCON_FUNC4 | IOCON_DIGITAL_EN); /* Flexcomm 7 / WS */
/* MCLK output for I2S */
IOCON_PinMuxSet(IOCON, 1, 17, IOCON_FUNC4 | IOCON_MODE_INACT | IOCON_DIGITAL_EN);
SYSCON->MCLKIO = 1U;
WM8904_GetDefaultConfig(&wm8904_config);
snd_dev.wm8904_handle.i2c = (struct rt_i2c_bus_device *)rt_device_find(CODEC_I2C_NAME);
if (WM8904_Init(&snd_dev.wm8904_handle, &wm8904_config) != kStatus_Success)
{
rt_kprintf("wm8904 init failed\n");
return -RT_ERROR;
}
WM8904_SetMute(&snd_dev.wm8904_handle, RT_TRUE, RT_TRUE);
I2S_TxGetDefaultConfig(&tx_i2s_config);
tx_i2s_config.divider = CLOCK_GetPllOutFreq() / 48000U / 16 / 2;
I2S_TxInit(I2S_TX, &tx_i2s_config);
DMA_Init(DMA0);
DMA_EnableChannel(DMA0, I2S_DMA_TX);
DMA_SetChannelPriority(DMA0, I2S_DMA_TX, kDMA_ChannelPriority3);
DMA_CreateHandle(&snd_dev.tx_dma_handle, DMA0, I2S_DMA_TX);
I2S_TxTransferCreateHandleDMA(I2S_TX,
&snd_dev.tx_i2s_dma_handle,
&snd_dev.tx_dma_handle,
i2s_tx_transfer_callback,
(void *)&snd_dev);
return RT_EOK;
}
static rt_err_t lpc_audio_start(struct rt_audio_device *audio, int stream)
{
RT_ASSERT(audio != RT_NULL);
if (stream == AUDIO_STREAM_REPLAY)
{
struct rt_audio_caps caps;
caps.main_type = AUDIO_TYPE_MIXER;
caps.sub_type = AUDIO_MIXER_VOLUME;
audio->ops->getcaps(audio, &caps);
audio->ops->configure(audio, &caps);
rt_audio_tx_complete(audio);
}
return RT_EOK;
}
static rt_err_t lpc_audio_stop(struct rt_audio_device *audio, int stream)
{
if (stream == AUDIO_STREAM_REPLAY)
{
WM8904_SetMute(&snd_dev.wm8904_handle, RT_TRUE, RT_TRUE);
I2S_TransferAbortDMA(I2S_TX, &snd_dev.tx_i2s_dma_handle);
}
return RT_EOK;
}
static rt_err_t lpc_audio_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev;
RT_ASSERT(audio != RT_NULL);
snd_dev = (struct sound_device *)audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_QUERY: /* qurey the types of hw_codec device */
{
switch (caps->sub_type)
{
case AUDIO_TYPE_QUERY:
caps->udata.mask = AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_OUTPUT: /* Provide capabilities of OUTPUT unit */
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
caps->udata.config.samplerate = snd_dev->replay_config.samplerate;
caps->udata.config.channels = snd_dev->replay_config.channels;
caps->udata.config.samplebits = snd_dev->replay_config.samplebits;
break;
case AUDIO_DSP_SAMPLERATE:
caps->udata.config.samplerate = snd_dev->replay_config.samplerate;
break;
case AUDIO_DSP_CHANNELS:
caps->udata.config.channels = snd_dev->replay_config.channels;
break;
case AUDIO_DSP_SAMPLEBITS:
caps->udata.config.samplebits = snd_dev->replay_config.samplebits;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
case AUDIO_TYPE_MIXER: /* report the Mixer Units */
{
switch (caps->sub_type)
{
case AUDIO_MIXER_QUERY:
caps->udata.mask = AUDIO_MIXER_VOLUME;
break;
case AUDIO_MIXER_VOLUME:
caps->udata.value = snd_dev->volume;
break;
default:
result = -RT_ERROR;
break;
}
break;
}
default:
result = -RT_ERROR;
break;
}
return result;
}
static rt_err_t lpc_audio_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
{
rt_err_t result = RT_EOK;
struct sound_device *snd_dev = audio->parent.user_data;
switch (caps->main_type)
{
case AUDIO_TYPE_MIXER:
{
switch (caps->sub_type)
{
case AUDIO_MIXER_MUTE:
{
WM8904_SetMute(&snd_dev->wm8904_handle, RT_TRUE, RT_TRUE);
snd_dev->volume = 0;
break;
}
case AUDIO_MIXER_VOLUME:
{
int volume = caps->udata.value / 2;
WM8904_SetMute(&snd_dev->wm8904_handle, RT_FALSE, RT_FALSE);
WM8904_SetVolume(&snd_dev->wm8904_handle, volume, volume);
snd_dev->volume = volume;
break;
}
}
break;
}
case AUDIO_TYPE_OUTPUT:
{
switch (caps->sub_type)
{
case AUDIO_DSP_PARAM:
{
struct rt_audio_configure config = caps->udata.config;
i2s_config_t tx_i2s_config;
snd_dev->replay_config.channels = config.channels;
snd_dev->replay_config.samplebits = config.samplebits;
snd_dev->replay_config.samplerate = config.samplerate;
I2S_TxGetDefaultConfig(&tx_i2s_config);
tx_i2s_config.divider = CLOCK_GetPllOutFreq() / config.samplerate / 16 / 2;
I2S_TxInit(I2S_TX, &tx_i2s_config);
break;
}
case AUDIO_DSP_SAMPLERATE:
{
struct rt_audio_configure config = caps->udata.config;
i2s_config_t tx_i2s_config;
snd_dev->replay_config.samplerate = config.samplerate;
I2S_TxGetDefaultConfig(&tx_i2s_config);
tx_i2s_config.divider = CLOCK_GetPllOutFreq() / config.samplerate / 16 / 2;
I2S_TxInit(I2S_TX, &tx_i2s_config);
break;
}
default:
result = -RT_ERROR;
break;
}
break;
}
}
return result;
}
static rt_size_t lpc_audio_transmit(struct rt_audio_device *audio, const void *writeBuf, void *readBuf, rt_size_t size)
{
RT_ASSERT(audio != RT_NULL);
i2s_transfer_t transfer;
transfer.data = (uint8_t *)writeBuf;
transfer.dataSize = size;
I2S_TxTransferSendDMA(I2S_TX, &snd_dev.tx_i2s_dma_handle, transfer);
return RT_EOK;
}
static void lpc_audio_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
{
RT_ASSERT(audio != RT_NULL);
/**
* TX_FIFO
* +----------------+----------------+
* | block1 | block2 |
* +----------------+----------------+
* \ block_size /
*/
info->buffer = snd_dev.tx_fifo;
info->total_size = TX_FIFO_SIZE;
info->block_size = TX_FIFO_SIZE / 2;
info->block_count = 2;
}
static struct rt_audio_ops audio_ops =
{
.getcaps = lpc_audio_getcaps,
.configure = lpc_audio_configure,
.init = lpc_audio_init,
.start = lpc_audio_start,
.stop = lpc_audio_stop,
.transmit = lpc_audio_transmit,
.buffer_info = lpc_audio_buffer_info,
};
int rt_hw_sound_init(void)
{
rt_uint8_t *tx_fifo = RT_NULL;
tx_fifo = rt_malloc(TX_FIFO_SIZE);
if (tx_fifo == NULL)
{
return -RT_ENOMEM;
}
snd_dev.tx_fifo = tx_fifo;
/* init default configuration */
{
snd_dev.replay_config.samplerate = 44100;
snd_dev.replay_config.channels = 2;
snd_dev.replay_config.samplebits = 16;
snd_dev.volume = 30;
}
snd_dev.audio.ops = &audio_ops;
rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_sound_init);
bsp/lpc54114-lite/drivers/audio/drv_sound.h
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@@ -0,0 +1,17 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-11-17 LiWeiHao First implementation
*/
#ifndef __DRV_SOUND_H__
#define __DRV_SOUND_H__
#include <rtthread.h>
#include <rtdevice.h>
#endif
bsp/lpc54114-lite/drivers/audio/fsl_wm8904.c
Executable
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bsp/lpc54114-lite/drivers/audio/fsl_wm8904.h
Executable
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@@ -0,0 +1,247 @@
/*
* The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Change Logs:
* Date Author Notes
* 2019-11-09 LiWeiHao Porting to RT-Thread
*/
#ifndef _FSL_WM8904_H_
#define _FSL_WM8904_H_
#include "fsl_common.h"
#include "rtdevice.h"
#include "rtthread.h"
/*!
* @addtogroup wm8904
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief WM8904 I2C address. */
#define WM8904_I2C_ADDRESS (0x1A)
/*! @brief WM8904 I2C bit rate. */
#define WM8904_I2C_BITRATE (400000U)
/*! @brief WM8904 status return codes. */
enum _wm8904_status
{
kStatus_WM8904_Success = 0x0, /*!< Success */
kStatus_WM8904_Fail = 0x1 /*!< Failure */
};
/*! @brief The audio data transfer protocol. */
typedef enum _wm8904_protocol
{
kWM8904_ProtocolRightJustified = 0x0, /*!< Right justified mode */
kWM8904_ProtocolLeftJustified = 0x1, /*!< Left justified mode */
kWM8904_ProtocolI2S = 0x2, /*!< I2S mode */
kWM8904_ProtocolDSP = 0x3 /*!< DSP mode */
} wm8904_protocol_t;
/*! @brief The SYSCLK / fs ratio. */
typedef enum _wm8904_fs_ratio
{
kWM8904_FsRatio64X = 0x0, /*!< SYSCLK is 64 * sample rate * frame width */
kWM8904_FsRatio128X = 0x1, /*!< SYSCLK is 128 * sample rate * frame width */
kWM8904_FsRatio192X = 0x2, /*!< SYSCLK is 192 * sample rate * frame width */
kWM8904_FsRatio256X = 0x3, /*!< SYSCLK is 256 * sample rate * frame width */
kWM8904_FsRatio384X = 0x4, /*!< SYSCLK is 384 * sample rate * frame width */
kWM8904_FsRatio512X = 0x5, /*!< SYSCLK is 512 * sample rate * frame width */
kWM8904_FsRatio768X = 0x6, /*!< SYSCLK is 768 * sample rate * frame width */
kWM8904_FsRatio1024X = 0x7, /*!< SYSCLK is 1024 * sample rate * frame width */
kWM8904_FsRatio1408X = 0x8, /*!< SYSCLK is 1408 * sample rate * frame width */
kWM8904_FsRatio1536X = 0x9 /*!< SYSCLK is 1536 * sample rate * frame width */
} wm8904_fs_ratio_t;
/*! @brief Sample rate. */
typedef enum _wm8904_sample_rate
{
kWM8904_SampleRate8kHz = 0x0, /*!< 8 kHz */
kWM8904_SampleRate12kHz = 0x1, /*!< 11.025kHz, 12kHz */
kWM8904_SampleRate16kHz = 0x2, /*!< 16kHz */
kWM8904_SampleRate24kHz = 0x3, /*!< 22.05kHz, 24kHz */
kWM8904_SampleRate32kHz = 0x4, /*!< 32kHz */
kWM8904_SampleRate48kHz = 0x5 /*!< 44.1kHz, 48kHz */
} wm8904_sample_rate_t;
/*! @brief Bit width. */
typedef enum _wm8904_bit_width
{
kWM8904_BitWidth16 = 0x0, /*!< 16 bits */
kWM8904_BitWidth20 = 0x1, /*!< 20 bits */
kWM8904_BitWidth24 = 0x2, /*!< 24 bits */
kWM8904_BitWidth32 = 0x3 /*!< 32 bits */
} wm8904_bit_width_t;
/*! @brief Audio format configuration. */
typedef struct _wm8904_audio_format
{
wm8904_fs_ratio_t fsRatio; /*!< SYSCLK / fs ratio */
wm8904_sample_rate_t sampleRate; /*!< Sample rate */
wm8904_bit_width_t bitWidth; /*!< Bit width */
} wm8904_audio_format_t;
/*! @brief WM8904 data. */
typedef struct _wm8904_handle
{
struct rt_i2c_bus_device *i2c; /*!< Configured I2C instance */
} wm8904_handle_t;
/*! @brief Configuration structure of WM8904. */
typedef struct _wm8904_config
{
bool master; /*!< Master or slave */
wm8904_protocol_t protocol; /*!< Audio transfer protocol */
wm8904_audio_format_t format; /*!< Audio format */
} wm8904_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C"
{
#endif
/*!
* @brief Initializes WM8904.
*
* @param handle WM8904 handle structure.
* @param codec_config WM8904 configuration structure.
*/
status_t WM8904_Init(wm8904_handle_t *handle, wm8904_config_t *config);
/*!
* @brief Deinitializes the WM8904 codec.
*
* This function resets WM8904.
*
* @param handle WM8904 handle structure.
*
* @return kStatus_WM8904_Success if successful, different code otherwise.
*/
status_t WM8904_Deinit(wm8904_handle_t *handle);
/*!
* @brief Fills the configuration structure with default values.
*
* The default values are:
*
* master = false;
* protocol = kWM8904_ProtocolI2S;
* format.fsRatio = kWM8904_FsRatio64X;
* format.sampleRate = kWM8904_SampleRate48kHz;
* format.bitWidth = kWM8904_BitWidth16;
*
* @param handle WM8904 handle structure to be filled with default values.
*/
void WM8904_GetDefaultConfig(wm8904_config_t *config);
/*!
* @brief Sets WM8904 as master or slave.
*
* @param handle WM8904 handle structure.
* @param master true for master, false for slave.
*
* @return kStatus_WM8904_Success if successful, different code otherwise.
*/
status_t WM8904_SetMasterSlave(wm8904_handle_t *handle, bool master);
/*!
* @brief Sets the audio data transfer protocol.
*
* @param handle WM8904 handle structure.
* @param protocol Audio transfer protocol.
*
* @return kStatus_WM8904_Success if successful, different code otherwise.
*/
status_t WM8904_SetProtocol(wm8904_handle_t *handle, wm8904_protocol_t protocol);
/*!
* @brief Sets the audio data format.
*
* @param handle WM8904 handle structure.
* @param format Audio format parameters.
*
* @return kStatus_WM8904_Success if successful, different code otherwise.
*/
status_t WM8904_SetAudioFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format);
/*!
* @brief Sets the headphone output volume.
*
* The parameter should be from 0 to 63.
* The resulting volume will be (parameter - 57 dB).
* 0 for -57 dB, 57 for 0 dB, 63 for +6 dB etc.
*
* @param handle WM8904 handle structure.
* @param volumeLeft Volume of the left channel.
* @param volumeRight Volume of the right channel.
*
* @return kStatus_WM8904_Success if successful, different code otherwise.
*/
status_t WM8904_SetVolume(wm8904_handle_t *handle, uint16_t volumeLeft, uint16_t volumeRight);
/*!
* @brief Sets the headphone output mute.
*
* @param handle WM8904 handle structure.
* @param muteLeft true to mute left channel, false to unmute.
* @param muteRight true to mute right channel, false to unmute.
*
* @return kStatus_WM8904_Success if successful, different code otherwise.
*/
status_t WM8904_SetMute(wm8904_handle_t *handle, bool muteLeft, bool muteRight);
/*!
* @brief Reads content of all WM8904 registers and prints it to debug console.
*
* @param handle WM8904 handle structure.
*
* @return kStatus_WM8904_Success if successful, different code otherwise.
*/
status_t WM8904_PrintRegisters(wm8904_handle_t *handle);
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* _FSL_WM8904_H_ */
bsp/stm32/docs/STM32系列外设驱动添加指南.md
+1
View File
@@ -95,6 +95,7 @@
| 10 | Watchdog | **开启该外设** |
| 11 | EMAC | **配置 ETH 外设的工作模式（一般为 RMII 模式）** |
| 12 | SDRAM | **需要根据板载的 SDRAM 型号配置片选脚，地址线，数据线等** |
| 13 | SDIO | **开启该外设，配置引脚（或者使用默认引脚），SDIO会改变时钟结构，故需重新配置时钟并修改board.c** |
### 5.3 复杂外设配置说明
bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
+23
View File
@@ -133,6 +133,29 @@ extern "C" {
#endif /* UART5_DMA_RX_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = USART6, \
.irq_type = USART6_IRQn, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_UART6_RX_USING_DMA)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.Instance = UART6_RX_DMA_INSTANCE, \
.channel = UART6_RX_DMA_CHANNEL, \
.dma_rcc = UART6_RX_DMA_RCC, \
.dma_irq = UART6_RX_DMA_IRQ, \
}
#endif /* UART6_DMA_RX_CONFIG */
#endif /* BSP_UART6_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h
+69
View File
@@ -7,6 +7,7 @@
* Date Author Notes
* 2019-01-05 zylx first version
* 2019-01-08 SummerGift clean up the code
* 2019-12-01 armink add DMAMUX support
*/
#ifndef __DMA_CONFIG_H__
@@ -25,7 +26,11 @@ extern "C" {
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
#if defined(DMAMUX1) /* for L4+ */
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
#else /* for L4 */
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_1
#endif /* DMAMUX1 */
#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
#endif
@@ -34,13 +39,21 @@ extern "C" {
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
#if defined(DMAMUX1) /* for L4+ */
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
#else /* for L4 */
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_1
#endif /* DMAMUX1 */
#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART3_RX_DMA_INSTANCE DMA1_Channel3
#if defined(DMAMUX1) /* for L4+ */
#define UART3_RX_DMA_REQUEST DMA_REQUEST_USART3_RX
#else /* for L4 */
#define UART3_RX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
#endif
@@ -49,13 +62,21 @@ extern "C" {
#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART1_TX_DMA_INSTANCE DMA1_Channel4
#if defined(DMAMUX1) /* for L4+ */
#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
#else /* for L4 */
#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
#if defined(DMAMUX1) /* for L4+ */
#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
#else /* for L4 */
#define SPI2_RX_DMA_REQUEST DMA_REQUEST_1
#endif /* DMAMUX1 */
#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
#endif
@@ -64,19 +85,31 @@ extern "C" {
#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART1_RX_DMA_INSTANCE DMA1_Channel5
#if defined(DMAMUX1) /* for L4+ */
#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
#else /* for L4 */
#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN
#define QSPI_DMA_INSTANCE DMA1_Channel5
#if defined(DMAMUX1) /* for L4+ */
#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1
#else /* for L4 */
#define QSPI_DMA_REQUEST DMA_REQUEST_5
#endif /* DMAMUX1 */
#define QSPI_DMA_IRQ DMA1_Channel5_IRQn
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
#if defined(DMAMUX1) /* for L4+ */
#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
#else /* for L4 */
#define SPI2_TX_DMA_REQUEST DMA_REQUEST_1
#endif /* DMAMUX1 */
#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
#endif
@@ -85,7 +118,11 @@ extern "C" {
#define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Channel6
#if defined(DMAMUX1) /* for L4+ */
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
#else /* for L4 */
#define UART2_RX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn
#endif
@@ -96,7 +133,11 @@ extern "C" {
#define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler
#define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART5_TX_DMA_INSTANCE DMA2_Channel1
#if defined(DMAMUX1) /* for L4+ */
#define UART5_TX_DMA_REQUEST DMA_REQUEST_UART5_TX
#else /* for L4 */
#define UART5_TX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn
#endif
@@ -105,7 +146,11 @@ extern "C" {
#define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART5_RX_DMA_INSTANCE DMA2_Channel2
#if defined(DMAMUX1) /* for L4+ */
#define UART5_RX_DMA_REQUEST DMA_REQUEST_UART5_RX
#else /* for L4 */
#define UART5_RX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn
#endif
@@ -114,7 +159,11 @@ extern "C" {
#define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Channel3
#if defined(DMAMUX1) /* for L4+ */
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
#else /* for L4 */
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_4
#endif /* DMAMUX1 */
#define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn
#endif
@@ -123,7 +172,11 @@ extern "C" {
#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Channel4
#if defined(DMAMUX1) /* for L4+ */
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
#else /* for L4 */
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_4
#endif /* DMAMUX1 */
#define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn
#endif
@@ -134,7 +187,11 @@ extern "C" {
#define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_TX_DMA_INSTANCE DMA2_Channel6
#if defined(DMAMUX1) /* for L4+ */
#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
#else /* for L4 */
#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn
#endif
@@ -143,19 +200,31 @@ extern "C" {
#define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_RX_DMA_INSTANCE DMA2_Channel7
#if defined(DMAMUX1) /* for L4+ */
#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
#else /* for L4 */
#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
#endif /* DMAMUX1 */
#define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
#define QSPI_DMA_INSTANCE DMA2_Channel7
#if defined(DMAMUX1) /* for L4+ */
#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1
#else /* for L4 */
#define QSPI_DMA_REQUEST DMA_REQUEST_3
#endif /* DMAMUX1 */
#define QSPI_DMA_IRQ DMA2_Channel7_IRQn
#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
#define LPUART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler
#define LPUART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define LPUART1_RX_DMA_INSTANCE DMA2_Channel7
#if defined(DMAMUX1) /* for L4+ */
#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX
#else /* for L4 */
#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_4
#endif /* DMAMUX1 */
#define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn
#endif
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
+1 -1
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@@ -270,7 +270,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, 2048, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+7 -1
View File
@@ -22,7 +22,7 @@
!defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
#ifdef RT_SERIAL_USING_DMA
@@ -749,6 +749,12 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1)
/* enable DMAMUX clock for L4+ and G4 */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
#endif
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
bsp/stm32/libraries/HAL_Drivers/drv_usbd.c
+16
View File
@@ -239,11 +239,27 @@ const static struct udcd_ops _udc_ops =
_wakeup,
};
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops _ops =
{
_init,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
};
#endif
int stm_usbd_register(void)
{
rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd));
_stm_udc.parent.type = RT_Device_Class_USBDevice;
#ifdef RT_USING_DEVICE_OPS
_stm_udc.parent.ops = &_ops;
#else
_stm_udc.parent.init = _init;
#endif
_stm_udc.parent.user_data = &_stm_pcd;
_stm_udc.ops = &_udc_ops;
/* Register endpoint infomation */
bsp/stm32/stm32f103-dofly-M3S/.cproject
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bsp/stm32/stm32f103-yf-ufun/.cproject
+1 -1
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bsp/stm32/stm32f401-st-nucleo/.cproject
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bsp/stm32/stm32f405-smdz-breadfruit/.cproject
+152 -152
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bsp/stm32/stm32f407-atk-explorer/.cproject
+1 -1
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bsp/stm32/stm32f411-st-nucleo/.cproject
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bsp/stm32/stm32f427-robomaster-a/README.md
+1 -1
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@@ -37,7 +37,7 @@ RoboMaster开发板套件是一款面向机器人DIY的开源主控套件。开
| **板载外设** | **支持情况** | **备注** |
| :----------------- | :----------: | :------------------------------------- |
| SD卡 | 暂不支持 | |
| SD卡 | 支持 | |
| CAN | 支持 | 需通过24vXT30接口或usb接口供电 |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/.mxproject
+2 -2
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bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/CubeMX_Config.ioc
+69 -49
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@@ -8,59 +8,66 @@ KeepUserPlacement=true
Mcu.Family=STM32F4
Mcu.IP0=CAN1
Mcu.IP1=CAN2
Mcu.IP10=UART8
Mcu.IP11=USART1
Mcu.IP12=USART3
Mcu.IP13=USART6
Mcu.IP10=UART7
Mcu.IP11=UART8
Mcu.IP12=USART1
Mcu.IP13=USART3
Mcu.IP14=USART6
Mcu.IP2=NVIC
Mcu.IP3=RCC
Mcu.IP4=SPI5
Mcu.IP5=SYS
Mcu.IP6=TIM4
Mcu.IP7=TIM5
Mcu.IP8=TIM12
Mcu.IP9=UART7
Mcu.IPNb=14
Mcu.IP4=SDIO
Mcu.IP5=SPI5
Mcu.IP6=SYS
Mcu.IP7=TIM4
Mcu.IP8=TIM5
Mcu.IP9=TIM12
Mcu.IPNb=15
Mcu.Name=STM32F427I(G-I)Hx
Mcu.Package=UFBGA176
Mcu.Pin0=PE1
Mcu.Pin1=PE0
Mcu.Pin10=PI0
Mcu.Pin11=PH0/OSC_IN
Mcu.Pin12=PH1/OSC_OUT
Mcu.Pin13=PF7
Mcu.Pin14=PF6
Mcu.Pin15=PH12
Mcu.Pin16=PF9
Mcu.Pin17=PF8
Mcu.Pin18=PH11
Mcu.Pin19=PH10
Mcu.Pin10=PC10
Mcu.Pin11=PG9
Mcu.Pin12=PD1
Mcu.Pin13=PD2
Mcu.Pin14=PI0
Mcu.Pin15=PC9
Mcu.Pin16=PH0/OSC_IN
Mcu.Pin17=PC8
Mcu.Pin18=PH1/OSC_OUT
Mcu.Pin19=PF7
Mcu.Pin2=PG14
Mcu.Pin20=PD15
Mcu.Pin21=PH6
Mcu.Pin22=PD14
Mcu.Pin23=PD13
Mcu.Pin24=PD12
Mcu.Pin25=PE8
Mcu.Pin26=PE11
Mcu.Pin27=PB12
Mcu.Pin28=PB13
Mcu.Pin29=PD9
Mcu.Pin3=PA14
Mcu.Pin30=PD8
Mcu.Pin31=PF14
Mcu.Pin32=PE7
Mcu.Pin33=VP_SYS_VS_Systick
Mcu.Pin34=VP_TIM4_VS_ClockSourceINT
Mcu.Pin35=VP_TIM5_VS_ClockSourceINT
Mcu.Pin36=VP_TIM12_VS_ClockSourceINT
Mcu.Pin4=PA13
Mcu.Pin5=PB7
Mcu.Pin6=PB6
Mcu.Pin7=PD0
Mcu.Pin8=PG9
Mcu.Pin9=PD1
Mcu.PinsNb=37
Mcu.Pin20=PF6
Mcu.Pin21=PH12
Mcu.Pin22=PF9
Mcu.Pin23=PF8
Mcu.Pin24=PH11
Mcu.Pin25=PH10
Mcu.Pin26=PD15
Mcu.Pin27=PH6
Mcu.Pin28=PD14
Mcu.Pin29=PD13
Mcu.Pin3=PC12
Mcu.Pin30=PD12
Mcu.Pin31=PE8
Mcu.Pin32=PE11
Mcu.Pin33=PB12
Mcu.Pin34=PB13
Mcu.Pin35=PD9
Mcu.Pin36=PD8
Mcu.Pin37=PF14
Mcu.Pin38=PE7
Mcu.Pin39=VP_SYS_VS_Systick
Mcu.Pin4=PA14
Mcu.Pin40=VP_TIM4_VS_ClockSourceINT
Mcu.Pin41=VP_TIM5_VS_ClockSourceINT
Mcu.Pin42=VP_TIM12_VS_ClockSourceINT
Mcu.Pin5=PA13
Mcu.Pin6=PB7
Mcu.Pin7=PB6
Mcu.Pin8=PD0
Mcu.Pin9=PC11
Mcu.PinsNb=43
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32F427IIHx
@@ -93,6 +100,16 @@ PB6.Signal=USART1_TX
PB7.Locked=true
PB7.Mode=Asynchronous
PB7.Signal=USART1_RX
PC10.Mode=SD_4_bits_Wide_bus
PC10.Signal=SDIO_D2
PC11.Mode=SD_4_bits_Wide_bus
PC11.Signal=SDIO_D3
PC12.Mode=SD_4_bits_Wide_bus
PC12.Signal=SDIO_CK
PC8.Mode=SD_4_bits_Wide_bus
PC8.Signal=SDIO_D0
PC9.Mode=SD_4_bits_Wide_bus
PC9.Signal=SDIO_D1
PCC.Checker=false
PCC.Line=STM32F427/437
PCC.MCU=STM32F427I(G-I)Hx
@@ -114,6 +131,8 @@ PD14.Locked=true
PD14.Signal=S_TIM4_CH3
PD15.Locked=true
PD15.Signal=S_TIM4_CH4
PD2.Mode=SD_4_bits_Wide_bus
PD2.Signal=SDIO_CMD
PD8.Locked=true
PD8.Mode=Asynchronous
PD8.Signal=USART3_TX
@@ -194,7 +213,7 @@ ProjectManager.TargetToolchain=MDK-ARM V5
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-true,3-MX_SPI5_Init-SPI5-false-HAL-true,4-MX_USART6_UART_Init-USART6-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_CAN2_Init-CAN2-false-HAL-true,7-MX_TIM4_Init-TIM4-false-HAL-true,8-MX_TIM5_Init-TIM5-false-HAL-true,9-MX_TIM12_Init-TIM12-false-HAL-true,10-MX_UART7_Init-UART7-false-HAL-true,11-MX_UART8_Init-UART8-false-HAL-true,12-MX_USART1_UART_Init-USART1-false-HAL-true,13-MX_USART3_UART_Init-USART3-false-HAL-true
RCC.48MHZClocksFreq_Value=90000000
RCC.48MHZClocksFreq_Value=45000000
RCC.AHBFreq_Value=180000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=45000000
@@ -210,14 +229,15 @@ RCC.HCLKFreq_Value=180000000
RCC.HSE_VALUE=12000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=192000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VcooutputI2S,VcooutputI2SQ
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VcooutputI2S,VcooutputI2SQ
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=180000000
RCC.PLLCLKFreq_Value=180000000
RCC.PLLM=6
RCC.PLLN=180
RCC.PLLQCLKFreq_Value=90000000
RCC.PLLQ=8
RCC.PLLQCLKFreq_Value=45000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RTCFreq_Value=32000
RCC.RTCHSEDivFreq_Value=6000000
bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h
+1 -1
View File
@@ -58,7 +58,7 @@
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
#define HAL_SD_MODULE_ENABLED
/* #define HAL_MMC_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/main.c
+42 -1
View File
@@ -65,6 +65,8 @@
CAN_HandleTypeDef hcan1;
CAN_HandleTypeDef hcan2;
SD_HandleTypeDef hsd;
SPI_HandleTypeDef hspi5;
TIM_HandleTypeDef htim4;
@@ -95,6 +97,7 @@ static void MX_UART7_Init(void);
static void MX_UART8_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_USART3_UART_Init(void);
static void MX_SDIO_SD_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@@ -144,6 +147,7 @@ int main(void)
MX_UART8_Init();
MX_USART1_UART_Init();
MX_USART3_UART_Init();
MX_SDIO_SD_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@@ -181,7 +185,7 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLM = 6;
RCC_OscInitStruct.PLL.PLLN = 180;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLQ = 8;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
@@ -281,6 +285,42 @@ static void MX_CAN2_Init(void)
}
/**
* @brief SDIO Initialization Function
* @param None
* @retval None
*/
static void MX_SDIO_SD_Init(void)
{
/* USER CODE BEGIN SDIO_Init 0 */
/* USER CODE END SDIO_Init 0 */
/* USER CODE BEGIN SDIO_Init 1 */
/* USER CODE END SDIO_Init 1 */
hsd.Instance = SDIO;
hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
hsd.Init.ClockDiv = 0;
if (HAL_SD_Init(&hsd) != HAL_OK)
{
Error_Handler();
}
if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SDIO_Init 2 */
/* USER CODE END SDIO_Init 2 */
}
/**
* @brief SPI5 Initialization Function
* @param None
@@ -690,6 +730,7 @@ static void MX_GPIO_Init(void)
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
bsp/stm32/stm32f427-robomaster-a/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c
+85
View File
@@ -222,6 +222,91 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
}
/**
* @brief SD MSP Initialization
* This function configures the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hsd->Instance==SDIO)
{
/* USER CODE BEGIN SDIO_MspInit 0 */
/* USER CODE END SDIO_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SDIO_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**SDIO GPIO Configuration
PC12 ------> SDIO_CK
PC11 ------> SDIO_D3
PC10 ------> SDIO_D2
PD2 ------> SDIO_CMD
PC9 ------> SDIO_D1
PC8 ------> SDIO_D0
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9
|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_2;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/* USER CODE BEGIN SDIO_MspInit 1 */
/* USER CODE END SDIO_MspInit 1 */
}
}
/**
* @brief SD MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
{
if(hsd->Instance==SDIO)
{
/* USER CODE BEGIN SDIO_MspDeInit 0 */
/* USER CODE END SDIO_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SDIO_CLK_DISABLE();
/**SDIO GPIO Configuration
PC12 ------> SDIO_CK
PC11 ------> SDIO_D3
PC10 ------> SDIO_D2
PD2 ------> SDIO_CMD
PC9 ------> SDIO_D1
PC8 ------> SDIO_D0
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9
|GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
/* USER CODE BEGIN SDIO_MspDeInit 1 */
/* USER CODE END SDIO_MspDeInit 1 */
}
}
/**
* @brief SPI MSP Initialization
* This function configures the hardware resources used in this example
bsp/stm32/stm32f427-robomaster-a/board/Kconfig
+12
View File
@@ -8,6 +8,12 @@ config SOC_STM32F427II
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
endmenu
menu "On-chip Peripheral Drivers"
@@ -76,6 +82,12 @@ menu "On-chip Peripheral Drivers"
default n
endif
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
menuconfig BSP_USING_PWM
bool "Enable pwm"
default n
bsp/stm32/stm32f427-robomaster-a/board/SConscript
+3
View File
@@ -12,6 +12,9 @@ board.c
CubeMX_Config/Src/stm32f4xx_hal_msp.c
''')
if GetDepend(['BSP_USING_SDCARD']):
src += Glob('ports/sdcard_port.c')
path = [cwd]
path += [cwd + '/CubeMX_Config/Inc']
path += [cwd + '/ports']
bsp/stm32/stm32f427-robomaster-a/board/board.c
+1 -1
View File
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLM = 6;
RCC_OscInitStruct.PLL.PLLN = 180;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLQ = 8;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
+62
View File
@@ -0,0 +1,62 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-13 balanceTWK add sdcard port file
*/
#include <rtthread.h>
#ifdef RT_USING_DFS
#include <dfs_elm.h>
#include <dfs_fs.h>
#include <dfs_posix.h>
#define DBG_TAG "app.card"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void sd_mount(void *parameter)
{
while (1)
{
rt_thread_mdelay(500);
if(rt_device_find("sd0") != RT_NULL)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
break;
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
}
int stm32_sdcard_mount(void)
{
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
1024, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_thread_startup(tid);
}
else
{
LOG_E("create sd_mount thread err!");
}
return RT_EOK;
}
INIT_APP_EXPORT(stm32_sdcard_mount);
#endif
bsp/stm32/stm32f429-atk-apollo/.cproject
+1 -1
View File
File diff suppressed because one or more lines are too long
bsp/stm32/stm32f429-fire-challenger/.cproject
+1 -1
View File
File diff suppressed because one or more lines are too long
bsp/stm32/stm32f767-atk-apollo/.cproject
+1 -1
View File
File diff suppressed because one or more lines are too long
bsp/stm32/stm32l475-atk-pandora/.cproject
+1 -1
View File
File diff suppressed because one or more lines are too long
bsp/x1000/SConstruct
+1 -1
View File
@@ -28,7 +28,7 @@ Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
if GetDepend('RT_USING_HARD_FLOAT'):
env['CCFLAGS'] = env['CCFLAGS'].replace('-msoft-float', '-mhard-float')
bsp/x1000/cpu/SConscript
+18
View File
@@ -0,0 +1,18 @@
# RT-Thread building script for bridge
import os
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
group = []
list = os.listdir(cwd)
# add common code files
group = group + SConscript(os.path.join('common', 'SConscript'))
# cpu porting code files
group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
Return('group')
libcpu/mips/x1000/SConscript → bsp/x1000/cpu/common/SConscript
View File
bsp/x1000/cpu/common/asm.h
+220
View File
@@ -0,0 +1,220 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
*
* Some useful macros for MIPS assembler code
*
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
*/
#ifndef __ASM_H__
#define __ASM_H__
/*
* LEAF - declare leaf routine
*/
#define LEAF(symbol) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp,0,ra
/*
* NESTED - declare nested routine entry point
*/
#define NESTED(symbol, framesize, rpc) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
#define END(function) \
.end function; \
.size function,.-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol,@function; \
symbol:
/*
* Global data declaration with size.
*/
#define EXPORTS(name,sz) \
.globl name; \
.type name,@object; \
.size name,sz; \
name:
/*
* Weak data declaration with size.
*/
#define WEXPORT(name,sz) \
.weakext name; \
.type name,@object; \
.size name,sz; \
name:
/*
* Global data reference with size.
*/
#define IMPORT(name, size) \
.extern name,size
/*
* Global zeroed data.
*/
#define BSS(name,size) \
.type name,@object; \
.comm name,size
/*
* Local zeroed data.
*/
#define LBSS(name,size) \
.lcomm name,size
/*
* ABS - export absolute symbol
*/
#define ABS(symbol,value) \
.globl symbol; \
symbol = value
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
#define ENTRY(name) \
.globl name; \
.align 2; \
.ent name,0; \
name##:
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
/*
* Size of a register
*/
#define SZREG 4
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#define REG_S sw
#define REG_L lw
#define REG_SUBU subu
#define REG_ADDU addu
/*
* How to add/sub/load/store/shift C int variables.
*/
#define INT_ADD add
#define INT_ADDU addu
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
/*
* How to add/sub/load/store/shift C long variables.
*/
#define LONG_ADD add
#define LONG_ADDU addu
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
#define LONG .word
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
/*
* How to add/sub/load/store/shift pointers.
*/
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
#define PTRSIZE 4
#define PTRLOG 2
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
#define MFC0 mfc0
#define MTC0 mtc0
#define SSNOP sll zero, zero, 1
#endif /* end of __ASM_H__ */
bsp/x1000/cpu/common/exception.h
+166
View File
@@ -0,0 +1,166 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#ifndef __EXCEPTION_H__
#define __EXCEPTION_H__
/*
* important register numbers
*/
#define REG_EPC 37
#define REG_FP 72
#define REG_SP 29
/*
* Stack layout for the GDB exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
#define NUMREGS 90
#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
///*
// * Saved floating point registers
// */
//#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
//#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
//#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
//#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
//#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
//#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
//#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
//#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
//#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
//#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
//#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
//#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
//#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
//#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
//#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
//#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
//#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
//#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
//#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
//#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
//#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
//#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
//#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
//#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
//#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
//#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
//#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
//#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
//#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
//#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
//#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
//#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
//
//#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
//#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
//#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
//
//#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
//
///*
// * Again, CP0 registers
// */
//#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
#define GDB_FR_FRP ((GDB_FR_EPC) + LONGSIZE) /* 72 */
#define GDB_FR_CP0_INDEX ((GDB_FR_FRP) + LONGSIZE) /* 74 */
#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
/*
* This is the same as above, but for the high-level
* part of the INT stub.
*/
typedef struct pt_regs_s
{
/* Saved main processor registers. */
rt_base_t regs[32];
/* Saved special registers. */
rt_base_t cp0_status;
rt_base_t hi;
rt_base_t lo;
rt_base_t cp0_badvaddr;
rt_base_t cp0_cause;
rt_base_t cp0_epc;
} pt_regs_t;
typedef void (* exception_func_t)(pt_regs_t *regs);
extern exception_func_t sys_exception_handlers[];
exception_func_t rt_set_except_vector(int n, exception_func_t func);
void install_default_execpt_handle(void);
#endif /* end of __EXCEPTION_H__ */
bsp/x1000/cpu/common/mips.h
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2016-09-07 Urey first version
*/
#ifndef _COMMON_MIPS_H_
#define _COMMON_MIPS_H_
#include "mips_cfg.h"
#include "mips_types.h"
#include "mips_asm.h"
#include "mips_def.h"
#include "mips_regs.h"
#include "mips_addrspace.h"
#include "mips_cache.h"
#include "mips_context.h"
#include "mips_excpt.h"
#endif /* _COMMON_MIPS_H_ */
bsp/x1000/cpu/common/mips.inc
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/*
* File : mips.inc
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 sangwei first version
*/
#ifndef __MIPS_INC__
#define __MIPS_INC__
#define zero $0 /* wired zero */
// #define at $1
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* caller saved */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* caller saved */
#define t9 $25
#define jp $25 /* PIC jump register */
#define k0 $26 /* kernel scratch */
#define k1 $27
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define s8 $30 /* same like fp! */
#define ra $31 /* return address */
#endif /* end of __MIPS_INC__ */
bsp/x1000/cpu/common/mips_addrspace.h
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/*
* File : mips_addrspace.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2016Äê9ÔÂ12ÈÕ Urey the first version
*/
#ifndef _MIPS_ADDRSPACE_H_
#define _MIPS_ADDRSPACE_H_
/*
* Configure language
*/
#ifdef __ASSEMBLY__
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
#define _CONST64_(x) x
#else
#define _ATYPE_ __PTRDIFF_TYPE__
#define _ATYPE32_ int
#define _ATYPE64_ __s64
#ifdef CONFIG_64BIT
#define _CONST64_(x) x ## L
#else
#define _CONST64_(x) x ## LL
#endif
#endif
/*
* 32-bit MIPS address spaces
*/
#ifdef __ASSEMBLY__
#define _ACAST32_
#define _ACAST64_
#else
#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
#endif
/*
* Returns the kernel segment base of a given address
*/
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
/*
* Returns the physical address of a CKSEGx / XKPHYS address
*/
#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_(a)) & \
_CONST64_(0x000000ffffffffff))
#ifdef CONFIG_64BIT
/*
* Memory segments (64bit kernel mode addresses)
* The compatibility segments use the full 64-bit sign extended value. Note
* the R8000 doesn't have them so don't reference these in generic MIPS code.
*/
#define XKUSEG _CONST64_(0x0000000000000000)
#define XKSSEG _CONST64_(0x4000000000000000)
#define XKPHYS _CONST64_(0x8000000000000000)
#define XKSEG _CONST64_(0xc000000000000000)
#define CKSEG0 _CONST64_(0xffffffff80000000)
#define CKSEG1 _CONST64_(0xffffffffa0000000)
#define CKSSEG _CONST64_(0xffffffffc0000000)
#define CKSEG3 _CONST64_(0xffffffffe0000000)
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
#else
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
/*
* Map an address to a certain kernel segment
*/
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE)
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE)
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE)
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE)
/*
* Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe.
*/
//#define KUSEGBASE 0x00000000
//#define KSEG0BASE 0x80000000
//#define KSEG1BASE 0xa0000000
//#define KSEG2BASE 0xc0000000
//#define KSEG3BASE 0xe0000000
#define CKUSEG 0x00000000
#define CKSEG0 0x80000000
#define CKSEG1 0xa0000000
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
#endif
/*
* Cache modes for XKPHYS address conversion macros
*/
#define K_CALG_COH_EXCL1_NOL2 0
#define K_CALG_COH_SHRL1_NOL2 1
#define K_CALG_UNCACHED 2
#define K_CALG_NONCOHERENT 3
#define K_CALG_COH_EXCL 4
#define K_CALG_COH_SHAREABLE 5
#define K_CALG_NOTUSED 6
#define K_CALG_UNCACHED_ACCEL 7
/*
* 64-bit address conversions
*/
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
(_CONST64_(cm) << 59) | (a))
/*
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
/*
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
* the region, 3 bits for the CCA mode. This leaves 59 bits of which the
* R8000 implements most with its 48-bit physical address space.
*/
#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
#ifndef CONFIG_CPU_R8000
/*
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
* in order to catch bugs in the source code.
*/
#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
#endif
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
#ifndef __ASSEMBLY__
/*
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/MIPS mapping
*/
static inline phys_addr_t virt_to_phys(volatile void * address)
{
#ifndef CONFIG_64BIT
return CPHYSADDR(address);
#else
return XPHYSADDR(address);
#endif
}
static inline void * phys_to_virt(unsigned long address)
{
#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
#else
return (void *)CKSEG0ADDR(address);
#endif
}
#endif
#endif /* _MIPS_ADDRSPACE_H_ */
bsp/x1000/cpu/common/mips_asm.h
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/*
* File : mips_asm.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2016Äê9ÔÂ7ÈÕ Urey the first version
*/
#ifndef _MIPS_ASM_H_
#define _MIPS_ASM_H_
/* ********************************************************************* */
/* Interface macro & data definition */
#ifdef __ASSEMBLY__
/******** ASSEMBLER SPECIFIC DEFINITIONS ********/
#ifdef __ghs__
#define ALIGN(x) .##align (1 << (x))
#else
#define ALIGN(x) .##align (x)
#endif
#ifdef __ghs__
#define SET_MIPS3()
#define SET_MIPS0()
#define SET_PUSH()
#define SET_POP()
#else
#define SET_MIPS3() .##set mips3
#define SET_MIPS0() .##set mips0
#define SET_PUSH() .##set push
#define SET_POP() .##set pop
#endif
/* Different assemblers have different requirements for how to
* indicate that the next section is bss :
*
* Some use : .bss
* Others use : .section bss
*
* We select which to use based on _BSS_OLD_, which may be defined
* in makefile.
*/
#ifdef _BSS_OLD_
#define BSS .##section bss
#else
#define BSS .##bss
#endif
#define LEAF(name)\
.##text;\
.##globl name;\
.##ent name;\
name:
#define SLEAF(name)\
.##text;\
.##ent name;\
name:
#ifdef __ghs__
#define END(name)\
.##end name
#else
#define END(name)\
.##size name,.-name;\
.##end name
#endif
#define EXTERN(name)
#else
#define U64 unsigned long long
#define U32 unsigned int
#define U16 unsigned short
#define U8 unsigned char
#define S64 signed long long
#define S32 int
#define S16 short int
#define S8 signed char
//#define bool U8
#ifndef _SIZE_T_
#define _SIZE_T_
#ifdef __ghs__
typedef unsigned int size_t;
#else
typedef unsigned long size_t;
#endif
#endif
/* Sets the result on bPort */
#define BIT_SET(bPort,bBitMask) (bPort |= bBitMask)
#define BIT_CLR(bPort,bBitMask) (bPort &= ~bBitMask)
/* Returns the result */
#define GET_BIT_SET(bPort,bBitMask) (bPort | bBitMask)
#define GET_BIT_CLR(bPort,bBitMask) (bPort & ~bBitMask)
/* Returns 0 if the condition is False & a non-zero value if it is True */
#define TEST_BIT_SET(bPort,bBitMask) (bPort & bBitMask)
#define TEST_BIT_CLR(bPort,bBitMask) ((~bPort) & bBitMask)
/* Split union definitions */
typedef union tunSU16
{
U16 hwHW;
struct tst2U8
{
U8 bB0;
U8 bB1;
}st2U8;
}tunSU16;
typedef union tunSU32
{
U32 wW;
struct tst2U16
{
U16 hwHW0;
U16 hwHW1;
}st2U16;
struct tst4U8
{
U8 bB0;
U8 bB1;
U8 bB2;
U8 bB3;
}st4U8;
}tunSU32;
#endif /* #ifdef __ASSEMBLY__ */
/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/
#define NO_ERR 0x00000000 /* operation completed successfully */
#define ERR 0xffffffff /* operation completed not successfully */
#define False 0
#define True !False
#ifndef NULL
#define NULL ((void *)0)
#endif//NULL
#ifndef MIN
#define MIN(x,y) ((x) < (y) ? (x) : (y))
#endif//MIN
#ifndef MAX
#define MAX(x,y) ((x) > (y) ? (x) : (y))
#endif//MAX
#define MAXUINT(w) (\
((w) == sizeof(U8)) ? 0xFFU :\
((w) == sizeof(U16)) ? 0xFFFFU :\
((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\
)
#define MAXINT(w) (\
((w) == sizeof(S8)) ? 0x7F :\
((w) == sizeof(S16)) ? 0x7FFF :\
((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\
)
#define MSK(n) ((1 << (n)) - 1)
#define KUSEG_MSK 0x80000000
#define KSEG_MSK 0xE0000000
#define KUSEGBASE 0x00000000
#define KSEG0BASE 0x80000000
#define KSEG1BASE 0xA0000000
#define KSSEGBASE 0xC0000000
#define KSEG3BASE 0xE0000000
/* Below macros perform the following functions :
*
* KSEG0 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0.
* KSEG1 : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1.
* PHYS : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address.
* KSSEG : Not relevant for converting, but used for determining range.
* KSEG3 : Not relevant for converting, but used for determining range.
* KUSEG : Not relevant for converting, but used for determining range.
* KSEG0A : Same as KSEG0 but operates on register rather than constant.
* KSEG1A : Same as KSEG1 but operates on register rather than constant.
* PHYSA : Same as PHYS but operates on register rather than constant.
* CACHED : Alias for KSEG0 macro .
* (Note that KSEG0 cache attribute is determined by K0
* field of Config register, but this is typically cached).
* UNCACHED : Alias for KSEG1 macro .
*/
#ifdef __ASSEMBLY__
#define KSEG0(addr) (((addr) & ~KSEG_MSK) | KSEG0BASE)
#define KSEG1(addr) (((addr) & ~KSEG_MSK) | KSEG1BASE)
#define KSSEG(addr) (((addr) & ~KSEG_MSK) | KSSEGBASE)
#define KSEG3(addr) (((addr) & ~KSEG_MSK) | KSEG3BASE)
#define KUSEG(addr) (((addr) & ~KUSEG_MSK) | KUSEGBASE)
#define PHYS(addr) ( (addr) & ~KSEG_MSK)
#define KSEG0A(reg) and reg, ~KSEG_MSK; or reg, KSEG0BASE
#define KSEG1A(reg) and reg, ~KSEG_MSK; or reg, KSEG1BASE
#define PHYSA(reg) and reg, ~KSEG_MSK
#else
#define KSEG0(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG0BASE)
#define KSEG1(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG1BASE)
#define KSSEG(addr) (((U32)(addr) & ~KSEG_MSK) | KSSEGBASE)
#define KSEG3(addr) (((U32)(addr) & ~KSEG_MSK) | KSEG3BASE)
#define KUSEG(addr) (((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE)
#define PHYS(addr) ((U32)(addr) & ~KSEG_MSK)
#endif
#define CACHED(addr) KSEG0(addr)
#define UNCACHED(addr) KSEG1(addr)
#ifdef __ASSEMBLY__
/* Macroes to access variables at constant addresses
* Compensates for signed 16 bit displacement
* Typical use: li a0, HIKSEG1(ATLAS_ASCIIWORD)
* sw v1, LO_OFFS(ATLAS_ASCIIWORD)(a0)
*/
#define HIKSEG0(addr) ((KSEG0(addr) + 0x8000) & 0xffff0000)
#define HIKSEG1(addr) ((KSEG1(addr) + 0x8000) & 0xffff0000)
#define HI_PART(addr) (((addr) + 0x8000) & 0xffff0000)
#define LO_OFFS(addr) ((addr) & 0xffff)
#endif
/* Most/Least significant 32 bit from 64 bit double word */
#define HI32(data64) ((U32)(data64 >> 32))
#define LO32(data64) ((U32)(data64 & 0xFFFFFFFF))
#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY)))
#define REG8( addr ) (*(volatile U8 *) (addr))
#define REG16( addr ) (*(volatile U16 *)(addr))
#define REG32( addr ) (*(volatile U32 *)(addr))
#define REG64( addr ) (*(volatile U64 *)(addr))
#endif
/* Register field mapping */
#define REGFIELD(reg, rfld) (((reg) & rfld##_MSK) >> rfld##_SHF)
/* absolute register address, access */
#define REGA(addr) REG32(addr)
/* physical register address, access: base address + offsett */
#define REGP(base,phys) REG32( (U32)(base) + (phys) )
/* relative register address, access: base address + offsett */
#define REG(base,offs) REG32( (U32)(base) + offs##_##OFS )
/* relative register address, access: base address + offsett */
#define REG_8(base,offs) REG8( (U32)(base) + offs##_##OFS )
/* relative register address, access: base address + offsett */
#define REG_16(base,offs) REG16( (U32)(base) + offs##_##OFS )
/* relative register address, access: base address + offsett */
#define REG_64(base,offs) REG64( (U32)(base) + offs##_##OFS )
/**************************************
* Macroes not used by YAMON any more
* (kept for backwards compatibility)
*/
/* register read field */
#define REGARD(addr,fld) ((REGA(addr) & addr##_##fld##_##MSK) \
>> addr##_##fld##_##SHF)
/* register write numeric field value */
#define REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
| ((intval) << addr##_##fld##_##SHF))
/* register write enumerated field value */
#define REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
| ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF))
/* Examples:
*
* exccode = REGARD(CPU_CAUSE,EXC);
*
* REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17)
* | REGAWRE(OSG_CONTROL,DTYPE,PC1);
*/
/* register read field */
#define REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) \
>> offs##_##fld##_##SHF)
/* register write numeric field value */
#define REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\
| (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK))
/* register write enumerated field value */
#define REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\
| ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF))
/* physical register read field */
#define REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) \
>> phys##_##fld##_##SHF)
/* physical register write numeric field value */
#define REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\
| ((intval) << phys##_##fld##_##SHF))
/* physical register write enumerated field value */
#define REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\
| ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF))
/*
* End of macroes not used by YAMON any more
*********************************************/
/* Endian related macros */
#define SWAP_BYTEADDR32( addr ) ( (addr) ^ 0x3 )
#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 )
/* Set byte address to little endian format */
#ifdef EL
#define SWAP_BYTEADDR_EL(addr) addr
#else
#define SWAP_BYTEADDR_EL(addr) SWAP_BYTEADDR32( addr )
#endif
/* Set byte address to big endian format */
#ifdef EB
#define SWAP_BYTEADDR_EB(addr) addr
#else
#define SWAP_BYTEADDR_EB(addr) SWAP_BYTEADDR32( addr )
#endif
/* Set U16 address to little endian format */
#ifdef EL
#define SWAP_U16ADDR_EL(addr) addr
#else
#define SWAP_U16ADDR_EL(addr) SWAP_U16ADDR32( addr )
#endif
/* Set U16 address to big endian format */
#ifdef EB
#define SWAP_U16ADDR_EB(addr) addr
#else
#define SWAP_U16ADDR_EB(addr) SWAP_U16ADDR32( addr )
#endif
#ifdef EL
#define REGW32LE(addr, data) REG32(addr) = (data)
#define REGR32LE(addr, data) (data) = REG32(addr)
#else
#define REGW32LE(addr, data) REG32(addr) = SWAPEND32(data)
#define REGR32LE(addr, data) (data) = REG32(addr), (data) = SWAPEND32(data)
#endif
/* Set of 'LE'-macros, convert by BE: */
#ifdef EL
#define CPU_TO_LE32( value ) (value)
#define LE32_TO_CPU( value ) (value)
#define CPU_TO_LE16( value ) (value)
#define LE16_TO_CPU( value ) (value)
#else
#define CPU_TO_LE32( value ) ( ( ((U32)value) << 24) | \
((0x0000FF00UL & ((U32)value)) << 8) | \
((0x00FF0000UL & ((U32)value)) >> 8) | \
( ((U32)value) >> 24) )
#define LE32_TO_CPU( value ) CPU_TO_LE32( value )
#define CPU_TO_LE16( value ) ( ((U16)(((U16)value) << 8)) | \
((U16)(((U16)value) >> 8)) )
#define LE16_TO_CPU( value ) CPU_TO_LE16( value )
#endif
/* Set of 'BE'-macros, convert by LE: */
#ifdef EB
#define CPU_TO_BE32( value ) (value)
#define BE32_TO_CPU( value ) (value)
#define CPU_TO_BE16( value ) (value)
#define BE16_TO_CPU( value ) (value)
#else
#define CPU_TO_BE32( value ) ( ( ((U32)value) << 24) | \
((0x0000FF00UL & ((U32)value)) << 8) | \
((0x00FF0000UL & ((U32)value)) >> 8) | \
( ((U32)value) >> 24) )
#define BE32_TO_CPU( value ) CPU_TO_BE32( value )
#define CPU_TO_BE16( value ) ( ((U16)(((U16)value) << 8)) | \
((U16)(((U16)value) >> 8)) )
#define BE16_TO_CPU( value ) CPU_TO_BE16( value )
#endif
/* Control characters */
#define CTRL_A ('A'-0x40)
#define CTRL_B ('B'-0x40)
#define CTRL_C ('C'-0x40)
#define CTRL_D ('D'-0x40)
#define CTRL_E ('E'-0x40)
#define CTRL_F ('F'-0x40)
#define CTRL_H ('H'-0x40)
#define CTRL_K ('K'-0x40)
#define CTRL_N ('N'-0x40)
#define CTRL_P ('P'-0x40)
#define CTRL_U ('U'-0x40)
#define BACKSPACE 0x08
#define DEL 0x7F
#define TAB 0x09
#define CR 0x0D /* Enter Key */
#define LF 0x0A
#define ESC 0x1B
#define SP 0x20
#define CSI 0x9B
/* DEF2STR(x) converts #define symbol to string */
#define DEF2STR1(x) #x
#define DEF2STR(x) DEF2STR1(x)
#endif /* _MIPS_ASM_H_ */
bsp/x1000/cpu/common/mips_cache.c
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/*
* File : mips_cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2016Äê9ÔÂ7ÈÕ Urey the first version
*/
#include <rtthread.h>
#include "mips.h"
extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
void r4k_cache_init(void)
{
// cache_init(dcache_size, cpu_dcache_line_size);
}
void r4k_cache_flush_all(void)
{
blast_dcache16();
blast_icache16();
}
void r4k_icache_flush_all(void)
{
blast_icache16();
}
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
if (size > g_mips_core.icache_size)
{
blast_icache16();
}
else
{
rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
while (1)
{
flush_icache_line(a);
if (a == end)
break;
a += ic_lsize;
}
}
}
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
a = addr & ~(ic_lsize - 1);
end = ((addr + size) - 1) & ~(ic_lsize - 1);
while (1)
{
lock_icache_line(a);
if (a == end)
break;
a += ic_lsize;
}
}
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
a = addr & ~(dc_lsize - 1);
end = ((addr + size) - 1) & ~(dc_lsize - 1);
while (1)
{
invalidate_dcache_line(a);
if (a == end)
break;
a += dc_lsize;
}
}
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
{
rt_ubase_t end, a;
if (size >= g_mips_core.dcache_size)
{
blast_dcache16();
}
else
{
rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
a = addr & ~(dc_lsize - 1);
end = ((addr + size) - 1) & ~(dc_lsize - 1);
while (1)
{
flush_dcache_line(a);
if (a == end)
break;
a += dc_lsize;
}
}
}
#define dma_cache_wback_inv(start,size) \
do { (void) (start); (void) (size); } while (0)
#define dma_cache_wback(start,size) \
do { (void) (start); (void) (size); } while (0)
#define dma_cache_inv(start,size) \
do { (void) (start); (void) (size); } while (0)
void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction)
{
switch (direction)
{
case DMA_TO_DEVICE:
r4k_dcache_wback_inv(addr, size);
break;
case DMA_FROM_DEVICE:
r4k_dcache_wback_inv(addr, size);
break;
case DMA_BIDIRECTIONAL:
dma_cache_wback_inv(addr, size);
break;
default:
RT_ASSERT(0) ;
}
}
bsp/x1000/cpu/common/mips_cache.h
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/*
* File : mips_cache.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2016Äê9ÔÂ10ÈÕ Urey the first version
*/
#ifndef _MIPS_CACHE_H_
#define _MIPS_CACHE_H_
#ifndef __ASSEMBLER__
#include <rtdef.h>
#include <mips_cfg.h>
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
#define INDEX_INVALIDATE_I 0x00
#define INDEX_WRITEBACK_INV_D 0x01
#define INDEX_LOAD_TAG_I 0x04
#define INDEX_LOAD_TAG_D 0x05
#define INDEX_STORE_TAG_I 0x08
#define INDEX_STORE_TAG_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
#define HIT_INVALIDATE_I 0x00
#else
#define HIT_INVALIDATE_I 0x10
#endif
#define HIT_INVALIDATE_D 0x11
#define HIT_WRITEBACK_INV_D 0x15
/*
*The lock state is cleared by executing an Index
Invalidate, Index Writeback Invalidate, Hit
Invalidate, or Hit Writeback Invalidate
operation to the locked line, or via an Index
Store Tag operation with the lock bit reset in
the TagLo register.
*/
#define FETCH_AND_LOCK_I 0x1c
#define FETCH_AND_LOCK_D 0x1d
enum dma_data_direction
{
DMA_BIDIRECTIONAL = 0,
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
DMA_NONE = 3,
};
/*
* R4000-specific cacheops
*/
#define CREATE_DIRTY_EXCL_D 0x0d
#define FILL 0x14
#define HIT_WRITEBACK_I 0x18
#define HIT_WRITEBACK_D 0x19
/*
* R4000SC and R4400SC-specific cacheops
*/
#define INDEX_INVALIDATE_SI 0x02
#define INDEX_WRITEBACK_INV_SD 0x03
#define INDEX_LOAD_TAG_SI 0x06
#define INDEX_LOAD_TAG_SD 0x07
#define INDEX_STORE_TAG_SI 0x0A
#define INDEX_STORE_TAG_SD 0x0B
#define CREATE_DIRTY_EXCL_SD 0x0f
#define HIT_INVALIDATE_SI 0x12
#define HIT_INVALIDATE_SD 0x13
#define HIT_WRITEBACK_INV_SD 0x17
#define HIT_WRITEBACK_SD 0x1b
#define HIT_SET_VIRTUAL_SI 0x1e
#define HIT_SET_VIRTUAL_SD 0x1f
/*
* R5000-specific cacheops
*/
#define R5K_PAGE_INVALIDATE_S 0x17
/*
* RM7000-specific cacheops
*/
#define PAGE_INVALIDATE_T 0x16
/*
* R10000-specific cacheops
*
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
#define INDEX_WRITEBACK_INV_S 0x03
#define INDEX_LOAD_TAG_S 0x07
#define INDEX_STORE_TAG_S 0x0B
#define HIT_INVALIDATE_S 0x13
#define CACHE_BARRIER 0x14
#define HIT_WRITEBACK_INV_S 0x17
#define INDEX_LOAD_DATA_I 0x18
#define INDEX_LOAD_DATA_D 0x19
#define INDEX_LOAD_DATA_S 0x1b
#define INDEX_STORE_DATA_I 0x1c
#define INDEX_STORE_DATA_D 0x1d
#define INDEX_STORE_DATA_S 0x1f
#define cache_op(op, addr) \
__asm__ __volatile__( \
".set push\n" \
".set noreorder\n" \
".set mips3\n" \
"cache %0, %1\n" \
".set pop\n" \
: \
: "i" (op), "R" (*(unsigned char *)(addr)))
#define cache16_unroll32(base, op) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips3 \n" \
" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
" .set mips0 \n" \
" .set reorder \n" \
: \
: "r" (base), \
"i" (op));
static inline void flush_icache_line_indexed(rt_ubase_t addr)
{
cache_op(INDEX_INVALIDATE_I, addr);
}
static inline void flush_dcache_line_indexed(rt_ubase_t addr)
{
cache_op(INDEX_WRITEBACK_INV_D, addr);
}
static inline void flush_icache_line(rt_ubase_t addr)
{
cache_op(HIT_INVALIDATE_I, addr);
}
static inline void lock_icache_line(rt_ubase_t addr)
{
cache_op(FETCH_AND_LOCK_I, addr);
}
static inline void lock_dcache_line(rt_ubase_t addr)
{
cache_op(FETCH_AND_LOCK_D, addr);
}
static inline void flush_dcache_line(rt_ubase_t addr)
{
cache_op(HIT_WRITEBACK_INV_D, addr);
}
static inline void invalidate_dcache_line(rt_ubase_t addr)
{
cache_op(HIT_INVALIDATE_D, addr);
}
static inline void blast_dcache16(void)
{
rt_ubase_t start = KSEG0BASE;
rt_ubase_t end = start + g_mips_core.dcache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
}
static inline void inv_dcache16(void)
{
rt_ubase_t start = KSEG0BASE;
rt_ubase_t end = start + g_mips_core.dcache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
cache16_unroll32(addr, HIT_INVALIDATE_D);
}
static inline void blast_icache16(void)
{
rt_ubase_t start = KSEG0BASE;
rt_ubase_t end = start + g_mips_core.icache_size;
rt_ubase_t addr;
for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
cache16_unroll32(addr, INDEX_INVALIDATE_I);
}
void r4k_cache_init(void);
void r4k_cache_flush_all(void);
void r4k_icache_flush_all(void);
void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction);
#endif
#endif /* _MIPS_CACHE_H_ */
bsp/x1000/cpu/common/mips_cfg.h
+48
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/*
* File : mips_cfg.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2016Äê9ÔÂ10ÈÕ Urey the first version
*/
#ifndef _MIPS_CFG_H_
#define _MIPS_CFG_H_
#ifndef __ASSEMBLY__
#include <stdint.h>
typedef struct mips32_core_cfg
{
uint16_t icache_line_size;
// uint16_t icache_lines_per_way;
// uint16_t icache_ways;
uint16_t icache_size;
uint16_t dcache_line_size;
// uint16_t dcache_lines_per_way;
// uint16_t dcache_ways;
uint16_t dcache_size;
uint16_t max_tlb_entries; /* number of tlb entry */
} mips32_core_cfg_t;
extern mips32_core_cfg_t g_mips_core;
#endif /* __ASSEMBLY__ */
#endif /* _MIPS_CFG_H_ */
bsp/x1000/cpu/common/mips_context.h
+280
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/*
* File : mips_context_asm.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2016Äê9ÔÂ7ÈÕ Urey the first version
*/
#ifndef _MIPS_CONTEXT_ASM_H_
#define _MIPS_CONTEXT_ASM_H_
#define CONTEXT_SIZE ( STK_CTX_SIZE + FPU_ADJ )
#ifdef __mips_hard_float
#define FPU_ADJ (32 * 4 + 8) /* FP0-FP31 + CP1_STATUS */
#define FPU_CTX ( CONTEXT_SIZE - FPU_ADJ )
#else
#define FPU_ADJ 0
#endif
#ifdef __ASSEMBLY__
#ifdef __mips_hard_float
.global _fpctx_save
.global _fpctx_load
#endif
.macro SAVE_CONTEXT
.set push
.set noat
.set noreorder
.set volatile
//save SP
move k1, sp
move k0, sp
subu sp, k1, CONTEXT_SIZE
sw k0, (29 * 4)(sp)
//save REG
sw $0, ( 0 * 4)(sp)
sw $1, ( 1 * 4)(sp)
sw $2, ( 2 * 4)(sp)
sw $3, ( 3 * 4)(sp)
sw $4, ( 4 * 4)(sp)
sw $5, ( 5 * 4)(sp)
sw $6, ( 6 * 4)(sp)
sw $7, ( 7 * 4)(sp)
sw $8, ( 8 * 4)(sp)
sw $9, ( 9 * 4)(sp)
sw $10, (10 * 4)(sp)
sw $11, (11 * 4)(sp)
sw $12, (12 * 4)(sp)
sw $13, (13 * 4)(sp)
sw $14, (14 * 4)(sp)
sw $15, (15 * 4)(sp)
sw $16, (16 * 4)(sp)
sw $17, (17 * 4)(sp)
sw $18, (18 * 4)(sp)
sw $19, (19 * 4)(sp)
sw $20, (20 * 4)(sp)
sw $21, (21 * 4)(sp)
sw $22, (22 * 4)(sp)
sw $23, (23 * 4)(sp)
sw $24, (24 * 4)(sp)
sw $25, (25 * 4)(sp)
/* K0 K1 */
sw $28, (28 * 4)(sp)
/* SP */
sw $30, (30 * 4)(sp)
sw $31, (31 * 4)(sp)
/* STATUS CAUSE EPC.... */
mfc0 $2, CP0_STATUS
sw $2, STK_OFFSET_SR(sp)
mfc0 $2, CP0_CAUSE
sw $2, STK_OFFSET_CAUSE(sp)
mfc0 $2, CP0_BADVADDR
sw $2, STK_OFFSET_BADVADDR(sp)
MFC0 $2, CP0_EPC
sw $2, STK_OFFSET_EPC(sp)
mfhi $2
sw $2, STK_OFFSET_HI(sp)
mflo $2
sw $2, STK_OFFSET_LO(sp)
#ifdef __mips_hard_float
add a0, sp,STK_CTX_SIZE
mfc0 t0, CP0_STATUS
.set push
.set at
or t0, M_StatusCU1
.set push
mtc0 t0, CP0_STATUS
cfc1 t0, CP1_STATUS
sw t0 , 0x00(a0)
swc1 $f0,(0x04 * 1)(a0)
swc1 $f1,(0x04 * 2)(a0)
swc1 $f2,(0x04 * 3)(a0)
swc1 $f3,(0x04 * 4)(a0)
swc1 $f4,(0x04 * 5)(a0)
swc1 $f5,(0x04 * 6)(a0)
swc1 $f6,(0x04 * 7)(a0)
swc1 $f7,(0x04 * 8)(a0)
swc1 $f8,(0x04 * 9)(a0)
swc1 $f9,(0x04 * 10)(a0)
swc1 $f10,(0x04 * 11)(a0)
swc1 $f11,(0x04 * 12)(a0)
swc1 $f12,(0x04 * 13)(a0)
swc1 $f13,(0x04 * 14)(a0)
swc1 $f14,(0x04 * 15)(a0)
swc1 $f15,(0x04 * 16)(a0)
swc1 $f16,(0x04 * 17)(a0)
swc1 $f17,(0x04 * 18)(a0)
swc1 $f18,(0x04 * 19)(a0)
swc1 $f19,(0x04 * 20)(a0)
swc1 $f20,(0x04 * 21)(a0)
swc1 $f21,(0x04 * 22)(a0)
swc1 $f22,(0x04 * 23)(a0)
swc1 $f23,(0x04 * 24)(a0)
swc1 $f24,(0x04 * 25)(a0)
swc1 $f25,(0x04 * 26)(a0)
swc1 $f26,(0x04 * 27)(a0)
swc1 $f27,(0x04 * 28)(a0)
swc1 $f28,(0x04 * 29)(a0)
swc1 $f29,(0x04 * 30)(a0)
swc1 $f30,(0x04 * 31)(a0)
swc1 $f31,(0x04 * 32)(a0)
nop
#endif
//restore a0
lw a0, (REG_A0 * 4)(sp)
.set pop
.endm
.macro RESTORE_CONTEXT
.set push
.set noat
.set noreorder
.set volatile
#ifdef __mips_hard_float
add a0, sp,STK_CTX_SIZE
mfc0 t0, CP0_STATUS
.set push
.set at
or t0, M_StatusCU1
.set noat
mtc0 t0, CP0_STATUS
lw t0 , 0x00(a0)
lwc1 $f0,(0x04 * 1)(a0)
lwc1 $f1,(0x04 * 2)(a0)
lwc1 $f2,(0x04 * 3)(a0)
lwc1 $f3,(0x04 * 4)(a0)
lwc1 $f4,(0x04 * 5)(a0)
lwc1 $f5,(0x04 * 6)(a0)
lwc1 $f6,(0x04 * 7)(a0)
lwc1 $f7,(0x04 * 8)(a0)
lwc1 $f8,(0x04 * 9)(a0)
lwc1 $f9,(0x04 * 10)(a0)
lwc1 $f10,(0x04 * 11)(a0)
lwc1 $f11,(0x04 * 12)(a0)
lwc1 $f12,(0x04 * 13)(a0)
lwc1 $f13,(0x04 * 14)(a0)
lwc1 $f14,(0x04 * 15)(a0)
lwc1 $f15,(0x04 * 16)(a0)
lwc1 $f16,(0x04 * 17)(a0)
lwc1 $f17,(0x04 * 18)(a0)
lwc1 $f18,(0x04 * 19)(a0)
lwc1 $f19,(0x04 * 20)(a0)
lwc1 $f20,(0x04 * 21)(a0)
lwc1 $f21,(0x04 * 22)(a0)
lwc1 $f22,(0x04 * 23)(a0)
lwc1 $f23,(0x04 * 24)(a0)
lwc1 $f24,(0x04 * 25)(a0)
lwc1 $f25,(0x04 * 26)(a0)
lwc1 $f26,(0x04 * 27)(a0)
lwc1 $f27,(0x04 * 28)(a0)
lwc1 $f28,(0x04 * 29)(a0)
lwc1 $f29,(0x04 * 30)(a0)
lwc1 $f30,(0x04 * 31)(a0)
lwc1 $f31,(0x04 * 32)(a0)
ctc1 t0, CP1_STATUS ;/* restore fpp status reg */
nop
#endif
/* ͨÓüĴæÆ÷ */
/* ZERO */
lw $1, ( 1 * 4)(sp)
/* V0 */
lw $3, ( 3 * 4)(sp)
lw $4, ( 4 * 4)(sp)
lw $5, ( 5 * 4)(sp)
lw $6, ( 6 * 4)(sp)
lw $7, ( 7 * 4)(sp)
lw $8, ( 8 * 4)(sp)
lw $9, ( 9 * 4)(sp)
lw $10, (10 * 4)(sp)
lw $11, (11 * 4)(sp)
lw $12, (12 * 4)(sp)
lw $13, (13 * 4)(sp)
lw $14, (14 * 4)(sp)
lw $15, (15 * 4)(sp)
lw $16, (16 * 4)(sp)
lw $17, (17 * 4)(sp)
lw $18, (18 * 4)(sp)
lw $19, (19 * 4)(sp)
lw $20, (20 * 4)(sp)
lw $21, (21 * 4)(sp)
lw $22, (22 * 4)(sp)
lw $23, (23 * 4)(sp)
lw $24, (24 * 4)(sp)
lw $25, (25 * 4)(sp)
lw $26, (26 * 4)(sp)
lw $27, (27 * 4)(sp)
lw $28, (28 * 4)(sp)
/* SP */
lw $30, (30 * 4)(sp)
lw $31, (31 * 4)(sp)
/* STATUS CAUSE EPC.... */
lw $2, STK_OFFSET_HI(sp)
mthi $2
lw $2, STK_OFFSET_LO(sp)
mtlo $2
lw $2, STK_OFFSET_SR(sp)
mtc0 $2, CP0_STATUS
lw $2, STK_OFFSET_BADVADDR(sp)
mtc0 $2, CP0_BADVADDR
lw $2, STK_OFFSET_CAUSE(sp)
mtc0 $2, CP0_CAUSE
lw $2, STK_OFFSET_EPC(sp)
MTC0 $2, CP0_EPC
//restore $2
lw $2, ( 2 * 4)(sp)
//restore sp
lw $29, (29 * 4)(sp)
eret
nop
.set pop
.endm
#endif
#endif /* _MIPS_CONTEXT_ASM_H_ */
bsp/x1000/cpu/common/mips_def.h
+2296
View File
File diff suppressed because it is too large Load Diff
libcpu/mips/xburst/stack.h → bsp/x1000/cpu/common/mips_excpt.h
+18 -7
View File
@@ -1,6 +1,7 @@
/*
* File : stack.h
* COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
* File : mips_excpt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -18,11 +19,21 @@
*
* Change Logs:
* Date Author Notes
*/
* 2016Äê9ÔÂ7ÈÕ Urey the first version
*/
#ifndef __STACK_H__
#define __STACK_H__
#ifndef _MIPS_EXCPT_H_
#define _MIPS_EXCPT_H_
#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
#include "mips_regs.h"
#endif
#ifndef __ASSEMBLY__
typedef void (* exception_func_t)(mips_reg_ctx *regs);
//extern exception_func_t mips_exception_handlers[];
int rt_hw_exception_init(void);
exception_func_t rt_set_except_vector(int n, exception_func_t func);
void install_default_execpt_handle(void);
#endif /* __ASSEMBLY__ */
#endif /* _MIPS_EXCPT_H_ */

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